US20080017407A1 - Interposer and electronic device using the same - Google Patents

Interposer and electronic device using the same Download PDF

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Publication number
US20080017407A1
US20080017407A1 US11/491,288 US49128806A US2008017407A1 US 20080017407 A1 US20080017407 A1 US 20080017407A1 US 49128806 A US49128806 A US 49128806A US 2008017407 A1 US2008017407 A1 US 2008017407A1
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United States
Prior art keywords
interposer
hole conductors
substrate
electrodes
lower electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/491,288
Inventor
Shuichi Kawano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to US11/491,288 priority Critical patent/US20080017407A1/en
Assigned to IBIDEN CO., LTD. reassignment IBIDEN CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAWANO, SHUICHI
Priority to JP2008509262A priority patent/JPWO2008013054A1/en
Priority to PCT/JP2007/063757 priority patent/WO2008013054A1/en
Priority to EP07790575A priority patent/EP1928022A1/en
Priority to CN2007800024254A priority patent/CN101371355B/en
Priority to KR1020087009227A priority patent/KR100977436B1/en
Priority to TW096126344A priority patent/TWI360210B/en
Priority to US11/860,132 priority patent/US8149585B2/en
Publication of US20080017407A1 publication Critical patent/US20080017407A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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Definitions

  • the present invention relates to an interposer and an electronic device using it, and, more particularly, to an interposer interposed between a semiconductor chip and a package substrate as well as to an electronic device composed of a combination of the semiconductor chip, the interposer, and the package substrate.
  • interposer utilizing a printed wiring board for carrying out wiring between a semiconductor chip and a package substrate.
  • the interposer is a wiring device used to mutually connect a conductor circuit of a semiconductor chip which has an ultra dense pitch (for example, 50 ⁇ m) and a conductor circuit of a package substrate (also referred to as “mounting substrate”) which has a pitch more coarse than the above pitch (for example, 150 ⁇ m).
  • Claim 1 of the Laid-open publication states “An interposer for a semiconductor device having first electrodes, dielectric layers formed on the first electrodes, and second electrodes formed on the dielectric layer, characterized in that a necessary number of capacitors composed of the first electrodes, the dielectric layers, and the second electrodes are formed on the interposer”.
  • the Japanese Patent laid-open Publication describes “Further, since a wiring is carried out by a wiring pattern on the interposer, a fine pattern can be achieved. Accordingly, since the wiring is carried out on the interposer, it is possible to reduce one layer from the layers on a mounting substrate made by a multilayer board” (see paragraph 0006).
  • an object of the present invention is to provide a novel interposer and electronic device using it.
  • An interposer of the present invention comprises a capacitor formed on a generally entire surface of a substrate.
  • the interposer may comprise the substrate including a plurality of through-hole conductors; some of the through hole conductors that have land portions formed with an upper electrode of the capacitors; some of the remaining of the through-hole conductors that have land portions formed with a lower electrode of the capacitor; and a dielectric layer interposed between the upper electrodes and the lower electrodes.
  • some of the through-hole conductors may be formed as through-hole conductors for signal on a central portion of the surface of the substrate, and through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes may be formed surrounding the through-hole conductors for signal.
  • some of the through-hole conductors may be formed as through-hole conductors for signal on a peripheral region of the surface of the substrate, and through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes may be formed inside of the peripheral region.
  • the interposer may further comprise a wiring layer that is formed on at least one insulating layer disposed above the capacitors.
  • the substrate may be a silicon substrate.
  • the through-hole conductors may be made of copper.
  • the upper and lower electrodes may be made of nickel or platinum.
  • the dielectric layer may be made of a ferroelectric substance.
  • the dielectric layer may be made of barium titanate.
  • At least one surface of the interposer may be covered with a solder resist layer or an insulating resin layer.
  • An electronic device of the present invention comprises an IC chip; a package substrate; and an interposer, according to claim 1 or 2 , interposed between the IC chip and the package substrate and electrically connected to the both, wherein the interposer provides capacitors.
  • FIG. 1 is a sectional view showing a main portion of an embodiment of an interposer according to this invention
  • FIG. 2 is a sectional view showing a main portion of another interposer according to this invention.
  • FIG. 3 is a sectional view showing an actual arrangement of the interposer.
  • FIG. 4 is a sectional view showing an actual arrangement of the another interposer.
  • FIG. 1 is a sectional view showing an embodiment of a main portion of an interposer 10 according to this invention.
  • the main portion of the interposer 10 includes through-hole conductors 20 - 1 , 20 - 2 , 20 - 3 formed on a silicon substrate 12 , lower electrodes 18 formed on a surface of the silicon substrate 12 , a dielectric layer 16 formed on the lower electrodes 18 , and upper electrodes 14 formed on the dielectric layer 16 .
  • the surface of the silicon substrate 12 When the surface of the silicon substrate 12 is properly polished, it has such a property that the surface is very flat and smooth.
  • a glass substrate and a polyimide substrate may be used in place of the silicon substrate when they satisfy the level of a surface flatness required in this embodiment.
  • the through-hole conductors 20 - 1 of the through-hole conductors 20 formed on the silicon substrate 12 are conductors for signal supply and transmit a signal between a semiconductor chip (not shown) and a package substrate (not shown) as described later.
  • the through-hole conductors 20 - 2 are conductors for power supply, and the land portions of the through-hole conductors 20 - 2 extend to form, for example, the lower broad electrodes 18 .
  • the through-hole conductors 20 - 3 are conductors for ground (GND), and the land portions of the through-hole conductors 20 - 3 extend to form, for example, the upper broad electrodes 14 .
  • the upper electrodes 14 may be formed as the land portions of the through-hole conductors 20 - 2 for power supply, while the lower electrodes 18 may be formed as the land portions of the through-hole conductors 20 - 3 for GND.
  • the upper and lower electrodes 14 , 18 each are formed of an appropriate metal.
  • the upper electrodes 14 are formed of, for example, nickel (Ni)
  • the lower electrodes 18 are formed of, for examples, platinum (Pt), for convenience of production.
  • they may be formed of other metals.
  • the dielectric layer 16 is preferably composed of a high dielectric substance, for example, barium titanate (BaTiO 3 ) having ferroelectricity.
  • the upper electrodes 14 (the land portions of the through-hole conductors 20 - 3 for GND), the dielectric layer 16 , and the lower electrodes 18 (or the land portions of the through-hole conductors 20 - 2 for power supply) form capacitors 15 .
  • the interposer 10 shown in FIG. 1 is interposed between a semiconductor chip (not shown) and a package substrate (also referred to as a “mounting substrate”) (not shown).
  • the interposer 10 is located very near to the semiconductor chip and functions as a decoupling capacitor between a power supply and the ground to absorb noise.
  • a features of the interposer 10 shown in FIG. 1 are that only the through-hole conductors 20 and the dielectric layer 16 are formed on the silicon substrate 12 and that the land portions of the through-hole conductors 20 form the upper or lower electrodes 14 , 18 .
  • a wiring pattern that occupies the surface area of the silicon substrate 12 does not exist in the interposer 10 shown in FIG. 1 . Accordingly, the electrodes 14 , 18 of the capacitors can be spread out on the surface of the silicon substrate 12 to have a large area.
  • the dielectric layer 16 can be formed very thin since the gap between the upper electrode 14 and the lower electrode 18 can be formed very narrow.
  • a barium titanate (BaTIO 3 ) layer being of ferroelectricity can be employed as the dielectric layer 16 used for the interposer 10 shown in FIG. 1 .
  • the interposer 10 shown in FIG. 1 can form a capacitor (condenser) having a very large capacity by employing at least one of above described factors.
  • FIG. 2 is a sectional view showing another embodiment of main portion of an interposer according to this invention.
  • the capacitors 15 are formed in that the through-hole conductors 20 - 2 for power supply and the through-hole conductors 20 - 3 for ground are disposed on a central portion of the surface of the silicon substrate 12 and that these through-hole conductors 20 - 2 , 20 - 3 are surrounded by the through-hole conductors 20 - 1 for signal supply disposed on a peripheral region of the surface of the silicon substrate 12 .
  • the main portion of the interposer shown in FIG. 2 is different from that shown in FIG.
  • the through-hole conductors 20 - 2 for power supply and the through-hole conductors 20 - 3 for ground are disposed on the peripheral region of the surface of the silicon substrate 12 and the through-hole conductors 20 - 1 for signal are disposed to a central portion surrounded by these through-hole conductors 20 - 2 , 20 - 3 .
  • the land portions of the through-hole conductors 20 - 2 for power supply extend to form the broad upper electrodes 14 and are insulated from the lower electrodes 18 by gap 16 .
  • the through-hole conductors 20 - 1 for signal are insulated from the upper electrodes 14 by clearances 24 and are insulated from the lower electrodes 18 by the clearances 26 .
  • the land portions of the through-hole conductors 20 - 3 extend to form the lower electrodes 18 .
  • the through-hole conductors 20 - 1 , the through-hole conductors 20 - 2 , and the through-hole conductors 20 - 3 may be disposed in mixture.
  • FIG. 3 is a sectional view showing an actual arrangement of the interposer 10 .
  • the interposer 10 is interposed between an IC chip (IC) 40 and a package substrate (PK) 42 and is connected to the IC chip 40 through solder bumps 26 and to the package substrate 42 through solder bumps 30 , respectively, by soldering.
  • IC IC chip
  • PK package substrate
  • the interposer 10 shown in FIG. 3 includes an insulating resin layer 21 formed on the upper electrodes 14 , nickel (Ni) lands 24 - 1 connected to the through-hole conductor through openings of the insulating resin layer 21 , gold (Au) plated layers 24 - 2 overlaying the nickel lands 24 - 1 , the solder bumps 26 formed on the gold plated layers 24 - 2 , a solder resist layer 28 formed on the lower surface of the silicon substrate 12 , and the solder bumps 30 formed on land portions of the through-hole conductors 20 through openings of the solder resist layer 28 .
  • the interposer 10 shown in FIG. 3 possesses the same function and features as those of the interposer explained in relation to FIGS. 1 and 2 . That is, the interposer 10 is located very near to the semiconductor chip 40 so that it absorbs noise by functioning as a decoupling capacitor between a power supply and the ground.
  • the feature of the interposer 10 resides in the facts that: (1) since these exists no a wiring pattern that occupies the surface of the silicon substrate 12 , the electrodes 14 , 18 for capacitor (condenser) having large areas can be formed; (2) since the surface of the silicon substrate 12 is very flat and smooth, the gap between the upper electrodes 14 and the lower electrodes 18 can be narrowed; and (3) since ferroelectric dielectric substance can be employed for the dielectric layer 16 , the capacitor (condenser) having the greatly large capacity can be formed.
  • FIG. 4 is a sectional view showing an actual arrangement of another interposer 10 .
  • the arrangement of the interposer 10 shown in FIG. 4 is different from that of FIG. 3 in that wiring layers 23 - 1 , 23 - 2 are added.
  • the interposer 10 shown in FIG. 4 includes a lower interlayer insulating resin layer 21 - 1 on which the land portions of the through-hole conductor or the wiring patterns 23 - 1 are formed, and an upper interlayer insulating resin layer 21 - 2 on which the land portion of the through hole conductor portions or the wiring patterns 23 - 2 are formed.
  • the wiring patterns 23 - 1 , 23 - 2 are formed on the layers different from those of the capacitors 15 (i.e. on the interlayer insulating resin layers 21 - 1 , 21 - 2 ). That is, since no wiring pattern exists in the capacitors 15 formed by the upper electrodes 14 , the dielectric layer 16 , and the lower electrodes 18 , capacitor electrodes having a large area can be still formed.
  • the interposer 10 shown in FIG. 4 possesses the same function and features as those of the interposer explained in relation to FIGS. 1 and 3 . That is, the function of the interposer 10 shown in FIG. 4 is such that it is located very near to the semiconductor chip 40 to function as a decoupling capacitor between a power supply and the ground to absorb noise.
  • the features of the interposer 10 are as follows: Since no wiring pattern exists in the portions of the capacitors 15 , the electrodes for capacitors having a large area can be formed. Since the surface of the silicon substrate 12 is very flat and smooth, the space between the upper electrodes 14 and the lower electrodes 18 can be made very narrow. Since a ferroelectric substance can be utilized for the dielectric layer 16 , the capacitor (condenser) having the greatly large capacity can be formed.
  • the interposers 10 shown in FIGS. 2 and 3 can be manufactured as described, for example, below.
  • the silicon substrate 12 is prepared, the lower electrodes 18 are then formed by patterning on the silicon substrate 12 , the dielectric layer 16 is then formed on the lower electrode by sputtering and the like while controlling its thickness, and further the upper electrodes 14 are formed on the dielectric layer by patterning.
  • the lower and upper interlayer insulating resin layers 21 - 1 , 21 - 2 may be formed to form wiring layers. They are formed by a known buildup method. Further, openings are formed from the back surface of the silicon substrate 12 , and the through-hole conductors 20 are formed.
  • solder resists 28 , 38 may be formed by, for example, a screen printing.
  • the interposer 10 shown in FIG. 2 is interposed between the IC chip 40 and the package substrate 42 , and is connected to the both to form electronic device 70 that is composed of a combination of the semiconductor chip, the interposer, and the package substrate.
  • the electronic device 70 is formed by subjecting the solder bumps 26 , 30 to reflow and connecting the interposer 10 to the semiconductor chip 40 and the package substrate 42 , respectively, by soldering.
  • the interposer 10 is located in the vicinity of the semiconductor chip 40 and functions as the decoupling capacitor having a large capacity.
  • the interposer 10 shown in FIG. 3 is interposed between the IC chip 40 and the package substrate 42 to be connected to each other, and forms electronic device 70 that is composed of a combination of the semiconductor chip, the interposer, and the package substrate.
  • the electronic device 70 is formed by reflowing the solder bumps 26 , 30 to connect the interposer 10 to the IC chip 40 and the package substrate 42 , respectively, by soldering.
  • the interposer 10 is located in the vicinity of the semiconductor chip 40 and functions as a decoupling capacitor having a large capacity. Further, the interposer 10 shown in FIG. 4 also provides the wiring layers 23 - 1 , 23 - 2 between the IC chip 40 and the package substrate 42 .
  • interposers 10 possess the following features and advantages.
  • the electrodes for capacitor having a large area can be formed.
  • the dielectric layer 16 can be formed very thin, whereby the space between the upper electrodes 14 and the lower electrodes 18 can be formed very narrow.
  • a ferroelectric material for example, barium titanate (BaTiO 3 ), can be used for the dielectric layer 16 of the interposer 10 .
  • the interposer 10 can provide capacitors (condenser) having a very large capacity by employing at least one of the above factors.
  • the electronic devices according to the embodiments has the following features and advantages.
  • Noise can be absorbed by providing a decoupling capacitor having large capacity that is connected between the power supply and the ground at a position very near the semiconductor chip 40 in the devices composing the combination of the semiconductor chip 40 , the interposer 10 , and the package substrate 42 .
  • the wiring layers 23 - 1 , 23 - 2 can be also provided by using the interposer 10 explained in relation to FIG. 4 while providing the decoupling capacitor having the large capacity at the position very near the semiconductor chip 40 .

Abstract

A novel interposer(10) includes a silicon substrate(12), a plurality of through-hole conductors (20) formed on the silicon substrate, and capacitors (15) having of upper and lower electrodes (14,18) formed with land portions, respectively, of the through-hole conductors, and a dielectric layer (16) formed between both the electrodes. When desired, wiring pattern layers can be formed on a layer separate from the capacitors.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to an interposer and an electronic device using it, and, more particularly, to an interposer interposed between a semiconductor chip and a package substrate as well as to an electronic device composed of a combination of the semiconductor chip, the interposer, and the package substrate.
  • 2. Description of the Related Art
  • There is conventionally known an interposer utilizing a printed wiring board for carrying out wiring between a semiconductor chip and a package substrate. The interposer is a wiring device used to mutually connect a conductor circuit of a semiconductor chip which has an ultra dense pitch (for example, 50 μm) and a conductor circuit of a package substrate (also referred to as “mounting substrate”) which has a pitch more coarse than the above pitch (for example, 150 μm).
  • Recently, an example of an interposer including a capacitor is disclosed in Japanese Patent Laid-open Publication No. 2001-326305 entitled “Interposer for Semiconductor Device, Method of Manufacturing the Same, and Semiconductor Device (published on Nov. 22, 2001).
  • Claim 1 of the Laid-open publication states “An interposer for a semiconductor device having first electrodes, dielectric layers formed on the first electrodes, and second electrodes formed on the dielectric layer, characterized in that a necessary number of capacitors composed of the first electrodes, the dielectric layers, and the second electrodes are formed on the interposer”.
  • The Japanese Patent laid-open Publication describes “Further, since a wiring is carried out by a wiring pattern on the interposer, a fine pattern can be achieved. Accordingly, since the wiring is carried out on the interposer, it is possible to reduce one layer from the layers on a mounting substrate made by a multilayer board” (see paragraph 0006).
    • SUMMARY OF THE INVENTION
  • However, the inventor has found by his study carried out thereafter that various problems may arise when a capacitor and a wiring layer are formed together on the interposer as disclosed in the Japanese Patent laid-open Publication.
  • Accordingly, an object of the present invention is to provide a novel interposer and electronic device using it.
  • An interposer of the present invention comprises a capacitor formed on a generally entire surface of a substrate.
  • The interposer may comprise the substrate including a plurality of through-hole conductors; some of the through hole conductors that have land portions formed with an upper electrode of the capacitors; some of the remaining of the through-hole conductors that have land portions formed with a lower electrode of the capacitor; and a dielectric layer interposed between the upper electrodes and the lower electrodes.
  • In the interposer, some of the through-hole conductors may be formed as through-hole conductors for signal on a central portion of the surface of the substrate, and through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes may be formed surrounding the through-hole conductors for signal.
  • In the interposer, some of the through-hole conductors may be formed as through-hole conductors for signal on a peripheral region of the surface of the substrate, and through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes may be formed inside of the peripheral region.
  • The interposer may further comprise a wiring layer that is formed on at least one insulating layer disposed above the capacitors.
  • In the interposer, the substrate may be a silicon substrate.
  • In the interposer, the through-hole conductors may be made of copper.
  • In the interposer, the upper and lower electrodes may be made of nickel or platinum.
  • In the interposer, the dielectric layer may be made of a ferroelectric substance.
  • In the interposer, the dielectric layer may be made of barium titanate.
  • In the interposer, at least one surface of the interposer may be covered with a solder resist layer or an insulating resin layer.
  • An electronic device of the present invention comprises an IC chip; a package substrate; and an interposer, according to claim 1 or 2, interposed between the IC chip and the package substrate and electrically connected to the both, wherein the interposer provides capacitors.
  • According to the present invention, there are provided the novel interposer and the electronic device using it.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a sectional view showing a main portion of an embodiment of an interposer according to this invention;
  • FIG. 2 is a sectional view showing a main portion of another interposer according to this invention;
  • FIG. 3 is a sectional view showing an actual arrangement of the interposer; and
  • FIG. 4 is a sectional view showing an actual arrangement of the another interposer.
    •  DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Embodiments of novel interposers and electronic devices using the interposers according to the present invention will be explained below in detail with reference to the accompanying drawings. It should be understood that the embodiments are only exemplified and the present invention is not limited thereto. Also, note that, in the drawings, the same components are denoted by the same reference numerals to omit duplicate explanation.
    • [Interposer]
  • FIG. 1 is a sectional view showing an embodiment of a main portion of an interposer 10 according to this invention. The main portion of the interposer 10 includes through-hole conductors 20-1, 20-2, 20-3 formed on a silicon substrate 12, lower electrodes 18 formed on a surface of the silicon substrate 12, a dielectric layer 16 formed on the lower electrodes 18, and upper electrodes 14 formed on the dielectric layer 16.
  • When the surface of the silicon substrate 12 is properly polished, it has such a property that the surface is very flat and smooth. Alternatively a glass substrate and a polyimide substrate may be used in place of the silicon substrate when they satisfy the level of a surface flatness required in this embodiment.
  • The through-hole conductors 20-1 of the through-hole conductors 20 formed on the silicon substrate 12 are conductors for signal supply and transmit a signal between a semiconductor chip (not shown) and a package substrate (not shown) as described later. The through-hole conductors 20-2 are conductors for power supply, and the land portions of the through-hole conductors 20-2 extend to form, for example, the lower broad electrodes 18. The through-hole conductors 20-3 are conductors for ground (GND), and the land portions of the through-hole conductors 20-3 extend to form, for example, the upper broad electrodes 14.
  • Alternatively, the upper electrodes 14 may be formed as the land portions of the through-hole conductors 20-2 for power supply, while the lower electrodes 18 may be formed as the land portions of the through-hole conductors 20-3 for GND.
  • The upper and lower electrodes 14, 18 each are formed of an appropriate metal. In this embodiment the upper electrodes 14 are formed of, for example, nickel (Ni), and the lower electrodes 18 are formed of, for examples, platinum (Pt), for convenience of production. However, they may be formed of other metals.
  • The dielectric layer 16 is preferably composed of a high dielectric substance, for example, barium titanate (BaTiO3) having ferroelectricity.
  • Here, the upper electrodes 14 (the land portions of the through-hole conductors 20-3 for GND), the dielectric layer 16, and the lower electrodes 18 (or the land portions of the through-hole conductors 20-2 for power supply) form capacitors 15.
  • As described later, the interposer 10 shown in FIG. 1 is interposed between a semiconductor chip (not shown) and a package substrate (also referred to as a “mounting substrate”) (not shown). The interposer 10 is located very near to the semiconductor chip and functions as a decoupling capacitor between a power supply and the ground to absorb noise.
  • A features of the interposer 10 shown in FIG. 1 are that only the through-hole conductors 20 and the dielectric layer 16 are formed on the silicon substrate 12 and that the land portions of the through-hole conductors 20 form the upper or lower electrodes 14, 18. In other words, a wiring pattern that occupies the surface area of the silicon substrate 12 does not exist in the interposer 10 shown in FIG. 1. Accordingly, the electrodes 14, 18 of the capacitors can be spread out on the surface of the silicon substrate 12 to have a large area.
  • Further, since the silicon substrate 12 used for the interposer 10 shown in FIG. 1 has a very flat and smooth surface, the dielectric layer 16 can be formed very thin since the gap between the upper electrode 14 and the lower electrode 18 can be formed very narrow.
  • Further, a barium titanate (BaTIO3) layer being of ferroelectricity can be employed as the dielectric layer 16 used for the interposer 10 shown in FIG. 1.
  • The interposer 10 shown in FIG. 1 can form a capacitor (condenser) having a very large capacity by employing at least one of above described factors.
  • FIG. 2 is a sectional view showing another embodiment of main portion of an interposer according to this invention. On the main portion of the interposer shown in FIG. 1, the capacitors 15 are formed in that the through-hole conductors 20-2 for power supply and the through-hole conductors 20-3 for ground are disposed on a central portion of the surface of the silicon substrate 12 and that these through-hole conductors 20-2, 20-3 are surrounded by the through-hole conductors 20-1 for signal supply disposed on a peripheral region of the surface of the silicon substrate 12. In contrast, the main portion of the interposer shown in FIG. 2 is different from that shown in FIG. 1 in that the through-hole conductors 20-2 for power supply and the through-hole conductors 20-3 for ground are disposed on the peripheral region of the surface of the silicon substrate 12 and the through-hole conductors 20-1 for signal are disposed to a central portion surrounded by these through-hole conductors 20-2, 20-3.
  • As shown in FIG. 2, the land portions of the through-hole conductors 20-2 for power supply extend to form the broad upper electrodes 14 and are insulated from the lower electrodes 18 by gap 16. The through-hole conductors 20-1 for signal are insulated from the upper electrodes 14 by clearances 24 and are insulated from the lower electrodes 18 by the clearances 26. The land portions of the through-hole conductors 20-3 extend to form the lower electrodes 18.
  • Alternatively, the through-hole conductors 20-1, the through-hole conductors 20-2, and the through-hole conductors 20-3 may be disposed in mixture.
  • FIG. 3 is a sectional view showing an actual arrangement of the interposer 10. The interposer 10 is interposed between an IC chip (IC) 40 and a package substrate (PK) 42 and is connected to the IC chip 40 through solder bumps 26 and to the package substrate 42 through solder bumps 30, respectively, by soldering.
  • In addition to the upper electrodes 14, the dielectric layer 16, the lower electrodes 18, the silicon substrate 12, and the through-hole conductors 20 explained in relation to FIGS. 1 and 2, the interposer 10 shown in FIG. 3 includes an insulating resin layer 21 formed on the upper electrodes 14, nickel (Ni) lands 24-1 connected to the through-hole conductor through openings of the insulating resin layer 21, gold (Au) plated layers 24-2 overlaying the nickel lands 24-1, the solder bumps 26 formed on the gold plated layers 24-2, a solder resist layer 28 formed on the lower surface of the silicon substrate 12, and the solder bumps 30 formed on land portions of the through-hole conductors 20 through openings of the solder resist layer 28.
  • The interposer 10 shown in FIG. 3 possesses the same function and features as those of the interposer explained in relation to FIGS. 1 and 2. That is, the interposer 10 is located very near to the semiconductor chip 40 so that it absorbs noise by functioning as a decoupling capacitor between a power supply and the ground. The feature of the interposer 10 resides in the facts that: (1) since these exists no a wiring pattern that occupies the surface of the silicon substrate 12, the electrodes 14, 18 for capacitor (condenser) having large areas can be formed; (2) since the surface of the silicon substrate 12 is very flat and smooth, the gap between the upper electrodes 14 and the lower electrodes 18 can be narrowed; and (3) since ferroelectric dielectric substance can be employed for the dielectric layer 16, the capacitor (condenser) having the greatly large capacity can be formed.
  • FIG. 4 is a sectional view showing an actual arrangement of another interposer 10. The arrangement of the interposer 10 shown in FIG. 4 is different from that of FIG. 3 in that wiring layers 23-1, 23-2 are added.
  • In addition to the upper electrodes 14, the dielectric layer 16, the lower electrodes 18, the silicon substrate 12, the through-hole conductors 20, the solder bumps 26, the solder resist layer 28, and the solder bumps 30 explained in relation to FIG. 3, the interposer 10 shown in FIG. 4 includes a lower interlayer insulating resin layer 21-1 on which the land portions of the through-hole conductor or the wiring patterns 23-1 are formed, and an upper interlayer insulating resin layer 21-2 on which the land portion of the through hole conductor portions or the wiring patterns 23-2 are formed.
  • However, the wiring patterns 23-1, 23-2 are formed on the layers different from those of the capacitors 15 (i.e. on the interlayer insulating resin layers 21-1, 21-2). That is, since no wiring pattern exists in the capacitors 15 formed by the upper electrodes 14, the dielectric layer 16, and the lower electrodes 18, capacitor electrodes having a large area can be still formed.
  • Accordingly, the interposer 10 shown in FIG. 4 possesses the same function and features as those of the interposer explained in relation to FIGS. 1 and 3. That is, the function of the interposer 10 shown in FIG. 4 is such that it is located very near to the semiconductor chip 40 to function as a decoupling capacitor between a power supply and the ground to absorb noise. The features of the interposer 10 are as follows: Since no wiring pattern exists in the portions of the capacitors 15, the electrodes for capacitors having a large area can be formed. Since the surface of the silicon substrate 12 is very flat and smooth, the space between the upper electrodes 14 and the lower electrodes 18 can be made very narrow. Since a ferroelectric substance can be utilized for the dielectric layer 16, the capacitor (condenser) having the greatly large capacity can be formed.
    • (Manufacturing Method)
  • Although a method of manufacturing the interposers 10 shown in FIGS. 2 and 3 is not shown, they can be manufactured as described, for example, below. First, the silicon substrate 12 is prepared, the lower electrodes 18 are then formed by patterning on the silicon substrate 12, the dielectric layer 16 is then formed on the lower electrode by sputtering and the like while controlling its thickness, and further the upper electrodes 14 are formed on the dielectric layer by patterning. When desired, the lower and upper interlayer insulating resin layers 21-1, 21-2 may be formed to form wiring layers. They are formed by a known buildup method. Further, openings are formed from the back surface of the silicon substrate 12, and the through-hole conductors 20 are formed. When desired, solder resists 28, 38 may be formed by, for example, a screen printing.
    • [Electronic Device Using Interposer]
  • The interposer 10 shown in FIG. 2 is interposed between the IC chip 40 and the package substrate 42, and is connected to the both to form electronic device 70 that is composed of a combination of the semiconductor chip, the interposer, and the package substrate.
  • After the interposer 10 is manufactured, the electronic device 70 is formed by subjecting the solder bumps 26, 30 to reflow and connecting the interposer 10 to the semiconductor chip 40 and the package substrate 42, respectively, by soldering. The interposer 10 is located in the vicinity of the semiconductor chip 40 and functions as the decoupling capacitor having a large capacity.
  • The interposer 10 shown in FIG. 3 is interposed between the IC chip 40 and the package substrate 42 to be connected to each other, and forms electronic device 70 that is composed of a combination of the semiconductor chip, the interposer, and the package substrate. After the interposer 10 is manufactured, the electronic device 70 is formed by reflowing the solder bumps 26, 30 to connect the interposer 10 to the IC chip 40 and the package substrate 42, respectively, by soldering. The interposer 10 is located in the vicinity of the semiconductor chip 40 and functions as a decoupling capacitor having a large capacity. Further, the interposer 10 shown in FIG. 4 also provides the wiring layers 23-1, 23-2 between the IC chip 40 and the package substrate 42.
    • Features, Advantages, and the Like of the Embodiments
  • The interposers 10 according to the embodiments possess the following features and advantages.
  • (1) Because of no wiring pattern that occupies the surface of the silicon substrate 12, the electrodes for capacitor having a large area can be formed.
  • (2) Since the silicon substrate 12 has very flat and smooth surface, the dielectric layer 16 can be formed very thin, whereby the space between the upper electrodes 14 and the lower electrodes 18 can be formed very narrow.
  • (3) A ferroelectric material, for example, barium titanate (BaTiO3), can be used for the dielectric layer 16 of the interposer 10.
  • (4) The interposer 10 can provide capacitors (condenser) having a very large capacity by employing at least one of the above factors.
  • The electronic devices according to the embodiments has the following features and advantages.
  • (1) Noise can be absorbed by providing a decoupling capacitor having large capacity that is connected between the power supply and the ground at a position very near the semiconductor chip 40 in the devices composing the combination of the semiconductor chip 40, the interposer 10, and the package substrate 42.
  • (2) The wiring layers 23-1, 23-2 can be also provided by using the interposer 10 explained in relation to FIG. 4 while providing the decoupling capacitor having the large capacity at the position very near the semiconductor chip 40.
    • [Others]
  • The embodiments of the interposers and the electronic devices making use of the interposers according to the present invention have been explained above. It should be noted that they are only examples, and the present invention is not limited thereto.
  • The technical scope of the present invention should be determined according to the description of the accompanying claims.

Claims (12)

1. An interposer comprising a capacitor formed on a generally entire surface of a substrate.
2. The interposer according to claim 1, comprising:
the substrate including a plurality of through-hole conductors;
some of the through hole conductors that have land portions formed with an upper electrode of the capacitors;
some of the remaining of the through-hole conductors that have land portions formed with a lower electrode of the capacitor; and
a dielectric layer interposed between the upper electrodes and the lower electrodes.
3. The interposer according to claim 2, wherein
some of the through-hole conductors are formed as through-hole conductors for signal on a central portion of the surface of the substrate, and
through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes are formed surrounding the through-hole conductors for signal.
4. The interposer according to claim 2, wherein
some of the through-hole conductors are formed as through-hole conductors for signal on a peripheral region of the surface of the substrate, and
through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes are formed inside of the peripheral region of the surface of the substrate.
5. The interposer according to claim 1 or 2, further comprising a wiring layer that is formed on at least one insulating layer disposed above the capacitors.
6. The interposer according to claim 1 or 2, wherein the substrate is a silicon substrate.
7. The interposer according to claim 1 or 2, wherein the through-hole conductors are made of copper.
8. The interposer according to claim 1 or 2, wherein the upper and lower electrodes are made of nickel or platinum.
9. The interposer according to claim 1 or 2, wherein the dielectric layer is made of a ferroelectric substance.
10. The interposer according to claim 1 or 2, wherein the dielectric layer is made of barium titanate.
11. The interposer according to claim 1 or 2, wherein at least one surface of the interposer is covered with a solder resist layer or an insulating resin layer.
12. An electronic device comprising
an IC chip;
a package substrate; and
an interposer, according to claim 1 or 2, interposed between the IC chip and the package substrate and electrically connected to the both,
wherein the interposer provides capacitors.
US11/491,288 2006-07-24 2006-07-24 Interposer and electronic device using the same Abandoned US20080017407A1 (en)

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US11/491,288 US20080017407A1 (en) 2006-07-24 2006-07-24 Interposer and electronic device using the same
JP2008509262A JPWO2008013054A1 (en) 2006-07-24 2007-07-10 Interposer and electronic equipment using the same
PCT/JP2007/063757 WO2008013054A1 (en) 2006-07-24 2007-07-10 Interposer and electronic device using the same
EP07790575A EP1928022A1 (en) 2006-07-24 2007-07-10 Interposer and electronic device using the same
CN2007800024254A CN101371355B (en) 2006-07-24 2007-07-10 Interposer and electronic device using the same and their production method
KR1020087009227A KR100977436B1 (en) 2006-07-24 2007-07-10 Interposer and electronic device using the same
TW096126344A TWI360210B (en) 2006-07-24 2007-07-19 Interposer and electronic device using the same
US11/860,132 US8149585B2 (en) 2006-07-24 2007-09-24 Interposer and electronic device using the same

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Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060281292A1 (en) * 2005-06-14 2006-12-14 John Trezza Rigid-backed, membrane-based chip tooling
US20060278981A1 (en) * 2005-06-14 2006-12-14 John Trezza Electronic chip contact structure
US20060278996A1 (en) * 2005-06-14 2006-12-14 John Trezza Active packaging
US20060281363A1 (en) * 2005-06-14 2006-12-14 John Trezza Remote chip attachment
US20060281296A1 (en) * 2005-06-14 2006-12-14 Abhay Misra Routingless chip architecture
US20070158839A1 (en) * 2005-06-14 2007-07-12 John Trezza Thermally balanced via
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
US20080062665A1 (en) * 2006-09-12 2008-03-13 Tetsuya Nakatsuka Mounting structure
US20080253097A1 (en) * 2007-04-10 2008-10-16 Ibiden Co., Ltd Interposer
US20080291649A1 (en) * 2006-08-10 2008-11-27 Shinko Electric Industries Co., Ltd. Capacitor built-in substrate and method of manufacturing the same and electronic component device
US20090174079A1 (en) * 2007-02-16 2009-07-09 John Trezza Plated pillar package formation
US20090269888A1 (en) * 2005-06-14 2009-10-29 John Trezza Chip-based thermo-stack
US20100140776A1 (en) * 2005-06-14 2010-06-10 John Trezza Triaxial through-chip connecton
US20100148343A1 (en) * 2005-06-14 2010-06-17 John Trezza Side stacking apparatus and method
US20100290201A1 (en) * 2009-05-13 2010-11-18 Hitoshi Takeuchi Electronic component, manufacturing method for electronic component, and electronic device
US20110037489A1 (en) * 2009-08-13 2011-02-17 International Business Machines Corporation Silicon chicklet pedestal
US20110075393A1 (en) * 2009-09-28 2011-03-31 Qualcomm Incorporated Semiconductor Die-Based Packaging Interconnect
US8053903B2 (en) 2005-06-14 2011-11-08 Cufer Asset Ltd. L.L.C. Chip capacitive coupling
US20130032390A1 (en) * 2011-08-05 2013-02-07 Industrial Technology Research Institute Packaging substrate having embedded interposer and fabrication method thereof
US20140167239A1 (en) * 2012-12-14 2014-06-19 Samsung Electro-Mechanics Co., Ltd. Power module package
CN104465570A (en) * 2014-12-31 2015-03-25 江阴长电先进封装有限公司 TSV Interposer structure and packaging method thereof
US11259401B2 (en) * 2017-11-16 2022-02-22 Murata Manufacturing Co., Ltd. Resin multilayer substrate, electronic component, and mounting structure thereof
US20220189864A1 (en) * 2014-05-24 2022-06-16 Broadpak Corporation 3d integrations and methods of making thereof

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4980419B2 (en) 2007-04-18 2012-07-18 イビデン株式会社 Multilayer printed wiring board and manufacturing method thereof
US20090224410A1 (en) * 2008-03-07 2009-09-10 Advanced Inquiry Systems, Inc. Wafer translator having a silicon core fabricated with printed circuit board manufacturing techniques
US7791174B2 (en) * 2008-03-07 2010-09-07 Advanced Inquiry Systems, Inc. Wafer translator having a silicon core isolated from signal paths by a ground plane
JP2009224492A (en) * 2008-03-14 2009-10-01 Oki Semiconductor Co Ltd Semiconductor device and method of manufacturing the same
JP5138459B2 (en) * 2008-05-15 2013-02-06 新光電気工業株式会社 Wiring board manufacturing method
KR101010672B1 (en) * 2008-12-01 2011-01-24 윌테크놀러지(주) Interposer unit and manufacturing method for the same
KR101060862B1 (en) 2009-09-14 2011-08-31 삼성전기주식회사 Interposer and manufacturing method thereof
JP2011082450A (en) 2009-10-09 2011-04-21 Elpida Memory Inc Semiconductor device, and information processing system with the same
JP5569840B2 (en) * 2010-06-24 2014-08-13 学校法人福岡大学 Wiring board forming method and wiring board
US8884431B2 (en) * 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9449941B2 (en) 2011-07-07 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting function chips to a package to form package-on-package
US8748284B2 (en) 2011-08-12 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing decoupling MIM capacitor designs for interposers
US9093396B2 (en) * 2011-10-31 2015-07-28 Masahiro Lee Silicon interposer systems
KR101225451B1 (en) * 2012-03-27 2013-01-24 (주) 이피웍스 A general purpose silicon interposer having through silicon via and method for application using the same
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
JP6105209B2 (en) * 2012-04-25 2017-03-29 京セラ株式会社 Wiring board and mounting structure using the same
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
JP5531122B1 (en) * 2013-01-25 2014-06-25 株式会社野田スクリーン Semiconductor device
US9105629B2 (en) * 2013-03-07 2015-08-11 International Business Machines Corporation Selective area heating for 3D chip stack
KR102079283B1 (en) 2013-10-15 2020-02-19 삼성전자 주식회사 Integrated circuit device having through-silicon via structure and method of manufacturing the same
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
JP5686211B2 (en) * 2014-03-10 2015-03-18 大日本印刷株式会社 Component built-in wiring board
KR102368070B1 (en) 2015-04-13 2022-02-25 삼성전자주식회사 Semiconductor package
CN105390480B (en) * 2015-10-23 2017-11-28 西安理工大学 Three-dimensional high level integrated capacitor based on silicon hole array and preparation method thereof
JP2016106427A (en) * 2016-03-03 2016-06-16 京セラサーキットソリューションズ株式会社 Wiring board manufacturing method and package structure manufacturing method
JP6750462B2 (en) 2016-11-04 2020-09-02 Tdk株式会社 Substrate with built-in thin film capacitors and electronic components
WO2020185016A1 (en) 2019-03-12 2020-09-17 에스케이씨 주식회사 Packaging substrate and semiconductor device comprising same
JP7087205B2 (en) 2019-03-29 2022-06-20 アブソリックス インコーポレイテッド Packaging glass substrate for semiconductors, packaging substrate for semiconductors and semiconductor devices
CN113366633B (en) * 2019-08-23 2022-07-12 爱玻索立克公司 Package substrate and semiconductor device including the same
JP2022161248A (en) * 2021-04-08 2022-10-21 イビデン株式会社 Printed wiring board and manufacturing method therefor
JP2022161250A (en) * 2021-04-08 2022-10-21 イビデン株式会社 Printed wiring board and manufacturing method for printed wiring board

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6507497B2 (en) * 2000-05-12 2003-01-14 Shinko Electric Industries, Co., Ltd. Interposer for semiconductor, method for manufacturing the same and semiconductor device using such interposer
US6791035B2 (en) * 2002-02-21 2004-09-14 Intel Corporation Interposer to couple a microelectronic device package to a circuit board
US6794729B2 (en) * 2001-03-01 2004-09-21 Nec Corporation Stacked capacitor and method of forming the same as well as semiconductor device using the same and circuit board using the same
US7209366B2 (en) * 2004-03-19 2007-04-24 Intel Corporation Delivery regions for power, ground and I/O signal paths in an IC package
US7388293B2 (en) * 2004-06-30 2008-06-17 Shinko Electric Industries, Co. Interposer method of fabricating same, and semiconductor device using the same having two portions with different constructions

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5177670A (en) * 1991-02-08 1993-01-05 Hitachi, Ltd. Capacitor-carrying semiconductor module
US6052287A (en) * 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
JP4479015B2 (en) * 1999-06-10 2010-06-09 パナソニック株式会社 Carrier substrate with built-in capacitor and method for manufacturing the same
US7095619B2 (en) * 2002-02-25 2006-08-22 Molex Incorporated Power delivery to base of processor
US6791133B2 (en) * 2002-07-19 2004-09-14 International Business Machines Corporation Interposer capacitor built on silicon wafer and joined to a ceramic substrate
CN100477180C (en) * 2003-09-24 2009-04-08 揖斐电株式会社 Relay base plate and multilayer printed wiring board
US7265995B2 (en) * 2003-12-29 2007-09-04 Intel Corporation Array capacitors with voids to enable a full-grid socket
JP2005310814A (en) * 2004-04-16 2005-11-04 Alps Electric Co Ltd Substrate with built-in capacitor
TWI264257B (en) * 2004-11-24 2006-10-11 Via Tech Inc Signal transmission structure and circuit substrate thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6507497B2 (en) * 2000-05-12 2003-01-14 Shinko Electric Industries, Co., Ltd. Interposer for semiconductor, method for manufacturing the same and semiconductor device using such interposer
US6794729B2 (en) * 2001-03-01 2004-09-21 Nec Corporation Stacked capacitor and method of forming the same as well as semiconductor device using the same and circuit board using the same
US6791035B2 (en) * 2002-02-21 2004-09-14 Intel Corporation Interposer to couple a microelectronic device package to a circuit board
US7209366B2 (en) * 2004-03-19 2007-04-24 Intel Corporation Delivery regions for power, ground and I/O signal paths in an IC package
US7388293B2 (en) * 2004-06-30 2008-06-17 Shinko Electric Industries, Co. Interposer method of fabricating same, and semiconductor device using the same having two portions with different constructions

Cited By (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100197134A1 (en) * 2005-06-14 2010-08-05 John Trezza Coaxial through chip connection
US20060278996A1 (en) * 2005-06-14 2006-12-14 John Trezza Active packaging
US20060278331A1 (en) * 2005-06-14 2006-12-14 Roger Dugas Membrane-based chip tooling
US20060278980A1 (en) * 2005-06-14 2006-12-14 John Trezza Patterned contact
US20060278993A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip connector
US20060278994A1 (en) * 2005-06-14 2006-12-14 John Trezza Inverse chip connector
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US20060281363A1 (en) * 2005-06-14 2006-12-14 John Trezza Remote chip attachment
US20060278988A1 (en) * 2005-06-14 2006-12-14 John Trezza Profiled contact
US20060281296A1 (en) * 2005-06-14 2006-12-14 Abhay Misra Routingless chip architecture
US20070120241A1 (en) * 2005-06-14 2007-05-31 John Trezza Pin-type chip tooling
US20070138562A1 (en) * 2005-06-14 2007-06-21 Cubic Wafer, Inc. Coaxial through chip connection
US20070158839A1 (en) * 2005-06-14 2007-07-12 John Trezza Thermally balanced via
US20070172987A1 (en) * 2005-06-14 2007-07-26 Roger Dugas Membrane-based chip tooling
US20070182020A1 (en) * 2005-06-14 2007-08-09 John Trezza Chip connector
US20070196948A1 (en) * 2005-06-14 2007-08-23 John Trezza Stacked chip-based system and method
US20070228576A1 (en) * 2005-06-14 2007-10-04 John Trezza Isolating chip-to-chip contact
US8093729B2 (en) 2005-06-14 2012-01-10 Cufer Asset Ltd. L.L.C. Electrically conductive interconnect system and method
US10340239B2 (en) 2005-06-14 2019-07-02 Cufer Asset Ltd. L.L.C Tooling for coupling multiple electronic chips
US7785987B2 (en) 2005-06-14 2010-08-31 John Trezza Isolating chip-to-chip contact
US9754907B2 (en) 2005-06-14 2017-09-05 Cufer Asset Ltd. L.L.C. Tooling for coupling multiple electronic chips
US20060281292A1 (en) * 2005-06-14 2006-12-14 John Trezza Rigid-backed, membrane-based chip tooling
US20090137116A1 (en) * 2005-06-14 2009-05-28 Cufer Asset Ltd. L.L.C. Isolating chip-to-chip contact
US9324629B2 (en) 2005-06-14 2016-04-26 Cufer Asset Ltd. L.L.C. Tooling for coupling multiple electronic chips
US9147635B2 (en) 2005-06-14 2015-09-29 Cufer Asset Ltd. L.L.C. Contact-based encapsulation
US20090269888A1 (en) * 2005-06-14 2009-10-29 John Trezza Chip-based thermo-stack
US20100140776A1 (en) * 2005-06-14 2010-06-10 John Trezza Triaxial through-chip connecton
US20100148343A1 (en) * 2005-06-14 2010-06-17 John Trezza Side stacking apparatus and method
US8154131B2 (en) 2005-06-14 2012-04-10 Cufer Asset Ltd. L.L.C. Profiled contact
US20060278981A1 (en) * 2005-06-14 2006-12-14 John Trezza Electronic chip contact structure
US20080171174A1 (en) * 2005-06-14 2008-07-17 John Trezza Electrically conductive interconnect system and method
US7785931B2 (en) 2005-06-14 2010-08-31 John Trezza Chip-based thermo-stack
US7808111B2 (en) 2005-06-14 2010-10-05 John Trezza Processed wafer via
US20100261297A1 (en) * 2005-06-14 2010-10-14 John Trezza Remote chip attachment
US8846445B2 (en) 2005-06-14 2014-09-30 Cufer Asset Ltd. L.L.C. Inverse chip connector
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7847412B2 (en) 2005-06-14 2010-12-07 John Trezza Isolating chip-to-chip contact
US7851348B2 (en) 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US7884483B2 (en) 2005-06-14 2011-02-08 Cufer Asset Ltd. L.L.C. Chip connector
US8643186B2 (en) 2005-06-14 2014-02-04 Cufer Asset Ltd. L.L.C. Processed wafer via
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7919870B2 (en) 2005-06-14 2011-04-05 Cufer Asset Ltd. L.L.C. Coaxial through chip connection
US7932584B2 (en) 2005-06-14 2011-04-26 Cufer Asset Ltd. L.L.C. Stacked chip-based system and method
US8283778B2 (en) 2005-06-14 2012-10-09 Cufer Asset Ltd. L.L.C. Thermally balanced via
US7942182B2 (en) 2005-06-14 2011-05-17 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
US7946331B2 (en) 2005-06-14 2011-05-24 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US7969015B2 (en) 2005-06-14 2011-06-28 Cufer Asset Ltd. L.L.C. Inverse chip connector
US7989958B2 (en) 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
US8232194B2 (en) 2005-06-14 2012-07-31 Cufer Asset Ltd. L.L.C. Process for chip capacitive coupling
US8197626B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
US8197627B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US20110212573A1 (en) * 2005-06-14 2011-09-01 John Trezza Rigid-backed, membrane-based chip tooling
US8021922B2 (en) 2005-06-14 2011-09-20 Cufer Asset Ltd. L.L.C. Remote chip attachment
US8053903B2 (en) 2005-06-14 2011-11-08 Cufer Asset Ltd. L.L.C. Chip capacitive coupling
US8067312B2 (en) 2005-06-14 2011-11-29 Cufer Asset Ltd. L.L.C. Coaxial through chip connection
US8084851B2 (en) 2005-06-14 2011-12-27 Cufer Asset Ltd. L.L.C. Side stacking apparatus and method
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
US20080291649A1 (en) * 2006-08-10 2008-11-27 Shinko Electric Industries Co., Ltd. Capacitor built-in substrate and method of manufacturing the same and electronic component device
US7936568B2 (en) * 2006-08-10 2011-05-03 Shinko Electric Industries Co., Ltd. Capacitor built-in substrate and method of manufacturing the same and electronic component device
US20080062665A1 (en) * 2006-09-12 2008-03-13 Tetsuya Nakatsuka Mounting structure
US20090174079A1 (en) * 2007-02-16 2009-07-09 John Trezza Plated pillar package formation
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
US20080253097A1 (en) * 2007-04-10 2008-10-16 Ibiden Co., Ltd Interposer
US8441799B2 (en) * 2009-05-13 2013-05-14 Seiko Instruments Inc. Electronic component and electronic device
US20100290201A1 (en) * 2009-05-13 2010-11-18 Hitoshi Takeuchi Electronic component, manufacturing method for electronic component, and electronic device
US20110199108A1 (en) * 2009-08-13 2011-08-18 International Business Machines Corporation Silicon chicklet pedestal
US7987591B2 (en) * 2009-08-13 2011-08-02 International Business Machines Corporation Method of forming silicon chicklet pedestal
US8595919B2 (en) 2009-08-13 2013-12-03 International Business Machines Corporation Silicon chicklet pedestal
US20110037489A1 (en) * 2009-08-13 2011-02-17 International Business Machines Corporation Silicon chicklet pedestal
US20110199109A1 (en) * 2009-08-13 2011-08-18 International Business Machines Corporation Silicon chicklet pedestal
US8806740B2 (en) 2009-08-13 2014-08-19 International Business Machines Corporation Silicon chicklet pedestal
US8391018B2 (en) * 2009-09-28 2013-03-05 Qualcomm Incorporated Semiconductor die-based packaging interconnect
US20110075393A1 (en) * 2009-09-28 2011-03-31 Qualcomm Incorporated Semiconductor Die-Based Packaging Interconnect
US9385056B2 (en) * 2011-08-05 2016-07-05 Unimicron Technology Corporation Packaging substrate having embedded interposer and fabrication method thereof
US20130032390A1 (en) * 2011-08-05 2013-02-07 Industrial Technology Research Institute Packaging substrate having embedded interposer and fabrication method thereof
US9105601B2 (en) * 2012-12-14 2015-08-11 Samsung Electro-Mechanics Co., Ltd. Power module package
US20140167239A1 (en) * 2012-12-14 2014-06-19 Samsung Electro-Mechanics Co., Ltd. Power module package
US20220189864A1 (en) * 2014-05-24 2022-06-16 Broadpak Corporation 3d integrations and methods of making thereof
CN104465570A (en) * 2014-12-31 2015-03-25 江阴长电先进封装有限公司 TSV Interposer structure and packaging method thereof
US11259401B2 (en) * 2017-11-16 2022-02-22 Murata Manufacturing Co., Ltd. Resin multilayer substrate, electronic component, and mounting structure thereof

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US20080142976A1 (en) 2008-06-19

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