Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20070254406 A1
Publication typeApplication
Application numberUS 11/819,624
Publication date1 Nov 2007
Filing date28 Jun 2007
Priority date24 Apr 2006
Also published asUS7242081
Publication number11819624, 819624, US 2007/0254406 A1, US 2007/254406 A1, US 20070254406 A1, US 20070254406A1, US 2007254406 A1, US 2007254406A1, US-A1-20070254406, US-A1-2007254406, US2007/0254406A1, US2007/254406A1, US20070254406 A1, US20070254406A1, US2007254406 A1, US2007254406A1
InventorsYonggill Lee
Original AssigneeAdvanced Semiconductor Engineering Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for manufacturing stacked package structure
US 20070254406 A1
Abstract
A method for manufacturing a stacked package structure is disclosed, comprising: forming a first chip package structure, comprising: providing a chip carrier having a first and a second surface in opposition to each other; forming bonding wires on the first surface; providing at least one chip on and electrically connected to the first surface; and forming an encapsulant covering the first surface, the chip and the bonding wires, wherein a top end of each bonding wire is exposed at a surface of the encapsulant; forming a plurality of electrical connections respectively deposed on the top end of each bonding wire; and providing a second chip structure electrically jointed with the electrical connections and stacked on the first chip package structure.
Images(12)
Previous page
Next page
Claims(13)
1. A method for manufacturing a stacked package structure, comprising:
forming a first chip package structure, comprising:
providing a first chip carrier having a first surface and a second surface in opposition to each other;
forming a plurality of bonding wires on the first surface of the first chip carrier;
providing at least one first chip on and electrically connected to the first surface of the first chip carrier, wherein each bonding wire is higher than the at least one first chip in altitude; and
forming an encapsulant covering the first surface of the first chip carrier, the at least one first chip and the bonding wires, wherein at least one top end of each bonding wire is exposed at a surface of the encapsulant; and
providing a second chip package structure electrically connected to and stacked on the first chip package structure.
2. The method for manufacturing a stacked package structure according to claim 1, wherein before providing the second chip package structure, forming a plurality of first electrical connections respectively deposed on the top end of each bonding wire, so that the second chip package structure is electrically connected to the first chip package structure via the first electrical connections.
3. The method for manufacturing a stacked package structure according to claim 1, wherein the step of forming the encapsulant comprises:
providing an encapsulant material layer to cover the first surface of the first chip carrier, the at least one first chip and the bonding wires; and
performing a grinding step to remove a portion of the encapsulant material layer, until the top end of each bonding wire is exposed.
4. The method for manufacturing a stacked package structure according to claim 3, wherein the grinding step is a mechanical grinding step or a chemical grinding step.
5. The method for manufacturing a stacked package structure according to claim 2, wherein the step of forming the first chip package structure further comprises forming a plurality of second electrical connections respectively deposed on the second surface of the first chip carrier.
6. The method for manufacturing a stacked package structure according to claim 1, wherein a material of the bonding wires is selected from the group consisting of Cu, Al, Au, Sn and an alloy thereof.
7. The method for manufacturing a stacked package structure according to claim 2, wherein the step of forming the first electrical connections is performed by a direct ball attach method, a screen print method, an electro plating method or an electroless plating method.
8. The method for manufacturing a stacked package structure according to claim 1, wherein before the step of forming the encapsulant, the step of forming the first chip package structure further comprises forming at least one passive device on the first surface of the first chip carrier.
9. The method for manufacturing a stacked package structure according to claim 1, wherein the step of providing the second chip structure comprises:
providing a second chip carrier having a first surface and a second surface in opposition to each other;
forming a plurality of electrical connection devices on the first surface of the second chip carrier;
providing at least one second chip on and electrically connected to the first surface of the second chip carrier, wherein each electrical connection device is higher than the at least one second chip in altitude; and
forming another encapsulant covering the first surface of the second chip carrier, the at least one second chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the another encapsulant.
10. The method for manufacturing a stacked package structure according to claim 9, wherein the step of forming the another encapsulant comprises:
providing an encapsulant material layer to cover the first surface of the second chip carrier, the at least one second chip and the electrical connection devices; and
performing a grinding step to remove a portion of the encapsulant material layer, until the top end of each electrical connection device is exposed.
11. The method for manufacturing a stacked package structure according to claim 9, wherein the electrical connection devices are selected from the group consisting of bonding wires, conductive studs, pins, electronic components and any combination thereof.
12. The method for manufacturing a stacked package structure according to claim 1, wherein the chip carrier is a substrate or a leadframe.
13. The method for manufacturing a stacked package structure according to claim 2, wherein the first electrical connections are connection bumps or balls.
Description
    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application is a continuation-in-part of U.S. application Ser. No. 11/409,933, filed on Apr. 24, 2006, hereby incorporated by reference as it fully set forth herein.
  • FIELD OF THE INVENTION
  • [0002]
    The present invention relates to a system-in-package (SiP) structure and a method for manufacturing the same, and more particularly, to a stacked package structure and a method for manufacturing the same.
  • BACKGROUND OF THE INVENTION
  • [0003]
    The demand for low cost, small size, and more functionality has become the main driving force in the electronic industry. To achieve such goals, advanced packaging techniques like flip chip, chip scale package, wafer level packaging, and 3D packages have been developed. The 3D packaging technique is developed to integrate dies, packages and passive components into one package, in other words, to achieve system in a package solution. The integration can be made in side-by-side, stacked, or both manners. The outstanding advantages of 3D package are small footprint, high performance and low cost.
  • [0004]
    FIGS. 1 to 3 are schematic flow diagrams showing the process for manufacturing a conventional stacked package structure. In the fabrication of a conventional stacked package structure 250, a chip package structure 100 is firstly provided typically, in which the chip package structure 100 is generally a chip scale package (CSP). The chip package structure 100 mainly includes a substrate 102, a chip 104, an encapsulant 108 and solder balls 110, such as shown in FIG. 1. The chip 104 is attached on a top surface 112 of the substrate 102, and is electrically connected to pads (not shown) of the substrate 102 by wires 106. The encapsulant 108 is formed on the top surface 112 of the substrate 102 and fully covers the chip 104, the wires 106 and the top surface 112 of the substrate 102. The solder balls 110 are set on the outer portion of a bottom surface 114 of the substrate 102, in which the solder balls 110 are electrically connected to the chip 104.
  • [0005]
    Next, another chip package structure 200 is provided, in which the chip package structure 200 is mainly composed of a substrate 202, a chip 204, an encapsulant 208 and solder balls 210, such as shown in FIG. 2. The chip 204 is attached on a top surface 212 of the substrate 202, and is electrically connected to pads (not shown) of the substrate 202 by wires 206. The encapsulant 208 is formed on a portion of the top surface 212 of the substrate 202 and fully covers the chip 204 and the wires 206. The solder balls 210 are set on a bottom surface 214 of the substrate 202, in which the solder balls 210 are electrically connected to the chip 204. The top surface 212 of the substrate 202 of the chip package structure 200 further includes a plurality of connection pads 216 deposed thereon, in which the locations of the connection pads 216 are corresponding to that of the solder balls 110 on the bottom surface 114 of the substrate 102.
  • [0006]
    Then, the chip package structure 100 is stacked on the chip package structure 200, and the solder balls 110 of the chip package structure 100 are respectively connected to the corresponding connection pads 216. Subsequently, a reflow step is performed, so as to connect the solder balls 110 of the chip package structure 100 to the connection pads 216 of the chip package structure 200 to complete the stacked package structure 250.
  • [0007]
    However, in the connection treatment of the chip package structure 100 and the chip package structure 200, warpage will occur in the chip package structure 100 and the chip package structure 200, especially the chip package structure 100. Furthermore, the room between the substrate 102 of the chip package structure 100 and the substrate 202 of the chip package structure 200 is still large, and the connection locations between the chip package structure 100 and the chip package structure 200 are at the outer region, so that a cold joint occurs between the chip package structure 100 and the chip package structure 200. As a result, the reliability of the stacked package structure is seriously deteriorated, the yield of the package process is greatly reduced, and the cost is substantially increased.
  • SUMMARY OF THE INVENTION
  • [0008]
    Therefore, one objective of the present invention is to provide a method for manufacturing a stacked package structure, which can reduce the area occupied by the package structure to greatly decrease the area of a printed circuit board.
  • [0009]
    Another objective of the present invention is to provide a method for manufacturing a stacked package structure, which can integrate the connection between an upper chip package structure and a bottom chip package structure.
  • [0010]
    Still another objective of the present invention is to provide a method for manufacturing a stacked package structure, which can effectively avoid warpage from occurring in the connection of chip package structures, and prevent a cold joint condition from occurring between the chip package structures, so as to greatly enhance the yield of the stacked package structure.
  • [0011]
    According to the aforementioned objectives, the present invention provides a method for manufacturing a stacked package structure, comprising: forming a first chip package structure, comprising: providing a first chip carrier having a first surface and a second surface in opposition to each other; forming a plurality of bonding wires on the first surface of the first chip carrier; providing at least one first chip on and electrically connected to the first surface of the first chip carrier, wherein each bonding wire is higher than the at least one first chip in altitude; and forming an encapsulant covering the first surface of the first chip carrier, the at least one first chip and the bonding wires, wherein at least one top end of each bonding wire is exposed at a surface of the encapsulant; and providing a second chip package structure electrically connected to and stacked on the first chip package structure.
  • [0012]
    According to a preferred embodiment of the present invention, the step of providing the second chip structure comprises: providing a second substrate having a first surface and a second surface in opposition to each other; forming a plurality of electrical connection devices on the first surface of the second substrate; providing at least one second chip on and electrically connected to the first surface of the second substrate, wherein each electrical connection device is higher than the at least one second chip in altitude; and forming another encapsulant covering the first surface of the second substrate, the at least one second chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the another encapsulant.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0013]
    The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
  • [0014]
    FIGS. 1 to 3 are schematic flow diagrams showing the process for manufacturing a conventional stacked package structure.
  • [0015]
    FIGS. 4 to 9 b are schematic flow diagrams showing the process for manufacturing a stacked package structure in accordance with a first preferred embodiment of the present invention, wherein FIG. 7 d is a cross-sectional view of a package structure in accordance with another embodiment of the present invention.
  • [0016]
    FIG. 9 c is a cross-sectional view of a stacked package structure in accordance with another embodiment of the present invention.
  • [0017]
    FIGS. 10 a and 10 b are cross-sectional views of a stacked package structure in accordance with a second preferred embodiment of the present invention.
  • [0018]
    FIGS. 11 a and 11 b are cross-sectional views of a stacked package structure in accordance with a third preferred embodiment of the present invention.
  • [0019]
    FIG. 12 a is a cross-sectional view of a substrate of a stacked package structure in accordance with a fourth preferred embodiment of the present invention.
  • [0020]
    FIGS. 12 b and 12 c are cross-sectional views of a stacked package structure in accordance with a fourth preferred embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • [0021]
    The present invention discloses a stacked package structure and a method for manufacturing the same. In order to make the illustration of the present invention more explicit and complete, the following description is stated with reference to FIGS. 4 to 12 c.
  • [0022]
    Referring to FIGS. 4 to 9 b and FIG. 12 a, in which FIGS. 4 to 9 b are schematic flow diagrams showing the process for manufacturing a stacked package structure in accordance with a first preferred embodiment of the present invention. In the fabrication of a stacked package structure of the present invention, a chip package structure 324 a, such as illustrated in FIG. 8, is typically formed firstly. In the formation of the chip package structure 324 a, a substrate 300 a or a substrate 300 b is provided, in which the substrate 300 a or the substrate 300 b may be a printed circuit board, for example. Alternatively, the substrate 300 a or 300 b can be replaced by other chip carrier, such as a QFP leadframe or a QFN leadframe. The substrate 300 a has a surface 326 a and a surface 328 a in opposition to each other, while the substrate 300 b has a surface 326 b and a surface 328 b in opposition to each other. It should be noted that when the substrate 300 b is provided by a supplier, a plurality of electrical connection devices 312 d have already been set on the surface 326 b, such as shown in FIG. 12 a, the connection devices 312 d are preferably deposed on the periphery of the substrate 326 b; when the substrate 300 a is provided by a supplier, no device is set on the opposite surface 326 a and the surface 328 a, such as shown in FIG. 4. In the present embodiment, the chip package structure 324 a is fabricated on the substrate 300 a.
  • [0023]
    Next, a chip structure 308 is attached to a central region of the surface 326 a of the substrate 300 a, and several wires 316 are formed to connect the chip structure 308 and pads (not shown) at the surface 326 a of the substrate 300 a by, for example, a wire bonding method, so as to electrically connect the chip structure 308 and the substrate 300 a. Alternatively, the wires 316 also can be replaced by bumps (not shown), and the chip structure 308 can be electrically connected to the substrate 300 a by a flip-chip method. The passive devices 310 according to the requirements are provided and attached to the surface 326 a of the substrate 300 a at the periphery of the chip structure 308, in which the passive devices 310 may be resistors, inductors or capacitors, for example. In the present embodiment, the chip structure 308 is a multi-chip structure including a chip 302 and a chip 306, in which the chip 302 and the chip 306 can be jointed by an adhesion layer 304, and a material of the adhesion layer 304 can be, for example, epoxy. However, it is worthy of note that the chip structure of the present invention may be composed of a single chip. A plurality of electrical connection devices 312 a are formed in the outer region of the surface 326 a of the substrate 300 a, in which the electrical connection devices 312 a are preferably located at the periphery of the chip structure 308 and the passive devices 310, such as shown in FIG. 5. The electrical connection devices 312 a must be higher than the chip structure 308 in altitude. The electrical connection devices 312 a in the exemplary embodiment are wires. In an exemplary embodiment, the electrical connection devices 312 a are formed by, for example, a wire bonding method, and the electrical connection devices 312 a are preferably bonding wires. In the exemplary embodiment, each electrical connection device 312 a composed of a bonding wire is connected to two pads on the substrate 300 a by a wire bonding method.
  • [0024]
    However, in the other embodiments of the present invention, various types of electrical connection devices, such as electrical connection devices 312 b shown in FIG. 10 a, electrical connection devices 312 c shown in FIG. 11 a and electrical connection devices 312 d shown in FIG. 12 a, may be used, in which the electrical connection devices 312 b are conductive studs, the electrical connection devices 312 c are electronic components, such as passive devices, and the electrical connection devices 312 d are pins. Furthermore, note that the electrical connection devices of the stacked package structure in the present invention can be any combination of the electrical connection devices in the aforementioned embodiments, such as a chip package structure 324 c in FIG. 11 a. In the present invention, the electrical connection devices 312 a, the electrical connection devices 312 b and the electrical connection devices 312 d may be composed of Au, Al, Cu, Sn and the alloys thereof, for example. The electrical connection devices 312 a, the electrical connection devices 312 b, the electrical connection devices 312 c and the electrical connection devices 312 d can be respectively attached to the surface 326 a of the substrate 300 a by an adhesion material, such as solder or an alloy of the solder. In the exemplary embodiments, the electrical connection devices 312 a are attached to the surface 326 a of the substrate 300 a by a wire bonding method.
  • [0025]
    Next, such as shown in FIG. 6, an encapsulant material layer 317 is formed to cover the surface 326 a of the substrate 300 a, and wrap the chip structure 308, the wires 316, the passive devices 310 and the electrical connection devices 312 a on the surface 326 a of the substrate 300 a by, for example, a molding or coating method. A plurality of solder balls 320 are formed to joint on the outer region of the surface 328 a of the substrate 300 a, and a heat sink 330 is preferably formed on a central region of the surface 328 a of the substrate 300 a for dissipating heat, such as shown in FIG. 7 c. The chip structure 308 and the electrical connection devices 312 a are electrically connected to the solder balls respectively. Subsequently, the encapsulant material layer 317 is ground to remove a portion of the encapsulant material layer 317 by a mechanical method or a chemical method, such as a chemical mechanical polishing method, until the top end 314 a of each electrical connection device 312 a is exposed, so as to form an encapsulant 318, such as shown in FIG. 7 a. In the exemplary embodiment, after the encapsulant material layer 317 is ground, only one top end 314 a of each electrical connection device 312 a is exposed. In the other embodiments, according to the requirements of the product, two top ends 311 a and 311 b of each electrical connection device 312 a composed of a bonding wire are exposed after the encapsulant material layer 317 is ground, such as shown in FIG. 7 d. In the package structure shown in FIG. 7 d, the projected positions of the two top ends 311 a and 311 b projected on the substrate 300 a are different from two lower ends of the electrical connection device 312 a connected to the pads on the substrate 300 a. Furthermore, the pitch between the two top ends 311 a and 311 b of each electrical connection device 312 a is preferably smaller than the pitch between the two lower ends thereof. In addition, the pitch between the two top ends 311 a and 311 b of each electrical connection device 312 a can be changed by adjusting the parameters of a wire bonding process or the grinding degree of the encapsulant 318. Moreover, the substrate 300 a can be replaced by other chip carrier, such as a QFP leadframe or a QFN leadframe.
  • [0026]
    In the exemplary embodiment, after the encapsulant 318 is formed, several connection bumps 322 a or solder balls are formed and respectively attached on the top end 314 a of each electrical connection device 312 a, so as to complete the chip package structure 324 a, such as shown in FIG. 7 b. The connection bumps 322 a can be formed by a direct ball attach method, a screen print method, an electro plating method or an electroless plating method.
  • [0027]
    A chip package structure 420 a is formed by a method similar to the method for manufacturing the chip package structure 324 a. The chip package structure 420 a is mainly composed of a substrate 400, a chip structure 408 and electrical connection devices 412 a. The substrate 400 has a surface 422 and a surface 424 in opposition to each other. A chip structure 408 is attached to a central region of the surface 422 of the substrate 400, and several wires 416 are formed to connect the chip structure 408 and pads (not shown) at the surface 422 of the substrate 400 by, for example, a wire bonding method, so as to electrically connect the chip structure 408 and the substrate 400. In the present embodiment, the chip structure 408 is a multi-chip structure including a chip 402 and a chip 406, in which the chip 402 and the chip 408 can be jointed by an adhesion layer 404, and a material of the adhesion layer 404 can be, for example, epoxy. It is worthy of note that the chip structure of the present invention may be composed of a single chip. A plurality of electrical connection devices 412 a are formed in the outer region of the surface 422 of the substrate 400. In a preferred embodiment of the present invention, the passive devices 410 according to the requirements are provided and attached to the surface 422 of the substrate 400 at the periphery of the chip structure 408, in which the passive devices 410 may be resistors, inductors or capacitors, for example. The electrical connection devices 412 a are preferably located at the periphery of the chip structure 408 and the passive devices 410, and the electrical connection devices 412 a must be higher than the chip structure 408 in altitude, such as shown in FIG. 9 a. The electrical connection devices 412 a in the exemplary embodiment are wires. In an exemplary embodiment, the electrical connection devices 412 a are formed by, for example, a wire bonding method, and the electrical connection devices 412 a are preferably bonding wires. However, various types of electrical connection devices, such as conductive studs, electronic components, pins or any combination of the aforementioned electrical connection devices, may be used. The electrical connection devices 412 a may be composed of Au, Al, Cu, Sn and the alloys thereof, for example, the electrical connection devices 412 a can be respectively attached to the surface 422 of the substrate 400 by an adhesion material, such as solder or an alloy of the solder. In the exemplary embodiments, the electrical connection devices 412 a are attached to the surface 422 of the substrate 400 by a wire bonding method. An encapsulant material layer (not shown) is formed to cover the surface 422 of the substrate 400, and wrap the chip structure 408, the wires 416, the passive devices 410 and the electrical connection devices 412 a on the surface 422 of the substrate 400 by a molding or coating method. Then, a portion of the encapsulant material layer is removed by a mechanical grinding method or a chemical grinding method, such as a chemical mechanical polishing method, until the top end 414 a of each electrical connection device 412 a is exposed, so as to form an encapsulant 418 and complete the chip package structure 420 a. Similarly, in the exemplary embodiment, after the encapsulant material layer is ground, only one top end 414 a of each electrical connection device 412 a is exposed. However, it should be noted that according to the requirements of the product, two top ends 411 a and 411 b of each electrical connection device 412 a composed of a bonding wire may be exposed after the encapsulant material layer is ground, such as the package structure 423 shown in FIG. 9 c. Subsequently, the chip package structure 420 a is stacked and jointed on the chip package structure 324 a, in which the surface 424 of the substrate 400 is jointed with the connection bumps 322 a, and the chip structure 408 and the electrical connection devices 412 a are electrically connected to the connection bumps 322 a respectively, so that a stacked package structure, such as shown in FIG. 9 a, is complete.
  • [0028]
    In the other embodiments, such as shown in FIG. 9 c, the chip package structure 423 is stacked and jointed on the chip package structure 325, in which the surface 424 of the substrate 400 is jointed with the connection bumps 322 a, and the chip structure 408 and the electrical connection devices 412 a are electrically connected to the connection bumps 322 a respectively, so that a stacked package structure as shown in FIG. 9 c is complete. In the stacked package structure shown in FIG. 9 c, two connection bumps 322 a are respectively attached on the top ends 311 a and 311 b of each electrical connection device 312 a, so that each electrical connection device 312 a is electrically connected to the surface 424 of the substrate 400 through two connection bumps 322 a. Furthermore, in addition to the chip package structure 423, other type of package structure (not-shown), such as a BGA package structure, a QFP package structure, a QFN package structure, or a flip chip CSP, also can be selectively stacked on the chip package structure 325 and electrically connected to the chip package structure 325 via the top ends 311 a and 311 b of each electrical connection device 312 a.
  • [0029]
    In the other embodiments of the present invention, various types of electrical connection devices or any combination of these electrical connection devices, such as electrical connection devices 412 b of the chip package structure 420 b (such as shown in FIG. 10 a), electrical connection devices 412 d of the chip package structure 420 d (such as shown in FIG. 12 a) and the combination of electrical connection devices 412 c and the electrical connection devices 430 of the chip package structure 420 c (such as shown in FIG. 11 a), may be used, in which a contact 434 and a contact 436 of the electrical connection devices 430 are respectively located at a top end 432 and a bottom end of the electrical connection devices 430, and the contact 434 at the top end 432 of the electrical connection devices 430 is exposed. In the embodiments, the top end 414 b of each electrical connection device 412 b, the top end 414 c of each electrical connection device 412 c, and the top end 414 d of each electrical connection device 412 d are exposed. Accordingly, except the stacked structure shown in FIG. 9 a, the stacked package structure of the present invention can be the structure such as shown in FIGS. 10 a, 11 a or 12 b.
  • [0030]
    In the stacked package structure of the present invention, a chip 426 and passive devices 428 can be further set on the surface 424 of the substrate 400, and connection bumps 322 b larger than the connection bumps 322 a are used and the height of the connection bumps 322 b is larger than that of the chip 426, so as to prevent the chip 426 and the passive devices 428 from contacting the underlying chip package structure. In the embodiments, a chip package structure 421 a such as shown in FIG. 9 b, a chip package structure 421 b such as shown in FIG. 10 b, a chip package structure 421 c such as shown in FIG. 11 b, and a chip package structure 421 d such as shown in FIG. 12 c can be formed.
  • [0031]
    In some embodiment of the present invention, the encapsulant 318 may be formed by using a mold, wherein the mold includes a plurality of pillars corresponding to the connection pads on the substrate 300 a. After the encapsulant material is filled and hardened, the encapsulant 318 is formed with a plurality of openings therein and the connection pads on the substrate 300 a are exposed by the openings. Then, a conductive material is fill into the openings, and the electrical connection devices are respectively formed in the openings to connect with the exposed connection pads on the substrate 300 a. In the other embodiment of the present invention, an encapsulant material layer is firstly formed on the substrate 300 a by, for example, a molding or coating method. Then, the encapsulant material layer is drilled to form a plurality of openings in the encapsulant material layer, wherein the openings expose the connection pads on the substrate 300 a. Subsequently, a conductive material is fill into the openings, and the electrical connection devices are respectively formed in the openings to connect with the exposed connection pads on the substrate 300 a.
  • [0032]
    According to the aforementioned exemplary embodiments, it is known that a greater portion of the room between the substrates of the two chip package structures has been filled with encapsulant materials, so that the room between the two chip package structures is greatly decreased. Accordingly, in the stack process of the two chip package structures, the warpage can be prevented from occurring in the chip package structures, to avoid cold joint from arising between the chip package structures.
  • [0033]
    Each stacked package structures disclosed in the aforementioned embodiments is a two-chip stacked package structure, however, it should be noted that the stacked package structure of the present invention may be a stacked package structure including more than two chips, and the present invention is not limited thereto.
  • [0034]
    According to the aforementioned description, one advantage of the present invention is that the application of the present stacked package structure can decrease the area of the package structure, so the area of the printed circuit board can be greatly reduced.
  • [0035]
    According to the aforementioned description, another advantage of the present invention is that the application of the present method can integrate the connection between an upper chip package structure and a bottom chip package structure, effectively avoid the warpage from occurring, prevent a cold joint condition from arising between two chip package structures, and greatly enhance the yield of the stacked package process.
  • [0036]
    As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8546954 *22 Sep 20111 Oct 2013Samsung Electronics Co., Ltd.Stacked semiconductor package having electrical connections or varying heights between substrates, and semiconductor device including the stacked semiconductor package
US871687219 Aug 20136 May 2014Samsung Electronics Co., Ltd.Stacked semiconductor package including connections electrically connecting first and second semiconductor packages
US883613624 Feb 201216 Sep 2014Invensas CorporationPackage-on-package assembly with wire bond vias
US890746625 Jun 20139 Dec 2014Tessera, Inc.Stackable molded microelectronic packages
US892733727 Aug 20136 Jan 2015Tessera, Inc.Stacked packaging improvements
US895752710 Feb 201417 Feb 2015Tessera, Inc.Microelectronic package with terminals on dielectric mass
US897573812 Nov 201210 Mar 2015Invensas CorporationStructure for microelectronic packaging with terminals on dielectric mass
US904122712 Mar 201326 May 2015Invensas CorporationPackage-on-package assembly with wire bond vias
US909343511 Mar 201328 Jul 2015Tessera, Inc.Package-on-package assembly with wire bonds to encapsulation surface
US909507417 Oct 201428 Jul 2015Invensas CorporationStructure for microelectronic packaging with bond elements to encapsulation surface
US910548324 Feb 201211 Aug 2015Invensas CorporationPackage-on-package assembly with wire bond vias
US91236643 Dec 20141 Sep 2015Tessera, Inc.Stackable molded microelectronic packages
US915356218 Dec 20146 Oct 2015Tessera, Inc.Stacked packaging improvements
US915970819 Jul 201013 Oct 2015Tessera, Inc.Stackable molded microelectronic packages with area array unit connectors
US92189881 Apr 201422 Dec 2015Tessera, Inc.Microelectronic packages and methods therefor
US92247179 Dec 201429 Dec 2015Tessera, Inc.Package-on-package assembly with wire bonds to encapsulation surface
US925212214 Aug 20132 Feb 2016Invensas CorporationPackage-on-package assembly with wire bond vias
US932468126 Sep 201426 Apr 2016Tessera, Inc.Pin attachment
US934970614 Feb 201324 May 2016Invensas CorporationMethod for package-on-package assembly with wire bonds to encapsulation surface
US939100831 Jul 201212 Jul 2016Invensas CorporationReconstituted wafer-level package DRAM
US941271430 May 20149 Aug 2016Invensas CorporationWire bond support structure and microelectronic package including wire bonds therefrom
US950239012 Mar 201322 Nov 2016Invensas CorporationBVA interposer
US9543269 *22 Mar 201210 Jan 2017Nantong Fujitsu Microelectronics Co., Ltd.System-level packaging methods and structures
US95530768 Oct 201524 Jan 2017Tessera, Inc.Stackable molded microelectronic packages with area array unit connectors
US957038225 Aug 201514 Feb 2017Tessera, Inc.Stackable molded microelectronic packages
US957041630 Sep 201514 Feb 2017Tessera, Inc.Stacked packaging improvements
US958341117 Jan 201428 Feb 2017Invensas CorporationFine pitch BVA using reconstituted wafer with area array accessible for testing
US960145410 Sep 201521 Mar 2017Invensas CorporationMethod of forming a component having wire bonds and a stiffening layer
US960145813 Mar 201421 Mar 2017Samsung Electronics Co., Ltd.Stacked semiconductor package including connections electrically connecting first and second semiconductor packages
US961545627 Jul 20154 Apr 2017Invensas CorporationMicroelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US964691729 May 20149 May 2017Invensas CorporationLow CTE component with wire bond interconnects
US965984831 Mar 201623 May 2017Invensas CorporationStiffened wires for offset BVA
US96853658 Aug 201320 Jun 2017Invensas CorporationMethod of forming a wire bond having a free end
US969167919 May 201627 Jun 2017Invensas CorporationMethod for package-on-package assembly with wire bonds to encapsulation surface
US969173122 Dec 201527 Jun 2017Tessera, Inc.Package-on-package assembly with wire bonds to encapsulation surface
US9721872 *16 Feb 20121 Aug 2017Amkor Technology, Inc.Methods and structures for increasing the allowable die size in TMV packages
US972852728 Oct 20158 Aug 2017Invensas CorporationMultiple bond via arrays of different wire heights on a same substrate
US973508411 Dec 201415 Aug 2017Invensas CorporationBond via array for thermal conductivity
US9741680 *29 Aug 201622 Aug 2017Pfg Ip LlcWire bond through-via structure and method
US976155410 Jul 201512 Sep 2017Invensas CorporationBall bonding metal wire bond wires to metal pads
US976155821 May 201512 Sep 2017Invensas CorporationPackage-on-package assembly with wire bond vias
US20120091597 *22 Sep 201119 Apr 2012Samsung Electronics Co., Ltd.Stacked semiconductor package, semiconductor device including the stacked semiconductor package and method of manufacturing the stacked semiconductor package
US20120146206 *13 Dec 201014 Jun 2012Tessera Research LlcPin attachment
US20130320534 *22 Mar 20125 Dec 2013Yujuan TaoSystem-level packaging methods and structures
CN103579171A *11 Oct 201312 Feb 2014三星半导体(中国)研究开发有限公司Semiconductor packaging piece and manufacturing method thereof
Legal Events
DateCodeEventDescription
28 Jun 2007ASAssignment
Owner name: ADVANCED SEMICONDUCTOR ENGINEERING INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, YONGGILL;REEL/FRAME:019539/0944
Effective date: 20070604