US20070235881A1 - Semiconductor Device and Method of Manufacturing the Same, Circuit Board and Electronic Device - Google Patents

Semiconductor Device and Method of Manufacturing the Same, Circuit Board and Electronic Device Download PDF

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Publication number
US20070235881A1
US20070235881A1 US11/764,684 US76468407A US2007235881A1 US 20070235881 A1 US20070235881 A1 US 20070235881A1 US 76468407 A US76468407 A US 76468407A US 2007235881 A1 US2007235881 A1 US 2007235881A1
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United States
Prior art keywords
wiring board
semiconductor device
resin
electronic components
disposed
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Abandoned
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US11/764,684
Inventor
Shingo Horii
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to US11/764,684 priority Critical patent/US20070235881A1/en
Publication of US20070235881A1 publication Critical patent/US20070235881A1/en
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165Containers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/1053Mounted components directly electrically connected to each other, i.e. not via the PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10636Leadless chip, e.g. chip capacitor or resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, a circuit board and an electronic device.
  • a semiconductor device that has a semiconductor chip mounted on one surface of a wiring board and an external terminal on the other surface thereof is known.
  • the semiconductor device is mounted and when the height of the external terminal can be made constant, the reliability of the semiconductor device after mounting can be improved.
  • An advantage of the present invention is to provide a semiconductor device high in reliability and a method of manufacturing the same, a circuit board and an electronic device.
  • a semiconductor device includes a wiring board having a wiring pattern, a semiconductor chip that has an integrated circuit and is mounted on a first surface of the wiring board to electrically connect with the wiring pattern, a spacer that is disposed on a second surface of the wiring board and has inside thereof an electronic component that is electrically connected with the wiring pattern and an external terminal that is disposed on the second surface and electrically connected with the wiring pattern.
  • a spacer and an external terminal are disposed on the second surface of the wiring board.
  • the height of the external terminal disposed on the same surface as the spacer can be maintained constant. Furthermore, since the electronic component is disposed inside of the spacer, the spacer can inhibit the electronic component from being displaced or falling off. Thereby, a semiconductor device high in reliability can be provided.
  • a recess may be formed on a surface that is opposite to a surface that faces the wiring board in the spacer.
  • the recess may be disposed avoiding a region that overlaps with the electronic component.
  • the height of the external terminal may be higher than that of the spacer.
  • the abovementioned semiconductor device is mounted on the circuit board according to an embodiment of the present invention.
  • An electronic device according to an embodiment of the present invention has the abovementioned semiconductor device.
  • a method of manufacturing a semiconductor device includes preparing a wiring board on a first surface of which a semiconductor chip is mounted and on a second surface of which an electronic component is mounted and forming on the second surface a spacer that seals the electronic component.
  • a spacer is formed on the second surface of the wiring board. Accordingly, a semiconductor device that can maintain a distance between the wiring board and the circuit board at a definite value or more when mounting on the circuit board and so on, and is high in reliability can be manufactured. Furthermore, with the electronic component sealed with the spacer, a semiconductor device that can inhibit the electronic component from being displaced or falling off and is high in reliability can be manufactured.
  • the spacer may be formed so as to have a recess on a surface opposite to a surface that faces the wiring board.
  • the spacer may be formed so as to be disposed avoiding a region where the recess overlaps with the electronic component.
  • On the second surface an external terminal may be further disposed and the external terminal may be formed so as to be higher in height than the spacer.
  • FIG. 1 is a diagram showing a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 2 is a diagram showing a circuit board of which a semiconductor device according to an embodiment thereto the present invention is applied is mounted.
  • FIG. 3 is a diagram showing an electronic device having a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 4 is a diagram showing another electronic device having a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 5 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 6 is a diagram showing another method of manufacturing a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 7 is a diagram showing still another method of manufacturing a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 8 is a diagram for explaining a modified example of a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 9 is a diagram for explaining another modified example of a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 10 is a diagram for explaining still another modified example of a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment to which the present invention is applied.
  • FIG. 1 is a sectional view of a semiconductor device according to an embodiment to which the present invention is applied.
  • a semiconductor device has a wiring board 10 .
  • a material of the wiring board 10 may be an organic material (such as epoxy board), an inorganic material (such as a ceramic board and a glass board), or a material having a composite structure thereof (such as a glass/epoxy board).
  • the wiring board 10 may be a rigid board and at this time the wiring board 10 may be called an interposer.
  • the wiring board 10 may be a flexible board such as a polyester board and a polyimide board.
  • the wiring board 10 may be a board for a Chip On Film (COF).
  • COF Chip On Film
  • the wiring board 10 may be a single layer board made of a single layer or a laminated board having a plurality of laminated layers. The shape and the thickness of the wiring board 10 are not particularly restricted.
  • the wiring board 10 has a wiring pattern 12 .
  • the wiring pattern 12 may be formed by laminating any of copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium-tungsten (Ti—W), gold (Au), aluminum (Al), nickel-vanadium (NiV) and tungsten (W) or of any one layer thereof.
  • the wiring pattern 12 may be formed so as to electrically connect one surface of the wiring board 10 and the other surface thereof. For instance, as shown in FIG. 1 , the wiring pattern 12 may have pads 13 , 15 and 17 .
  • the pad 13 is a pad that is disposed on one surface of the wiring board 10
  • the pads 15 and 17 are pads that are disposed on the other surface of the wiring board 10 .
  • the wiring pattern 12 may be disposed between the respective layers.
  • a method of forming the wiring pattern 12 is not particularly restricted.
  • the wiring pattern 12 may be formed by means of sputtering or the like or an additive method in which the wiring pattern 12 is formed by means of the electroless plating may be applied.
  • the wiring pattern 12 may be plated with solder, tin, gold, nickel or the like.
  • a semiconductor device has a semiconductor chip 20 .
  • the semiconductor chip 20 has an integrated circuit 22 made of a transistor, a memory element or the like.
  • the semiconductor chip 20 is mounted on a first surface 14 of the wiring board 10 .
  • a surface on which the semiconductor chip 20 is disposed in the wiring board 10 may be called a first surface 14 .
  • the semiconductor chip 20 is electrically connected with the wiring pattern 12 .
  • the semiconductor chip 20 may have an electrode 24 , and the electrode 24 may electrically connect the semiconductor chip 20 and the wiring pattern 12 .
  • the electrode 24 and the pad 13 of the wiring pattern 12 may face each other and may be electrically connected.
  • the pad 13 is a pad that is disposed on the first surface of the wiring board 10 .
  • the semiconductor chip 20 may be solidly adhered to the wiring board 10 .
  • a mounting mode of the semiconductor chip 20 is not restricted thereto.
  • a semiconductor device has a spacer 30 .
  • the spacer 30 is disposed on a second surface 16 of the wiring board 10 .
  • the spacer 30 is disposed on a surface opposite to a surface (first surface 14 ) on which the semiconductor chip 20 of the wiring board 10 is mounted.
  • a material of the spacer 30 may be made of, for instance, a resin.
  • only one spacer 30 may be formed on the second surface 16 .
  • the spacer 30 has inside thereof an electronic component 40 that is electrically connected with the wiring pattern 12 .
  • the electronic component 40 may be electrically connected with the wiring pattern 12 by means of, for instance, solder. As shown in FIG.
  • the electronic component 40 by making use of the pad 15 , may be electrically connected with the wiring pattern 12 .
  • the pad 15 is a pad disposed on the second surface 16 of the wiring board 10 .
  • the electronic component 40 without restricting to a particular electronic component, may be a chip component (such as chip capacitor and chip coil).
  • a semiconductor device has an external terminal 50 .
  • the external terminal 50 is disposed on the second surface 16 of the wiring board 10 .
  • the external terminal 50 is electrically connected with the wiring pattern 12 .
  • the external terminal 50 as shown in FIG. 1 , may be disposed on the pad 17 to be electrically connected with the wiring pattern 12 .
  • the external terminal 50 may be, for instance, a solder ball.
  • a height of the external terminal 50 may be higher than a height of the spacer 30 . Thereby, when the semiconductor device is mounted on a circuit board (such as mother board), the external terminal 50 and a wiring or the like of the circuit board can be brought into contact. Accordingly, both can be easily electrically connected.
  • the height of the spacer 30 may indicate a height of the spacer 30 from the second surface 16 of the wiring board 10 .
  • the height of the external terminal 50 may indicate the height of the external terminal 50 from the second surface 16 of the wiring board 10 .
  • a semiconductor device 1 according to an embodiment of the present invention is constituted as mentioned above.
  • the semiconductor device 1 has the spacer 30 disposed on the second surface 16 of the wiring board 10 . Accordingly, when the semiconductor device 1 is mounted so that the second surface 16 faces the circuit board, the spacer 30 restricts a distance between the wiring board 10 and the circuit board. Since the external terminal 50 is disposed on the same surface as the spacer 30 , after mounting, the dispersion in the height of the external terminal 50 can be made smaller ( FIG. 2 ). When the dispersion of the height of the external terminal 50 is made smaller, the dispersion of the forces applied on the respective external terminals 50 can be made smaller. Accordingly, after mounting, a large force can be inhibited from being applying on a particular external terminal 50 and thereby the reliability of the semiconductor device can be improved.
  • FIG. 2 a circuit board 1000 thereon the semiconductor device 1 is mounted is shown.
  • the semiconductor device 1 may be mounted so that the spacer 30 comes into contact with the circuit board 1000 .
  • the semiconductor device 1 may be mounted so that a surface opposite to a surface that faces the wiring board 10 of the spacer 30 may come into contact with the circuit board 1000 .
  • the spacer 30 has inside thereof an electronic component 40 .
  • the electronic component 40 is sealed with the spacer 30 . Accordingly, the electronic component 40 can be inhibited from falling off or being displaced.
  • FIG. 3 and FIG. 4 respectively, show a note type personal computer 2000 and a portable telephone 3000 .
  • FIGS. 5 through 7 are diagrams for explaining a method of manufacturing a semiconductor device according to the embodiment to which the invention is applied.
  • a method of manufacturing a semiconductor device includes preparing a wiring board 10 .
  • a semiconductor chip 20 is mounted on a first surface 14 of a wiring board 10 .
  • an electronic component 40 is mounted on a second surface 16 of the wiring board 10 .
  • a method of mounting the semiconductor chip 20 and the electronic component 40 is not particularly restricted and any known methods may be applied.
  • the semiconductor chip 20 and the electronic component 40 may be electrically connected with the wiring pattern 12 . For instance, as shown in FIG. 5 , after a resin paste is disposed on the first surface 14 of the wiring board 10 , the semiconductor chip 20 may be mounted so that the pad 13 and the electrode 24 may face each other.
  • the semiconductor chip 20 may be mounted on the wiring board 10 .
  • the electronic component 40 may be mounted on the pad 15 .
  • a method of manufacturing a semiconductor device includes forming, on the second surface 16 , a spacer 30 that seals the electronic component 40 .
  • a method of forming the spacer 30 is not particularly restricted.
  • a spacer 30 may be formed according to a molding process.
  • a resin paste 32 is filled in a cavity 62 followed by curing, and thereby a spacer 30 may be formed.
  • a spacer 30 may be formed.
  • a resin paste is dropped on the second surface 16 of the wiring board 10 , it may be cured to form a spacer 30 .
  • the height of the spacer 30 may be controlled or a top end surface of the spacer 30 may be made a planar surface.
  • a material (resin paste 32 ) of the spacer 30 is not particularly restricted.
  • a method of manufacturing a semiconductor device may include disposing an external terminal 50 on the second surface 16 .
  • the external terminal 50 may be disposed so as to electrically connect with the wiring pattern 12 .
  • the external terminal 50 may be disposed on the pad 17 ( FIG. 1 ).
  • the external terminal 50 may be formed so as to have a height higher than that of the spacer 30 . Then, after undergoing an inspection process and a marking process, the semiconductor device 1 shown in FIG. 1 may be manufactured.
  • a semiconductor device has a spacer 34 .
  • the spacer 34 has a recess 36 .
  • the recess 36 is formed on a surface opposite to a surface that faces a wiring board 10 in the spacer 34 .
  • the spacer 34 as well can exhibit an effect similar to that of the spacer 30 .
  • the recess 36 may be disposed avoiding a region that overlaps with the electronic component 40 .
  • a process of forming the spacer 34 may include a potting process. That is, as shown in FIG.
  • a resin paste 35 may be dropped on the second surface 16 of the wiring board 10 . Then, after undergoing a process of curing or leveling this, the spacer 34 may be formed. At this time, an amount of the resin paste 35 that is dropped on the wiring board 10 may be controlled to form the spacer 34 with a recess 36 .
  • a plurality of spacers 38 is disposed on a second surface 16 of a wiring board 10 .
  • the respective spacers 38 can be made smaller.
  • the respective spacers 38 can be made smaller. Accordingly, a degree of freedom of disposition of the spacer 38 becomes high.
  • the spacers 38 each have, inside thereof, an electronic component 40 .
  • the spacers 38 each may have, inside thereof, only one electronic component 40 .
  • the spacers 38 each may have, inside thereof, a plurality of electronic components 40 (not shown in the drawing).
  • the spacers 38 may be formed by, for instance, mold sealing the respective electronic components 40 .
  • the invention includes a configuration (such as a configuration same in the function, method and result, or a configuration the same in the advantage and effect) substantially same as that explained in the embodiment.
  • the invention includes a configuration in which a portion that is not essential to the configuration explained in the embodiment is replaced.
  • the invention includes a configuration that can exhibit an operational effect the same as that of the configuration explained in the embodiment or a configuration that can attain the same advantage.
  • the invention includes a configuration in which a known technique is added to the configuration explained in the embodiment.

Abstract

A semiconductor device includes a wiring board having a wiring pattern, a semiconductor chip that has an integrated circuit and is mounted on a first surface of the wiring board to electrically connect with the wiring pattern, a spacer that is disposed on a second surface of the wiring board and has inside thereof an electronic component that is electrically connected with the wiring pattern and an external terminal that is disposed on the second surface and electrically connected with the wiring pattern.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device and a method of manufacturing the same, a circuit board and an electronic device.
  • 2. Detailed Description of Related Art
  • A semiconductor device that has a semiconductor chip mounted on one surface of a wiring board and an external terminal on the other surface thereof is known. When the semiconductor device is mounted and when the height of the external terminal can be made constant, the reliability of the semiconductor device after mounting can be improved.
  • An advantage of the present invention is to provide a semiconductor device high in reliability and a method of manufacturing the same, a circuit board and an electronic device.
  • SUMMARY OF THE INVENTION
  • A semiconductor device according to an embodiment of the present invention includes a wiring board having a wiring pattern, a semiconductor chip that has an integrated circuit and is mounted on a first surface of the wiring board to electrically connect with the wiring pattern, a spacer that is disposed on a second surface of the wiring board and has inside thereof an electronic component that is electrically connected with the wiring pattern and an external terminal that is disposed on the second surface and electrically connected with the wiring pattern. According to an embodiment of the present invention, on the second surface of the wiring board a spacer and an external terminal are disposed. When the semiconductor device is mounted so that the second surface of the wiring board may face a circuit board, owing to the spacer, a distance between the wiring board and the circuit board can be restricted. Accordingly, the height of the external terminal disposed on the same surface as the spacer can be maintained constant. Furthermore, since the electronic component is disposed inside of the spacer, the spacer can inhibit the electronic component from being displaced or falling off. Thereby, a semiconductor device high in reliability can be provided.
  • According to an embodiment of the present invention, on a surface that is opposite to a surface that faces the wiring board in the spacer, a recess may be formed. The recess may be disposed avoiding a region that overlaps with the electronic component. The height of the external terminal may be higher than that of the spacer. Thereby, a semiconductor device high in reliability in the electrical connection with the circuit board can be provided.
  • On the circuit board according to an embodiment of the present invention, the abovementioned semiconductor device is mounted. An electronic device according to an embodiment of the present invention has the abovementioned semiconductor device.
  • A method of manufacturing a semiconductor device according to an embodiment of the present invention includes preparing a wiring board on a first surface of which a semiconductor chip is mounted and on a second surface of which an electronic component is mounted and forming on the second surface a spacer that seals the electronic component. According to the embodiment of the present invention, on the second surface of the wiring board, a spacer is formed. Accordingly, a semiconductor device that can maintain a distance between the wiring board and the circuit board at a definite value or more when mounting on the circuit board and so on, and is high in reliability can be manufactured. Furthermore, with the electronic component sealed with the spacer, a semiconductor device that can inhibit the electronic component from being displaced or falling off and is high in reliability can be manufactured.
  • According to the method of manufacturing a semiconductor device, the spacer may be formed so as to have a recess on a surface opposite to a surface that faces the wiring board. The spacer may be formed so as to be disposed avoiding a region where the recess overlaps with the electronic component. On the second surface an external terminal may be further disposed and the external terminal may be formed so as to be higher in height than the spacer.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • FIG. 1 is a diagram showing a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 2 is a diagram showing a circuit board of which a semiconductor device according to an embodiment thereto the present invention is applied is mounted.
  • FIG. 3 is a diagram showing an electronic device having a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 4 is a diagram showing another electronic device having a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 5 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 6 is a diagram showing another method of manufacturing a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 7 is a diagram showing still another method of manufacturing a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 8 is a diagram for explaining a modified example of a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 9 is a diagram for explaining another modified example of a semiconductor device according to an embodiment thereto the present invention is applied.
  • FIG. 10 is a diagram for explaining still another modified example of a semiconductor device according to an embodiment thereto the present invention is applied.
  • DETAILED DESCRIPTION OF THE INVENTION
  • In what follows, embodiments to which the present invention is applied will be explained with reference to the drawings. However, the present invention is not restricted to the embodiments below.
  • FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment to which the present invention is applied. FIG. 1 is a sectional view of a semiconductor device according to an embodiment to which the present invention is applied.
  • A semiconductor device according to the present embodiment has a wiring board 10. A material of the wiring board 10, without restricting to a particular one, may be an organic material (such as epoxy board), an inorganic material (such as a ceramic board and a glass board), or a material having a composite structure thereof (such as a glass/epoxy board). The wiring board 10 may be a rigid board and at this time the wiring board 10 may be called an interposer. Alternatively, the wiring board 10 may be a flexible board such as a polyester board and a polyimide board. Furthermore, the wiring board 10 may be a board for a Chip On Film (COF). The wiring board 10 may be a single layer board made of a single layer or a laminated board having a plurality of laminated layers. The shape and the thickness of the wiring board 10 are not particularly restricted.
  • The wiring board 10, as shown in FIG. 1, has a wiring pattern 12. The wiring pattern 12 may be formed by laminating any of copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium-tungsten (Ti—W), gold (Au), aluminum (Al), nickel-vanadium (NiV) and tungsten (W) or of any one layer thereof. The wiring pattern 12 may be formed so as to electrically connect one surface of the wiring board 10 and the other surface thereof. For instance, as shown in FIG. 1, the wiring pattern 12 may have pads 13, 15 and 17. At this time, the pad 13 is a pad that is disposed on one surface of the wiring board 10, and the pads 15 and 17 are pads that are disposed on the other surface of the wiring board 10. By electrically connecting the pad 13 and the pads 15 and 17, the electrical connection between both surfaces of the wiring board 10 may be attained. In the case of a laminated board being prepared as the wiring board 10, the wiring pattern 12 may be disposed between the respective layers. A method of forming the wiring pattern 12 is not particularly restricted. For instance, the wiring pattern 12 may be formed by means of sputtering or the like or an additive method in which the wiring pattern 12 is formed by means of the electroless plating may be applied. The wiring pattern 12 may be plated with solder, tin, gold, nickel or the like.
  • A semiconductor device according to an embodiment of the present invention has a semiconductor chip 20. The semiconductor chip 20 has an integrated circuit 22 made of a transistor, a memory element or the like. The semiconductor chip 20 is mounted on a first surface 14 of the wiring board 10. In other words, a surface on which the semiconductor chip 20 is disposed in the wiring board 10 may be called a first surface 14. The semiconductor chip 20 is electrically connected with the wiring pattern 12. For instance, as shown in FIG. 1, the semiconductor chip 20 may have an electrode 24, and the electrode 24 may electrically connect the semiconductor chip 20 and the wiring pattern 12. As shown in FIG. 1, the electrode 24 and the pad 13 of the wiring pattern 12 may face each other and may be electrically connected. The pad 13 is a pad that is disposed on the first surface of the wiring board 10. At this time, by the use of a resin portion 26, the semiconductor chip 20 may be solidly adhered to the wiring board 10. However, in the semiconductor device according to the embodiment of the present invention, a mounting mode of the semiconductor chip 20 is not restricted thereto.
  • A semiconductor device according to an embodiment of the present invention has a spacer 30. The spacer 30 is disposed on a second surface 16 of the wiring board 10. In more detail, the spacer 30 is disposed on a surface opposite to a surface (first surface 14) on which the semiconductor chip 20 of the wiring board 10 is mounted. A material of the spacer 30, without restricting to particular material, may be made of, for instance, a resin. As shown in FIG. 1, only one spacer 30 may be formed on the second surface 16. The spacer 30 has inside thereof an electronic component 40 that is electrically connected with the wiring pattern 12. The electronic component 40 may be electrically connected with the wiring pattern 12 by means of, for instance, solder. As shown in FIG. 1, the electronic component 40, by making use of the pad 15, may be electrically connected with the wiring pattern 12. The pad 15 is a pad disposed on the second surface 16 of the wiring board 10. The electronic component 40, without restricting to a particular electronic component, may be a chip component (such as chip capacitor and chip coil).
  • A semiconductor device according to the embodiment of the present invention has an external terminal 50. The external terminal 50 is disposed on the second surface 16 of the wiring board 10. The external terminal 50 is electrically connected with the wiring pattern 12. The external terminal 50, as shown in FIG. 1, may be disposed on the pad 17 to be electrically connected with the wiring pattern 12. The external terminal 50 may be, for instance, a solder ball. A height of the external terminal 50 may be higher than a height of the spacer 30. Thereby, when the semiconductor device is mounted on a circuit board (such as mother board), the external terminal 50 and a wiring or the like of the circuit board can be brought into contact. Accordingly, both can be easily electrically connected. The height of the spacer 30 may indicate a height of the spacer 30 from the second surface 16 of the wiring board 10. Furthermore, the height of the external terminal 50 may indicate the height of the external terminal 50 from the second surface 16 of the wiring board 10.
  • A semiconductor device 1 according to an embodiment of the present invention is constituted as mentioned above. As explained above, the semiconductor device 1 has the spacer 30 disposed on the second surface 16 of the wiring board 10. Accordingly, when the semiconductor device 1 is mounted so that the second surface 16 faces the circuit board, the spacer 30 restricts a distance between the wiring board 10 and the circuit board. Since the external terminal 50 is disposed on the same surface as the spacer 30, after mounting, the dispersion in the height of the external terminal 50 can be made smaller (FIG. 2). When the dispersion of the height of the external terminal 50 is made smaller, the dispersion of the forces applied on the respective external terminals 50 can be made smaller. Accordingly, after mounting, a large force can be inhibited from being applying on a particular external terminal 50 and thereby the reliability of the semiconductor device can be improved.
  • In FIG. 2, a circuit board 1000 thereon the semiconductor device 1 is mounted is shown. As shown in FIG. 2, the semiconductor device 1 may be mounted so that the spacer 30 comes into contact with the circuit board 1000. In more detail, the semiconductor device 1 may be mounted so that a surface opposite to a surface that faces the wiring board 10 of the spacer 30 may come into contact with the circuit board 1000. Thereby, since the external terminal 50 after mounting can be made to a designated height, the reliability of the semiconductor device can be improved. Furthermore, as explained above, the spacer 30 has inside thereof an electronic component 40. In other words, the electronic component 40 is sealed with the spacer 30. Accordingly, the electronic component 40 can be inhibited from falling off or being displaced.
  • As electronic devices having the semiconductor device according to the embodiment to which the present invention is applied, FIG. 3 and FIG. 4, respectively, show a note type personal computer 2000 and a portable telephone 3000.
  • In what follows, a method of manufacturing a semiconductor device according to the embodiment to which the present invention is applied will be explained. FIGS. 5 through 7 are diagrams for explaining a method of manufacturing a semiconductor device according to the embodiment to which the invention is applied.
  • A method of manufacturing a semiconductor device according to an embodiment of the present invention includes preparing a wiring board 10. On a first surface 14 of a wiring board 10, a semiconductor chip 20 is mounted. On a second surface 16 of the wiring board 10, an electronic component 40 is mounted. A method of mounting the semiconductor chip 20 and the electronic component 40 is not particularly restricted and any known methods may be applied. At this time, the semiconductor chip 20 and the electronic component 40 may be electrically connected with the wiring pattern 12. For instance, as shown in FIG. 5, after a resin paste is disposed on the first surface 14 of the wiring board 10, the semiconductor chip 20 may be mounted so that the pad 13 and the electrode 24 may face each other. Then, by curing the resin paste, the semiconductor chip 20 may be mounted on the wiring board 10. Thereafter, on the second surface 16 of the wiring board 10, the electronic component 40 may be mounted. As shown in FIG. 6, the electronic component 40 may be mounted on the pad 15.
  • A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on the second surface 16, a spacer 30 that seals the electronic component 40. A method of forming the spacer 30 is not particularly restricted. For instance, a spacer 30 may be formed according to a molding process. In more detail, as shown in FIG. 7, after a molding die 60 is set to the wiring board 10, a resin paste 32 is filled in a cavity 62 followed by curing, and thereby a spacer 30 may be formed. Alternatively, according to a potting process, a spacer 30 may be formed. In more detail, after a resin paste is dropped on the second surface 16 of the wiring board 10, it may be cured to form a spacer 30. At this time, according to a leveling process, the height of the spacer 30 may be controlled or a top end surface of the spacer 30 may be made a planar surface. A material (resin paste 32) of the spacer 30 is not particularly restricted.
  • A method of manufacturing a semiconductor device according to an embodiment of the present invention may include disposing an external terminal 50 on the second surface 16. The external terminal 50 may be disposed so as to electrically connect with the wiring pattern 12. The external terminal 50 may be disposed on the pad 17 (FIG. 1). At this time, the external terminal 50 may be formed so as to have a height higher than that of the spacer 30. Then, after undergoing an inspection process and a marking process, the semiconductor device 1 shown in FIG. 1 may be manufactured.
  • MODIFICATION EXAMPLE
  • In what follows, a modification example of a semiconductor device according to an embodiment thereto the present invention is applied will be explained. In the following modification example, contents mentioned above are applied as far as possible.
  • In an example shown in FIG. 8, a semiconductor device has a spacer 34. The spacer 34 has a recess 36. In more detail, on a surface opposite to a surface that faces a wiring board 10 in the spacer 34 the recess 36 is formed. The spacer 34 as well can exhibit an effect similar to that of the spacer 30. Furthermore, since an amount of a material used for the spacer 34 can be reduced, a manufacturing cost of the semiconductor device can be suppressed low. At this time, as shown in FIG. 8, the recess 36 may be disposed avoiding a region that overlaps with the electronic component 40. A process of forming the spacer 34 may include a potting process. That is, as shown in FIG. 9, on the second surface 16 of the wiring board 10, a resin paste 35 may be dropped. Then, after undergoing a process of curing or leveling this, the spacer 34 may be formed. At this time, an amount of the resin paste 35 that is dropped on the wiring board 10 may be controlled to form the spacer 34 with a recess 36.
  • In an example shown in FIG. 10, on a second surface 16 of a wiring board 10, a plurality of spacers 38 is disposed. According to this, the respective spacers 38 can be made smaller. In more detail, since there is no need of sealing all of the electronic components 40 with one spacer, the respective spacers 38 can be made smaller. Accordingly, a degree of freedom of disposition of the spacer 38 becomes high. The spacers 38 each have, inside thereof, an electronic component 40. As shown in FIG. 10, the spacers 38 each may have, inside thereof, only one electronic component 40. Alternatively, the spacers 38 each may have, inside thereof, a plurality of electronic components 40 (not shown in the drawing). The spacers 38 may be formed by, for instance, mold sealing the respective electronic components 40.
  • The present invention, without restricting to the abovementioned embodiments, may be variously modified. For instance, the invention includes a configuration (such as a configuration same in the function, method and result, or a configuration the same in the advantage and effect) substantially same as that explained in the embodiment. Furthermore, the invention includes a configuration in which a portion that is not essential to the configuration explained in the embodiment is replaced. Still furthermore, the invention includes a configuration that can exhibit an operational effect the same as that of the configuration explained in the embodiment or a configuration that can attain the same advantage. Furthermore, the invention includes a configuration in which a known technique is added to the configuration explained in the embodiment.

Claims (19)

1-20. (canceled)
21. A semiconductor device, comprising:
a wiring board that has a wiring pattern;
a semiconductor chip that has an integrated circuit, the semiconductor chip being disposed on a first surface of the wiring board, the semiconductor chip being electrically connected with the wiring pattern;
a plurality of electronic components that are disposed on a second surface of the wiring board opposite to the first surface of the wiring board, the plurality of electronic components being electrically connected to the wiring pattern;
a resin that is disposed on the second surface of the wiring board, the resin covering the plurality of electronic components, the resin including a first surface being facing the second surface of the wiring board and a second surface opposite to the first surface of the resin, the second surface of the resin being flat; and
an external terminal that is disposed on the second surface of the wiring board, the external terminal being electrically connected with the wiring pattern.
22. The semiconductor device according to claim 21, the external terminal having a height higher than that of the resin.
23. The semiconductor device according to claim 21, the resin covering each of first surfaces of the plurality of electronic components opposite to each of second surfaces of the plurality of electronic components, the each of the second surfaces of the plurality of electronic components facing the second surface of the wiring board.
24. The semiconductor device according to claim 21, one of the plurality of the electronic components being a chip component.
25. The semiconductor device according to claim 21, one of the plurality of the electronic components being a capacitor.
26. The semiconductor device according to claim 21, one of the plurality of the electronic components being a coil.
27. An electronic device comprising:
a wiring board that has a first wiring pattern;
a semiconductor chip that has an integrated circuit, the semiconductor chip being disposed on a first surface of the wiring board, the semiconductor chip being electrically connected with the first wiring pattern;
a plurality of electronic components that are disposed on a second surface of the wiring board opposite to the first surface of the wiring board, the plurality of electronic components being electrically connected to the first wiring pattern;
a resin that is disposed on the second surface of the wiring board, the resin covering the plurality of electronic components, the resin including a first surface being facing the second surface of the wiring board and a second surface opposite to the first surface of the resin, the second surface of the resin being flat;
an external terminal that is disposed on the second surface of the wiring board, the external terminal being electrically connected with the first wiring pattern; and
a circuit board that has a second wiring pattern, the second wiring pattern having a part being in contact with the external terminal.
28. The electronic device according to claim 27, the second surface of the resin being in contact with the circuit board.
29. A method of manufacturing a semiconductor device, comprising:
preparing a wiring board having a first surface on which a semiconductor chip is mounted and a second surface on which a plurality of electronic components are mounted; and
forming on the second surface a resin covering the plurality of electronic components, a first surface of the resin being flat, a second surface of the resin facing the wiring board, the second surface being opposite to the first surface of the resin.
30. The method of manufacturing a semiconductor device according to claim 29, further comprising disposing an external terminal on the second surface.
31. The method of manufacturing a semiconductor device according to claim 30, the external terminal being formed so as to be higher in height than the spacer.
32. The method of manufacturing a semiconductor device according to claim 29, forming the resin being performed according to a molding process.
33. The method of manufacturing a semiconductor device according to claim 29, forming the resin including;
setting the wiring board to a molding die so that the plurality of the electronic components are in a cavity of the molding die; and
filling the resin in the cavity.
34. The method of manufacturing a semiconductor device according to claim 29, one of the plurality of the electronic components being a chip component.
35. The method of manufacturing a semiconductor device according to claim 29, one of the plurality of the electronic components being a capacitor.
36. The method of manufacturing a semiconductor device according to claim 29, one of the plurality of the electronic components being a coil.
37. A method of manufacturing an electronic component, comprising:
preparing a wiring board having a first surface on which a semiconductor chip is mounted, a second surface on which a plurality of electronic components are mounted, and an external electrode being disposed on the second surface;
forming on the second surface a resin covering the plurality of electronic components, a first surface of the resin being flat, a second surface of the resin facing the wiring board, the second surface being opposite to the first surface of the resin; and
mounting the wiring board on a circuit board via the external electrode.
38. The method of manufacturing an electronic device according to claim 37, the wiring board being mounted so that the first surface of the resin is in contact with the wiring board.
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