US20070223270A1 - High write selectivity and low power magnetic random access memory and method for fabricating the same - Google Patents
High write selectivity and low power magnetic random access memory and method for fabricating the same Download PDFInfo
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- US20070223270A1 US20070223270A1 US11/756,246 US75624607A US2007223270A1 US 20070223270 A1 US20070223270 A1 US 20070223270A1 US 75624607 A US75624607 A US 75624607A US 2007223270 A1 US2007223270 A1 US 2007223270A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
Definitions
- the invention relates to a magnetic random access memory (MRAM) and, in particular, to an MRAM with high write selectivity and low power consumption.
- MRAM magnetic random access memory
- Magnetic random access memory is nonvolatile memory. Using its magnetic resistance property to record information, it has the advantages of non-volatility, high densities, high access speeds, and anti-radiation.
- the basic operation principles of the MRAM are the same as storing data on a hard disk drive (HDD). Each bit of data is determined by its magnetization orientation to be either 0 or 1. The stored data are permanent until being modified by an external magnetic field.
- HDD hard disk drive
- MTJ magnetic tunnel junction
- the resistance value determines the numerical value of the data.
- a common method uses two wires (a bit line and a write word line) to induce a magnetic field at the selected cell, thereby changing the magnetization orientation of the magnetic material at the position and the data thereof.
- the MTJ cell between the bit line and the write word line has a stack structure of multi-layer magnetic metal materials.
- the structure basically contains a soft magnetic layer, a nonmagnetic conductor or tunnel barrier, and a hard magnetic layer. Whether the magnetization orientations of the two layers of ferromagnetic materials are parallel or anti-parallel determines whether the stored datum is 1 or 0.
- the U.S. Pat. No. 6,642,595 discloses a memory structure.
- the MTJ cell formed from a magnetic tunnel junction cell 10 has a lower electrode 20 below it.
- An insulator 30 is below the lower electrode 20 .
- the magnetic tunnel junction cell 10 is connected to the bit line 50 via a middle metal pillar 70 .
- the write word line is composed of an upper layer write word line 40 A and a lower layer write word line 40 B.
- the induced total magnetic is further enhanced by the pillar write word lines (PWWL's) 60 on both sides of the magnetic tunnel junction cell 10 .
- the PWWL's near the MTJ can produce a larger magnetic field focused on the MTJ. Therefore, the threshold current needed by the MRAM is reduced.
- a primary objective of the invention is to provide a magnetic random access memory (MRAM) with high write selectivity and low power consumption.
- the invention reduces the write current required by the MRAM, thereby reducing the power consumption during the write period thereof.
- the disclosed structure can eliminate the magnetic interference problem of the write word lines on adjacent MTJ's. This increases the write selectivity of the MRAM.
- the disclosed MRAM has a plurality of MTJ cells, a plurality of bit lines, a plurality of middle metal pillars, and a plurality of PWWL's.
- Each MTJ cell is comprised of a magnetic tunnel junction cell and a lower electrode. Changing the magnetization orientation of the magnetic tunnel junction cell determines the memory state.
- Each bit line provides the read and write current channels for the corresponding MTJ cell.
- Each middle metal pillar connects the MTJ cell and the bit line.
- Each write word line is comprised of an upper layer write word line, a lower layer write word line and a pair of PWWL's, providing the write current channel for the MTJ cell. This increases the induced magnetic field at the MTJ cell.
- the PWWL's of the adjacent MTJ cells are disposed in an interleaving fashion (zigzag pattern as shown in the FIG. 2 ). Aside from the part of the PWWL facing the surrounding of the magnetic tunnel junction cell, the rest is covered by a sidewall keeper.
- the sidewall keeper covering the PWWL's of the disclosed MRAM can reduce the write current required by the MRAM.
- the invention has to add a photo mask process after the PWWL process. Furthermore, the disclosed sidewall keeper structure confines the magnetic flux on the MTJ so that adjacent MTJ's are not affected by the magnetic field produced by the PWWL's. The write selectivity of the MRAM is thus greatly increased.
- FIG. 1 is a MRAM with PWWL's disclosed in the prior art
- FIG. 2 is a schematic layout of the MRAM with PWWL's according to the invention.
- FIG. 3 is a schematic view of a PWWL covered with a sidewall keeper
- FIG. 4 is a figure of simulated data for the disclosed MRAM with PWWL's.
- the invention employs the photo mask to arrange a PWWL and its PWWL's of write word lines with the same electrical currents flow in an interleaving fashion.
- FIG. 2 shows the mask layout of a MRAM. As shown in the drawing, it contains magnetic memory cells 1 , 2 , 3 , 4 .
- the magnetic memory cell 1 and the magnetic memory cell 2 are next to each other; likewise, the magnetic memory cell 3 and the magnetic memory cell 4 are next to each other.
- Each memory unit has a magnetic tunnel junction cell 10 A, an upper layer write word line 40 C, a lower layer write word line 40 D, a PWWL 60 A, and a middle metal pillar 70 A.
- the memory unit 1 and the memory unit 3 are controlled using the bit line 50 A.
- the magnetic tunnel junction cell 10 A further contains a lower electrode (not shown) to form a MTJ.
- the magnetic memory cell 1 and the magnetic memory cell 2 are affected under the current-induced magnetic field of the same write word line.
- the magnetic memory cell 3 and the magnetic memory cell 4 are affected under the current-induced magnetic field of the same write word line.
- the layout in the prior art is to arrange the magnetic memory cells next to one another.
- a layout will result in interference of adjacent PWWL's on a MTJ.
- the PWWL and its adjacent PWWL's of the write word lines with the same current flow in a zigzag fashion, eliminating the negative magnetic field produced by the adjacent PWWL's.
- Such a zigzag layout renders a smaller bit size and a smaller write current.
- a sidewall keeper 80 formed from a magnetic material with high permeability. Once an electrical current flows through the PWWL, the magnetic flux will be confined within the sidewall keeper without spreading all over the space. This reduces the magnetic interference of a PWWL on adjacent MTJ's.
- the PWWL covered with a sidewall keeper can increase the induced magnetic field to two times that of uncovered ones, while the write current can be roughly reduced by a factor of two.
- a new photo mask as shown in FIG. 3 , is used to block the surface facing the MTJ, with a pattern to prevent light from going through.
- the etching process performed subsequently has a very large etching selection ratio for copper; thus, the PWWL's made before can be preserved during the etching process.
- the next step is to fill a material with high permeability, generally a permally or Ferri magnet. Its top surface is removed by etching back or CMP. Finally, an upper electrode is formed on the MRAM to be the bit line.
- a material with high permeability generally a permally or Ferri magnet. Its top surface is removed by etching back or CMP.
- an upper electrode is formed on the MRAM to be the bit line.
- the sidewall keeper structure effectively converge the magnetic flux generated by the PWWL's on a specific MTJ.
- a simulation result is shown in FIG. 4 .
- the horizontal coordinate is the distance between the PWWL and the magnetic tunnel junction cell; the vertical coordinate is the write current.
- the curve with circular black dots is the write current required for PWWL's.
- the curve with rectangular blocks is the write current required for PWWL's covered with sidewall keepers. From the figure, it is appreciated that the PWWL design can lower the write current by about a factor of two. After covering the PWWL with a sidewall keeper, the write current is further lowered to one-fourth of that in the prior art. Therefore, the disclosed MRAM structure does not only reduce the write power consumption, but also greatly increase the write selectivity of memory.
- the disclosed MRAM adopts zigzag write word lines so that it has a smaller bit size and a lower write current. This can resolve the magnetic interference problem of adjacent PWWL's on a MTJ.
- the disclosed vertical sidewall keeper can prevent magnetic interference of a PWWL on its adjacent MTJ. Therefore, the adjacent MTJ's will not incorrectly change their memory states.
- the write selectivity of the MRAM is thus enhanced.
- the write current of the MRAM with PWWL's can be lowered to about one-fourth of that in the prior art, consequently reducing the power consumption of the MRAM.
Abstract
A low-power magnetic random access memory (MRAM) with high write selectivity is provided. Write word lines and pillar write word lines covered with a magnetic material are disposed in an zigzag relation, solving the magnetic interference problem generated by cells adjacent to the pillar write word line in the magnetic RAM with the pillar write word line form. According to the disclosed structure, each of the cells has a smaller bit size and a lower write current. This effectively reduces the power consumption of the MRAM.
Description
- This application is a Divisional of co-pending application Ser. No. 10/846,663 filed on May 14, 2004, and for which priority is claimed under 35 U.S.C. §120; and this application claims priority of Application No. 92136353 filed in Taiwan on Dec. 19, 2003 under 35 U.S.C. §119; the entire contents of all are hereby incorporated by reference.
- 1. Field of Invention
- The invention relates to a magnetic random access memory (MRAM) and, in particular, to an MRAM with high write selectivity and low power consumption.
- 2. Related Art
- Magnetic random access memory (MRAM) is nonvolatile memory. Using its magnetic resistance property to record information, it has the advantages of non-volatility, high densities, high access speeds, and anti-radiation.
- The basic operation principles of the MRAM are the same as storing data on a hard disk drive (HDD). Each bit of data is determined by its magnetization orientation to be either 0 or 1. The stored data are permanent until being modified by an external magnetic field.
- When data is read from the MRAM, an electrical current has to flow to a selected magnetic tunnel junction (MTJ) cell. The resistance value determines the numerical value of the data. When writing in data, a common method uses two wires (a bit line and a write word line) to induce a magnetic field at the selected cell, thereby changing the magnetization orientation of the magnetic material at the position and the data thereof.
- The MTJ cell between the bit line and the write word line has a stack structure of multi-layer magnetic metal materials. The structure basically contains a soft magnetic layer, a nonmagnetic conductor or tunnel barrier, and a hard magnetic layer. Whether the magnetization orientations of the two layers of ferromagnetic materials are parallel or anti-parallel determines whether the stored datum is 1 or 0.
- As memory devices are becoming smaller, the MRAM starts to encounter the electron migration problem because the write-in electrical current needed to change data approaches the current density limit that can be carried by a metal wire. To solve the problem, the U.S. Pat. No. 6,642,595 discloses a memory structure. As shown in
FIG. 1 , the MTJ cell formed from a magnetictunnel junction cell 10 has alower electrode 20 below it. Aninsulator 30 is below thelower electrode 20. The magnetictunnel junction cell 10 is connected to thebit line 50 via amiddle metal pillar 70. The write word line is composed of an upper layer writeword line 40A and a lower layer writeword line 40B. The induced total magnetic is further enhanced by the pillar write word lines (PWWL's) 60 on both sides of the magnetictunnel junction cell 10. The PWWL's near the MTJ can produce a larger magnetic field focused on the MTJ. Therefore, the threshold current needed by the MRAM is reduced. - Nonetheless, this structure has a problem. If the PWWL's point in the normal direction, they will produce a negative contribution to the magnetic field on the adjacent MTJ, enlarging the device size. Moreover, to avoid the interference of the write word line on MTJ's that are not selected, a better design for increasing the MRAM write selectivity is to let the magnetic field produced by the write word line pass through as few MTJ's as possible.
- In view of the foregoing, a primary objective of the invention is to provide a magnetic random access memory (MRAM) with high write selectivity and low power consumption. The invention reduces the write current required by the MRAM, thereby reducing the power consumption during the write period thereof.
- The disclosed structure can eliminate the magnetic interference problem of the write word lines on adjacent MTJ's. This increases the write selectivity of the MRAM.
- To achieve the above-mentioned objective, the disclosed MRAM has a plurality of MTJ cells, a plurality of bit lines, a plurality of middle metal pillars, and a plurality of PWWL's. Each MTJ cell is comprised of a magnetic tunnel junction cell and a lower electrode. Changing the magnetization orientation of the magnetic tunnel junction cell determines the memory state. Each bit line provides the read and write current channels for the corresponding MTJ cell. Each middle metal pillar connects the MTJ cell and the bit line. Each write word line is comprised of an upper layer write word line, a lower layer write word line and a pair of PWWL's, providing the write current channel for the MTJ cell. This increases the induced magnetic field at the MTJ cell. The PWWL's of the adjacent MTJ cells are disposed in an interleaving fashion (zigzag pattern as shown in the
FIG. 2 ). Aside from the part of the PWWL facing the surrounding of the magnetic tunnel junction cell, the rest is covered by a sidewall keeper. The sidewall keeper covering the PWWL's of the disclosed MRAM can reduce the write current required by the MRAM. - The invention has to add a photo mask process after the PWWL process. Furthermore, the disclosed sidewall keeper structure confines the magnetic flux on the MTJ so that adjacent MTJ's are not affected by the magnetic field produced by the PWWL's. The write selectivity of the MRAM is thus greatly increased.
- The invention will become more filly understood from the detailed description given hereinbelow illustration only, and thus are not limitative of the present invention, and wherein:
-
FIG. 1 is a MRAM with PWWL's disclosed in the prior art; -
FIG. 2 is a schematic layout of the MRAM with PWWL's according to the invention; -
FIG. 3 is a schematic view of a PWWL covered with a sidewall keeper; and -
FIG. 4 is a figure of simulated data for the disclosed MRAM with PWWL's. - To reduce negative interference of adjacent PWWL's on a MTJ, the invention employs the photo mask to arrange a PWWL and its PWWL's of write word lines with the same electrical currents flow in an interleaving fashion.
-
FIG. 2 shows the mask layout of a MRAM. As shown in the drawing, it containsmagnetic memory cells magnetic memory cell 1 and themagnetic memory cell 2 are next to each other; likewise, themagnetic memory cell 3 and the magnetic memory cell 4 are next to each other. Each memory unit has a magnetictunnel junction cell 10A, an upper layer writeword line 40C, a lower layer writeword line 40D, aPWWL 60A, and amiddle metal pillar 70A. Thememory unit 1 and thememory unit 3 are controlled using thebit line 50A. The magnetictunnel junction cell 10A further contains a lower electrode (not shown) to form a MTJ. Themagnetic memory cell 1 and themagnetic memory cell 2 are affected under the current-induced magnetic field of the same write word line. Likewise, themagnetic memory cell 3 and the magnetic memory cell 4 are affected under the current-induced magnetic field of the same write word line. - The layout in the prior art is to arrange the magnetic memory cells next to one another. However, such a layout will result in interference of adjacent PWWL's on a MTJ. With reference to
FIG. 2 , the PWWL and its adjacent PWWL's of the write word lines with the same current flow in a zigzag fashion, eliminating the negative magnetic field produced by the adjacent PWWL's. Such a zigzag layout renders a smaller bit size and a smaller write current. - With further reference to
FIG. 3 , aside from the part of thePWWL 60 that faces the magnetictunnel junction cell 10, the rest is covered by asidewall keeper 80 formed from a magnetic material with high permeability. Once an electrical current flows through the PWWL, the magnetic flux will be confined within the sidewall keeper without spreading all over the space. This reduces the magnetic interference of a PWWL on adjacent MTJ's. - Generally speaking, the PWWL covered with a sidewall keeper can increase the induced magnetic field to two times that of uncovered ones, while the write current can be roughly reduced by a factor of two.
- In the following, we describe the manufacturing process of the MRAM disclosed in the invention. After forming the lower electrode and the MTJ's, there is a step of forming a via as the PWWL and the middle metal pillar. It is normally performed using single-time photolithography alignment, etching, copper plating, and chemical mechanical polishing (CMP).
- Afterwards, a new photo mask, as shown in
FIG. 3 , is used to block the surface facing the MTJ, with a pattern to prevent light from going through. The etching process performed subsequently has a very large etching selection ratio for copper; thus, the PWWL's made before can be preserved during the etching process. - The next step is to fill a material with high permeability, generally a permally or Ferri magnet. Its top surface is removed by etching back or CMP. Finally, an upper electrode is formed on the MRAM to be the bit line.
- The sidewall keeper structure effectively converge the magnetic flux generated by the PWWL's on a specific MTJ. A simulation result is shown in
FIG. 4 . The horizontal coordinate is the distance between the PWWL and the magnetic tunnel junction cell; the vertical coordinate is the write current. The curve with circular black dots is the write current required for PWWL's. The curve with rectangular blocks is the write current required for PWWL's covered with sidewall keepers. From the figure, it is appreciated that the PWWL design can lower the write current by about a factor of two. After covering the PWWL with a sidewall keeper, the write current is further lowered to one-fourth of that in the prior art. Therefore, the disclosed MRAM structure does not only reduce the write power consumption, but also greatly increase the write selectivity of memory. - The disclosed MRAM adopts zigzag write word lines so that it has a smaller bit size and a lower write current. This can resolve the magnetic interference problem of adjacent PWWL's on a MTJ.
- Moreover, the disclosed vertical sidewall keeper can prevent magnetic interference of a PWWL on its adjacent MTJ. Therefore, the adjacent MTJ's will not incorrectly change their memory states. The write selectivity of the MRAM is thus enhanced. Using the structure, the write current of the MRAM with PWWL's can be lowered to about one-fourth of that in the prior art, consequently reducing the power consumption of the MRAM.
- Certain variations would be apparent to those skilled in the art, which variations are considered within the spirit and scope of the claimed invention.
Claims (19)
1. A magnetic random access memory (MRAM) with high write selectivity and low power consumption, comprising:
a plurality of magnetic memory cells, each of the magnetic memory cells having a magnetic tunnel junction cell and a lower electrode, the memory state of the magnetic memory cells being determined by the magnetization orientation of the magnetic tunnel junction cell;
a plurality of bit lines, each of the bit lines providing a channel for the read and write currents of the corresponding magnetic memory cell;
a plurality of middle metal pillars, each of the middle metal pillars connecting to the corresponding magnetic memory cell and the corresponding bit line;
a plurality of write word lines, each of the write word lines having an upper layer write word line and a lower layer write word line; and
a plurality of pillar write word lines, each of the pillar write word lines connecting the associated upper layer write word line and lower layer write word line for providing a write current channel for the corresponding magnetic memory cell, thereby enhancing the induced magnetic field at the corresponding magnetic memory cell, wherein the pillar write word lines of the adjacent magnetic memory cells are disposed in an zigzag relation.
2. The MRAM of claim 1 , wherein the pillar write word lines is covered with a sidewall keeper except for the part facing the magnetic tunnel junction cell.
3. The MRAM of claim 2 , wherein the sidewall keeper is made of a magnetic material with high permeability.
4. The MRAM of claim 3 , wherein the magnetic material is one selected from the group consisting of the permalloy and the Ferri magnet.
5. A method for making a magnetic random access memory (MRAM) with high write selectivity and low power consumption, after forming the MTJ cell of the MRAM, the method further comprising steps of:
forming two pillar write word lines on both sides of the magnetic memory cell and a middle metal pillar;
forming a sidewall keeper on the pillar write word line except for the part facing the magnetic memory cell; and
forming a bit line of the MRAM.
6. The method of claim 5 , wherein the sidewall keeper is made of magnetic material with high permeability.
7. The method of claim 6 , wherein the magnetic material is one selected from the group consisting of the permalloy and the Ferri magnet.
8. The method of claim 5 , wherein the step of forming the middle metal pillar and the pillar write word lines is accomplished using the processes of lithography alignment, etching, filling, and chemical mechanical polishing (CMP) sequentially.
9. The method of claim 5 , wherein the step of forming the sidewall keeper is accomplished using the processes of lithography alignments etching, filling a magnetic material, and etching back sequentially.
10. A magnetic random access memory (MRAM) comprising:
a plurality of magnetic memory cells, each of the magnetic memory cells having a magnetic tunnel junction cell and a lower electrode and whose memory state is determined by changing its magnetization orientation;
a plurality of bit lines, each of the bit lines providing a read/write current channel for a corresponding magnetic memory cell;
a plurality of middle metal pillars, each of the middle metal pillars connecting the associated magnetic memory cell and bit line;
a plurality of write word lines, having an upper layer write word line and a lower layer write word line; and
a plurality of pillar write word lines, each of the pillar write word lines connecting the upper layer write word line and the lower layer write word line for providing the write current channel for the magnetic memory cell, thereby enhancing the induced magnetic field at the magnetic memory cell, the pillar write word lines of the adjacent memory units disposed in an zigzag relation.
11. The MRAM of claim 10 , wherein each of the pillar write word lines is covered by a sidewall keeper except for the part facing the magnetic tunnel junction cell.
12. The MRAM of claim 11 , wherein the sidewall keeper is made of magnetic material with high permeability.
13. The MRAM of claim 12 , wherein the magnetic material is one selected from the group consisting of the permalloy and the Ferri magnet.
14. The MRAM of claim 1 , wherein each of the pillar write word lines extends in a vertical direction, an upper end of each of the pillar write word lines being inn contact with a corresponding upper layer write word line, a lower end of each of the pillar write word lines being in contact with a corresponding lower layer write word line, the upper layer write word line and the lower layer write word line being perpendicular to the corresponding pillar write word line.
15. The MRAM of claim 2 , wherein the side wall keeper confines magnetic flux on the magnetic tunnel junction cell so that the adjacent magnetic tunnel junction cells are not affected by the magnetic field produced by the pillar write word line.
16. The MRAM of claim 2 , wherein the side wall keeper is in contact with the corresponding pillar write word.
17. The MRAM of claim 10 , wherein each of the pillar write word lines extends in a vertical direction, an upper end of each of the pillar write word lines being inn contact with a corresponding upper layer write word line, a lower end of each of the pillar write word lines being in contact with a corresponding lower layer write word line, the upper layer write word line and the lower layer write word line being perpendicular to the corresponding pillar write word line.
18. The MRAM of claim 11 , wherein the side wall keeper confines magnetic flux on the magnetic tunnel junction cell so that the adjacent magnetic tunnel junction cells are not affected by the magnetic field produced by the pillar write word line.
19. The MRAM of claim 11 , wherein the side wall keeper is in contact with the corresponding pillar write word.
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US11/756,246 US20070223270A1 (en) | 2003-12-19 | 2007-05-31 | High write selectivity and low power magnetic random access memory and method for fabricating the same |
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TW92136333 | 2003-12-19 | ||
TW092136333A TWI226636B (en) | 2003-12-19 | 2003-12-19 | Magnetic random access memory with high selectivity and low power and production method thereof |
US10/846,663 US7359237B2 (en) | 2003-12-19 | 2004-05-17 | High write selectivity and low power magnetic random access memory and method for fabricating the same |
US11/756,246 US20070223270A1 (en) | 2003-12-19 | 2007-05-31 | High write selectivity and low power magnetic random access memory and method for fabricating the same |
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US10/846,663 Division US7359237B2 (en) | 2003-12-19 | 2004-05-17 | High write selectivity and low power magnetic random access memory and method for fabricating the same |
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US11/756,246 Abandoned US20070223270A1 (en) | 2003-12-19 | 2007-05-31 | High write selectivity and low power magnetic random access memory and method for fabricating the same |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013123363A1 (en) * | 2012-02-17 | 2013-08-22 | Crocus Technology Inc. | Magnetic logic units configured as an amplifier |
WO2015116601A1 (en) * | 2014-01-28 | 2015-08-06 | Crocus Technology Inc. | Analog circuits incorporating magnetic logic units |
WO2015116600A1 (en) * | 2014-01-28 | 2015-08-06 | Crocus Technology Inc. | Mlu configured as analog circuit building blocks |
US20200212030A1 (en) * | 2018-12-27 | 2020-07-02 | United Microelectronics Corp. | Layout pattern for magnetoresistive random access memory |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7180160B2 (en) * | 2004-07-30 | 2007-02-20 | Infineon Technologies Ag | MRAM storage device |
US10008537B2 (en) * | 2015-06-19 | 2018-06-26 | Qualcomm Incorporated | Complementary magnetic tunnel junction (MTJ) bit cell with shared bit line |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5587943A (en) * | 1995-02-13 | 1996-12-24 | Integrated Microtransducer Electronics Corporation | Nonvolatile magnetoresistive memory with fully closed flux operation |
US5640343A (en) * | 1996-03-18 | 1997-06-17 | International Business Machines Corporation | Magnetic memory array using magnetic tunnel junction devices in the memory cells |
US5956267A (en) * | 1997-12-18 | 1999-09-21 | Honeywell Inc | Self-aligned wordline keeper and method of manufacture therefor |
US6174737B1 (en) * | 1998-08-31 | 2001-01-16 | Motorola, Inc. | Magnetic random access memory and fabricating method thereof |
US6430085B1 (en) * | 2001-08-27 | 2002-08-06 | Motorola, Inc. | Magnetic random access memory having digit lines and bit lines with shape and induced anisotropy ferromagnetic cladding layer and method of manufacture |
US6541815B1 (en) * | 2001-10-11 | 2003-04-01 | International Business Machines Corporation | High-density dual-cell flash memory structure |
US20030185065A1 (en) * | 2002-03-26 | 2003-10-02 | Mitsubishi Denki Kabushiki Kaisha | Thin film magnetic memory device selecting access to a memory cell by a transistor of a small gate capacitance |
US6639830B1 (en) * | 2002-10-22 | 2003-10-28 | Btg International Ltd. | Magnetic memory device |
US6642595B1 (en) * | 2002-07-29 | 2003-11-04 | Industrial Technology Research Institute | Magnetic random access memory with low writing current |
US20040061156A1 (en) * | 2001-03-28 | 2004-04-01 | Cha Seon Yong | Magnetic random access memory having transistor of vertical structure with writing line formed on an upper portion of the magnetic tunnel junction cell |
US6797536B2 (en) * | 2002-07-30 | 2004-09-28 | Kabushiki Kaisha Toshiba | Magnetic memory device having yoke layer, and manufacturing method |
US6815290B2 (en) * | 2002-10-21 | 2004-11-09 | Nanya Technology Corporation | Stacked gate flash memory device and method of fabricating the same |
US20050030786A1 (en) * | 2002-05-02 | 2005-02-10 | Micron Technology, Inc. | Low remanence flux concentrator for MRAM devices |
US20050051839A1 (en) * | 2003-09-04 | 2005-03-10 | Johnathan Faltermeier | Reduced cap layer erosion for borderless contacts |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2737759B2 (en) * | 1991-01-08 | 1998-04-08 | 富士電機株式会社 | Pass / fail judgment method for paper sheets |
JP2001273759A (en) * | 2000-03-27 | 2001-10-05 | Sharp Corp | Magnetic memory cell and magnetic memory device |
KR100389923B1 (en) * | 2001-01-16 | 2003-07-04 | 삼성전자주식회사 | Semiconductor device having trench isolation structure and trench isolation method |
JP2002246567A (en) * | 2001-02-14 | 2002-08-30 | Toshiba Corp | Magnetic random access memory |
US6865109B2 (en) * | 2003-06-06 | 2005-03-08 | Seagate Technology Llc | Magnetic random access memory having flux closure for the free layer and spin transfer write mechanism |
US6969895B2 (en) * | 2003-12-10 | 2005-11-29 | Headway Technologies, Inc. | MRAM cell with flat topography and controlled bit line to free layer distance and method of manufacture |
US6955926B2 (en) * | 2004-02-25 | 2005-10-18 | International Business Machines Corporation | Method of fabricating data tracks for use in a magnetic shift register memory device |
US7266486B2 (en) * | 2004-03-23 | 2007-09-04 | Freescale Semiconductor, Inc. | Magnetoresistive random access memory simulation |
-
2003
- 2003-12-19 TW TW092136333A patent/TWI226636B/en not_active IP Right Cessation
-
2004
- 2004-05-17 US US10/846,663 patent/US7359237B2/en not_active Expired - Fee Related
-
2007
- 2007-05-31 US US11/756,246 patent/US20070223270A1/en not_active Abandoned
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5587943A (en) * | 1995-02-13 | 1996-12-24 | Integrated Microtransducer Electronics Corporation | Nonvolatile magnetoresistive memory with fully closed flux operation |
US5640343A (en) * | 1996-03-18 | 1997-06-17 | International Business Machines Corporation | Magnetic memory array using magnetic tunnel junction devices in the memory cells |
US5956267A (en) * | 1997-12-18 | 1999-09-21 | Honeywell Inc | Self-aligned wordline keeper and method of manufacture therefor |
US6174737B1 (en) * | 1998-08-31 | 2001-01-16 | Motorola, Inc. | Magnetic random access memory and fabricating method thereof |
US20040061156A1 (en) * | 2001-03-28 | 2004-04-01 | Cha Seon Yong | Magnetic random access memory having transistor of vertical structure with writing line formed on an upper portion of the magnetic tunnel junction cell |
US6855564B2 (en) * | 2001-03-28 | 2005-02-15 | Hynix Semiconductor Inc. | Magnetic random access memory having transistor of vertical structure with writing line formed on an upper portion of the magnetic tunnel junction cell |
US6430085B1 (en) * | 2001-08-27 | 2002-08-06 | Motorola, Inc. | Magnetic random access memory having digit lines and bit lines with shape and induced anisotropy ferromagnetic cladding layer and method of manufacture |
US6541815B1 (en) * | 2001-10-11 | 2003-04-01 | International Business Machines Corporation | High-density dual-cell flash memory structure |
US20030185065A1 (en) * | 2002-03-26 | 2003-10-02 | Mitsubishi Denki Kabushiki Kaisha | Thin film magnetic memory device selecting access to a memory cell by a transistor of a small gate capacitance |
US20050030786A1 (en) * | 2002-05-02 | 2005-02-10 | Micron Technology, Inc. | Low remanence flux concentrator for MRAM devices |
US6642595B1 (en) * | 2002-07-29 | 2003-11-04 | Industrial Technology Research Institute | Magnetic random access memory with low writing current |
US6797536B2 (en) * | 2002-07-30 | 2004-09-28 | Kabushiki Kaisha Toshiba | Magnetic memory device having yoke layer, and manufacturing method |
US6815290B2 (en) * | 2002-10-21 | 2004-11-09 | Nanya Technology Corporation | Stacked gate flash memory device and method of fabricating the same |
US6639830B1 (en) * | 2002-10-22 | 2003-10-28 | Btg International Ltd. | Magnetic memory device |
US20050051839A1 (en) * | 2003-09-04 | 2005-03-10 | Johnathan Faltermeier | Reduced cap layer erosion for borderless contacts |
Cited By (8)
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US8933750B2 (en) | 2012-02-17 | 2015-01-13 | Crocus Technology Inc. | Magnetic logic units configured as an amplifier |
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US20200212030A1 (en) * | 2018-12-27 | 2020-07-02 | United Microelectronics Corp. | Layout pattern for magnetoresistive random access memory |
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Also Published As
Publication number | Publication date |
---|---|
TW200522071A (en) | 2005-07-01 |
US20050135149A1 (en) | 2005-06-23 |
TWI226636B (en) | 2005-01-11 |
US7359237B2 (en) | 2008-04-15 |
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