US20070217177A1 - Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus - Google Patents

Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus Download PDF

Info

Publication number
US20070217177A1
US20070217177A1 US11/798,259 US79825907A US2007217177A1 US 20070217177 A1 US20070217177 A1 US 20070217177A1 US 79825907 A US79825907 A US 79825907A US 2007217177 A1 US2007217177 A1 US 2007217177A1
Authority
US
United States
Prior art keywords
semiconductor device
mark
insulation layer
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/798,259
Inventor
Nobuaki Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to US11/798,259 priority Critical patent/US20070217177A1/en
Publication of US20070217177A1 publication Critical patent/US20070217177A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a semiconductor device, a manufacturing method and a mounting method of the semiconductor device, a circuit board, and an electronic apparatus.
  • Wafer level chip size package is widely spreading as a package of a semiconductor device.
  • an orientation of a semiconductor device, as an end product is specified by markings provided on the reverse of the element forming side on which its elements are formed.
  • it is impossible to determine an orientation of a semiconductor device from the element forming side because of structural limitations of a semiconductor device.
  • a plurality of external terminals are disposed symmetrically, it is extremely difficult to determine an orientation of the semiconductor device according to its structure.
  • an orientation of a semiconductor can be easily determined.
  • a semiconductor device includes: a substrate having an electrode electrically connected to at least one integrated circuit; an external terminal electrically connected to the electrode; a light transmissive insulation layer disposed on the external terminal side of the substrate; and a mark provided on the substrate and covered by the insulation layer so as to be recognized through the insulation layer.
  • an orientation of the semiconductor device can be easily determined by recognizing the mark through the insulation layer from the external terminal side of the substrate.
  • the substrate can be a semiconductor substrate, and the integrated circuit can be formed on the semiconductor substrate.
  • the mark may be provided on the resin layer.
  • a passivation film provided on the semiconductor substrate, and the mark may be provided on the passivation film.
  • the mark may be made of the same material as at least a part of the material which the interconnection layer is made of.
  • the interconnection layer and the mark are formed in the same manufacturing process.
  • the mark may be provided on an area not contacting with the interconnection layer.
  • the interconnection layer may include a plurality of lands including a first land having a shape incorporating the mark and a second land having a shape different from the shape of the first land. According to this, since a part or the whole of the first land serves as the mark, the number of components can be reduced.
  • the external terminal may be a solder ball
  • the insulation layer may be a solder resist
  • the semiconductor substrate may be a semiconductor chip.
  • the mark may be provided on at least one of the four corners of the semiconductor chip.
  • the semiconductor substrate may be a semiconductor wafer including the integrated circuit for each of plural areas.
  • a circuit board according to another aspect of the present invention has a semiconductor device mentioned above mounted thereon.
  • An electronic apparatus includes a semiconductor device mentioned above.
  • a method of mounting a semiconductor device onto a circuit board includes: determining a mounting orientation of the semiconductor device mentioned above by recognizing the mark though the insulation layer.
  • a method of manufacturing a semiconductor device includes: providing a mark on one side of a substrate having an electrode electrically connected to an integrated circuit; providing an external terminal electrically connected to the electrode on the mark side of the substrate; and providing a light transmissive insulation layer to cover the mark.
  • FIG. 1 shows a plan view of a semiconductor device according to an exemplary embodiment of the present invention
  • FIG. 2 shows a cross-sectional view of the semiconductor device according to an exemplary embodiment of the present invention
  • FIG. 3 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention
  • FIG. 4 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention
  • FIG. 5 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention
  • FIG. 6 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention.
  • FIG. 7 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention.
  • FIG. 8 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention.
  • FIG. 9 shows a circuit board according to an exemplary embodiment of the present invention.
  • FIG. 10 shows an electronic apparatus according to an exemplary embodiment of the present invention.
  • FIG. 11 shows an electronic apparatus according to an exemplary embodiment of the present invention.
  • FIG. 1 shows a plan view of a semiconductor device of the present exemplary embodiment with a part (a insulation layer 50 ) thereof removed.
  • FIG. 2 shows a cross-sectional view (a section along II-II plane in FIG. 1 ) of the semiconductor device of the present exemplary embodiment.
  • FIGS. 3 through 6 show partial plan views of semiconductor devices showing other examples of the mark.
  • a semiconductor device 1 includes a substrate (a semiconductor substrate 10 in the present exemplary embodiment).
  • the semiconductor substrate 10 can be a semiconductor chip as shown in FIG. 1 or a semiconductor wafer.
  • the semiconductor substrate 10 is provided with an integrated circuit 12 formed thereon (See FIG. 2 .) and further with an electrode (e.g., a pad) 14 electrically connected with the integrated circuit 12 .
  • the integrated circuit 12 is often formed on a single region, while the integrated circuit 12 is often formed on each of multiple regions in case of a semiconductor wafer.
  • a plurality of electrodes 14 may be formed on either surface of the semiconductor substrate 10 .
  • the plurality of electrodes 14 can be arranged along an edge portion (e.g., two opposing sides or four sides) of the semiconductor chip (or a region to become the semiconductor chip).
  • the side of the semiconductor substrate 10 (the side with the electrode 14 formed thereon) is provided with a passivation film (e.g., a silicon nitride film or a silicon oxide film) 16 formed thereon.
  • the side of the semiconductor substrate 10 (e.g., a surface of the passivation film 16 ) provided with the electrode 14 is further provided with a resin layer 18 including a single layer or multiple layers.
  • the resin layer 18 is formed around the electrodes 14 . As shown in FIG. 1 , the resin layer 18 can be formed on a center portion of the semiconductor chip.
  • the resin layer 18 may have a side face slanted so that the bottom surface thereof is larger than the opposing upper surface thereof.
  • the resin layer 18 may have a tension reduction function.
  • the resin layer 18 may be made of resin, such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), or polybenzoxazole (PBO).
  • the resin layer 18 may be formed between the semiconductor substrate 10 and an external terminal 40 described later.
  • the semiconductor device 1 includes interconnection layer 20 .
  • the interconnection layer 20 is formed on the same side of the semiconductor substrate 10 as the side provided with the electrode 14 .
  • the interconnection layer 20 is made of conductive material (e.g., metal).
  • a plurality of discrete regions of the interconnection layer 20 is formed as shown in FIG. 1 each consisting of one or more layers.
  • the interconnection layer 20 may be made of a combination of a plurality of different materials (e.g., copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium-tungsten (TiW), gold (Au), aluminum (Al), nickel-vanadium (NiV), tungsten (W), etc.).
  • the discrete regions of the interconnection layer 20 are formed to cover the electrodes 14 and electrically connected with the electrodes 14 .
  • the discrete regions of the interconnection layer 20 extend from the electrodes 14 onto the resin layer 18 .
  • the discrete regions of the interconnection layer 20 are formed so as to extend to the upper surface of the resin layer 18 through its side face (the slanted face).
  • the discrete regions of the interconnection layer 20 include plural lands (a first and second lands 22 , 24 in the present exemplary embodiment).
  • the lands are electrical terminals, and provided with plated layers (not shown in the figures) to enhance electrical characteristics.
  • the lands are formed on the resin layer 18 .
  • the lands are wider than lines of the discrete regions of the interconnection layer 20 , and can be shaped as, for example round lands.
  • the semiconductor device 1 includes a plurality of external terminals 40 .
  • the external terminals 40 are formed on the same side of the semiconductor substrate 10 as the side on which the electrodes 14 are formed.
  • the external terminals 40 are electrically connected to the electrodes 14 .
  • the external terminals 40 are electrically connected to the discrete regions of the interconnection layer 20 .
  • the external terminals 40 can be formed on the lands.
  • the external terminals 40 can be made of conductive metal.
  • the external terminals 40 can also be made of brazing material.
  • the external terminals 40 can be shaped as, for example, a sphere, and can be solder balls. In the example shown in FIG. 1 , the plurality of external terminals 40 is disposed symmetrically in plan view of the semiconductor substrate 10 .
  • the semiconductor device 1 includes an insulation layer 50 (e.g., a layer made of resin).
  • the insulation layer 50 has translucency, and can be made of translucent or transparent material.
  • the insulation layer 50 is formed of a single or multiple layers (a first and second insulation layers 54 , 52 in the example shown in FIG. 2 ).
  • the insulation layer 50 is formed on the same side of the semiconductor substrate 10 as the side on which the external terminals 40 are formed.
  • the insulation layer 50 is formed to cover the interconnection layer 20 with at least a part of the external terminals 40 exposed (with the tip of the external terminals 40 exposed).
  • the insulation layer 50 can also serve as a solder resist.
  • the insulation layer 50 includes the first and the second insulation layers 54 , 52 .
  • the first and the second insulation layers 54 , 52 are translucent as described above.
  • the first insulation layer 54 can be formed after fabrication of the interconnection layer 20 so as to cover at least a part of each of the discrete regions of the interconnection layer 20 .
  • the first insulation layer 54 can be formed outside at least center portions of the lands. Oxidization, corrosion, or breaking of the interconnection layer 20 can be avoided by forming the first insulation layer 54 .
  • the second insulation layer 52 is stacked on the first insulation layer 54 .
  • the second insulation layer 52 can be formed on the first insulation layer 54 after fabrication of the external terminals 40 .
  • the second insulation layer 52 is formed with tip portions of the external terminals 40 exposed.
  • the second insulation layer 52 covers root portions (lower end portions) of the external terminals 40 .
  • the root portions of the external terminals 40 are reinforced.
  • the semiconductor device 1 includes a mark 30 .
  • the mark 30 is formed on the same side of the semiconductor substrate 10 as the side on which the external terminals 40 are formed (e.g., on the resin layer 18 ), and is covered with the insulation layer 50 (the first and the second insulation layers 54 , 52 in FIG. 2 ). Since the insulation layer 50 has translucency, the mark 30 can be recognized through the insulation layer 50 . Thus, since the insulation layer 50 is provided on the mark 30 , breakage, separation, or discoloration caused by oxidization can be reduced or prevented ensuring that an orientation of a semiconductor device is determined using the mark 30 .
  • the position or the shape of the mark 30 is arranged so that at least an orientation (plan orientation) of the semiconductor device 1 (or the semiconductor substrate 10 ) can be acknowledged.
  • the mark 30 may be formed to have a shape by which either direction can be recognized (e.g., a shape of an arrow or the like).
  • the mark 30 may be disposed at an end portion of the semiconductor substrate 10 (e.g., at a corner thereof).
  • an orientation of the semiconductor device can be determined only by recognizing the position of the mark 30 (even if its shape cannot be recognized).
  • the mark 30 may be a single mark or a plurality of marks as well.
  • the mark 30 can be made of the same material as at least a part of the interconnection layer 20 (at least one layer if the interconnection layer 20 comprises multiple layers). For example, if the interconnection layer 20 is made of metal, the mark 30 may also be made of the metal. If the interconnection layer 20 includes multiple layers, the mark 30 may also include the multiple layers. By this structure, the mark 30 may be formed in the process for forming the interconnection layer 20 , thus reducing the cost and the number of manufacturing processes.
  • any one of the plural lands has the mark 30 as its part.
  • the shape of the first land 22 provided at least one includes the mark 30
  • the shape of the second land 24 is different from the shape of the first land 22 .
  • the shape of the first land 22 includes a round part and a protrusion (a quadrangular part in FIG. 1 ) protruding from the round part, one of the external terminals 40 being provided on a center portion of the round part, and the protrusion serving as the mark 30 .
  • the protrusion may be provided on the opposite side of the first land 22 to the line thereof.
  • the first land 22 as a whole may be recognized as the mark 30 .
  • the part or the whole of the first land 22 serves as the mark 30 .
  • the number of components of the semiconductor device can be reduced.
  • space of the semiconductor device can be efficiently used compared to the case of forming the mark 30 independently. This is especially efficient for application to CSP (chip size package) in which the sizes of the semiconductor device and the semiconductor chip are substantially the same.
  • the shape of the mark (or the surface shape of the first land 22 ) is not limited, but may be modified to various shapes as shown in FIGS. 3 through 6 .
  • the protrusion as a mark 32 may be shaped as a triangle.
  • the protrusion as a mark 34 may be shaped as a combination of multiple polygons (e.g., a convex shape).
  • the position of the protrusion as a mark 36 may not be limited to the opposite side to a line of the first land 22 , but the protrusion can be, for example, positioned at the point having a normal perpendicular to a normal at the line.
  • the plural protrusions as marks 38 may be disposed at plural positions (e.g., the both positions shown in FIGS. 1 and 5 ).
  • a mark 60 may be provided independently from discrete regions of the interconnection layer 20 , as shown in FIGS. 7 and 8 . That is, the mark 60 (the mark 62 ) may be provided on a region not contacting the discrete regions of the interconnection layer 20 (the land 22 ). As an example shown in FIG. 7 , the mark 60 can be formed on a passivation 16 (See FIG. 2 .) in the same process as that for the interconnection layer 20 , as previously described. As an example shown in FIG. 8 , the mark 62 may be formed on the resin layer 18 in the same process as that for the interconnection layer 20 , as previously described.
  • the mark since the mark may be provided without any limitations derived from the position of the land, the mark may be provided on a position easy to be recognized resulting in easy determination of an orientation of the semiconductor device. Furthermore, since the mark need not be positioned adjacent to the discrete regions of the interconnection layer 20 , the flexibility of the interconnection layer 20 in wiring from electrodes 14 to the land 22 can be enhanced. Also, as shown in FIGS. 7 and 8 , the mark 60 (the mark 62 ) may be provided at least one of the four corners of the semiconductor chip.
  • the semiconductor device may include a substrate (e.g., an interposer) and a semiconductor chip (on which an integrated circuit is formed) mounted on the substrate.
  • a substrate e.g., an interposer
  • a semiconductor chip on which an integrated circuit is formed
  • a mark to determine an orientation of the semiconductor device is formed on the substrate (more precisely, on the same side of the substrate as the side provided with the electrode).
  • an orientation of the semiconductor device can easily be determined.
  • an orientation of the semiconductor device can be determined from the structure of the semiconductor device in itself offering high efficiency in handling of the semiconductor device.
  • a semiconductor device manufacturing method includes: forming the mark 30 on one side (e.g., the side on which the electrodes 14 are formed) of the substrate (the semiconductor substrate 10 in the present exemplary embodiment); forming the external terminals 40 on the same side of the semiconductor device as the side provided with the mark 30 ; and providing the insulation layer 50 so as to cover the mark 30 . Since the insulation layer 50 has translucency as previously described, the mark 30 can be recognized through the insulation layer 50 . If the semiconductor wafer is used as the semiconductor substrate 10 , the semiconductor substrate 10 is cut into plural regions each corresponding to the integrated circuit 12 . A plurality of semiconductor devices is obtained by cutting the semiconductor substrate 10 . In this case, packaging is performed every wafer. Note that other details and advantages of the present exemplary embodiment can be reached from the above description regarding the semiconductor device, and therefore are omitted from the description of this section.
  • a semiconductor device mounting method includes mounting the semiconductor device 1 (including a semiconductor chip) on a circuit board (e.g., a mother-board (See FIG. 9 .)), and a mounting orientation of the semiconductor device 1 is determined by recognizing the mark 30 through the insulation layer 50 . According to the above, the orientation of the semiconductor device can be determined from the structure thereof in itself. Note that other details and advantages of the present exemplary embodiment can be reached from the above description regarding the semiconductor device, and therefore are omitted from the description of this section.
  • FIG. 9 shows a circuit board 1000 according to still another exemplary embodiment of the present invention having the semiconductor device 1 mounted thereon.
  • FIG. 10 shows a laptop personal computer 2000
  • FIG. 11 shows a cellular phone 3000 .
  • the present invention is not limited to the aforementioned exemplary embodiments, but various modifications thereof are possible.
  • the present invention may include substantially the same structures as explained in the description of the exemplary embodiments (e.g., structures with the same function, way, and results or structures with the same objects and results).
  • the present invention may include structures obtained by replacing a nonessential part of the structure explained in the description of the exemplary embodiments.
  • the present invention may include structures offering the same action and results or structures achieving the same object as the structures explained in the description of the exemplary embodiments.
  • the present invention includes structures obtained by combining prior art with the structure explained in the description of the exemplary embodiments.

Abstract

To easily determine an orientation of a semiconductor device, a semiconductor device includes a substrate including electrode electrically connected to an integrated circuit, an external terminal electrically connected to the electrode, and a light transmissive insulation layer provided on the external terminal side of the substrate, and a mark provided on the substrate and covered by the insulation layer and recognizable through the insulation layer.

Description

  • This is a Divisional of application Ser. No. 11/413,042 filed Apr. 28, 2006 which is a Continuation of application Ser. No. 10/779,710 filed Feb. 18, 2004. The disclosure of the prior application is hereby incorporated by reference herein in its entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Field of Invention
  • The present invention relates to a semiconductor device, a manufacturing method and a mounting method of the semiconductor device, a circuit board, and an electronic apparatus.
  • 2. Description of Related Art
  • Wafer level chip size package (CSP) is widely spreading as a package of a semiconductor device. In the related art, an orientation of a semiconductor device, as an end product, is specified by markings provided on the reverse of the element forming side on which its elements are formed. In other words, in related art, it is impossible to determine an orientation of a semiconductor device from the element forming side because of structural limitations of a semiconductor device. In particular, if a plurality of external terminals are disposed symmetrically, it is extremely difficult to determine an orientation of the semiconductor device according to its structure.
  • In the present invention an orientation of a semiconductor can be easily determined.
    • SUMMARY OF THE INVENTION
  • (1) A semiconductor device according to one aspect of the present invention includes: a substrate having an electrode electrically connected to at least one integrated circuit; an external terminal electrically connected to the electrode; a light transmissive insulation layer disposed on the external terminal side of the substrate; and a mark provided on the substrate and covered by the insulation layer so as to be recognized through the insulation layer. According to an aspect of the present invention, an orientation of the semiconductor device can be easily determined by recognizing the mark through the insulation layer from the external terminal side of the substrate. Thus, an orientation of the
  • (2) In this semiconductor device, the substrate can be a semiconductor substrate, and the integrated circuit can be formed on the semiconductor substrate.
  • (3) In the above semiconductor device, there are provided: a resin layer formed around the electrode and on the same side of the semiconductor substrate as the side provided with the electrode; and a interconnection layer extending from the electrode to the upper surface of the resin layer and including at least one land formed on the resin layer; the external terminal may be provided on the land; and the insulation layer may be formed to cover the interconnection layer with at least a part of the external terminal exposed.
  • (4) In the above semiconductor device, the mark may be provided on the resin layer.
  • (5) In the above semiconductor device, there is provided a passivation film provided on the semiconductor substrate, and the mark may be provided on the passivation film.
  • (6) In the above semiconductor device, the mark may be made of the same material as at least a part of the material which the interconnection layer is made of. Thus, for example, the interconnection layer and the mark are formed in the same manufacturing process.
  • (7) In the above semiconductor device, the mark may be provided on an area not contacting with the interconnection layer.
  • (8) In the above semiconductor device, the interconnection layer may include a plurality of lands including a first land having a shape incorporating the mark and a second land having a shape different from the shape of the first land. According to this, since a part or the whole of the first land serves as the mark, the number of components can be reduced.
  • (9) In the above semiconductor device, the external terminal may be a solder ball, and the insulation layer may be a solder resist.
  • (10) In the above semiconductor device, the semiconductor substrate may be a semiconductor chip.
  • (11) In the above semiconductor device, the mark may be provided on at least one of the four corners of the semiconductor chip.
  • (12) In the above semiconductor device, the semiconductor substrate may be a semiconductor wafer including the integrated circuit for each of plural areas.
  • (13) A circuit board according to another aspect of the present invention has a semiconductor device mentioned above mounted thereon.
  • (14) An electronic apparatus according to still another aspect of the present invention includes a semiconductor device mentioned above.
  • (15) A method of mounting a semiconductor device onto a circuit board according to still another aspect of the present invention includes: determining a mounting orientation of the semiconductor device mentioned above by recognizing the mark though the insulation layer.
  • (16) A method of manufacturing a semiconductor device according to still another aspect of the present invention includes: providing a mark on one side of a substrate having an electrode electrically connected to an integrated circuit; providing an external terminal electrically connected to the electrode on the mark side of the substrate; and providing a light transmissive insulation layer to cover the mark.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a plan view of a semiconductor device according to an exemplary embodiment of the present invention;
  • FIG. 2 shows a cross-sectional view of the semiconductor device according to an exemplary embodiment of the present invention;
  • FIG. 3 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention;
  • FIG. 4 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention;
  • FIG. 5 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention;
  • FIG. 6 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention;
  • FIG. 7 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention;
  • FIG. 8 shows a partial plan view of a semiconductor device according to an exemplary embodiment of the present invention;
  • FIG. 9 shows a circuit board according to an exemplary embodiment of the present invention;
  • FIG. 10 shows an electronic apparatus according to an exemplary embodiment of the present invention; and
  • FIG. 11 shows an electronic apparatus according to an exemplary embodiment of the present invention.
    • DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
  • Hereinafter, exemplary embodiments of the present invention are explained referring to accompanying figures.
  • FIG. 1 shows a plan view of a semiconductor device of the present exemplary embodiment with a part (a insulation layer 50) thereof removed. FIG. 2 shows a cross-sectional view (a section along II-II plane in FIG. 1) of the semiconductor device of the present exemplary embodiment. FIGS. 3 through 6 show partial plan views of semiconductor devices showing other examples of the mark.
  • A semiconductor device 1 includes a substrate (a semiconductor substrate 10 in the present exemplary embodiment). The semiconductor substrate 10 can be a semiconductor chip as shown in FIG. 1 or a semiconductor wafer. The semiconductor substrate 10 is provided with an integrated circuit 12 formed thereon (See FIG. 2.) and further with an electrode (e.g., a pad) 14 electrically connected with the integrated circuit 12. In case of a semiconductor ship, the integrated circuit 12 is often formed on a single region, while the integrated circuit 12 is often formed on each of multiple regions in case of a semiconductor wafer. A plurality of electrodes 14 may be formed on either surface of the semiconductor substrate 10. The plurality of electrodes 14 can be arranged along an edge portion (e.g., two opposing sides or four sides) of the semiconductor chip (or a region to become the semiconductor chip). The side of the semiconductor substrate 10 (the side with the electrode 14 formed thereon) is provided with a passivation film (e.g., a silicon nitride film or a silicon oxide film) 16 formed thereon.
  • In the present exemplary embodiment, the side of the semiconductor substrate 10 (e.g., a surface of the passivation film 16) provided with the electrode 14 is further provided with a resin layer 18 including a single layer or multiple layers. The resin layer 18 is formed around the electrodes 14. As shown in FIG. 1, the resin layer 18 can be formed on a center portion of the semiconductor chip. The resin layer 18 may have a side face slanted so that the bottom surface thereof is larger than the opposing upper surface thereof. The resin layer 18 may have a tension reduction function. The resin layer 18 may be made of resin, such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), or polybenzoxazole (PBO). The resin layer 18 may be formed between the semiconductor substrate 10 and an external terminal 40 described later.
  • In the present exemplary embodiment, the semiconductor device 1 includes interconnection layer 20. The interconnection layer 20 is formed on the same side of the semiconductor substrate 10 as the side provided with the electrode 14. The interconnection layer 20 is made of conductive material (e.g., metal). A plurality of discrete regions of the interconnection layer 20 is formed as shown in FIG. 1 each consisting of one or more layers. In case of plural layers, the interconnection layer 20 may be made of a combination of a plurality of different materials (e.g., copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium-tungsten (TiW), gold (Au), aluminum (Al), nickel-vanadium (NiV), tungsten (W), etc.). The discrete regions of the interconnection layer 20 are formed to cover the electrodes 14 and electrically connected with the electrodes 14. The discrete regions of the interconnection layer 20 extend from the electrodes 14 onto the resin layer 18. The discrete regions of the interconnection layer 20 are formed so as to extend to the upper surface of the resin layer 18 through its side face (the slanted face).
  • The discrete regions of the interconnection layer 20 include plural lands (a first and second lands 22, 24 in the present exemplary embodiment). The lands are electrical terminals, and provided with plated layers (not shown in the figures) to enhance electrical characteristics. The lands are formed on the resin layer 18. The lands are wider than lines of the discrete regions of the interconnection layer 20, and can be shaped as, for example round lands.
  • The semiconductor device 1 includes a plurality of external terminals 40. The external terminals 40 are formed on the same side of the semiconductor substrate 10 as the side on which the electrodes 14 are formed. The external terminals 40 are electrically connected to the electrodes 14. As shown in FIGS. 1 and 2, the external terminals 40 are electrically connected to the discrete regions of the interconnection layer 20. The external terminals 40 can be formed on the lands. The external terminals 40 can be made of conductive metal. The external terminals 40 can also be made of brazing material. The external terminals 40 can be shaped as, for example, a sphere, and can be solder balls. In the example shown in FIG. 1, the plurality of external terminals 40 is disposed symmetrically in plan view of the semiconductor substrate 10.
  • The semiconductor device 1 includes an insulation layer 50 (e.g., a layer made of resin). The insulation layer 50 has translucency, and can be made of translucent or transparent material. The insulation layer 50 is formed of a single or multiple layers (a first and second insulation layers 54, 52 in the example shown in FIG. 2). The insulation layer 50 is formed on the same side of the semiconductor substrate 10 as the side on which the external terminals 40 are formed. In detail, the insulation layer 50 is formed to cover the interconnection layer 20 with at least a part of the external terminals 40 exposed (with the tip of the external terminals 40 exposed). The insulation layer 50 can also serve as a solder resist.
  • In the example shown in FIG. 2, the insulation layer 50 includes the first and the second insulation layers 54, 52. The first and the second insulation layers 54, 52 are translucent as described above. The first insulation layer 54 can be formed after fabrication of the interconnection layer 20 so as to cover at least a part of each of the discrete regions of the interconnection layer 20. As shown in FIG. 2, the first insulation layer 54 can be formed outside at least center portions of the lands. Oxidization, corrosion, or breaking of the interconnection layer 20 can be avoided by forming the first insulation layer 54.
  • The second insulation layer 52 is stacked on the first insulation layer 54. The second insulation layer 52 can be formed on the first insulation layer 54 after fabrication of the external terminals 40. The second insulation layer 52 is formed with tip portions of the external terminals 40 exposed. In this case, the second insulation layer 52 covers root portions (lower end portions) of the external terminals 40. Thus, the root portions of the external terminals 40 are reinforced.
  • The semiconductor device 1 includes a mark 30. The mark 30 is formed on the same side of the semiconductor substrate 10 as the side on which the external terminals 40 are formed (e.g., on the resin layer 18), and is covered with the insulation layer 50 (the first and the second insulation layers 54, 52 in FIG. 2). Since the insulation layer 50 has translucency, the mark 30 can be recognized through the insulation layer 50. Thus, since the insulation layer 50 is provided on the mark 30, breakage, separation, or discoloration caused by oxidization can be reduced or prevented ensuring that an orientation of a semiconductor device is determined using the mark 30.
  • The position or the shape of the mark 30 is arranged so that at least an orientation (plan orientation) of the semiconductor device 1 (or the semiconductor substrate 10) can be acknowledged. For example, the mark 30 may be formed to have a shape by which either direction can be recognized (e.g., a shape of an arrow or the like). Or, the mark 30 may be disposed at an end portion of the semiconductor substrate 10 (e.g., at a corner thereof). Thus, an orientation of the semiconductor device can be determined only by recognizing the position of the mark 30 (even if its shape cannot be recognized). Note that the mark 30 may be a single mark or a plurality of marks as well.
  • The mark 30 can be made of the same material as at least a part of the interconnection layer 20 (at least one layer if the interconnection layer 20 comprises multiple layers). For example, if the interconnection layer 20 is made of metal, the mark 30 may also be made of the metal. If the interconnection layer 20 includes multiple layers, the mark 30 may also include the multiple layers. By this structure, the mark 30 may be formed in the process for forming the interconnection layer 20, thus reducing the cost and the number of manufacturing processes.
  • In the example shown in FIGS. 1 and 2, any one of the plural lands has the mark 30 as its part. In further detail, the shape of the first land 22, provided at least one includes the mark 30, and the shape of the second land 24, is different from the shape of the first land 22. In the example shown in FIG. 1, the shape of the first land 22 includes a round part and a protrusion (a quadrangular part in FIG. 1) protruding from the round part, one of the external terminals 40 being provided on a center portion of the round part, and the protrusion serving as the mark 30. The protrusion may be provided on the opposite side of the first land 22 to the line thereof. For example, the first land 22 as a whole may be recognized as the mark 30. According to this, since the part or the whole of the first land 22 serves as the mark 30, the number of components of the semiconductor device can be reduced. Further, space of the semiconductor device can be efficiently used compared to the case of forming the mark 30 independently. This is especially efficient for application to CSP (chip size package) in which the sizes of the semiconductor device and the semiconductor chip are substantially the same.
  • The shape of the mark (or the surface shape of the first land 22) is not limited, but may be modified to various shapes as shown in FIGS. 3 through 6. As shown in FIG. 3, the protrusion as a mark 32 may be shaped as a triangle. As shown in FIG. 4, the protrusion as a mark 34 may be shaped as a combination of multiple polygons (e.g., a convex shape). As shown in FIG. 5, the position of the protrusion as a mark 36 may not be limited to the opposite side to a line of the first land 22, but the protrusion can be, for example, positioned at the point having a normal perpendicular to a normal at the line. As shown in FIG. 6, the plural protrusions as marks 38 may be disposed at plural positions (e.g., the both positions shown in FIGS. 1 and 5).
  • As a modification of the present exemplary embodiment, a mark 60 (a mark 62) may be provided independently from discrete regions of the interconnection layer 20, as shown in FIGS. 7 and 8. That is, the mark 60 (the mark 62) may be provided on a region not contacting the discrete regions of the interconnection layer 20 (the land 22). As an example shown in FIG. 7, the mark 60 can be formed on a passivation 16 (See FIG. 2.) in the same process as that for the interconnection layer 20, as previously described. As an example shown in FIG. 8, the mark 62 may be formed on the resin layer 18 in the same process as that for the interconnection layer 20, as previously described. According to the above, since the mark may be provided without any limitations derived from the position of the land, the mark may be provided on a position easy to be recognized resulting in easy determination of an orientation of the semiconductor device. Furthermore, since the mark need not be positioned adjacent to the discrete regions of the interconnection layer 20, the flexibility of the interconnection layer 20 in wiring from electrodes 14 to the land 22 can be enhanced. Also, as shown in FIGS. 7 and 8, the mark 60 (the mark 62) may be provided at least one of the four corners of the semiconductor chip.
  • As a modification of the present exemplary embodiment, the semiconductor device may include a substrate (e.g., an interposer) and a semiconductor chip (on which an integrated circuit is formed) mounted on the substrate. In this case, there is formed on the substrate an electrode (e.g., a terminal portion of an interconnection pattern) electrically connected to the integrated circuit of the semiconductor chip. A mark to determine an orientation of the semiconductor device is formed on the substrate (more precisely, on the same side of the substrate as the side provided with the electrode).
  • According to the semiconductor device of the present exemplary embodiment, by recognizing the mark 30 through the insulation layer 50 from the external terminals 40 side of the substrate (the semiconductor substrate 10), an orientation of the semiconductor device can easily be determined. Thus, an orientation of the semiconductor device can be determined from the structure of the semiconductor device in itself offering high efficiency in handling of the semiconductor device.
  • A semiconductor device manufacturing method according to another exemplary embodiment includes: forming the mark 30 on one side (e.g., the side on which the electrodes 14 are formed) of the substrate (the semiconductor substrate 10 in the present exemplary embodiment); forming the external terminals 40 on the same side of the semiconductor device as the side provided with the mark 30; and providing the insulation layer 50 so as to cover the mark 30. Since the insulation layer 50 has translucency as previously described, the mark 30 can be recognized through the insulation layer 50. If the semiconductor wafer is used as the semiconductor substrate 10, the semiconductor substrate 10 is cut into plural regions each corresponding to the integrated circuit 12. A plurality of semiconductor devices is obtained by cutting the semiconductor substrate 10. In this case, packaging is performed every wafer. Note that other details and advantages of the present exemplary embodiment can be reached from the above description regarding the semiconductor device, and therefore are omitted from the description of this section.
  • A semiconductor device mounting method according to still another exemplary embodiment includes mounting the semiconductor device 1 (including a semiconductor chip) on a circuit board (e.g., a mother-board (See FIG. 9.)), and a mounting orientation of the semiconductor device 1 is determined by recognizing the mark 30 through the insulation layer 50. According to the above, the orientation of the semiconductor device can be determined from the structure thereof in itself. Note that other details and advantages of the present exemplary embodiment can be reached from the above description regarding the semiconductor device, and therefore are omitted from the description of this section.
  • FIG. 9 shows a circuit board 1000 according to still another exemplary embodiment of the present invention having the semiconductor device 1 mounted thereon. As an electronic apparatus according to still another exemplary embodiment of the present invention including the semiconductor device, FIG. 10 shows a laptop personal computer 2000, and FIG. 11 shows a cellular phone 3000.
  • The present invention is not limited to the aforementioned exemplary embodiments, but various modifications thereof are possible. For example, the present invention may include substantially the same structures as explained in the description of the exemplary embodiments (e.g., structures with the same function, way, and results or structures with the same objects and results). Furthermore, the present invention may include structures obtained by replacing a nonessential part of the structure explained in the description of the exemplary embodiments. Still further, the present invention may include structures offering the same action and results or structures achieving the same object as the structures explained in the description of the exemplary embodiments. Still further, the present invention includes structures obtained by combining prior art with the structure explained in the description of the exemplary embodiments.

Claims (2)

1. A method of mounting a semiconductor device, comprising a substrate including an electrode electrically connected to at least one integrated circuit; an external terminal electrically connected to the electrode; a light transmissive insulation layer disposed on the external terminal side of the substrate; and a mark provided on the substrate and covered by the light transmissive insulation layer so as to be visible through the insulation layer, onto a circuit board, the method comprising:
determining a mounting orientation of the semiconductor device by recognizing the mark through the insulation layer.
2. A method of manufacturing a circuit board, comprising:
providing a mark on one side of a substrate having an electrode electrically connected to an integrated circuit;
providing an external terminal electrically connected to the electrode on the mark side of the substrate; and
providing a light transmissive insulation layer to cover the mark, the mark being visible through the light transmissive insulation layer.
US11/798,259 2003-02-27 2007-05-11 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus Abandoned US20070217177A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/798,259 US20070217177A1 (en) 2003-02-27 2007-05-11 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2003-051119 2003-02-27
JP2003051119A JP2004260074A (en) 2003-02-27 2003-02-27 Semiconductor device, method for manufacturing and mounting the same, circuit board, and electronic apparatus
US10/779,710 US7061127B2 (en) 2003-02-27 2004-02-18 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus
US11/413,042 US7245029B2 (en) 2003-02-27 2006-04-28 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus
US11/798,259 US20070217177A1 (en) 2003-02-27 2007-05-11 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/413,042 Division US7245029B2 (en) 2003-02-27 2006-04-28 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus

Publications (1)

Publication Number Publication Date
US20070217177A1 true US20070217177A1 (en) 2007-09-20

Family

ID=32984354

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/779,710 Expired - Lifetime US7061127B2 (en) 2003-02-27 2004-02-18 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus
US11/413,042 Expired - Lifetime US7245029B2 (en) 2003-02-27 2006-04-28 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus
US11/798,259 Abandoned US20070217177A1 (en) 2003-02-27 2007-05-11 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US10/779,710 Expired - Lifetime US7061127B2 (en) 2003-02-27 2004-02-18 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus
US11/413,042 Expired - Lifetime US7245029B2 (en) 2003-02-27 2006-04-28 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus

Country Status (3)

Country Link
US (3) US7061127B2 (en)
JP (1) JP2004260074A (en)
CN (1) CN1525555A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3885890B2 (en) * 2004-04-28 2007-02-28 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JP4635676B2 (en) * 2005-03-25 2011-02-23 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP4449830B2 (en) * 2005-06-14 2010-04-14 セイコーエプソン株式会社 Surface emitting semiconductor laser
JP5199189B2 (en) * 2009-06-29 2013-05-15 ラピスセミコンダクタ株式会社 Semiconductor device and manufacturing method of semiconductor device
US10492290B2 (en) * 2018-03-02 2019-11-26 Dell Products L.P. Circuit board pad mounting orientation system

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512712A (en) * 1993-10-14 1996-04-30 Ibiden Co., Ltd. Printed wiring board having indications thereon covered by insulation
US5876884A (en) * 1997-10-02 1999-03-02 Fujitsu Limited Method of fabricating a flat-panel display device and an apparatus therefore
US5887343A (en) * 1997-05-16 1999-03-30 Harris Corporation Direct chip attachment method
US5923966A (en) * 1994-07-28 1999-07-13 Semiconductor Energy Laboratory Co., Ltd. Laser processing method
US6180498B1 (en) * 1997-02-18 2001-01-30 International Business Machines Corporation Alignment targets having enhanced contrast
US6278193B1 (en) * 1998-12-07 2001-08-21 International Business Machines Corporation Optical sensing method to place flip chips
US6302313B1 (en) * 1998-02-20 2001-10-16 Kabushiki Kaisha Shinkawa Flip-chip bonding method and apparatus
US20010029755A1 (en) * 2000-04-12 2001-10-18 Hiromi Takahashi Method of forming an alignment marker for optical devices
US6355976B1 (en) * 1992-05-14 2002-03-12 Reveo, Inc Three-dimensional packaging technology for multi-layered integrated circuits
US6465898B1 (en) * 2001-07-23 2002-10-15 Texas Instruments Incorporated Bonding alignment mark for bonds over active circuits
US6583445B1 (en) * 2000-06-16 2003-06-24 Peregrine Semiconductor Corporation Integrated electronic-optoelectronic devices and method of making the same
US6630722B1 (en) * 1999-05-26 2003-10-07 Sharp Kabushiki Kaisha Solid state image sensing device having high image quality and fabricating method thereof
US6744144B2 (en) * 2000-06-28 2004-06-01 Micron Technology, Inc. Method and apparatus for marking microelectronic dies and microelectronic devices
US20050062156A1 (en) * 2003-06-03 2005-03-24 Martin Alter Integrating chip scale packaging metallization into integrated circuit die structures
US20070062729A1 (en) * 1996-12-19 2007-03-22 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3378880B2 (en) 1997-12-26 2003-02-17 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JPH11195667A (en) 1997-12-26 1999-07-21 New Japan Radio Co Ltd Alignment method for bonding pad and photo-mask
JP2000040773A (en) 1998-07-23 2000-02-08 Sony Corp Resin-sealed semiconductor device and manufacture thereof
JP3711341B2 (en) 2001-04-27 2005-11-02 沖電気工業株式会社 Semiconductor device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6355976B1 (en) * 1992-05-14 2002-03-12 Reveo, Inc Three-dimensional packaging technology for multi-layered integrated circuits
US5512712A (en) * 1993-10-14 1996-04-30 Ibiden Co., Ltd. Printed wiring board having indications thereon covered by insulation
US5923966A (en) * 1994-07-28 1999-07-13 Semiconductor Energy Laboratory Co., Ltd. Laser processing method
US20070062729A1 (en) * 1996-12-19 2007-03-22 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US6180498B1 (en) * 1997-02-18 2001-01-30 International Business Machines Corporation Alignment targets having enhanced contrast
US5887343A (en) * 1997-05-16 1999-03-30 Harris Corporation Direct chip attachment method
US5876884A (en) * 1997-10-02 1999-03-02 Fujitsu Limited Method of fabricating a flat-panel display device and an apparatus therefore
US6302313B1 (en) * 1998-02-20 2001-10-16 Kabushiki Kaisha Shinkawa Flip-chip bonding method and apparatus
US6278193B1 (en) * 1998-12-07 2001-08-21 International Business Machines Corporation Optical sensing method to place flip chips
US6630722B1 (en) * 1999-05-26 2003-10-07 Sharp Kabushiki Kaisha Solid state image sensing device having high image quality and fabricating method thereof
US20010029755A1 (en) * 2000-04-12 2001-10-18 Hiromi Takahashi Method of forming an alignment marker for optical devices
US6583445B1 (en) * 2000-06-16 2003-06-24 Peregrine Semiconductor Corporation Integrated electronic-optoelectronic devices and method of making the same
US6744144B2 (en) * 2000-06-28 2004-06-01 Micron Technology, Inc. Method and apparatus for marking microelectronic dies and microelectronic devices
US6465898B1 (en) * 2001-07-23 2002-10-15 Texas Instruments Incorporated Bonding alignment mark for bonds over active circuits
US20050062156A1 (en) * 2003-06-03 2005-03-24 Martin Alter Integrating chip scale packaging metallization into integrated circuit die structures

Also Published As

Publication number Publication date
JP2004260074A (en) 2004-09-16
US20060192303A1 (en) 2006-08-31
US7245029B2 (en) 2007-07-17
US7061127B2 (en) 2006-06-13
US20040183178A1 (en) 2004-09-23
CN1525555A (en) 2004-09-01

Similar Documents

Publication Publication Date Title
US7560810B2 (en) Semiconductor device, method of manufacturing the same, circuit board, and electronic instrument
US10734367B2 (en) Semiconductor package and method of fabricating the same
US7564142B2 (en) Electronic device and method of manufacturing the same, circuit board, and electronic instrument
KR101479512B1 (en) Method for manufacturing semiconductor package
US7981792B2 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US7323777B2 (en) Semiconductor device, method of manufacturing the same, circuit board, and electronic instrument
US7514350B2 (en) Electronic device and method of manufacturing the same, circuit board, and electronic instrument
US8110922B2 (en) Wafer level semiconductor module and method for manufacturing the same
US8153516B2 (en) Method of ball grid array package construction with raised solder ball pads
US7245029B2 (en) Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus
JP4269173B2 (en) Semiconductor device and manufacturing method thereof
JP3804797B2 (en) Semiconductor device and manufacturing method thereof
US7420280B1 (en) Reduced stress under bump metallization structure
US7075184B2 (en) Semiconductor device and manufacturing method, circuit board and electronic device thereof
JP3458056B2 (en) Semiconductor device and its mounting body
US7459637B2 (en) Semiconductor device, manufacturing method thereof, circuit board, and electronic appliance
JP4352263B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JPH09246274A (en) Semiconductor device
JP4067412B2 (en) Semiconductor device and manufacturing method of semiconductor device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION