US20070211535A1

US20070211535A1 - Dynamic random access memory

Info

Publication number: US20070211535A1
Application number: US11/755,197
Authority: US
Inventors: Juhan Kim
Original assignee: Individual
Current assignee: Individual
Priority date: 2005-12-08
Filing date: 2007-05-30
Publication date: 2007-09-13
Also published as: US20070133257A1; US7466586B2; US20070133258A1; US20070133243A1; US7242607B2; US7196926B1; US7209384B1; US20070133250A1

Abstract

DRAM includes a small capacitor as a storage device, a write MOS transistor as a write device, and a diode as a read device; the diode includes four terminals, the first terminal serves as a read word line, the second terminal serves as a storage node, the third terminal is floating, and the fourth terminal serves as a bit line; the diode can be composed of the parasitic bipolar transistor of the write MOS transistor with attaching one more terminal; the diode and the write MOS transistor can be formed from thin-film layer, thus multiple memory cells are stacked; the heavy routing lines are driven by the bipolar drivers which are part of the invention; the bipolar drivers and the control MOS transistors of the peripheral circuit can be formed from the thin-film transistor; hence the whole chip can be stacked over the wafer, such as silicon, quartz and others; additionally it applications are extended to a multi port memory and a content addressable memory.

Description

CROSS REFERENCE TO RELATED APPLICATION

The present invention is a continuation of application Ser. No. 11/307,318, filed on Feb. 1, 2006, now U.S. Pat. No. 7,242,607, which is a continuation of application Ser. No. 11/306,756, filed on Jan. 10, 2006, which is a continuation of application Ser. No. 11/164,919, filed on Dec. 11, 2005, now U.S. Pat. No. 7,196,926, which is a continuation of application Ser. No. 11/164,872, filed on Dec. 8, 2005, now U.S. Pat. No. 7,209,384, which are herein incorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits, in particular to RAM (Random Access Memory) including capacitor storage element, and its applications, such as single port memory, multi port memory and CAM (content addressable memory).

BACKGROUND OF THE INVENTION

A p-n-p-n diode known as Shockley diode or thyristor, is a solid-state semiconductor device similar to two-terminal p-n diode, with an extra terminal which is used to turn it on. Once turned on, diode (p-n-p-n diode or n-p-n-p diode) will remain on conducting state as long as there is a significant current flowing through it. If the current falls to zero, the device switches off. Diode has four layers, with each layer consisting of an alternately p-type or n-type material, for example p-n-p-n and n-p-n-p. The main terminals, labeled anode and cathode, are across the full four layers, and the control terminal, called the gate, is attached to one of the middle layers. The operation of a diode can be understood in terms of a pair of tightly coupled transistors, arranged to cause the self-latching action.
Diodes are mainly used where high currents and voltages are involved, and are often used to control alternating currents, where the change of polarity of the current causes the device to automatically switch off; referred to as ‘zero cross operation’. The device can also be said to be in synchronous operation as, once the device is open, it conducts in phase with the voltage applied over its anode to cathode junction. This is not to be confused with symmetrical operation, as the output is unidirectional, flowing only from anode to cathode, and so is asymmetrical in nature. These properties are used control the desired load regulation by adjusting the frequency of the trigger signal at the gate. The load regulation possible is broad as semiconductor based devices are capable of switching at extremely high speeds over extremely large numbers of switching cycles.
In FIG. 1A, the schematic of diode is illustrated. It consists of four terminals, such that the anode 111 is connected to power supply or regulating node, the base 112 of p-n-p transistor 115 serves as the collector 112 of n-p-n transistor 114, the collector 113 of p-n-p transistor 115 serves as the base of n-p-n transistor 114 which is controlled by the voltage controller 116. In order to turn on diode and hold the state of turn-on, the voltage controller should raise the voltage from ground level to VF (forward bias, 0.6 v-0.8 v for silicon). And the voltage controller 116 should supply the current 117, referred to as the base current, which current depends on the characteristic of transistor 114 and 115. Once the base current 117 establishes the forward bias (VF), the collector 112 of n-p-n transistor 114 holds the current path 119 from the base of p-n-p transistor 115. After then, p-n-p transistor 115 is turned on because the base 112 has forward bias from the emitter 111. This makes the current path 118 which can keep the turn-on state. This is the holding state as long as the base has not so much leakage to drive the base voltage under forward bias (VF) even though the voltage controller 116 is open. To turn off diode, the voltage controller 116 should lower the voltage of the base of n-p-n transistor 114 under forward bias. To do so, the voltage controller 116 should (negatively) flow more current than the current path 118.
The diode is mainly used for the high voltage regulation, while the MOS transistor is used for the memory operation in general because of the simplicity of the MOS transistor as an access device. However, fabricating the MOS transistor will be reached to the scaling limit in the near future, and also the process cost will be extremely expensive with smaller feature size, such as 45 nm, 32 nm and 22 nm. In the present invention, sophisticated circuit techniques are introduced in order to improve the memory operation. With this method, there is no need of extreme feature size device with multi stacked devices. Furthermore, there are no new materials are required to fabricate the new semiconductor memory chip. Before explaining the present invention, there is a need to review the conventional DRAM and other prior arts.
The conventional DRAM is illustrated in FIG. 1B, as a prior art, wherein a MOS transistor 133 serves as a read device and also a write device, and a capacitor 136 serves as a storage device. When read, the word line 131 is asserted to high. Thus the stored charge in the storage node 132 is transferred to the bit line 135, but the bit line is heavily loaded with multiple memory cells and relatively long metal line. After then, the stored charges are re-distributed with the bit line charges, which reduce or raise the bit line voltage slightly, such as 100 mV. The charge re-distribution time is relatively long, because the MOS transistor includes high turn-on resistance and the bit line capacitance is relatively heavy. When write, the word line is asserted to higher than the supply voltage in order to transfer full level of the bit line voltage, which eliminates the threshold voltage drop of the NMOS transistor 133. To do so, the NMOS transistor includes relatively thick gate oxide, and a charge pump circuit (not shown) generates a word line voltage. After write, the stored charges are reduced by the leakage current, thus the subthreshold leakage of the MOS transistor should be suppressed carefully. In order to reduce the subthreshold leakage, negative voltage is applied to the body of the MOS transistor, which also reduces the junction capacitance of the bit line, but the internal negative voltage generator consumes current and needs to be adjusted for the optimum voltage level for the use. And one more undesirable effect is the parasitic bipolar transistor in the bottom side of the MOS transistor which should be suppressed by applying the negative voltage to the body. The slight forward bias can remove the stored charge to the body. Furthermore, the storage capacitor should be big enough to drive the heavily loaded bit line directly, such as 20 fF to 30 fF. One of major drawback is that fabricating the MOS transistor on the surface of the wafer reaches to the scaling limit in the near future, such that smaller than 22 nm MOS transistor is more challenging with the existing materials. There are many prior arts for the conventional DRAM, as published, U.S. Pat. No. 6,191,448, No. 6,689,660, No. 7,303,439, and No. 7,221,014.
And there are many efforts to improve the conventional DRAM, with introducing new circuit concepts. One of the circuit is to use a four-terminal diode as a storage device to reduce the storage capacitor, but the MOS transistor still serves as an access device, such that the four-terminal diode holds the states of turn-on or turn-off, but it has very high holding current to store ‘on’ state, as published, “High density planar SRAM cell using bipolar latch-up and gated diode breakdown”, U.S. Pat. No. 6,104,045, and “Thyristor-type memory device” U.S. Pat. No. 6,967,358 and “Semiconductor capacitively-coupled negative differential resistance device and its applications in high-density high-speed memories and in power switches”, U.S. Pat. No. 6,229,161. And another report is reported, “A novel capacitor-less DRAM cell Thin Capacitively-Coupled Thyristor (TCCT)”, 2005 IEEE Electron Devices Meeting (IEDM) Tech. Dig. pp. 311. This approach requires very deep negative voltage in order to write data because the inversion layer of the gate is attached to the drain/source region (or emitter/collector), the gate can swing only ground to deep negative voltage (−1.5V) to avoid the leakage path to the drain, which needs negative pump circuit or external negative voltage. And high current flowing eventually raises operating temperature by “Joule heating”, which produces more junction leakage and gate leakage. Consequently, the data stored in the diode can be lost quickly by those leakages.
And a floating body memory is reported as published, U.S. Pat. No. 6,937,516 and No. 7,177,175. However, the memory cell can store the charges in the floating body of the SOI type wafer. Thus, the retention time is relatively short because there is only a parasitic capacitor to store charges. And the gate oxide may be damaged after long time use, because the impaction ionization may hurt the oxide with relatively high voltage when write. The read access device still uses a MOS transistor, which should drive heavily loaded bit line through the MOS transistor which includes higher turn-on resistance than bipolar transistor, thus the MOS transistor should be high-performance device to meet the access time. And a major drawback is that fabricating the MOS transistor on the surface of the wafer will be reached to the scaling limit in the near future as the conventional DRAM.
One more prior art is reported to reduce the storage capacitor, as published, “A Poly-Silicon TFT With a Sub-5-nm Thick Channel for Low-Power Gain Cell Memory in Mobile Applications”, IEEE Transactions on Electron Devices, Vol. 51, No. 11, pp. 1805-1810, November 2004, U.S. Pat. No. 7,009,243, and No. 6,646,300, wherein the polysilicon thin-film transistor serves as write device, and which stores the charges with low leakage. However, the read MOS transistor should drive the heavily loaded bit line as the floating body memory. The MOS transistor should be high-performance device, which will be reached to the scaling limit in the near future as well.
As reviewed the prior arts, the conventional DRAM and other prior arts use the bi-directional MOS transistor as a read device and also a write device, because it is straightforward to access the storage capacitor directly. However, the bi-directional traffic is generally slow. In this respect, the read path and the write path can be separately controlled as the express way has two way traffics with traffic signal in the street. And a small capacitor controls the strong diode read device when read, as a small car key can start several hundred horse power engine with two fingers (or three fingers may be available, but the whole body is not necessary). One more aspect is the memory cells are stacked over the control circuits, and multiple memory cells are stacked, as the multi-story building has more rooms on the ground, and the ground is a supporter for the building.
The major improvement of the present invention is that the active power is dramatically reduced by reducing the current loading, during read operation. In this manner, the bit line current loading is two or three because the delay signal sequentially enables the current path of the bit lines in the memory array when read. Furthermore, the write path uses the MOS transistor as the conventional DRAM, so that there is no current loading during write. Hence, the capacitive loading is easy to be driven by the strong bipolar buffer circuit which is also part of the present invention.
In order to do so, sophisticated circuit techniques are introduced to control the read path and the write path separately. In the present invention, the four-terminal diode is used as a read access device and the MOS transistor is still used as a write device, and a relatively small capacitor serves as a storage device. And adding one more terminal to the MOS transistor, the parasitic bipolar transistor of the write MOS transistor serves as a four-terminal diode for the read operation. Furthermore, the four-terminal diode serves as a sense amplifier as well, such that the diode output generates information “on” or “off” which is digital value. It gives as many as advantages to design and fabricate it. However the diode operation is not as simple as the MOS transistor because it has unidirectional current control characteristic and internal feedback loop. In the conventional MOS access transistor, there is a parasitic n-p-n bipolar transistor wherein the body serves as the base, source/drain serve as the emitter/collector. During read and write cycle, the base (body) is at ground (or negative) to prevent bipolar effect. The parasitic bipolar transistor is not wanted device in the conventional memory, which is usually turned off, but now adding one more terminal to the parasitic bipolar transistor, a p-n-p-n diode (or n-p-n-p) can serve as a read access device for the next generation memory device with good performance and simple structure. Thus, the diode serves as a read device, while the MOS transistor still serves as a write device. Additionally, the plate line of the capacitor enhances the write operation to boost the storage node.
Separately a capacitor is still required to store data as the conventional memories such as DRAM (Dynamic Random Access Memory), but now there is no need of high capacitance to drive the bit line directly. Instead, the capacitor drives only one of diode terminals which has very little capacitance, and the capacitor indirectly communicates to the bit line (or data line), while diode directly communicates to the bit line. As a result, diode serves as a sense amplifier to detect whether the storage node voltage is forward bias or not. This is different control method from the conventional DRAM, where the gate of MOS transistor is connected to the word line and turns on and off, but the load of the word line is only gate and routing capacitance, while the storage capacitor drives very heavy bit line directly, which means that the word line loading is very light, in the conventional DRAM. Conversely, using diode as a read access device gives the bit line loading to the word line through the diode, which makes the word line loading very heavy, but it is controllable to design with strong driver or segmentation for the word line. Even though the word line loading is high, it is desirable to configure a memory array because the word line driver is stronger than the weak storage capacitor. In the conventional DRAM, the weak storage capacitor directly drives the bit line, which needs time to redistribute charge from the capacitor to the bit line. The stored charge was lost during read cycle by the charge redistribution, which is referred to as destructive read.
Additionally, any types of capacitor can be used for storing data. Depending on the capacitor material, the retention time and the write time are different. For example, DRAM uses ordinary dielectric capacitor, such as silicon dioxide, silicon nitride, Ta₂O₅, TiO₂, Al₂O₃, TiN/HfO₂/TiN(TIT), and Ru/Insulator/TiN(RIT), which can store data in the range of 300 ms to 1 sec. It is called volatile memory. Alternatively, ferroelectric capacitor can be used as a storage capacitor, such as lead zirconate titanate (PZT), lead lanthanum zirconium titanate (PLZT), barium strontium titanate (BST), and strontium bismuth tantalate (SBT), as shown in the prior art, “Ferroelectric Random-Access Memory”, U.S. Pat. No. 5,600,587. In the present invention, ferroelectric capacitor can also be used as a volatile memory because the stored charges are gradually discharged after the electric field is off. Moreover, the read operation is different from FRAM (Ferroelectric Random Access Memory), such that the plate line is not moving when read, in the present invention, while the plate line moves in the FRAM read operation in order to measure the polarized capacitance in the ferroelectric capacitor. Thus the memory operation is still volatile mode, but retention time would be increased as long as high dielectric constant material is used, in the present invention. Furthermore, a series capacitor can be a storage capacitor, such that the memory cell works after one of the series capacitor is broken and shorted. When one of the series capacitor is shorted, the storage capacitance is increased twice. Thus, yield will be increased and the memory is more reliable in operation.
The MOS write device can be a coarse device such as thin-film transistor because the MOS transistor drives only a small storage capacitor, which ensures that the memory cells are formed in between the routing layers. In doing so, there is no high performance MOS transistor in the memory cell, and one more improvement is that the bipolar transistors can be used as internal buffers such as the word line driver and the bit line driver. Furthermore, the output driver can use the similar type of bipolar buffer circuit.
And one of major advantages of the present invention is that there is no need of extreme feature size transistors because the memory cells can be stacked over the control circuit. In stead of scaling the transistors to extreme geometry, topping more memory cells is more practical, which also achieves fast access with centralized control and short routing length in vertical direction. As a result, there is no scaling limit to fabricate the memory chip by topping multiple memory cells.
The heavily loaded control signals are driven by bipolar buffers which are also formed from the thin-film layers. This means that the control circuits can be stacked over the wafer with an insulator because there is no need for fabricating high-performance MOS transistor on the surface of the wafer. Consequently, the whole chip can be fabricated on the isolation layer on the wafer. In doing so, the wafer serves only as a supporter. Thus, any types of wafer can be a supporter to reduce the wafer cost, such as low purity silicon wafer, quartz wafer, ceramic wafer, glass, metal and so on.

SUMMARY OF THE INVENTION

In the present invention, dynamic random access memory including a four-terminal diode read device and its applications is described, wherein the four-terminal diode serves as a read access device, a MOS transistor serves as a write device and a small capacitor stores data. More specifically, the write MOS transistor includes a parasitic bipolar transistor which is unwanted device in the conventional DRAM, but now adding one more terminal to the parasitic bipolar transistor, the bipolar transistor serves as a strong four-terminal diode. During read operation, the read word line is asserted to activate the diode, while the write word line serves as a gate of the MOS transistor and the gate turns off the MOS transistor. In contrast, the write word line is asserted to write the charge to the capacitor node during write operation, while the read word line is de-asserted.
The memory cells can be formed within the current CMOS process environment, but with no new material. And one of major advantages of the present invention is that the memory cells can be formed in between the routing layers in order to reduce chip area, and also the memory cells can be stacked over the control circuits including MOS transistors when the memory cells are composed of the thin-film transistor such as polysilicon and amorphous silicon with low temperature process. The read diode need not be a high performance device nor have a high current gain, because the diode is used as a digital switch such that it is turned on or off depending on the stored voltage. And the current path of diode includes its whole junction area while the current path of MOS transistor includes a shallow inversion layer on the surface by the electric field. Thus, the current flow of the diode is much higher than that of the MOS transistor. The write MOS transistor need not be a high performance device nor have a high current gain either. During write, the write MOS transistor drives only a small storage capacitor only, which means that the write MOS device can be a coarse MOS transistor, such as polysilicon or amorphous thin-film MOS transistor. In order to store charges in the storage node of the capacitor, the capacitor node is enhanced by coupling the capacitor plate. In this manner, the coarse MOS transistor serves as a good write device. In addition, there is no need of high voltage write word line for the memory cell, while the conventional DRAM requires higher voltage than the supply voltage for the write operation. In addition, multiple memory cells can be stacked. Hence, topping the memory cells with low temperature is independent on fabricating the control circuits.
The peripheral circuits and the memory cells can be formed on the conventional wafer, such as the bulk wafer and the SOI wafer. Furthermore, the whole chip can be fabricated on the isolation layer over the wafer as an alternative embodiment, wherein the transistors do not use the surface of the wafer. To do so, the heavily loaded lines are driven by the bipolar output drivers which are part of the present invention, and the MOS transistor drive only lightly loaded signals. In doing so, the wafer only serves as a supporter while the conventional MOS transistors use the surface of the wafer, which means that the MOS transistors for the memory control and the memory cells are formed from the deposited polysilicon or amorphous silicon. Thus, any types of wafer can be a supporter in order to reduce the wafer cost. In this respect, there is no need of extreme feature size transistors because the memory cells can be stacked over the control circuit, and the control circuits can be stacked over the any type of wafer. In stead of scaling the transistors, multiple toppings are more meaningful, which also achieves fast access with centralized control and short routing length in vertical directions. In doing so, the present invention can overcome the scaling limit of the DRAM, because there is almost no limit to stack the memory cells in the vertical direction as long as the flatness is good enough to stack more memory cells.
The capacitor can be very small device, because the capacitor does not directly drive the heavily loaded bit line during read, the strong diode drives the bit line in stead of the capacitor. The retention time of the memory cell can be maintained by reducing the subthreshold leakage through the thin-film transistor with wide channel region and optimum doping rate, and reducing the diode reverse bias leakage. The memory cell structures are simpler than that of the conventional DRAM, because no big capacitor is required for the storage capacitor. Various types of capacitor can be used for storing data, such as ordinary capacitor including high dielectric constant and ferroelectric capacitor which includes also high dielectric constant. Both capacitors can be used as a volatile memory because the stored charges are gradually discharged after write, because read operation is different from FRAM (Ferroelectric Random Access Memory), such that the plate line is not moving when read in the present invention, while the plate line moves in FRAM operation in order to measure the polarized capacitance in the capacitor, thus FRAM is worn out after long time use. But the capacitor is not worn out for the DRAM operation because the operation is different. Thus the DRAM operation is still volatile mode, but retention time would be increased as long as high dielectric constant material is used. In addition, the write operation is enhanced by coupling the storage capacitor when the plate line is raised. In doing so, the stored charges are increased, which improves retention time. Furthermore, a series capacitor can be a storage capacitor, such that the memory cell works after one of the series capacitor is broken and shorted. When one of the series capacitor is shorted, the storage capacitance is increased twice. Thus, yield will be increased and the memory is more reliable in operation.
Various types of diode can be used to form the memory cell, such as silicon including solid-state, amorphous and stretchable silicon, germanium, compound semiconductors including GaAs, SiGe, and metal semiconductor diode (Schottky diode), as long as the reverse bias current is controllable.
However the operation of the four-terminal diode is not familiar with the memory operation, because it has unidirectional current control characteristic and internal feedback loop, even though it has almost no parasitic effect. In the present invention, sophisticated circuit techniques are introduced to use a diode as a read access device for the capacitor memory. Moreover, the diode serves as a sense amplifier to detect the voltage of the storage node whether it is forward bias or not, then diode sends binary results to the bit line, and the latch device including the current mirror receives the binary results from the bit line, on or off. The current mirror repeats the amount of current that the memory cell flows, and latches the result. After latching data, the output of the latch device cuts off the current path of the bit line, which reduces active current. And the diode read device realizes fast access time, and does not require reference bit line. Furthermore, dummy cells generate replica delay signals which guarantee internal timing margin and reduce operation cycle time. Furthermore, the diode can flow more current than the MOS transistor. The word line cuts off the holding current during standby. Thus there is no standby current except leakage current in the memory cell, which realizes low power consumption. Furthermore, the applications of the present memory cell are extendable for multi port memory and content addressable memory.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings which are incorporated in and form a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1A illustrates a p-n-p-n diode as a prior art. FIG. 1B depicts the schematic of the conventional DRAM, as prior arts.
FIG. 2 illustrates the basic schematics of capacitor memory and data latch as the present invention.
FIG. 3A illustrates a detailed circuit of the invented memory cell, and FIG. 3B illustrates an alternative configuration. And FIG. 3C illustrates a read path including the memory cell and read data latch, according to the teachings of the present invention.
FIG. 4A illustrates I-V curve of the memory cell, according to the teachings of the present invention. FIG. 4B illustrates I-V curve of conventional bipolar transistor is illustrated as a reference. FIG. 4C illustrates detailed I-V curve in linear scale and FIG. 4D illustrates detailed I-V curve in log scale, according to the teachings of the present invention.
FIG. 5A illustrates more detailed read path, according to the teachings of the present invention. FIG. 5B illustrates the relationship between voltage and temperature of the memory cell, according to the teachings of the present invention. FIG. 5C illustrates I-V curve of pull-down NMOS transistor, according to the teachings of the present invention. FIG. 5D illustrates I-V curve of the diode access device, according to the teachings of the present invention. And FIG. 5E illustrates I-V curve of pull-up device of row decoder, according to the teachings of the present invention.
FIG. 6A illustrates a timing diagram of read “1” operation, according to the teachings of the present invention. FIG. 6B illustrates a timing diagram of read “0” operation, according to the teachings of the present invention. And FIG. 6C illustrates a sequential read timing, according to the teachings of the present invention.
FIG. 7 illustrates the schematic for sequential read operation, according to the teachings of the present invention.
FIGS. 8A and 8B illustrate simplified read scheme, according to the teachings of the present invention.
FIG. 9A illustrates the equivalent circuit during write operation, and FIG. 9B illustrates the equivalent circuit during retention, according to the teachings of the present invention.
FIGS. 10A and 10B illustrate read-modify circuit including the memory cell, according to the teachings of the present invention.
FIG. 11A illustrates read “1” timing diagram, FIG. 11B illustrates read “0” timing diagram, FIG. 11C illustrates read “0” and modify “1” timing diagram, and FIG. 11D illustrates read “1” and modify “0” timing diagram, according to the teachings of the present invention.
FIG. 12A illustrates a whole read path including the output driver circuit. And FIGS. 12B, 12C, 12D and 12E illustrate related sub-circuits and timings of FIG. 12A, according to the teachings of the present invention.
FIG. 13A illustrates an alternative configuration with a ferroelectric capacitor, FIG. 13B illustrates an alternative configuration with a series capacitor, and FIG. 13C illustrates a reverse configuration, according to the teachings of the present invention.
FIG. 14 illustrates an example of multi-port memory application, according to the teachings of the present invention.
FIG. 15 illustrates an example application for content addressable memory, according to the teachings of the present invention.
FIG. 16 provides a truth table summarizing the logical relationships among various signals for content addressable memory, as shown in FIG. 15.
FIG. 17A illustrates a cross sectional view of stacked capacitor memory which is shown from the read word line direction, and FIG. 17B illustrates a cross sectional view shown from the bit line direction, according to the teachings of the present invention.
FIGS. 18A and 18B illustrate the cross sectional view of the memory cells. And FIGS. 18C and 18D illustrate global bit line and local bit line on the memory cells, according to the teachings of the present invention.
FIG. 19A illustrates global bit line structure, according to the teachings of the present invention.
FIG. 19B illustrates global bit line structure of the conventional DRAM, as a prior art.
FIG. 20 illustrates cross sectional views of the stacked capacitor memory on the bulk wafer, according to the teachings of the present invention.
FIG. 21 illustrates cross sectional views of the stacked capacitor memory on the MOS transistor, according to the teachings of the present invention.
FIG. 22 illustrates cross sectional views of the stacked capacitor memory under the MOS transistor, according to the teachings of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT(S)

Reference is made in detail to the preferred embodiments of the invention. While the invention is described in conjunction with the preferred embodiments, the invention is not intended to be limited by these preferred embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, as is obvious to one ordinarily skilled in the art, the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so that aspects of the invention will not be obscured.
The present invention is directed to a dynamic random access memory, as shown in FIG. 2, wherein a small capacitor storage element 205 is connected to a MOS transistor 209 and an additional p-type terminal 201 is attached to the storage node 202. The MOS transistor serves as a write device as the conventional memory when the write word line 208 is asserted. And the MOS transistor includes a parasitic n-p-n bipolar transistor, such that a body 203 serves as a base, a drain/source 202 serves as an emitter/collector, and another drain/source 204 serves as another emitter/collector. By adding p-type terminal 201 to the emitter/collector 202, the parasitic bipolar transistor serves as a four-terminal diode, wherein the first terminal 201 is p-type and connected to a read word line (RWL) 207 to activate the memory cell, the second terminal 202 is n-type and serves as a storage node 202 of the capacitor 205, the third terminal 203 is p-type and floating, the fourth terminal 204 is n-type and connected to a bit line to write or read data, and the plate line (PL) 206 is connected to an electrode of the capacitor 205. Unlike MOS access device, the diode is turned on or off, depending on the stored data during read cycle, which is quite different from the conventional switching concept to access the memory cell, such that the diode access device is turned on only if the storage node 202 is near VL level (ground). In contrast, the MOS write device 209 is turned on by the inversion layer (not shown), regardless of the stored data, when the write word line 208 is asserted to VH level (supply voltage), while the write word line is raised to higher than the supply voltage in the conventional memory.
In FIG. 3A, a detailed circuit of the memory cell as shown in FIG. 2 is illustrated, which circuit is also an equivalent circuit of the memory cell, wherein the MOS transistor 309 is composed of the gate 308, the source 302 and the drain 304, and the floating body 303. During write, the MOS transistor 309 is turned on by the gate electric field, while the read word line 307 keeps low (VL level) to turn off the diode and the body 303 is floating. During read, the write word line 308 keeps low (VL level). Thus, the MOS transistor is turned off, but the read word line 307 is asserted to high (VH level). When the storage node 302 stores low (near ground), p-n-p transistor Q1 is turned on, because the forward bias is set up by raising the read word line 307. By turning on p-n-p Q1, the floating body 303 is raised by p-n-p Q1. As a result, n-p-n Q2 is turned on, because the floating body 303 serves as the base of n-p-n Q2. In doing so, a current path is set up from the read word line 307 to the bit line 304. On the contrary, the current path is not set up when the stored voltage is higher than VH level, because the reverse bias is set up from the read word line to the storage node 302. Thus, the read output is the current from the diode, on or off. And the plate line 306 keeps a constant voltage during read.
In FIG. 3B, an alternative configuration is illustrated, wherein the diode and the MOS transistor are separately formed, thus the device optimization can be independently achieved for the diode and the MOS transistor, while the area of the memory cell is increased. The MOS transistor 319 is separately composed of the gate 318, the source 312 and the drain 314, and the body 313A. And the diode is separately formed, wherein the first terminal 311 is p-type and connected to a read word line (RWL) 317 to activate the memory cell, the second terminal 312 is n-type and connected to the storage node 312 of the capacitor 315, the third terminal 313 is p-type and floating, the fourth terminal 314 is n-type and connected to a bit line to write or read data, and the plate line (PL) 316 is connected to another electrode of the capacitor 315.
In FIG. 3C, a read path including the memory cell 300 (same circuit as FIG. 3A) and a data latch 330 is illustrated. In order to read, the read word line 307 is asserted to high, while the write word line 308 keeps low and the plate line 306 keep high. And the bit line 304 is floating from the pre-charged voltage at VL level, after then the read word line 307 is asserted. When the first terminal 301 (which is connected to the word line 307) is reached to VFP level (built-in voltage of p-n-p transistor Q1), p-n-p transistor Q1 is turned on if the storage node voltage 302 is near ground level. By turning on p-n-p transistor Q1, the collector 303 (floating node) of p-n-p transistor Q1 is raised and reached near the read word line voltage from ground level. At the same time, n-p-n transistor Q2 is turned on, because the collector 303 of p-n-p transistor Q1 serves as the base 303 of n-p-n transistor Q2. Turning on p-n-p transistor Q1 and n-p-n transistor Q2, the emitter 304 (also the bit line) of n-p-n transistor is raised by the current. Thus the bit line 304 is raised from ground level, where the initial voltage of the bit line 304 is set to ground level by NMOS 333 with pre-charge true (PT) signal, while the NMOS 331 and 332 are turned on. After then, pre-charge true (PT) signal is lowered to ground level before the read word line 307 is asserted. When the bit line 304 is reached to the threshold voltage (VTN) of the pull-down NMOS 335, pull-down device 335 is turned on, when the switch 332 is turned on by the inverter 343 which is driven by the latch node 337, where the latch node 337 is set by pre-charge-bar (PB) signal. As a result, a current path is set up from the read word line 307 to the bit line 304, which is read “1” operation. Hence, the read word line 307 indirectly turns on n-p-n Q2 through p-n-p Q1. In other words, diode access device detects whether the storage node is at forward bias or not. In this manner, the diode access device serves as a sense amplifier when read. When the current path is set up, the read word line voltage is determined by the result of the voltage dividing among the elements, the pull-down NMOS 335, the four-terminal diode, pull-up device of the read word line driver (not shown), and routing resistance.
As a result, the read word line voltage is near the sum of the bit line voltage and built-in voltage of the diode because the pull-down NMOS 335 has low resistance with common gate-drain connection like diode connection, which determines the bit line voltage, and four-terminal diode (including p-n-p Q1 and n-p-n Q2) has lower resistance, where the pull-up device of the read word line driver has high resistance at linear region, and routing resistance is negligible. After then, the current mirror 336 repeats the amount of the bit line current, where the current value can be controlled by the channel width, length, and multiple mirrors. By the current mirror, the pre-charged node 337 is discharged from pre-charged voltage to ground, where the latch node 337 is pre-charged by the PMOS 338 when pre-charge bar (PB) signal is at ground level during standby. After pre-charging, PB signal is de-asserted before the read word line is asserted. Hence, the data output (DO) of the inverter 339 is changed from low to high, and transferred to next stage (not shown). After latching the stored data, feedback inverter 340 and inverter 339 keep the stored data. Simultaneously, the switch 332 is turned off by the output 344 of the inverter 343 (at ground level), thus the data latch cuts off the current path of the bit line after reading data “1”, in order to reduce the active current.
After transferring data output DO, the read word line 307 is de-asserted to VL level to finish the read cycle. By lowering the read word line 307 to VL level, the collector 303 of p-n-p Q1 (also the base 303 of n-p-n Q2) is discharged by the read word line 307, but the read word line can not fully discharge the collector 303, because p-n-p Q1 is turned off when the collector 303 is reached around built-in voltage VFP. The remained charges are swept by the forward bias (from p-type region 303) to n-type region 304 because the read word line does not provide positive charges after de-asserted to VL level and the forward bias leakage current sweeps the remained positive charges. In general, forward bias leakage is much higher than reverse bias leakage. As a result, the diode access device can fully cut off the current path during standby or unselected after the read word line is de-asserted to VL level. In doing so, the unselected cell does not generate any interference or noise when read and write data. Furthermore, the read operation is nondestructive because the storage node 302 is still in forward bias region, but the stored voltage is slightly raised from ground level to VTN+VCE level. More detailed explanation will be followed in FIGS. 4C and 4D.
During read data “1”, the current mirror repeats the amount of the bit line current. At the same time, the pull-up PMOS of the feedback inverter 340 resists the latch node 337 to be discharged by the current mirror, which means that the current through the mirror should be higher than that of the pull-up device of the inverter 340. When the supply voltage is high enough, such as 1.2V, the current flow through the bit line is high enough to flip the latch node 337 even though the feedback inverter resists. In order to reduce the operating voltage, a bias voltage is applied to the pull-up device 341 of the feedback inverter, which effectively regulates the pull-up current. When the read word line 307 is asserted, the bias signal 342 is asserted. On the contrary, the slightly strong pull-up device 345 is turned on by the control signal 346, when the read word line is de-asserted, which keeps the stored data after the read word line is de-asserted. In order to reduce the operating voltage, lower built-in voltage is required, where the built-in voltage is determined by the p-n junction of the material. Additionally, lower threshold voltage of the current mirror is required as well. Furthermore, the bias voltage is generated by the dummy cell, which will be explained in FIG. 7.
In order to read data “0”, the read word line 307 is asserted, but p-n-p Q1 is not turned on because the storage node 302 is reverse-biased from the first terminal 301 which is connected to the read word line 307, when the storage node voltage is higher than the word line voltage. Hence, read data “0” is quite different from read data “1”. Neither the forward bias is established nor the current path be set up. In doing so, p-n-p Q1 and n-p-n Q2 are turned off. The storage node voltage is not changed, and the bit line voltage is not changed either. And the pre-charged node 337 is not changed because the current mirror 336 does not flow any current. Hence, data output DO keeps VL level. Neither the latch device require the reference voltage nor wait long discharging time of the bit line, while the conventional comparator type sense amplifier requires the reference voltage to compare, and waits the bit line to be discharged enough voltage because the MOS transistor is slow with shallow inversion layer.
Referring now to FIG. 4A in view of FIG. 3C, I-V curve of the memory cell is depicted. By raising the read word line, the diode is turned-on at Ion when the word line is reached to built-in voltage of the diode. After then, the current is saturated at Isat. During saturation, the word line voltage (VWL) is determined by three elements, such as the gate voltage (near threshold voltage, VTN) of pull-down NMOS device (335 in FIG. 3C), the collector-emitter voltage (VCE) of n-p-n Q2 in FIG. 3C and the base-emitter voltage (VBE) of p-n-p Q1 in FIG. 3C. Once the diode is turned on when reading data “1”, the current path is sustained by the feedback loop, which also sustains the word line voltage (VWL). On the contrary, when reading data “0”, the diode does not flow any current, except Ioff current (reverse bias leakage). And during standby, the read word line is de-asserted to ground level by the row decoder (not shown). Hence, there is no standby current except leakage current.
In FIG. 4B, I-V curve of conventional bipolar transistor is illustrated as a reference. The bipolar transistor's usefulness may be terminated as the collector voltage is increased, which is called “punch-through” or “reach-through” as described in the reference, “Microelectronics: Digital and Analog Circuits and Systems”, pp. 83, Jacob Millman, Ph. D. 1979 MacGraw-Hill, Inc. ISBN 0-07-042327-X, where punch-through is occurred when the base-collector voltage reaches a certain (device specific) value, the base-collector depletion region boundary meets the base-emitter depletion region boundary. When in this state the transistor effectively has no base. The device thus loses all gain when in this state. Thus, punch-through should be avoided having enough base area, or reducing the collector-emitter voltage. In the present invention, punch-through is simply avoided by selecting wide base region or reducing the collector-emitter voltage.
In FIG. 4C, more detailed read operation is illustrated with I-V curve in linear scale. By raising the read word line, the forward bias is set up from the read word line to the storage node when the storage node is near ground level. Thus, a current path is established at Ion point, which means that the NMOS pull-down transistor is turned on by the current path. After then, the read word line is raised higher. As a result, the current path is saturated at Isat point, because the read word line is raised by the strong driver. In contrast, the reverse bias is set up when the storage node is higher than the supply voltage, which is read “0”. Hence, no current path is set up except the reverse bias leakage current.
In FIG. 4D, I-V curve in log scale is illustrated, wherein the current path is established at Ion point, and the current path flows more current at Isat point when the read word line voltage is raised higher. When the storage node voltage is in forward bias, the current is increased exponentially from Ion point to Isat point. This graph shows that the diode sets up a current path as long as the forward bias, but the amount is different depending on the voltage, which means the strong forward bias can set up higher current flow to the pull-down device. This means that the high operating voltage can set up higher current, and achieves fast access time. When the stored voltage is higher than the supply voltage, the reverse bias is set up, but the reverse bias leakage is less affected depending on the stored charge as long as the storage node voltage is higher than the read word line voltage, which voltage is near the supply voltage when read.
In FIG. 5A, more detailed read path is illustrated as the present invention. In the memory array, multiple memory cells are connected to read word line 501 and a plate line 506, such that the memory cell 500A stores data “1” in the storage node 502A, the memory cell 500B stores data “0” in the storage node 502B, and dummy cell 500D stores data “1” in the storage node 502D. When read, at least one memory cell is turned on, in order to sustain almost same voltage of the read word line 501 regardless of the data pattern. In doing so, single or multiple dummy cells are added to limit the read word line voltage, as explained in FIG. 4A. Without dummy cell, the word line voltage can be reached to VH level by the pull-up device 520 of the word line driver, when all the stored data are “0” because all the memory cells are turned off. In order to apply strong reverse bias during read, the read word line voltage is sustained slightly lower than VH level by turning on at least one dummy cell, and the current does flow through the pull-down NMOS 521.
Thus, the read word line voltage is determined (as VWL in FIG. 5B), such that the read word line voltage is the sum of three elements, such as the gate voltage VGS (near threshold voltage of pull-down NMOS 521), VCE (the collector-emitter voltage of n-p-n Q2 in FIG. 3C), and VBE (near built-in voltage of p-n-p Q1 in FIG. 3C), where the gate voltage VGS is 0.25˜0.3V range in recent MOS transistor, VCE is lower than 0.1 v which is ignorable with strong bipolar gain, and VBE is 0.6˜0.8V for silicon, for example. In addition, the voltages depend on the ratio among the resistances of three elements. Moreover, the read word line voltage depends on temperature, because threshold voltage of MOS transistor and built-in voltage of bipolar transistor are decreased as temperature is increasing. As shown example in FIG. 5B, the read word line voltage VWL is 1.1V at 0° C. As temperature is increasing, the read word line voltage is decreased to 0.85V at 100° C. More detailed current-voltage curves are illustrated in FIGS. 5C, 5D and 5E. The I-V curve of pull-down NMOS transistor 521 is shown in FIG. 5C, wherein the threshold voltage of NMOS transistor is VTN, and the applied voltage of the transistor is VGS, where VGS level is determined by the current flow including pull-down NMOS, p-n-p-n diode and pull-up PMOS. Thus, VGS level is near threshold voltage of NMOS transistor when the diode is fully turned on and in latching state with the feedback loop, but VGS level is only slightly changed when the current is changed more because the curve is very steep above the threshold voltage of NMOS transistor. The I-V curve of base-emitter of p-n-p transistor is shown in FIG. 5D, wherein built-in voltage (or threshold voltage) of p-n-p Q1 transistor is VFP, and the applied voltage of the transistor is near VBE level, where VBE level is determined by the current flow including pull-down NMOS transistor, p-n-p-n diode and pull-up transistor 520. Thus, VBE level is near built-in voltage, but VBE level is only slightly changed when the current is changed more because the curve is very steep above the built-in voltage of p-n-p Q1 transistor. In FIG. 5E, I-V curve of pull-up device 520 is shown, wherein the applied voltage of pull-up transistor 520 is determined by subtracting the word line voltage VWL from VH level of supply voltage, which curve is less steep, thus the applied voltage of pull-up PMOS is varied by the read word line voltage. The applied voltage of pull-up transistor is VH−VWL as shown in FIG. 5E.
And the bit line voltage is near VGS level if the bit line resistance is ignorable, and the collector-emitter voltage VCE of n-p-n Q2 is relatively low because collector current is much higher than base current when the bipolar transistor is turned on in nature. Hence, VCE level is lower, which is ignorable. In this respect, the storage node voltage (VTN′) is very close to VTN level, when the stored data is “1”, where VTN′=VTN+VCE, and VTN′=VWL−VBE as shown in FIG. 5B.
By asserting the read word line 501, the memory cell 500A and 500D are turned on because the forward bias is set up from the read word line 501 to the storage nodes, where the storage node 502A and 502D are near ground level. After read, the storage nodes are raised to VTN′ level by the current flow. And then, the storage nodes are leaked by the reverse bias leakage through the emitter which is connected to the read word line 501 at VL level during standby, which helps to read data “1” by establishing the stronger forward bias for the next read cycle.
When the stored data is “0”, there is no current path, such that the memory cell 500B is not turned on because the storage node voltage 502B is higher than the read word line level (VWL), which results in reverse bias. With no current consumption when read “0”, power consumption is reduced. When all the memory cells store data “0”, only dummy cells are turned on, in order to apply strong reverse bias for the memory cells storing data “0”. Turning on dummy cells, the read word line voltage is limited lower than VH level as explained above, at VWL level.
Referring now to FIG. 6A in view of FIGS. 5A and 3C, timing diagram for read “1” operation is illustrated. In order to start read cycle, the read word line (RWL) 601 is asserted, while the plate line (PL) 606 keeps constant voltage and the write word line keeps low (not shown). Thus, the read word line voltage is reached to VWL level. When the stored data is “1”, the storage node (SN) 602 is near ground level. By asserting the read word line (RWL) 601, a forward bias is established. And then, the floating node (FN) 603 (which serves as the base 303 of n-p-n Q2 in FIG. 3C, and also the collector 303 of p-n-p Q1 in FIG. 3C) is raised near word line voltage. At the same time, n-p-n Q2 is turned on, which raises the bit line 604. When the bit line 604 is reached to threshold voltage (VTN) of pull-down NMOS 621, the pull-down NMOS is turned on. The bit line current IBL1 is appeared, such that Ion current is set up at the beginning of the asserting of the read word line. After then, the current path is saturated at Isat, thus, the storage node (SN) is raised around VTN′ level, and the bit line keeps around VTN level. While the read word line 601 is enabled, the control signal 612 sets up a bias voltage for the feedback inverter as shown 341 FIG. 3C. And the control signal 341 in FIG. 3C is disabled after the word line is de-asserted. And then, the control signal turns on the strong pull-up device 345 with another control signal 346 in FIG. 3C. In order to reduce the operating voltage for the memory array, the ratio between the current mirror (336 in FIG. 3C) and the feedback inverter (340 in FIG. 3C) is carefully adjust such that the current flow through the current mirror is 10 times higher, because the bit line current is drastically reduced at low voltage, where the bit line current is determined by the built-in voltage of the diode and the threshold voltage of the pull-down NMOS. Furthermore, the current is reduced at cold temperature. In order to reduce the operating voltage and increase the bit line current, germanium diode and Schottky diode can be useful. However, leakage current is relatively higher. Thus, retention time will be reduced, which means that more refresh cycles are required for the system applications. Additionally, low threshold MOS transistor is available to reduce the operating voltage, which requires more process steps, such as additional implant mask.
Referring now to FIG. 6B in view of FIG. 5A, timing diagram for read “0” operation is illustrated. The word line 651 is asserted to start reading data, where the plate line (PL) 656 keeps constant voltage and the write word line keeps low. Unlike read “1”, when the read word line 651 is raised, the forward bias is not established between the storage node 652 and the read word line 651, because the storage node 652 is higher than VH level. Hence, reverse bias is set up. As a result, there is no current path (IBL0) so that there is only leakage current Ioff. Thus, the floating node (FN) 653 keeps ground level with no pull-up current from the p-n-p transistor. Read “0” does not consume current from the read word line 651 to the bit line 654, which helps to save active power. After reading data “0”, the storage node is not changed, and the storage node (SN) is still in forward bias even though the node is slightly raised by the diode, thus the read operation is nondestructive.
When reading data “1”, the current is established while the word line is turned on. In order to reduce the power consumption, a replica delay signal is generated by the far-end dummy cell, as shown FIG. 6C. And the replica delay signal is returned to the read word line decoder, which signal de-asserts the read word line, wherein the nearest dummy word line RWL0 is asserted first, and next word lines are asserted sequentially, such as RWLi, RWLi+1, and RWLi+n. As a result, the bit lines, BL0, BLi, BLi+1 and BLi+n are sequentially raised by enabling read enable signals, RD0, RDi, RDi+1 and RDi+n. The related schematic is illustrated in FIG. 7.
In FIG. 7, more detailed read path is illustrated, wherein the memory cells 731, 732, 733 and 734 are connected to the read word lines RWL0, RWLi, RWLi+1 and RWLi+n from the read word line driver 719, and the memory cells are also connected to the read data latches 781, 782, 783, and 784 through the bit lines BL0, BLi, BLi+1, and BLi+n, respectively. And the memory cells are connected to the plate line (PL) and the write word line (WWL) which are part of the local row decoder 718.
In order to read data from the memory cells, the pre-charge true (PT) signal and the pre-charge bar (PB) signal are de-asserted, before the read word line is asserted. In doing so, the bit lines BL0, BLi, BLi+1 and BLi+n are floating. And the read enable (RD) signal is asserted to high. At the same time, the read word line (RWL) is asserted to high, while the plate line (PL) keeps high and the write word line (WWL) keeps low. By asserting the read word line (RWL), the nearest dummy cell 731 is turned on, which stores data “1” and sets up a current path from the read word line to the read latch device 761. Thus, the current path through the bit line BL0 raises the node 758 near the threshold voltage of the NMOS pull-down device. During read, the PT signal is low, thus the NMOS pre-charge device 751 and 757 are turned off, and the PMOS 753 is turned on. When the signal 758 is reached to the threshold voltage of the NMOS 756, a current path is set up through the PMOS 754 and 755. Hence, the bias voltage is raised by the current repeater circuit 750, where the current flow through the repeater devices 754, 755 and 756 is the same as the bit line current if the NMOS pull-down devices have same width and length. In this manner, the latch node of the (dummy) read data latch 781 is changed from the pre-charged VH level to VL level by the current mirror 761, because the pull-up device of the feedback inverter 759 is, for instance, 10 times weaker than that of the current mirror 761 when the bias signal 752 from the repeater circuit 750 is raised by the PMOS 754, where the pull-up PMOS 754 is 10 times stronger than the current repeater 759, such that 10 parallel devices (or 10 times wider channel) are used with the same channel length for the pull-up PMOS 754. Before the bias signal 752 is raised, the pull-up device 759 is relatively stronger than the current mirror, while the bias signal 752 is near ground level. The advantage of the biased pull-up device 759 is that the comparison between the bit line current and the pull-up current of the feedback inverter 759 is very accurate. Thus, the operating voltage can be reduced and also the bit line current itself can be reduced, in order to save power consumption, which reduces the current loading of the read word line as well. Hence, the read word line driver circuit can be smaller. For example, each bit line current can be reduced lower than 1 uA, thus the pull-up current of the feedback inverter is 0.1 uA. In doing so, wrong latch operation is prevented, because the latch node is not flipped before the bias signal is fully set up. The bias signal 752 is pre-charged to ground level before the read word line is asserted. Hence, the pull-up device of the feedback is very strong, before the bias signal is not set up. And the bias signal 752 is shielded from the adjacent signals to avoid coupling noise. After measuring all the stored data, the replica signal 726 and 727 are returned to the control circuit 725 which turns off the read word line (RWL). With this feedback scheme, the bias signal 752 is floating after the read word line is grounded. In order to sustain the latched data “0” after then, a pull-up device 763 is enabled by a signal 723B which is an inverted signal of the read word line enable 723. The latched data “1” is not affected even though the read word line is de-asserted, because the data “1” is sustained by the NMOS of the feedback inverter.
After establishing the dummy bit line current through the dummy bit line BL0, the dummy latch device 781 keeps the bit line current, in order to maintain the read word line voltage until the far end dummy data latch 784 generates a replica delay signal 727, and one more signal 726 can be generated by another far end dummy column (not shown), which means that the read word line can be controlled by one of dummy data latch, even though a dummy cell has failed. Thus, the inverter output 764 is floating, and NMOS transistor 760 is always on to keep the current path of the nearest dummy column. After the latch node 762 is flipped, the signal is transferred to OR gate 765. And the OR gate 765 generates the read enable (RD0) signal, in order to start measuring the bit line current of the main memory cells, which OR gate receives multiple signals from multiple dummy column. Thus, the replica delay signal RD0 is generated as long as one dummy column works, where only one dummy column BL0 is illustrated for simplifying the schematic. The OR gate 765 includes delay circuits to add time interval for measuring the main memory cell. In doing so, simultaneous current flow through the bit lines are reduced. When the read enable RD0 signal is reached to high, the latch device 782 measures the bit line current. When the bit line is raised by the diode if the stored data is “1”, the latch device 782 sets up a current path, and the current mirror latches the data. Thus the data output of the latch 782 is raised to high. Otherwise, the output keeps low if the stored data is “0”, because the bit line keeps low with no diode current. And the delay circuit 766 generates next read enable signal RDi for the next latch device 783, wherein the AND gate 766 receives RD signal and RD0 signal (from dummy cell), thus the AND gate generates RDi signal through the delay circuit. In this manner, all the bit line currents are measured by the read data latch sequentially with the time interval of the circuits 766 and 767, as long as the delay time is longer than the latching time. When the delay time is faster than the latching time, the read word line loading is increased, which may cause in stuck with no flipping of the rest of the latches 783 and 784. This should be avoided. With the sequential latching scheme, the read word line loading is only a few columns, in terms of the current loading, where each column has a delay circuit. Alternatively, the columns are grouped, and a delay circuit controls a group of columns to reduce area. In this case, the read word line should provide more current.
In order to control the memory cells efficiently, the row decoder 710 includes global row decoder 711 and local row decoder 718. One global row decoder 711 may drive multiple local row decoders, even though one local row decoder 718 is illustrated in FIG. 7 for simplifying the drawing. The global row decoder 711 receives row address through AND gate 712. When the AND gate 712 is selected, next stage AND gates 713, 714 and 715 are activated. Hence, the AND gate 713 is raised to high when the row decoder enable signal 723 is asserted to high, because the output of AND gate 712 is asserted to high before the enable signal 723 is asserted to high. To do so, the read word line control circuit 725 generates the signal 723 with the start signal 724 and feedback signals 726 and 727. The feedback signals are generated by far-end dummy column, in order to detect the completion of measuring of the far-end dummy columns. At least, one far-end dummy column generates a feedback signal. And the AND gate 714 is asserted to high when the plate control signal 716 is activated. One more enable signal is generated by the AND gate 715 to control the write word line, when the write control signal 717 is asserted.
The local row decoder includes three elements AND gate 719 (comprising NAND and inverter), NAND gate 720, and the AND gate 721, wherein the AND gate 719 generates the read word line (RWL), the NAND gate 720 generates the plate line (PL), and the AND gate 721 generates the write word line (WWL), when the local column selector 722 is asserted to high. As shown in FIG. 7, the plate line and the write word line drive only capacitive loading, but the read word line drives capacitive loading and the current loading through the pull-down transistors of the data latches, 781, 782, 783 and 784. The capacitive loading is simply managed by selecting the total number of the memory cells, thus, the capacitive loading of the plate line and the write word line can be simply determined. However, the read word line loading depends on how many memory cells store data “1”. When all the memory cells store data “1”, the read word line raises all the bit line to the threshold voltage of NMOS pull-down device.
An equivalent circuit of the read path is illustrated in FIG. 8A, wherein the local memory block 810 includes the read word line driver 820, the read word line 831, the dummy bit lines 832 and other bit line 836. The local read word line 831 is raised by the p-n-p transistor 828 to supply high current. When the read word line enable 801 is asserted to high, the pulse generator 803 generates a low pulse during the pre-determined time, such that more detailed pulse generator 850 is illustrated in FIG. 8B. The output 855 generates a low pulse when the input 851 is rising, so that the NAND gate 854 generates a low pulse only if the output 853 of the inverted delay circuit 852 and the input 851 are at high state. In doing so, the pulse generator 803 generates a low pulse. Thus, the read word line control circuit 800 generates a read word line enable signal 808. When the read word line enable signal 808 is asserted to high, the global read word line decoder 812 raises the global read word line 813, because the output of the address decoder 811 is already asserted to high. And the column select signal 814 is also asserted to high. Hence, the NAND gate 821 is activated, such that the output 822 is lowered, the inverter 824 turns on the n-p-n transistor 827. Thus, the base 826 of the p-n-p transistor 828 is turned on, which pulls up the local read word line 831. At the same time, the PMOS transistor 825 is turned off, and also the NMOS 829 is turned off before the p-n-p transistor 828 is turned on. When the p-n-p transistor is turned on, the local read word line 831 is quickly reached to the voltage VF+VT, where VF is built-in voltage of the diode and VT is the threshold voltage (VT) of the NMOS transistor of the data latch, after then the ramping depends on how many cells store data “1”. Thus, the data latching time is the charging time of the bit line. For instance, the charging time (Tau) is the equivalent resistance 833 of the diode (R) multiplied by the bit line capacitance 834 (C), so that the charging time is ins when the diode resistance is 10K ohms and the bit line capacitance is 100 fF, approximately. And for another example, the charging time is 2 ns when the diode resistance is 20K ohms and the bit line capacitance is 100 fF. In the calculation, the resistance of the read word line is ignored because the p-n-p transistor 828 includes relatively lower resistance.
After the bit lines are charged to the threshold voltage of the NMOS transistor, the pull-down NMOS transistor serves as a current source 835 equivalently, which is a part of the read data latch (781 as shown in FIG. 7), but the next data latch (782 in FIG. 7) waits until the read enable signal RD0 is asserted by the delay circuit (765 in FIG. 7). In this manner, only the current of the dummy bit line BL0 is the current loading of the read word line 831. And then, the next current source 837 of the data latch is turned through the bit line 836 on after the read enable signal RD0 is asserted to high. Thus, all the data are latched sequentially by the delayed read enable signal. At last, the far-end dummy data latch generates a signal to turn off the read word line, as shown 815 and 816. Furthermore, multiple far-end dummy columns generate the replica delay signals, in order to close the read word line even though one of the far-end dummy cell is failed. When the replica delay signals 815 and 816 are arrived, the read word line control circuit 810 de-asserts the read word line enable signal 808, such that the pulse generator 805 generates a low pulse, thus the output of the NAND gate 806 is raised to high. And then, the output of the NAND gate 804 is changed to low, because the output of another pulse generator 803 is already high, as explained above, where the latch circuit including two NAND gates 804 and 806 is reset by the power-up reset signal 802, during power-up, such that the power-up signal 802 is asserted to low during power-up, after then, the power-up signal 802 is always at high. The advantage of using bipolar driver circuit for the decoder is that the strong drive current can be provided by the bipolar transistor and the area of the driver is relatively small. There were many efforts to use the bipolar driver circuits on the wafer as reported, “BiCMOS buffer circuit”, U.S. Pat. No. 5,430,398. However, the prior art of the bipolar driver circuit can provide relatively low current because the base current of the output portion is driven by the MOS transistor. Moreover, the n-p-n transistor is turned off when the output node is reached to VH level-VF level (built-in voltage), which means that the prior art is only useful to drive relatively high supply voltage, such as 5V and 3.3V. In the present invention, the output portion 828 of the bipolar buffer circuit is also driven by the reverse type of bipolar transistor 827, and the reverse type of bipolar transistor is enabled by a MOS transistor of the inverter 824, so that the MOS transistor current I1 enables the n-p-n transistor 827, the collector current I20 turns on the p-n-p transistor 828, and the strong collector current I400 drives the read word line 831. For example, the current flow is amplified to 400 times from the MOS drain current I1, if the bipolar collector current gain is 20. And the bipolar transistors can be formed from the same layer for the diode access device, such as deposited polysilicon layer or single crystal layer of the SOI type wafer. In the prior art, the bipolar transistors can not be easily optimized on the conventional bulk CMOS process because all the transistors share the same substrate, such as p-type and n-type substrate.
In the present invention, the diode access device is not sensitive to storage capacitance variation while storing data. This means that the storage capacitor only contributes to set up the initial condition of storage node when read, while the prior art of capacitor memory is very sensitive to the capacitance value because the stored charges are redistributed with the heavily loaded bit line through the MOS access transistor. In the present invention, there is no need of high capacitance to read. Furthermore, the diode also serves as a sense amplifier to detect the initial voltage of the storage node whether it is forward bias or not, when the read word line is asserted to read. After detecting the forward bias, the diode is turned on, which sets up the current path to the bit line. In doing so, the memory yield will be increased by reducing the sensitivity of the capacitance variations. Moreover, access time is fast because the diode current is much higher than that of MOS access transistor. The capacitance variation may cause the retention time very slightly, but the retention is more sensitive to the leakage current of the storage node, so that low leakage MOS transistor and low leakage capacitor can be useful, and the diode should have low reverse bias current.
In FIG. 9A, the write path is illustrated. The write operation is similar to the conventional DRAM, wherein the MOS write device 909 is turned on by the write word line 908. Thus, the charges of the bit line 904 are transferred to the storage node 902 by the inversion channel. The storage node 902 can be fully discharged to low through the NMOS transistor 909, but the storage node 902 can not be charged to full level of the supply voltage, because the NMOS channel is disappeared when the storage node 902 is reached near (VH−VT) level where VT is the threshold voltage of the NMOS transistor. In order to charge full level, the write word line can be raised to higher than the supply voltage as the conventional DRAM. Alternatively, the plate line is raised in order to couple the storage node when write data “0”. Before the write word line 908 is asserted to high, the plate line 906 is lowered, which clears the storage node. After then, the plate line 906 is raised to couple the storage node 902, so that the storage node 902 is raised to higher than the supply voltage when the storage node is floating, which means that the NMOS transistor 909 is floating after the storage node is reached to VH−VT level (the supply voltage minus the threshold voltage of the NMOS transistor). In contrast, the storage node keeps ground level when the bit line is asserted to low because the NMOS transistor 909 strongly discharges the storage node with no threshold voltage drop. Hence, the plate line 906 can not couple the storage node when the stored data is “1”. One of aspect of the present invention is that the MOS access transistor can be coarse MOS transistor, because the MOS transistor does not work for the read operation, which serves only as a write device. Even though the current flow through the MOS device is weak, the plate line can raise the storage node when write data “0”, otherwise the storage node keeps ground level with no threshold voltage drop when write data “1”. Furthermore, the storage capacitor is relatively smaller than the conventional DRAM. For example, the storage capacitor is 2 fF, which is 10-15 times smaller than the conventional DRAM capacitor (20-30 fF), in these days. Thus, the write time through the MOS transistor is still faster than the conventional memory, such that the charging/discharging time is only 2 ns, when the turn-on resistance of the MOS transistor is 1 mega ohms, and the capacitor is 2 fF. Moreover, the plate line reduces the write time. Hence, the approximate write is faster than ins with the plate line coupling to write data “0”, while writing data “1” is even faster because the NMOS transistor is strong enough to discharge to ground level. But too weak turn-on resistance may cause a fail to write data “1”, because the storage node is coupled by the plate line, which should be avoided.
In FIG. 9B, an equivalent circuit of the memory cell when the data is retained. After storing the charges to the storage capacitor, the leakage helps to store data “1” near ground, because all the adjacent nodes are pre-charged at ground level, expect the plate line, where the leakage to the plate line is negligible with thick oxide capacitor. On the contrary, the leakage reduces the storage data “0”, which is higher than the supply voltage. The retention time is approximately calculated, such that the discharging time dt=c×dv/i=2 fF×1V/1 fA=2 sec, where c is the capacitance of the storage node, dv is the discharged voltage level of the storage node, and i is the total leakage of the storage node during retention. The diode access device can store data “0” until the discharged voltage is higher than 1V because the diode is turned off only if the storage node is higher than VTN′ level as explained above. In these days, the leakage of the storage node is around 1 fA for the conventional DRAM, and the discharged voltage is near 0.1V. The discharge voltage is extremely sensitive to the read operation, because the storage capacitor directly drives the heavily loaded bit line. In these respects, the retention time of the present invention is similar or longer, so that the leakage can be similar with the conventional DRAM process. Furthermore, leakage helps to store data “1”. And one aspect of the present invention is that the MOS write device can use a thin-film MOS transistor, because the MOS transistor serves only as a write device. And the leakage of the MOS write device can be reduced. For instance, the leakage current of the storage node can be reduced 10 times lower. In this case, the retention time is increased to 10 times, such that the retention time is 20 sec, dt=c×dv/i=2 fF×1V/0.1 fA=20 sec, approximately.
In FIG. 10A, the read-write circuit and the memory cell are illustrated in order to explain read-modify-write operation, wherein the read-write circuit 1030 is connected to the memory cell 1000 through the bit line 1004. Even though the read operation is nondestructive as explained above, the storage node voltage is slightly changed after reading data. For instance, the storage node 1002 is raised to VTN′ level (VTN+VCE level as shown FIG. 5B) from the ground level when the stored data is “1”, and the storage node voltage is raised slightly higher after the bit line is floating with the sequential read operation as shown in FIG. 7. And the data “0” is also slightly coupled by the read word line after read operation. Thus, the storage node voltage is written back after read operation, such that the selector circuit 1045 selects the writing voltage after read, wherein detailed selector circuit is illustrated in FIG. 10B. The CDi signal is inverted by the inverter 1051 to switch the transmission gates 1052 and 1053. When CDi signal is low, DO signal is transferred to output node C through the transmission gate 1052. And when CDi signal is high, DI signal is transferred to output node C through the transmission gate 1053.
And the refresh operation is similar to the read operation, except the output DO is not transferred to the external port (not shown). During read or refresh cycle, the read word line is asserted and the stored data is transferred to the latch node 1037 through the bit line 1004. The latched node 1037 is pre-charged to high by the PMOS transistor 1038 when the pre-charge bar (PB) signal is low, and the MOS switches 1031 and 1032 are turned on, before the read word line is asserted. When the stored data is “1”, the current path is set up through the diode, wherein the diode includes four-terminals, the first terminal 1001 is connected to the read word line 1007, the second terminal 1002 is connected to the storage node of the capacitor 1005, the third terminal 1003 serves as the floating body of the MOS transistor 1009, and the fourth terminal serves as the bit line 1004. Hence, the current mirror 1039 repeats the amount of the current flow of the pull-down NMOS transistor 1035 through the common node 1033. At this time, the pre-charge devices 1034, 1038, and 1047 are turned off. During read, the current limiter 1041 is turned on in order to regulate the pull-up current of the feedback inverter 1040. And the pull-up transistor 1042 sustains the pull-up after the current limiter is turned off. Thus, the stored data is latched to the latch node 1037, and the output node DO is asserted to high. After then, the read-out data is transferred to the write driver circuit 1046 through the selector circuit 1045 when the column decoder signal CDi is at low. In order to restore the data, the write driver circuit 1046 is enabled, and then the write word line 1008 is asserted to high to turn on the MOS transistor. In doing so, the storage node voltage 1002 is fully discharged to ground level to restore data “1”. When the stored data is “0”, the storage node 1002 is raised by the plate line 1006 while the MOS transistor 1009 is turned on. In contrast, the read-modify-write changes the write data through the selector circuit 1045, such that the column decoder signal CDi is asserted to high, and the external data input DI is transferred to the bit line. Hence, the external data input DI is stored in the storage node 1002.
The detailed timing diagrams are illustrated in FIG. 11A to 11D. The read “1” operation is illustrated in FIG. 11A, wherein the read word line (RWL) 1107 is asserted to high, thus the floating node (FN) 1103 (also the base 1003 of the n-p-n transistor as shown in FIG. 10A) is raised because the p-n-p transistor is turned on by the storage node (SN) 1102 near the ground level, which sets up a current path. After then, the current path is sustained by the feedback loop of the diode. As a result, the bit line 1104 is raised, which establishes the bit line current (iBL) 1114. In doing so, the data output (DO) is raised by the current mirror and latched to the latch device (1040A and 1040 in FIG. 10A), while the data input (DI) is don't care during read operation. After reading data “1”, the write word line (WWL) 1108 is asserted to write back the latched data in the output node (DO). Before the write word line is asserted, the read word line 1107 is de-asserted, and the plate line (PL) 1106 is lowered. Hence, the storage node is slightly lowered under the ground level, but the storage node is reached to −VF level (built-in voltage) because the n-type storage node is forward biased. And then, the write word line 1108 is asserted to high to turn on the MOS write device. Through the inversion channel of the MOS write device, the ground level of the bit line is transferred to the storage node 1102. At the same time, the plate line 1106 is returned to high level, but the storage node keeps ground level because the MOS transistor is still turned on.
In FIG. 1B, the read “0” operation is illustrated, wherein the storage node is higher than VH level, thus the reverse bias is established when the read word line (RWL) is asserted. In doing so, no current path is set up after the read word line is asserted. Hence, the bit line (BL) keeps the pre-charged voltage at ground level, and the latch node is still the pre-charged voltage at VH level. The data output (DO) keeps low. After read data “0”, the read word line is de-asserted, and the plate line (PL) is lowered to clear the storage node (SN), which couples the storage node lower than VH level. And then, the bit line is raised by the write buffer. The write word line is raised to high, in order to transfer the bit line voltage at high to the storage node. Hence, the storage node voltage 1122 is slightly raised, but the inversion channel of the MOS write device is disappeared when the storage node is reached to the threshold voltage of the MOS transistor. Thus, the storage node is floating at this time. After then, the plate line is returned to high, in order to couple the storage node to higher voltage than the supply voltage while the storage node is floating. Then, the bit line is pre-charged to ground level for the next cycle. The advantage of the write-back operation after read is that the storage node voltage is refreshed for the next read. In this manner, the refresh operation is also the same as the read operation with write-back, except no output to the external port. Thus, the timing diagram 11A and 11B illustrate the refresh operation as well.
In FIG. 11C, read-modify-write operation is illustrated, wherein the read word line (RWL) reads data “0”, and the write word line (WWL) writes data “1”. After read, the data output (DO) is remained in the latch node, but the external data input (DI) is transferred by the selector. Thus, the read operation and the write operation are independently executed by the selector. In FIG. 11D, read-modify-write operation is illustrated, wherein the read word line (RWL) reads data “1”, and the write word line (WWL) writes data “0”. After read, the data output is remained in the latch node, but the external data input (DI) is transferred by the selector, as FIG. 11C.
In FIG. 12A, the whole read path including the output driver circuit is illustrated, wherein the memory cell 1200 (1000 in FIG. 10A) and the read-write circuit 1230 (1030 in FIG. 10A) are connected to the output driver circuit including p-n-p pull-up 1261 and n-p-n dull-down 1267, and the output pad 1271 is connected to the receiver circuit 1276 through the transmission line 1272, where the multiplexers between the output driver and the read-write circuit 1230 are omitted for simplifying the schematics. The data in the memory cell 1200 is latched to the read data latch 1230. And then, the data output 1251 is transferred to NAND gate 1255 and NOR gate 1254 which are part of the output driver circuit. After arriving the data output 1251, the output enable signal 1252 is asserted to high to transfer the data output. When the read data is “1”, the NAND gate 1255 generates a logic low, which raises the output of inverter 1256 to high, thus the PMOS 1257 is turned off and the NMOS 1260 is turned on. At the same time, a pulse generator 1258 generates a high pulse to turn on the n-p-n transistor 1259, wherein more detailed schematic of the pulse generator 1258 is illustrated in FIG. 12B, and the timing diagram is illustrated in FIG. 12C. When the input signal 1281 is lowered, an inverter chain 1282 is generates a delayed signal 1283, and the NOR gate 1284 generates a high pulse based on the delay, where the delay time is longer than the transition time of the output node 1271. In this manner, the p-n-p output driver 1261 provides enough current to drive the heavily loaded output trace, when the base current is driven by the n-p-n transistor 1259. Simultaneously, the NMOS 1260 provides a weak base current. Hence, the NMOS 1260 keeps turn-on state of the p-n-p transistor after the strong n-p-n transistor is turned off by the delay circuit. And the resistor 1269 makes the pull-up path more linear when driving the output node. And the termination resistor 1273 is added in order to reduce reflection which is caused by the long transmission line 1272, while the short transmission line generates less reflection. The receiver circuit 1276 receives the data output from the memory cell through the receiving side output node 1274, and the receiver 1276 compares the data output 1274 to the reference signal 1275 which is near the half voltage of the supply voltage.
The falling path is composed of reverse configuration from the rising path, wherein the NOR gate 1254 is raised to high when the output 1251 is low and the output (enable signal) of the inverter 1253 is asserted to low. The p-n-p transistor 1263 is turned on by a low pulse generator 1262, wherein detailed schematic of the low pulse generator is illustrated in FIG. 12D and the timing diagram is illustrated in FIG. 12E, the input signal 1291 is raised to high, an inverter chain 1292 is generates a delayed signal 1293, and the NAND gate 1294 generates a low pulse based on the delay, where the delay time is longer than the transition time of the output node 1271. In doing so, the p-n-p transistor 1263 provides enough base current to the n-p-n transistor 1267. At the same time, inverter 1264 is asserted to low, thus the NMOS 1265 is turned off and the PMOS 1266 is turned on, where the PMOS 1266 keeps the output node 1271 after the strong p-n-p transistor 1263 is turned off by the delay circuit. In order to transfer the data output to the next chip, the bipolar output driver should drive relatively high capacitive loading and the current loading through the transmission line. Thus multiple pull-up and pull-down devices can be added to match the impedance of the transmission line, alternatively.
Using bipolar transistors as the output driver portion has many advantages, such that the speed is fast and the area is reduced. There are many prior arts to use the bipolar transistor as the output driver, as published, “BiCMOS TTL output driver”, U.S. Pat. No. 5,038,058, but as explained above, the bipolar transistors can not be easily optimized on the conventional bulk CMOS process because all the transistors share the same substrate. But now in the present invention, the bipolar transistors can be separately optimized because the bipolar transistors are independently formed from the MOS transistor with deposited thin-film layers.
In FIG. 13A, alternative configuration is illustrated, wherein a ferroelectric capacitor 1305 serves as a storage element, and the other elements are the same as the basic configuration in FIG. 2. The four-terminal diode serves as a read access device, wherein the first terminal 1301 is connected to the read word line 1307, the second terminal 1302 serves the storage node, the third terminal 1303 serves as the body of the MOS write device 1309, and the fourth terminal is connected to the bit line 1304. The write word line 1308 controls the MOS write device, and the plate line 1306 controls the storage capacitor 1305. The retention time would be increased when the ferroelectric capacitor 1305 serves as a storage element with high dielectric constant and low leakage, but the process cost would be increased with metal electrodes, such as platinum.
In FIG. 13B, a series capacitor serves as a storage element, because the storage capacitor does not drive heavily loaded bit line during read. In contrast, the capacitor only stores the charge with low leakage diode and low leakage MOS transistor. Thus, the series capacitor 1315 is equivalently two capacitors 1315A, which means that one of the two capacitors is broken and shorted, but the storage capacitance is increased twice. In consequence, the memory cell operation is very reliable with series capacitor. Furthermore, the memory yield will be increased even though one of two capacitors is shorted. And the other elements are the same as the memory cell as shown FIG. 13A.
And one more useful configuration is illustrated in FIG. 13C with reverse configuration, wherein the diode direction is reversed, the first terminal 1321 is n-type and connected to the read word line 1327, the second terminal 1322 p-type and serves the storage node, the third terminal 1323 is n-type and serves as the body of the p-channel MOS write device 1329, and the fourth terminal is p-type and connected to the bit line 1324. The write word line 1328 controls the MOS write device with active low signal when it is selected, and the plate line 1326 controls the storage capacitor 1325 with active high signal. In doing so, the reverse configuration equally works as a memory cell with reverse signal polarities as well.
In FIG. 14, a useful application is illustrated to use the invented memory as a multi-port memory, wherein multiple access devices share a capacitor storage element 1425. The access devices 1410 and 1430 are independently accessed, thereby the storage node 1422 is connected by a metal line, in order to remove p-n diode effect between the two access devices. Thus there is no interference when one of the access devices is activated by the read word line 1417 or 1437, because the storage node 1422 is reverse-biased for the unselected access device, as long as unselected word line and bit line keep ground level. In doing so, many access devices can be connected to a capacitor storage element. The multi-port memory is configured such that the read word line 1417 is connected to the first terminal 1411 of the p-n-p-n diode. And the p-n-p-n diode is formed with the parasitic elements of the write MOS transistor 1419 as explained above in FIG. 3A, thereby the first access device 1410 is composed of a diode and a MOS transistor to access the storage capacitor 1425. And another access device 1430 is configured such that the read word line 1437 is connected to the first terminal 1431 of the p-n-p-n diode. And the p-n-p-n diode shares the parasitic elements of the write MOS transistor 1439 as explained above in FIG. 3A, thereby the first access device 1430 is composed of a diode and a MOS transistor to access the storage capacitor 1425. The read and write operation are the same as that of single port RAM as explained above, but unselected word line and bit line keep VL level while selected word line and bit line are asserted. During read, the current flow is set up from the selected word line to the selected bit line, when the stored data is “1” otherwise the current path is not set up.
Additionally, in FIG. 15, an example embodiment to implement CAM (content addressable memory) using the capacitor storage memory as the present invention is illustrated. There are two memory cells and two compare circuits in a CAM cell. Read-write operation for the memory cells is the same as single port memory as explained above. And CAM operation is added in order to compare the stored data and the incoming data referred as comparand. In detail, a CAM is a storage device that is particularly suitable for matching functions because it can be instructed to compare a specific pattern of comparand data with data stored in an associative CAM array. A CAM can include a number of data storage locations, each of which can be accessed by a corresponding address. Functionality of a CAM depends at least in part on whether the CAM includes binary or ternary CAM cells. Ternary CAM cells are mask-per-bit CAM cells that effectively store three states of information, namely a logic “1” state, a logic “0” state, and a don't care state for compare operations. Ternary CAM cells typically include a second memory cell that stores local mask data for the each ternary CAM cell. The local mask data masks the comparison result of the comparand data with the data stored in the first memory cell such that, when the mask bit has a first predetermined value (a logic “0”, for example) its compare operation will be masked so that the comparison result does not affect the match line. The ternary CAM cell offers more flexibility to the user to determine on an entry-per-entry basis which bits in a word will be masked during a compare operation. There are prior arts using the conventional DRAM, “DRAM based refresh-free ternary CAM”, U.S. Pat. No. 6,331,961. But the process technology of the conventional DRAM reaches to the scaling limit within the current CMOS process. And another prior art is shown using negative differential resistance device, “Semiconductor capacitively-coupled negative differential resistance device and its applications in high-density high-speed memories and in power switches”, U.S. Pat. No. 6,229,161. As explained above, p-n-p-n diode itself (thyristor, or negative differential resistance device) can not be used as a storage element while the present invention uses a p-n-p-n diode as a read access device, not storage device. And conventional SRAM-based CAM is used only for low-density applications. Thus the capacitor storage is used for the CAM application in the present invention, which realizes high-density and high-speed CAM.
Detailed schematic is illustrated as shown in FIG. 15. The memory cell 1500 and 1510 store data in the storage node 1502 and 1512 which are connected to the capacitor storage 1505 and 1515, respectively. The plate line 1506 is connected to the plate of the capacitor 1505 and 1515. The emitter 1501 and 1511 are connected to the word line 1507, thereby the diode access devices serves as the read access device, where the diode read device is composed of the emitter and the parasitic element of the MOS write device M5 and M6 including the body 1503 and 1513, as explained above in FIG. 3A. Compare circuit including PMOS M1 and M2, M3 and M4 share a match line 1521 (ML).
Referring now to FIG. 16 in view of FIG. 15, a truth table is shown summarizing the behavior of CAM cell in relation to signal states maintained by various elements within CAM cell in accordance with the present invention, wherein the compare circuits are configured by the PMOS M1 to M4. Thus, the signal polarity of the internal nodes are inverted, such that VH level is provided by the logic “0”, and VL level is provided by the logic “1” in order to turn on the match line through the PMOS. All the internal polarities are revered from the NMOS type compare circuit (not shown) which is familiar to analyze it. First column T21 lists binary states of “0” (at VH) and “1” (at VL) that can be stored in storage node of the memory cell 1500; second column T22 lists binary states of “0” (at VH) and “1” (at VL) that can be stored in storage node of the memory cell 1510. Third column T23 lists the ternary states that can be maintained in one of the complement compare data lines, namely cdata which is the signal 1532. Fourth column T24 lists the ternary states that can be maintained in the other complement compare data line, namely ncdata which is the signal 1531. Fifth column T25 lists “low (negated logic)” and “high” as the two available voltage levels for match line ML. Finally, sixth column T26 lists “match” and “mismatch” as the two possible results for comparing states of ncdata line 1531 and cdata line 1532 with the states of CAM cell.
Continuing with FIG. 16 in view of FIG. 15, row T31 indicates masked case where sdata 1502 and nsdata 1512 are “0” (at VH) which makes match line to stay the pre-charge level (“low”), regardless of the compare data, such that the stored data “0” has potential VH level which turns off PMOS compare circuit M2 and M4, rows T32-T33 both indicate that “0” state of CAM cell is represented by “0” (at VH) of capacitor memory cell 1500, and “1” (at VL) of capacitor memory cell 1510. In row T32, because state “1” of cdata line 1532 does not match state “0” of CAM cell, match line ML is driven “high (negated logic)” to indicate a mismatch of the data key and the stored value (state “0” at VH) of CAM cell. In row T33, because state “0” (at VH) of cdata line 1532 matches state “0” (at VH) of CAM cell, match line ML is driven “low” to indicate a partial match of the comparand and the stored value (state “0”, at VH) of CAM.
Continuing still with FIG. 16 in view of FIG. 15, rows T34-T35 both indicate that “1” state of CAM cell is represented by “1” (at VL) of capacitor memory cell 1500 and “0” (at VH) of capacitor cell 1510. In row T34, because state “1” (at VL) of cdata line 1532 matches state “1” (at VL) of CAM cell, match line ML is driven “low (negated logic)” to indicate a partial match of the comparand and the stored value (state “1”, at VL) of CAM cell. In row T35, because state “0” (at VH) of cdata line 1532 does not match state “1” (at VL) of CAM cell, match line ML is driven “high (negated logic)” to indicate a mismatch of the comparand and the stored value (state “1”, at VL) of CAM cell.
Methods of Fabrication
The memory cell includes a small capacitor, a coarse MOS transistor, and a diode which is composed of the parasitic bipolar transistor of the MOS transistor by adding one terminal to the source. And the capacitor does not use new materials. Thus, the steps in the process flow should be compatible with the current CMOS manufacturing environment as published as the prior arts, such as U.S. Pat. No. 6,104,045, U.S. Pat. No. 6,229,161, U.S. Pat. No. 6,940,761, and U.S. Pat. No. 6,943,083 in order to form the memory cell with four-terminal diode. In this respect, there is no need of describing too much detailed process flow to form the memory cell, such as width, length, thickness, temperature, forming method or any other material related data. Instead of describing those details, the present invention focuses on illustrating the new memory cell structures which are practical and mass producible.
The memory cells can be formed from thin-film layer within the current CMOS process environment, as long as the reverse bias leakage and the oxide leakage are controllable. Furthermore, the memory cell can be formed in between the routing layers. In this manner, fabricating the memory cell is independent of fabricating the peripheral circuits. In order to form the memory cell in between the metal routing layers, LTPS (Low Temperature Polysilicon) can be used, as published, U.S. Pat. No. 5,395,804, U.S. Pat. No. 6,852,577 and U.S. Pat. No. 6,951,793. The LTPS has been developed for the low temperature process (around 500 centigrade) on the glass in order to apply the display panel, according to the prior arts. Now the LTPS can be used as a coarse MOS transistor during write and also as a p-n-p-n diode during read. Generally, polysilicon diode can flow less current than single crystal silicon diode, but the polysilicon diode can flow more current than MOS transistor, because the diode can flow the current through the whole junction while the MOS transistor can flow the current through the shallow inversion layer by the gate control. During write, the polysilicon MOS transistor drives the storage node, such that the storage capacitance of the invented memory cell is relatively smaller than the conventional DRAM, thus the coarse MOS transistor can drive the small capacitor to store the charges. In consequence, multiple memory cells can be stacked over the substrate with no very thin oxide layer. The insulator for the storage capacitor may be thicker than that of MOS transistor. Alternatively, ferroelectric capacitor can be used to provide more capacitance with slightly thick layer. During polysilicon process, the MOS transistor in the control circuit and routing metal are less degraded.
In FIG. 17A, a basic structure of the invented memory cell is illustrated, wherein the MOS write device is composed of a gate 1708 which serves as a write word line, the body 1703, the n-type drain/source 1704 and another n-type drain/source 1702. And silicide layer is added to the gate and the contact region (1701A) in order to reduce sheet and contact resistance. The MOS transistor is isolated from the substrate 1799 by the insulation layer 1798. And a p-n-p-n diode shares the p-type body, the drain and the source. Thereby a four-terminal diode is composed of adding one more p-type terminal 1701, so that the first terminal 1701 is attached to the second terminal 1702 which also serves a drain/source of the MOS transistor, the third terminal 1703 is attached to the second terminal, the fourth terminal 1704 is attached to the third terminal 1703, where the third terminal serves as a floating body, and the fourth terminal serves as the drain/source of the MOS transistor as well. The first terminal is connected to the read word line 1707 through an ohmic contact region 1701A to reduce contact resistance with silicide material. The storage capacitor 1705 is connected to the storage node 1702, and the isolation layer is formed between the plate line 1706 and the storage electrode which is connected to the storage node 1702. Furthermore, buffer layers can be added to the isolation layer of the capacitor in between the electrodes. Thus, the memory cell can be formed on the buried oxide layer of the substrate 1799, which structure is referred as the SOI wafer. However, the SOI wafer is relatively expensive to form the buried oxide with high voltage implantation, which causes crystal defect and reduces MOS transistor yield around 5 percent. Moreover, the SOI process may reach the scaling limit in the near future, such as 22 nm. In order to solve those, the thin-film MOS transistor and diode can be used as the access device of the memory cell, alternatively.
In FIG. 17B, the cross sectional view of the memory cell of the structure in FIG. 17A is shown from the bit line direction, wherein the bit line 1704 is shown on the capacitor 1705, and adjacent bit line 1714 is shown, but the adjacent bit line 1714 is formed from the upper metal layer in order to reduce coupling. In this manner, two bit line layers are used for the bit line wiring, which can suppress the bit line coupling and also the bit line capacitance itself with relatively longer distance to the adjacent metal lines. In contrast, the twisted bit line scheme (not shown) is used to reduce the coupling from the adjacent bit lines in the conventional DRAM. The bit line coupling is more critical for reading the invented memory cell because the read data latch for latching the memory cell data is sensitive to the bit line voltage, with no reference bit line. Thus, the coupling and capacitance of the bit line can be reduced by using two metal layers for this memory cell structure.
In FIG. 18A, the memory cell is formed in between the routing layer as an alternative embodiment, wherein the memory cell is composed of the capacitor 1805, the MOS transistor including the gate 1808, the drain/source 1802/1804, and the body 1803, and the first terminal 1801 of the p-n-p-n diode. The plate line 1806 is connected to the capacitor 1805, the read word line 1801 is connected to the first terminal of the diode, and the write word line 1808 is connected to the gate of the MOS transistor. The memory cell is formed on the adjacent global bit line 1814, and the global bit line 1814 is formed on the substrate 1899. As explained above, the MOS transistor is formed from the LTPS with low temperature, thus the metal bit line is not degraded while forming the memory cell. In doing so, the memory cell is formed between the adjacent global line 1814 and the bit line 1804 of the memory cell. With the LTPS process, the bit line architecture is more flexible to reduce the coupling from the adjacent bit lines. In FIG. 18B, the adjacent memory cell of the memory as shown in FIG. 18A is illustrated, the memory cell is composed of the capacitor 1825, the MOS transistor including the gate 1828, the drain/source 1822/1824, and the body 1823, and the first terminal 1821 of the p-n-p-n diode. The plate line 1826 is connected to the capacitor 1825, the read word line 1821 is connected to the first terminal of the diode, and the write word line 1828 is connected to the gate of the MOS transistor. The memory cell is formed on its bit line 1824, and the global bit line 1834 is formed on the memory cell. For ease of understanding, the top views are illustrated in FIG. 18C for the memory cell of the FIG. 18A, and FIG. 18D for the adjacent memory cell of the FIG. 18B, wherein the write word line 1808 and 1828 may be the same write word line as the memory cells are located next to each other. As shown in FIG. 18C, the (local) bit line 1804 is passing over the memory cell, but the adjacent (local) bit line 1824 is passing under the adjacent memory cell. On the contrary, the global bit line 1814 is passing under the memory cell, and the adjacent global bit line 1834 is passing over the adjacent memory cell, as shown in FIG. 18D.
More detailed bit line architecture is illustrated in FIG. 19A, wherein the selected local bit line 1904 is connected to the selected global bit line 1924 through the transmission gate, which transmission gate is controlled by the signal 1926. And the transmission gate includes relatively wide channel to drive the bit line directly. More detailed schematic of the transmission gate is shown in 1927. In actual design, the control signal of the transmission gate needs two signals, such as true and bar signal, but the drawing includes only a control signal 1926 for simplifying the schematic. The charges are flowing from the local bit line 1904 to the global bit line 1924. Thus, the coupling is occurred by a small fringing capacitor 1922 between the local bit line 1904 and the adjacent global bit line 1923. The other local bit lines are not activated. Thereby the total coupling noise is negligible because the unselected local bit lines serve as shielding element (as shown in broken lines in the FIG. 19A), when read. And fringing capacitor 1921 does not affect the read operation, which becomes the same lines after the transmission gate is turned on. Furthermore, the adjacent global bit lines 1923 and 1925 are located next to the local bit lines. In contrast, the conventional bit line scheme is illustrated as shown in FIG. 19B, Wherein the selected local bit line 1951 is connected to the global bit line 1952, thus there are so many fringing capacitors between the two adjacent global bit lines 1952, 1953 and 1954. To compensate the bit line coupling, twisted bit line scheme is used in the conventional memory (not shown), so that more switch area is added.
In FIG. 20, the memory cells are stacked over the wafer, wherein the lower memory cell 2010 is formed on the global bit line 2000, and the upper memory cell 2030 is formed on the lower memory cell 2010. The memory cell 2030 includes a vertical first terminal to reduce cell area, such that the memory cell is composed of the capacitor 2035, the MOS transistor including the gate 2038, the drain/source 2032/2034, and the body 2033. Furthermore, the drain/source 2032/2034 and the body 2033 are shared with a p-n-p-n diode as a read device, so that the drain/source 2032 serves as the second terminal 2032, the body 2033 serves as the third terminal 2033, and the drain/source 2034 serves as the fourth terminal 2034. The plate line 2036 is connected to the capacitor 2035, the read word line is connected to the first terminal 2031 of the diode, and the write word line 2038 serves as the gate of the MOS transistor. The lower memory cell 2010 has the same structure as the upper memory cell 2030. And the local bit line 2020 is shared with the upper cell and lower memory cell. In addition, there is a passing line 2040, which can be used as global read or write word line for the memory cells. In this manner, the stacked memory cells can be formed over the wafer. Moreover, the memory cells are formed on the control circuits. And the MOS transistors are separated by the shallow trench isolation (STI). Thus, fabricating the memory cells on the bulk wafer is compatible with the current CMOS process with low-temperature polysilicon layers.
In FIG. 21, the memory cells are stacked over the control circuits, wherein the upper memory cell 2110 is formed on the lower memory cell 2100, and the lower memory cell 2100 is formed on the control MOS transistors, which transistors can be part of decoders or read data latches. The PMOS transistor is composed of the gate 2134, the drain/ source region 2131 and 2133, and the body 2132. The NMOS transistor is composed of the gate 2124, the drain/ source region 2121 and 2123, and the body 2122. Additionally, the metal layers 2125 and 2126 are connected to the drain/ source region 2121 and 2123. And routing metal layer 2127 is formed on the MOS transistor. Thus, the routing layers 2127, 2125 and gate poly layer 2124 can be used as the connections of the peripheral circuits of the memory array. And one more layer is available to use as a short length routing layer, which is the polysilicon layer 2121 or 2131 with high doping. In doing so, many routing layers are available to configure the peripheral circuits of the memory array.
In FIG. 22, the memory cells are stacked under the control circuits as an alternative embodiment, wherein the upper memory cell 2210 is formed on the lower memory cell 2200, and the upper memory cell 2210 is formed under the control MOS transistor 2250 as an example, which transistor may be part of decoders or read data latches. Alternatively, the MOS transistor 2250 is formed on the flatter surface when the insulation layer 2251 is thicker than others. And the plug 2252 is used as a buffer region to the contacts. Hence, the control circuits are stacked over the memory cells, which enable to connect the output node to the external connector (not shown), such as package lead frame and the ball grid array, more efficiently.
Various diodes can be used as the read access device, such as silicon, germanium, compound-semiconductor, and metal-semiconductor, as long as the reverse bias leakage is controllable.
In addition, various capacitors can be used as the storage element, such as normal capacitor and ferroelectric capacitor. Furthermore, a series capacitor can be a storage element.
While the descriptions here have been given for configuring the memory circuit and structure, alternative embodiments would work equally well with reverse connection such that first terminal is n-type and serves as the read word line, the second terminal is p-type and serves as the storage node, third terminal is n-type and floating, and fourth terminal is p-type and serves as the bit line. And the write MOS transistor is PMOS transistor.
The foregoing descriptions of specific embodiments of the invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to explain the principles and the application of the invention, thereby enabling others skilled in the art to utilize the invention in its various embodiments and modifications according to the particular purpose contemplated. The scope of the invention is intended to be defined by the claims appended hereto and their equivalents.

Claims

1. A memory device, comprising:

a memory cell, wherein a MOS transistor serves as a write device, a diode serves as a read device, and a capacitor stores data; and the MOS transistor includes a gate as a write word line, a source as a storage node, a drain as a bit line, and a body; and the diode includes four terminals, the first terminal serves as a read word line, the second terminal is connected to the storage node, the third terminal is floating, and the fourth terminal is connected to the bit line; and the capacitor is composed of an insulator between two electrodes, one electrode is connected to the storage node, and another electrode is connected to a plate line; and

a memory array, wherein main memory cells configure main columns, dummy memory cells configure dummy columns; and the first dummy column generates the first delay signal for enabling the main columns, after the read word line is enabled; and the far end dummy column generates the second delay signal to disable the read word line; and

a peripheral circuit including a row decoder which controls the read word line, the write word line and the plate line; and a read data latch wherein a latch node is connected to a current mirror, a feedback inverter and a pre-charge device; and the latch node is pre-charged by the pre-charge device during standby; when reading data “1”, the current mirror repeats the bit line current, thus the current mirror changes the latch node, after then, the bit line current is cut off by the output of the latch node, otherwise the latch node keeps the pre-charged voltage when reading data “0”; and an output driver receives the output of the latch node and transfers the received data to the output pad.

2. The memory device of claim 1, wherein the four-terminal diode is composed of the parasitic bipolar transistor of the MOS transistor, the first terminal is added to the source of the MOS transistor which makes a p-n junction, the second terminal shares the source of the MOS transistor, the third terminal shares the floating body of the MOS transistor, and the fourth terminal shares the drain of the MOS transistor.

3. The memory device of claim 1, wherein the diode includes four terminals, the first terminal is p-type, the second terminal is n-type, the third terminal is p-type, and the fourth terminal is n-type.

4. The memory device of claim 1, wherein the diode includes four terminals, the first terminal is n-type, the second terminal is p-type, the third terminal is n-type, and the fourth terminal is p-type.

5. The memory device of claim 1, wherein the diode is formed from silicon including polysilicon, amorphous silicon and stretchable silicon, germanium, compound semiconductor, and metal to form a Schottky diode.

6. The memory device of claim 1, wherein the capacitor includes ordinary dielectric capacitor including high dielectric constant, and ferroelectric dielectric capacitor.

7. The memory device of claim 1, wherein the capacitor includes a floating plate which configures a series capacitor.

8. The memory device of claim 1, wherein the (local) bit line is connected to a (selected) global bit line through a transmission gate and the local bit line is located between the selected global bit line and the adjacent global bit line.

9. The memory device of claim 1, wherein the current mirror of the read data latch includes lower threshold MOS transistor than that of control circuit in the chip.

10. The memory device of claim 1, wherein the feedback inverter of the read data latch includes a current source which limits the current flow through the feedback inverter to have lower current than that of the current mirror when read data “1”, where the first dummy column sets up a current path which generates a bias voltage for regulating the current source of the feedback inverter.

11. The memory device of claim 1, wherein the read word line driver includes the first bipolar transistor and the second bipolar transistor; and the first bipolar transistor provides the base current of the second bipolar transistor; and the second bipolar transistor drives the read word line.

12. The memory device of claim 1, wherein the output driver includes the first bipolar transistor and the second bipolar transistor; and the first bipolar transistor provides the base current of the second bipolar transistor; and the second bipolar transistor drives the pull-up portion of the output node; and the third bipolar transistor and the fourth bipolar transistor; and the third bipolar transistor provides the base current of the fourth bipolar transistor; and the fourth bipolar transistor drives the pull-down portion of the output node.

13. The memory device of claim 1, wherein at least one terminal of the diode is vertically formed on the other terminal of the diode.

14. The memory device of claim 1, wherein the memory cells are formed in between the routing layers.

15. The memory device of claim 1, wherein the memory cells are formed on the peripheral circuit.

16. The memory device of claim 1, wherein multiple memory cells are stacked.

17. The memory device of claim 1, wherein the peripheral circuit is formed on the silicon substrate, such as the conventional bulk wafer, the compound semiconductor wafer or the SOI (Silicon-on-Insulator) wafer.

18. The memory device of claim 1, wherein the peripheral circuit is formed on the substrate, such as, a quartz wafer, a ceramic wafer, a glass, or a metal.

19. The memory device of claim 1, wherein the capacitor is shared by multiple access devices including the read diode and the write MOS transistor, in order to configure multi port memory.

20. The memory device of claim 1, wherein the peripheral circuit includes at least one compare circuit to configure a content addressable memory as an additional component; and the compare circuit includes the first transistor set and the second transistor set, wherein the first signal set couples to control a conduction state of the first transistor set and the second signal set couples to control a conduction state of the second transistor set, wherein the first signal set includes stored data in the memory cell and the second signal set includes comparand data from an input device; and at least one compare circuit coupled among the memory cells and at least one match line to receive first and second signal sets and affect a logical state of the match line in response to a predetermined logical relationship between the first and second signal sets.