US20070169697A1 - Method of manufacturing capacitor of semiconductor device by simplifying process of forming dielectric layer and apparatus thereof - Google Patents

Method of manufacturing capacitor of semiconductor device by simplifying process of forming dielectric layer and apparatus thereof Download PDF

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US20070169697A1
US20070169697A1 US11/710,099 US71009907A US2007169697A1 US 20070169697 A1 US20070169697 A1 US 20070169697A1 US 71009907 A US71009907 A US 71009907A US 2007169697 A1 US2007169697 A1 US 2007169697A1
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dielectric layer
chamber
capacitor
deposited
source gas
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Yong-kuk Jeong
Myong-Geun Yoon
Seok-jun Won
Dae-jin Kwon
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3141—Deposition using atomic layer deposition techniques [ALD]
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31637—Deposition of Tantalum oxides, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

Definitions

  • the present invention relates to methods of manufacturing semiconductor devices and apparatus therefor, and more particularly, to a method of manufacturing a capacitor of a semiconductor device and an apparatus for forming a dielectric layer of the capacitor.
  • dielectric layers are deposited using a source gas along with a reactant gas such as O 2 , H 2 O, H 2 O 2 , and N 2 O.
  • a reactant gas such as O 2 , H 2 O, H 2 O 2 , and N 2 O.
  • FIG. 1 to improve electrical properties, multiple dielectric layers are deposited (D 1 , D 2 , . . . , and Dn) between steps of forming a first electrode ( 1 ) and a second electrode ( 2 ), and multiple curing processes are performed (C 1 , C 2 , . . . , and Cn) between every two steps of forming dielectric layers.
  • a deposition process is performed twice and a curing process is performed twice. That is, as shown in FIG. 2 , two dielectric layers DL 1 and DL 2 are formed between two electrodes 15 and 30 . Assuming, for convenience, that the thickness of the first dielectric layer DL 1 is St 1 , the thickness of the second dielectric layer DL 2 is St 2 , and the sum of the thicknesses of the two dielectric layers DL 1 and DL 2 is t 1 (St 1 +St 2 ).
  • a dielectric layer for an analog capacitor, a radio frequency (RF) capacitor, or a high-voltage capacitor should be formed to a greater thickness than t 1 of FIG. 2 . Accordingly, deposition processes and curing processes are performed three times or more such that n dielectric layers (DL 1 , DL 2 , . . . , and DL n ) are formed between two electrodes 15 and 30 , as shown in FIG. 3 .
  • the sum of thicknesses of the n dielectric layers (DL 1 , DL 2 , . . . , and DL n ) is t 2 (t 2 >t 1 ).
  • FIG. 4 graphically explains the reasons for forming dielectric layers using multiple deposition and curing processes.
  • FIG. 4 is a graph showing the results of forming a Ta 2 O 5 layer by a twice-performed deposition and a twice-performed curing process for applying to the conventional stand-alone memory and embedded memory.
  • Squares ⁇ shown on the graph represents a leakage current density of a capacitor, which uses TiN deposited using physical vapor deposition (PVD) as electrodes.
  • the capacitor is manufactured by depositing a Ta 2 O 5 layer one time to a thickness of 150 ⁇ through chemical vapor deposition (CVD) using a source gas and an O 2 reactant gas.
  • Circle ⁇ represents the leakage current density of a capacitor manufactured by performing a deposition process twice and performing a curing process twice as shown in FIGS. 1 and 2 .
  • TiN deposited using PVD is also employed for electrodes, and a first Ta 2 O 5 layer is deposited to a thickness of 90 ⁇ by CVD using a source gas and an O 2 reactant gas and is then cured using O 3 .
  • a second Ta 2 O 5 layer is deposited thereon to a thickness of 60 ⁇ by the same method and is cured using O 3 such that the total thickness is 150 ⁇ .
  • a curing process is carried out following every deposition process of dielectric layers, the manufacturing process becomes complicated, thus reducing yield. Also, because several deposition chambers and several curing chambers are required, the structure of the equipment becomes complicated. Also, in the stand-alone memory and the embedded memory, a storage node contact plug may become oxidized due to a reactant gas such as O 2 , H 2 O, H 2 O 2 , and N 2 O injected together with the source gas during deposition. Further, in the conventional method, it is difficult to obtain good step coverage. Thus, dielectric layers having poor step coverage cannot be applied to highly integrated semiconductor devices having a narrow interval between storage electrodes (lower electrodes of a capacitor).
  • the present invention provides a method of manufacturing a capacitor by simplifying a process of forming a dielectric layer.
  • the present invention also provides an apparatus which can be used for the method of manufacturing a capacitor according to the present invention.
  • a method of manufacturing a capacitor comprising performing reactant-free deposition processes and performing a one-time curing process.
  • the method comprises forming a first electrode on a semiconductor substrate and then depositing a first dielectric layer on the first electrode.
  • the first dielectric layer is cured in an atmosphere containing oxygen and a second dielectric layer is then deposited on the cured first dielectric layer using a source gas without a reactant gas.
  • a second electrode is formed on the second dielectric layer without curing the second dielectric layer.
  • the first dielectric layer is deposited using only a source gas without a reactant gas, the resulting electrical properties of the device are improved.
  • the first and second dielectric layers may be deposited using CVD or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the source gas itself should include oxygen atoms.
  • the source gas may be Ta(OC 2 H 5 ) 5 (pentaethoxide tantalum (PET)), tetra ethoxide tantalum-dimethyl amine ethoxide (TET-DMAE), Ta(OsBu) 5 , Ta(OC 2 H 5 ) 4 (acacC 2 H 5 ), TaCl 2 (OC 2 H 5 ) 2 C 5 H 7 O 2 , or Ta(OCH 3 ) 5 .
  • PET pentethoxide tantalum
  • TET-DMAE tetra ethoxide tantalum-dimethyl amine ethoxide
  • Ta(OsBu) 5 tetra ethoxide tantalum-dimethyl amine ethoxide
  • Ta(OC 2 H 5 ) 4 acacC 2 H 5
  • TaCl 2 (OC 2 H 5 ) 2 C 5 H 7 O 2 or Ta(OCH 3 ) 5 .
  • the method comprises forming a first electrode on a semiconductor substrate and then depositing a first Ta 2 O 5 layer on the first electrode.
  • the first Ta 2 O 5 layer is cured in an ozone atmosphere, and a second Ta 2 O 5 layer is then deposited on the cured first Ta 2 O 5 layer using only a PET source gas without a reactant gas.
  • a second electrode is formed on the second Ta 2 O 5 layer without an additional curing process.
  • the first Ta 2 O 5 layer is also deposited using only a PET source gas without a reactant gas, and the first and second Ta 2 O 5 layers are deposited using CVD.
  • an apparatus for manufacturing a dielectric layer comprising two deposition chambers and a single curing chamber, which are positioned around a transfer chamber.
  • the apparatus comprises a loadlock chamber where a cassette, on which a plurality of semiconductor substrates are loaded, is positioned, a transfer chamber including a robot arm connected to the loadlock chamber for loading/unloading a semiconductor substrate, a first deposition chamber connected to the transfer chamber for depositing a first dielectric layer on the substrate, a curing chamber connected to the first deposition chamber, and a second deposition chamber connected to the transfer chamber for depositing a second dielectric layer on the substrate.
  • a first dielectric layer deposited in the first deposition chamber may be cured in the curing chamber and then a second dielectric layer may be deposited in the second deposition chamber.
  • steps from depositing a first dielectric layer to depositing a second dielectric layer can be carried out in-situ in a single apparatus for forming dielectric layers.
  • FIG. 1 is a flowchart illustrating a conventional method of manufacturing a capacitor of a semiconductor device
  • FIG. 2 is a cross-sectional view of a conventional capacitor according to the method of FIG. 1 for applying, for example, to a stand-alone memory or an embedded memory;
  • FIG. 3 is a cross-sectional view of a conventional capacitor according to the method of FIG. 1 for applying, for example, to an analog capacitor, a RF capacitor, or a high-voltage capacitor;
  • FIG. 4 is a graph showing the results of forming a Ta 2 O 5 layer by performing dual deposition and curing processes, for applying to the conventional stand-alone memory or embedded memory;
  • FIG. 5 is a flowchart illustrating a method of manufacturing a capacitor of a semiconductor device according to embodiments of the present invention
  • FIGS. 6 and 7 are cross-sectional views of a capacitor according to the method of FIG. 5 , for applying to a stand-alone memory or an embedded memory in accordance with a first embodiment of the present invention
  • FIG. 8 illustrates the present invention applied to the formation of a DRAM capacitor in accordance with a second embodiment of the present invention
  • FIG. 9 is a cross-sectional view of a capacitor according to the method of FIG. 5 , for applying to an analog capacitor, an RF capacitor, or a high-voltage capacitor, in accordance with a third embodiment of the present invention.
  • FIGS. 10, 11 , and 12 are graphs showing the results of depositing a dielectric layer using only a source gas, as in the method of FIG. 5 ;
  • FIG. 13 is a schematic top plan view of an apparatus for forming a dielectric layer according to the embodiments of the present invention.
  • FIGS. 1 and 2 a conventional dielectric layer of a capacitor, used in a stand-alone memory or an embedded memory, is formed by performing a curing process following each deposition process.
  • a dielectric layer can be simply formed by performing a deposition process twice and performing a single, one-time curing process.
  • FIG. 5 is a flowchart illustrating the method according to the present invention
  • FIGS. 6 and 7 are cross-sectional views illustrating respective steps thereof.
  • a first electrode 110 is formed on a semiconductor substrate (not shown) in Step S 1 .
  • a first dielectric layer 120 is deposited on the first electrode 110 in Step S 20 .
  • the first dielectric layer 120 is cured ( 130 ) in an atmosphere containing oxygen such as O 3 , O 2 , O 2 plasma, or N 2 O plasma.
  • a second dielectric layer 140 is deposited using only a source gas, without a reactant gas, in Step S 40 .
  • a second electrode 150 is directly formed on the second dielectric layer 140 without any additional curing process.
  • the first and second electrodes 110 and 150 can be formed of one of TiN, TaN, W, WN, Al, Cu, Ru, RuO 2 , Pt, Ir, IrO 2 , a doped polysilicon, and a combination thereof.
  • the first and second electrodes 110 and 150 can be formed using CVD, PVD, or ALD at a temperature of 25 to 1000° C.
  • a pre-treatment layer such as a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, is preferably further formed so as to prevent a reaction with the first and second dielectric layers 120 and 140 and diffusion thereof.
  • the pre-treatment layer may be formed using rapid thermal oxidation (RTO), rapid thermal nitridation (RTN), or CVD.
  • RTO rapid thermal oxidation
  • RTN rapid thermal nitridation
  • CVD chemical vapor deposition
  • the first electrode 110 may be formed as not only a stack, as shown in the drawings, but also a three-dimensional fin, trench, or cylinder.
  • the first dielectric layer 120 may be formed of one of Ta 2 O 5 , HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 and a combination thereof.
  • the first dielectric layer 120 is formed by CVD or ALD, using only a source gas without a reactant gas such as O 2 , H 2 O, H 2 O 2 , and N 2 O. Since the reactant gas is not used, the source gas should include oxygen atoms so as to deposit the foregoing dielectric oxide layer.
  • the first dielectric layer 120 is deposited, for example, to a thickness dt 1 of 5 to 200 ⁇ at a temperature of 100 to 600° C.
  • a source gas which enables reactant-free deposition of the dielectric layer.
  • a source gas may be Ta(OC 2 H 5 ) 5 (pentaethoxide tantalum (PET)), tetra ethoxide tantalum-dimethyl amine ethoxide (TET-DMAE), Ta(OsBu) 5 , Ta(OC 2 H 5 ) 4 (acacC 2 H 5 ), TaCl 2 (OC 2 H 5 ) 2 C 5 H 7 O 2 , or Ta(OCH 3 ) 5 .
  • the source gas may be, for example, Hf(OtBu) 4 or Hf(MMP) 4
  • an Al 2 O 3 layer may be deposited using a source gas such as Al(MMP) 3 , Al(OiPr) 3 , Al(acac) 3 , or Al(O 2 C(H)EtnBu) 3 .
  • the source gas may be Zr(OtBu) 4 , Zr(MMP) 4 , Zr(METHD) 4 , Zr(THD) 4 , or Zr(MTHD) 4 to deposit a ZrO 2 layer, and Ti(OC 2 H 5 ) 4 , Ti(MPD)(THD) 2 , Ti(MPD)(METHD) 2 , Ti(THD) 2 (OiPr) 2 , Ti(OiPr) 4 , Ti(MMP) 4 , or Ti(NPEB) 4 may be used as a source gas to deposit a TiO 2 layer.
  • acac represents acetyl acetone (CH 3 COCH 2 COCH 3 )
  • MMP represents 1-methoxy-2-methyl-2-propoxide
  • OiPr represents isopropoxy.
  • METHD is indicative of 1-(2-methoxyethoxy)-2,2,6,6-tetramethyl-3,5-heptanedionate
  • THD is indicative of 2,2,6,6-tetramethyl-3,5-heptanedionate
  • MTHD is indicative of 1-methoxy-tetramethyl-3,5-heptanedionate
  • MPD is indicative of 2-methyl-2,4-pentanedioxide
  • NPEB is indicative of 1-n-propoxy-2-ethyl-2-butoxide.
  • depositing a thin oxide layer using CVD comprises injecting a source gas into a deposition chamber together with a reactant gas such as O 2 , H 2 O, H 2 O 2 , and N 2 O, and then heating the semiconductor substrate.
  • a reactant gas such as O 2 , H 2 O, H 2 O 2 , and N 2 O
  • depositing a thin oxide layer using ALD comprises supplying a source gas to a deposition chamber and physically and chemically adsorbing the source gas on a semiconductor substrate. Then, the redundant source gas and the physisorbed source gas are purged using a purge gas such as N 2 .
  • a reactant gas such as O 2 , H 2 O, H 2 O 2 , and N 2 O is supplied to the deposition chamber and reacts with the chemisorbed source gas.
  • the redundant reactant gas is also purged using a purge gas. The foregoing steps are repeatedly performed until the thin oxide layer having a predetermined thickness is obtained.
  • a dielectric oxide layer may be deposited using only a source gas without a reactant gas such as O 2 , H 2 O, H 2 O 2 , and N 2 O.
  • a source gas including oxygen atoms By using the source gas including oxygen atoms, the thin dielectric oxide layer can be obtained without the reactant gas.
  • depositing the dielectric oxide layer using CVD comprises introducing a semiconductor substrate into a deposition chamber, supplying a source gas including oxygen atoms to the deposition chamber, and then heating the semiconductor substrate.
  • the source gas is thermally decomposed on the semiconductor substrate so as to deposit a stable dielectric oxide layer.
  • depositing a dielectric oxide layer using ALD comprises introducing a semiconductor substrate into a deposition chamber and injecting a source gas including oxygen atoms into the deposition chamber so as to induce chemical and physical adsorption.
  • the source gas is supplied using a bubbler technique or a liquid delivery system (LDS) technique.
  • LDS liquid delivery system
  • an N 2 or Ar inert gas is injected into the deposition chamber so as to remove the redundant source gas other than the chemisorbed source gas from the deposition chamber.
  • the adsorbed source gas is thermally decomposed to deposit a stable dielectric oxide layer.
  • the inside of the deposition chamber is purged using a purge gas so as to remove the residual materials resulting from the reaction.
  • a cycle of injecting a source gas, injecting a purge gas, reaction, and injecting a purge gas is repeated until the dielectric oxide layer having a predetermined thickness is formed.
  • the first dielectric layer 120 is cured ( 130 ) in an atmosphere containing oxygen, for example, an ozone or oxygen atmosphere, or using O 2 plasma or N 2 O plasma.
  • the plasma may be an RF plasma of 13.56 MHz or electron cyclotron resonance (ECR).
  • ECR electron cyclotron resonance
  • ECR electron cyclotron resonance
  • the temperature of the curing process 130 may be decided considering the type and the thickness of the deposited first dielectric layer 120 or other process conditions. Generally, the curing process 130 is carried out at a low temperature of approximately 350 to 650° C.
  • the second dielectric layer 140 is also deposited using only a source gas, without a reactant gas, by the same method as the first dielectric layer 120 .
  • the second dielectric layer 140 may be formed, for example, of one of Ta 2 O 5 , HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , and a combination thereof using CVD or ALD.
  • the second dielectric layer is deposited at a temperature of 100 to 600° C., like the first dielectric layer 120 , while the deposited thickness dt 2 ranges from 5 to 3000 ⁇ . Examples of the source gas are the same as those of the first dielectric layer 120 .
  • the thickness dt 2 of the second dielectric layer 140 should be greater than that dt 1 of the first dielectric layer 120 considering the step coverage and facility of the curing process. However, considering the electrical properties of the resulting device, the preferable thickness dt 1 of the first dielectric layer 120 may optionally be greater than that dt 2 of the second dielectric layer 140 .
  • the thicknesses dt 1 and dt 2 should be decided with all considerations for the step coverage, the facility of the curing process, and the electrical properties.
  • the thickness dt 1 may be thinner than that St 1 of FIG. 2 and the thickness dt 2 may be thicker than that St 2 of FIG. 2 , so that the thickness T 1 of the entire dielectric layer, i.e., the sum of the thicknesses dt 1 and dt 2 of the first and second dielectric layers 120 and 140 , can be maintained to be equal to the thickness t 1 of the dielectric layer of FIG. 2 . Because the entire dielectric layer can be formed to a desired thickness by forming the first dielectric layer to be thinner than St 1 of FIG. 2 , even if the dielectric layer is deposited on a first electrode having a relatively complicated structure, the step coverage can be improved and yield can be increased.
  • the dielectric layer is deposited using only a source gas, without a reactant gas such as O 2 , H 2 O, H 2 O 2 , and N 2 O, oxidation of a storage node contact plug caused by the reactant gas can be suppressed.
  • FIG. 8 illustrates the first embodiment of present invention, with reference to FIGS. 5 through 7 , as applied to the formation of a DRAM capacitor.
  • a transistor is formed at an active region of a semiconductor substrate 201 , which is defined by shallow trench isolation 203 .
  • the transistor includes a source region 205 , a drain region 207 , and a gate electrode 211 with an intervening gate oxide layer 209 .
  • a bit line 213 is connected to the drain region 207
  • a storage electrode i.e., a first electrode 221
  • the first electrode 221 has the three-dimensional cylinder shape.
  • the first electrode 221 is formed of one of TiN, TaN, W, WN, Al, Cu, Ru, RuO 2 , Pt, Ir, IrO 2 , a doped polysilicon, and a combination thereof. Also, the first electrode 221 can be formed using CVD, PVD, or ALD at a temperature of 25 to 1000° C. Next, a cleaning process is carried out to stabilize the interface of the first electrode 221 , and then dielectric layers 223 and 224 and a second electrode 225 are formed on the first electrode 221 .
  • the dielectric layers 223 and 224 are deposited using CVD or ALD using only a source gas without a reactant gas.
  • the first dielectric layer 223 is deposited to a relatively thin thickness and is then cured using O 3 .
  • the second dielectric layer 224 is deposited to provide a predetermined combined dielectric layer thickness, without performing an additional curing process.
  • the thickness of the first dielectric layer 223 is 90 ⁇ and a thickness of the second dielectric layer 224 is 60 ⁇ such that the total thickness is 150 ⁇ .
  • the first dielectric layer 223 is cured using 03 at 400° C. with 30 Torr for five minutes.
  • the second electrode 225 is formed by the same method as the first electrode 221 .
  • the preferable composition of the first electrode 221 /dielectric layers 223 and 224 /second electrode 225 is TiN/Ta 2 O 5 /TiN, between which reactivity is so low as to prevent degradation of the capacitor.
  • the second dielectric layer 224 is formed to meet the remaining required thickness.
  • the first electrode 221 having a complicated cylinder structure, as shown in FIG. 8 is able to satisfy the requirement for improved step coverage.
  • the dielectric layers 223 and 224 are deposited using only a source gas such as PET containing oxygen atoms, without a reactant gas such as O 2 , H 2 O, H 2 O 2 , and N 2 O, oxidation of the storage node contact plug 217 can be prevented.
  • an analog capacitor, an RF capacitor, or a high-voltage capacitor requires a thicker dielectric layer than a capacitor used in a stand-alone memory or embedded memory. Therefore, according to the conventional method, the dielectric layer was formed by performing repeated deposition curing processes. However, according to the present invention, even a relatively thick dielectric layer can be formed through a twice-performed deposition process and a one-time curing process. This is described hereinafter with reference to the flowchart of FIG. 5 and the cross-sectional view of FIG. 9 .
  • a first dielectric layer 320 and a second dielectric layer 340 are formed between a first electrode 310 and a second electrode 350 .
  • the first and second dielectric layers 320 and 340 are deposited using only a source gas, without a reactant gas.
  • the first dielectric layer 320 is cured in an atmosphere containing oxygen, whereas the second dielectric layer 340 is not cured.
  • a dielectric layer such as Al 2 O 3 may be applied between the first electrode 310 and first dielectric layer 320 , and the dielectric layer such as Al 2 O 3 may be inserted under the second electrode 350 in order to ensure suitable electrical properties.
  • n (n>3) dielectric layers (DL 1 , DL 2 , . . . , and DL n ) were deposited and n curing processes were performed to obtain the thickness t 2 of the dielectric layer.
  • the entire thickness T 2 i.e., the thickness DT 1 of the first dielectric layer+the thickness DT 2 of the second dielectric layer
  • the thickness t 2 of FIG. 3 can be ensured by properly controlling the respective thicknesses DT 1 and DT 2 of the first and second dielectric layers 320 and 340 , without adding any additional deposition and curing processes.
  • the thick dielectric layer required by the analog capacitor, the RF capacitor, or the high-voltage capacitor can be deposited, thus enabling the process simplification.
  • FIG. 10 is a graph illustrating the results of depositing a dielectric layer using only a source gas without a reactant gas when a Ta 2 O 5 dielectric layer is deposited to a thickness of 150 ⁇ using CVD without any curing process, and a comparison of these results to the result of depositing a dielectric layer using a source gas with a reactant gas.
  • Circles ⁇ shown on the graph represent a leakage current density in the case where the dielectric layer was deposited using a PET source gas and an O 2 reactant gas. Circles ⁇ on the graph represent a leakage current density in the case where the dielectric layer was deposited using only a PET source gas. In both cases, a cylinder-type capacitor, which includes electrodes formed of TiN using metal organic CVD (MOCVD), was formed as shown in FIG. 8 .
  • MOCVD metal organic CVD
  • FIG. 11 shows the resulting electrical properties in the case of the reactant-free deposition of the dielectric layer.
  • squares ⁇ represent measured leakage current density for a device formed according to the conventional method. That is, TiN deposited by MOCVD was used as device electrodes, and to form a Ta 2 O 5 layer, a deposition process was performed twice using an O 2 reactant gas and a PET source gas, and, following each deposition process, a curing process was performed, using O 3 .
  • the first Ta 2 O 5 layer had a thickness of 60 ⁇ and a second Ta 2 O 5 layer had a thickness of 90 ⁇ such that the total thickness is 150 ⁇ .
  • Circles ⁇ represent leakage current density in the case where TiN deposited by MOCVD was used as electrodes and a Ta 2 O 5 layer was deposited to a thickness of 150 ⁇ using only a PET source gas. Here, no curing process is performed.
  • the leakage current caused by a negative applied voltage is substantially equal to that of the conventional method, and the leakage current caused by a positive applied voltage is slightly degraded, thus resulting in excellent electrical properties. Because the leakage current caused by the positive applied voltage affects the initial dielectric layer, as long as the first dielectric layer of the present invention is properly cured, equivalent or better electrical properties can be obtained, as compared with the conventional method.
  • squares ⁇ represent measured leakage current density for a device formed according to the conventional method. That is, TiN deposited by PVD was used as device electrodes, and to form a Ta 2 O 5 layer, a deposition process was performed twice using an O 2 reactant gas and a PET source gas, and, following each deposition process, a curing process was performed using O 3 .
  • the first Ta 2 O 5 layer had a thickness of 60 ⁇ and the second Ta 2 O 5 layer had a thickness of 90 ⁇ such that the total thickness was 150 ⁇ .
  • Circles ⁇ represent leakage current density in the case where a first Ta 2 O 5 layer was deposited to a thickness of 60 ⁇ using only a PET source gas and is then cured using 03, and a second Ta 2 O 5 layer was deposited thereon to a thickness of 90 ⁇ using only a PET source gas without a curing process. Though the second Ta 2 O 5 layer was not cured, the leakage current density was reduced, as compared to the example of FIG. 11 .
  • FIG. 13 is a schematic top plan view of an apparatus for forming the dielectric layer according to the present invention.
  • the apparatus for forming the dielectric layer comprises a loadlock chamber 405 where a cassette 403 , on which semiconductor substrates 401 are loaded, is positioned, a transfer chamber 409 having a unit connected to the loadlock chamber 405 which is capable of loading/unloading a semiconductor substrate 401 , for example, a robot arm 407 , a first deposition chamber 411 connected to the transfer chamber 409 , and a curing chamber 413 connected to the first deposition chamber 411 .
  • the curing chamber 413 may be connected to an ozone generator or a plasma generator for generating oxygen radicals.
  • the apparatus further comprises a second deposition chamber 414 connected to the transfer chamber 409 .
  • the arrows indicate the manner in which the apparatus in forming a dielectric layer.
  • the semiconductor substrate 401 where the first electrode is formed, is introduced into the first deposition chamber 411 by the robot arm 407 in Step S 10 of FIG. 5 .
  • a first dielectric layer is deposited as shown in Step S 20 of FIG. 5 .
  • the first dielectric layer is preferably deposited using only a source gas without a reactant gas.
  • the semiconductor substrate 401 is moved into the curing chamber 413 and is cured in an atmosphere containing oxygen, i.e., using one of O 3 , O 2 , O 2 plasma, N 2 O plasma, and a combination thereof, according to Step S 30 of FIG. 5 .
  • the semiconductor substrate 401 is introduced into the second deposition chamber 414 .
  • a second dielectric layer is deposited to the remaining thickness on the semiconductor substrate 401 using only a source gas without a reactant gas, according to Step S 40 of FIG. 5 .
  • the semiconductor substrate 401 is then unloaded to the loadlock chamber 405 without additional curing.
  • a second electrode is formed on the second dielectric layer as shown in Step S 50 of FIG. 5 . Therefore, according to the present invention, steps from depositing the first dielectric layer to depositing the second dielectric layer can be performed by the use of a single apparatus for forming dielectric layers.
  • the apparatus of the present invention includes only a pair of deposition chambers and a single curing chamber. That is, the structure of the equipment is relatively simple, as compared to the conventional approach. Also, the time required for moving a semiconductor substrate to respective chambers can be shortened, thus reducing the manufacturing costs. Further, because a transfer chamber is shared, the apparatus price is reduced and the space of a clean room can be efficiently used.
  • a first dielectric layer of the present invention is preferably deposited using only a source gas without a reactant gas, it is also possible to deposit the first dielectric layer using both the source gas and the reactant gas.
  • the second dielectric layer should be deposited using only a source gas without a reactant gas.

Abstract

In a method of manufacturing a capacitor of a semiconductor device and an apparatus therefor, dielectric layers are deposited using only a source gas without a reactant gas and a curing process is performed a single time. As a result, process simplification, yield improvement, and equipment simplification are achieved. In a stand-alone memory or an embedded memory, the step coverage is enhanced and oxidation of a storage node contact plug is prevented. Also, in an analog capacitor, an RF capacitor, or a high-voltage capacitor, which uses thicker dielectric layers than the stand-alone capacitor or the embedded capacitor, the manufacturing process is greatly simplified.

Description

    RELATED APPLICATIONS
  • This application is a divisional of U.S. application Ser. No. 10/696,465, filed on Oct. 29, 2003, which relies for priority upon Korean Patent Application No. 2002-75693, filed on Nov. 30, 2002, the contents of which are herein incorporated by reference in their entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to methods of manufacturing semiconductor devices and apparatus therefor, and more particularly, to a method of manufacturing a capacitor of a semiconductor device and an apparatus for forming a dielectric layer of the capacitor.
  • 2. Description of the Related Art
  • According to a conventional method of manufacturing capacitors of semiconductor devices, dielectric layers are deposited using a source gas along with a reactant gas such as O2, H2O, H2O2, and N2O. Also, as shown in FIG. 1, to improve electrical properties, multiple dielectric layers are deposited (D1, D2, . . . , and Dn) between steps of forming a first electrode (1) and a second electrode (2), and multiple curing processes are performed (C1, C2, . . . , and Cn) between every two steps of forming dielectric layers.
  • For example, in the conventional method of forming a dielectric layer of a capacitor used in a stand-alone memory or an embedded memory a deposition process is performed twice and a curing process is performed twice. That is, as shown in FIG. 2, two dielectric layers DL1 and DL2 are formed between two electrodes 15 and 30. Assuming, for convenience, that the thickness of the first dielectric layer DL1 is St1, the thickness of the second dielectric layer DL2 is St2, and the sum of the thicknesses of the two dielectric layers DL1 and DL2 is t1(St1+St2).
  • Meanwhile, a dielectric layer for an analog capacitor, a radio frequency (RF) capacitor, or a high-voltage capacitor should be formed to a greater thickness than t1 of FIG. 2. Accordingly, deposition processes and curing processes are performed three times or more such that n dielectric layers (DL1, DL2, . . . , and DLn) are formed between two electrodes 15 and 30, as shown in FIG. 3. We suppose that the sum of thicknesses of the n dielectric layers (DL1, DL2, . . . , and DLn) is t2 (t2>t1).
  • FIG. 4 graphically explains the reasons for forming dielectric layers using multiple deposition and curing processes. FIG. 4 is a graph showing the results of forming a Ta2O5 layer by a twice-performed deposition and a twice-performed curing process for applying to the conventional stand-alone memory and embedded memory.
  • Squares ▪ shown on the graph represents a leakage current density of a capacitor, which uses TiN deposited using physical vapor deposition (PVD) as electrodes. The capacitor is manufactured by depositing a Ta2O5 layer one time to a thickness of 150 Å through chemical vapor deposition (CVD) using a source gas and an O2 reactant gas. Circle ● represents the leakage current density of a capacitor manufactured by performing a deposition process twice and performing a curing process twice as shown in FIGS. 1 and 2. In this case, TiN deposited using PVD is also employed for electrodes, and a first Ta2O5 layer is deposited to a thickness of 90 Å by CVD using a source gas and an O2 reactant gas and is then cured using O3. Then, a second Ta2O5 layer is deposited thereon to a thickness of 60 Å by the same method and is cured using O3 such that the total thickness is 150 Å.
  • As shown in FIG. 4, when a dielectric layer is formed by performing dual deposition and curing processes (results represented by circles ●), the leakage current density is lowered and electrical properties are markedly improved as compared to the results of the single deposit (results represented by squares ▪).
  • However, if a curing process is carried out following every deposition process of dielectric layers, the manufacturing process becomes complicated, thus reducing yield. Also, because several deposition chambers and several curing chambers are required, the structure of the equipment becomes complicated. Also, in the stand-alone memory and the embedded memory, a storage node contact plug may become oxidized due to a reactant gas such as O2, H2O, H2O2, and N2O injected together with the source gas during deposition. Further, in the conventional method, it is difficult to obtain good step coverage. Thus, dielectric layers having poor step coverage cannot be applied to highly integrated semiconductor devices having a narrow interval between storage electrodes (lower electrodes of a capacitor).
    • SUMMARY OF THE INVENTION
  • The present invention provides a method of manufacturing a capacitor by simplifying a process of forming a dielectric layer.
  • The present invention also provides an apparatus which can be used for the method of manufacturing a capacitor according to the present invention.
  • In accordance with an aspect of the present invention, there is provided a method of manufacturing a capacitor comprising performing reactant-free deposition processes and performing a one-time curing process. Thus, process simplification, yield improvement, and equipment simplification can be achieved.
  • In one embodiment of the present invention, the method comprises forming a first electrode on a semiconductor substrate and then depositing a first dielectric layer on the first electrode. The first dielectric layer is cured in an atmosphere containing oxygen and a second dielectric layer is then deposited on the cured first dielectric layer using a source gas without a reactant gas. Next, a second electrode is formed on the second dielectric layer without curing the second dielectric layer.
  • Here, like the second dielectric layer, if the first dielectric layer is deposited using only a source gas without a reactant gas, the resulting electrical properties of the device are improved. The first and second dielectric layers may be deposited using CVD or atomic layer deposition (ALD). To deposit the foregoing layers using only a source gas without a reactant gas, the source gas itself should include oxygen atoms. For example, when Ta2O5 layers are deposited as the first and second dielectric layers, the source gas may be Ta(OC2H5)5 (pentaethoxide tantalum (PET)), tetra ethoxide tantalum-dimethyl amine ethoxide (TET-DMAE), Ta(OsBu)5, Ta(OC2H5)4(acacC2H5), TaCl2(OC2H5)2C5H7O2, or Ta(OCH3)5.
  • In another embodiment of the present invention, the method comprises forming a first electrode on a semiconductor substrate and then depositing a first Ta2O5 layer on the first electrode. The first Ta2O5 layer is cured in an ozone atmosphere, and a second Ta2O5 layer is then deposited on the cured first Ta2O5 layer using only a PET source gas without a reactant gas. When the second Ta2O5 layer is deposited to a predetermined thickness, a second electrode is formed on the second Ta2O5 layer without an additional curing process.
  • Preferably, the first Ta2O5 layer is also deposited using only a PET source gas without a reactant gas, and the first and second Ta2O5 layers are deposited using CVD.
  • In accordance with another aspect of the present invention, there is provided an apparatus for manufacturing a dielectric layer, comprising two deposition chambers and a single curing chamber, which are positioned around a transfer chamber. The apparatus comprises a loadlock chamber where a cassette, on which a plurality of semiconductor substrates are loaded, is positioned, a transfer chamber including a robot arm connected to the loadlock chamber for loading/unloading a semiconductor substrate, a first deposition chamber connected to the transfer chamber for depositing a first dielectric layer on the substrate, a curing chamber connected to the first deposition chamber, and a second deposition chamber connected to the transfer chamber for depositing a second dielectric layer on the substrate. Using such an apparatus, a first dielectric layer deposited in the first deposition chamber may be cured in the curing chamber and then a second dielectric layer may be deposited in the second deposition chamber. In this manner, the steps from depositing a first dielectric layer to depositing a second dielectric layer can be carried out in-situ in a single apparatus for forming dielectric layers.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other features and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
  • FIG. 1 is a flowchart illustrating a conventional method of manufacturing a capacitor of a semiconductor device;
  • FIG. 2 is a cross-sectional view of a conventional capacitor according to the method of FIG. 1 for applying, for example, to a stand-alone memory or an embedded memory;
  • FIG. 3 is a cross-sectional view of a conventional capacitor according to the method of FIG. 1 for applying, for example, to an analog capacitor, a RF capacitor, or a high-voltage capacitor;
  • FIG. 4 is a graph showing the results of forming a Ta2O5 layer by performing dual deposition and curing processes, for applying to the conventional stand-alone memory or embedded memory;
  • FIG. 5 is a flowchart illustrating a method of manufacturing a capacitor of a semiconductor device according to embodiments of the present invention;
  • FIGS. 6 and 7 are cross-sectional views of a capacitor according to the method of FIG. 5, for applying to a stand-alone memory or an embedded memory in accordance with a first embodiment of the present invention;
  • FIG. 8 illustrates the present invention applied to the formation of a DRAM capacitor in accordance with a second embodiment of the present invention;
  • FIG. 9 is a cross-sectional view of a capacitor according to the method of FIG. 5, for applying to an analog capacitor, an RF capacitor, or a high-voltage capacitor, in accordance with a third embodiment of the present invention;
  • FIGS. 10, 11, and 12 are graphs showing the results of depositing a dielectric layer using only a source gas, as in the method of FIG. 5; and
  • FIG. 13 is a schematic top plan view of an apparatus for forming a dielectric layer according to the embodiments of the present invention.
    • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Hereinafter, embodiments of a method of manufacturing a capacitor by simplifying the process of forming a dielectric layer according to the present invention will be described. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the concept of the invention to those skilled in the art. To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
    • Embodiment 1
  • Referring to FIGS. 1 and 2, a conventional dielectric layer of a capacitor, used in a stand-alone memory or an embedded memory, is formed by performing a curing process following each deposition process. However, according to the present invention, a dielectric layer can be simply formed by performing a deposition process twice and performing a single, one-time curing process. FIG. 5 is a flowchart illustrating the method according to the present invention, and FIGS. 6 and 7 are cross-sectional views illustrating respective steps thereof.
  • The method of manufacturing a capacitor of a semiconductor device according to the present invention will be described hereinafter with reference to FIGS. 5 through 7. Referring to FIGS. 5 and 6, a first electrode 110 is formed on a semiconductor substrate (not shown) in Step S1. A first dielectric layer 120 is deposited on the first electrode 110 in Step S20. Here, only a source gas is used, without a reactant gas. In Step S30, the first dielectric layer 120 is cured (130) in an atmosphere containing oxygen such as O3, O2, O2 plasma, or N2O plasma. Next, referring to FIGS. 5 and 7, a second dielectric layer 140 is deposited using only a source gas, without a reactant gas, in Step S40. As shown in Step S50, a second electrode 150 is directly formed on the second dielectric layer 140 without any additional curing process.
  • Here, the first and second electrodes 110 and 150 can be formed of one of TiN, TaN, W, WN, Al, Cu, Ru, RuO2, Pt, Ir, IrO2, a doped polysilicon, and a combination thereof. Also, the first and second electrodes 110 and 150 can be formed using CVD, PVD, or ALD at a temperature of 25 to 1000° C. However, in the case where the first and second electrodes 110 and 150 are deposited using a doped polysilicon, a pre-treatment layer, such as a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, is preferably further formed so as to prevent a reaction with the first and second dielectric layers 120 and 140 and diffusion thereof. The pre-treatment layer may be formed using rapid thermal oxidation (RTO), rapid thermal nitridation (RTN), or CVD. In particular, the first electrode 110 may be formed as not only a stack, as shown in the drawings, but also a three-dimensional fin, trench, or cylinder.
  • The first dielectric layer 120 may be formed of one of Ta2O5, HfO2, ZrO2, Al2O3, TiO2 and a combination thereof. The first dielectric layer 120 is formed by CVD or ALD, using only a source gas without a reactant gas such as O2, H2O, H2O2, and N2O. Since the reactant gas is not used, the source gas should include oxygen atoms so as to deposit the foregoing dielectric oxide layer. The first dielectric layer 120 is deposited, for example, to a thickness dt1 of 5 to 200 Å at a temperature of 100 to 600° C.
  • In the present invention, there are various examples of the source gas, which enables reactant-free deposition of the dielectric layer. For example, to deposit a Ta2O5 layer, a source gas may be Ta(OC2H5)5 (pentaethoxide tantalum (PET)), tetra ethoxide tantalum-dimethyl amine ethoxide (TET-DMAE), Ta(OsBu)5, Ta(OC2H5)4(acacC2H5), TaCl2(OC2H5)2C5H7O2, or Ta(OCH3)5. To deposit an HfO2 layer, the source gas may be, for example, Hf(OtBu)4 or Hf(MMP)4, and an Al2O3 layer may be deposited using a source gas such as Al(MMP)3, Al(OiPr)3, Al(acac)3, or Al(O2C(H)EtnBu)3. Also, the source gas may be Zr(OtBu)4, Zr(MMP)4, Zr(METHD)4, Zr(THD)4, or Zr(MTHD)4 to deposit a ZrO2 layer, and Ti(OC2H5)4, Ti(MPD)(THD)2, Ti(MPD)(METHD)2, Ti(THD)2(OiPr)2, Ti(OiPr)4, Ti(MMP)4, or Ti(NPEB)4 may be used as a source gas to deposit a TiO2 layer. Here, acac represents acetyl acetone (CH3COCH2COCH3), MMP represents 1-methoxy-2-methyl-2-propoxide, and OiPr represents isopropoxy. METHD is indicative of 1-(2-methoxyethoxy)-2,2,6,6-tetramethyl-3,5-heptanedionate, THD is indicative of 2,2,6,6-tetramethyl-3,5-heptanedionate, and MTHD is indicative of 1-methoxy-tetramethyl-3,5-heptanedionate. Also, MPD is indicative of 2-methyl-2,4-pentanedioxide and NPEB is indicative of 1-n-propoxy-2-ethyl-2-butoxide.
  • Generally, depositing a thin oxide layer using CVD comprises injecting a source gas into a deposition chamber together with a reactant gas such as O2, H2O, H2O2, and N2O, and then heating the semiconductor substrate. Thus, oxides are deposited using thermal decomposition and reaction between gases that occur on the semiconductor substrate. Also, depositing a thin oxide layer using ALD comprises supplying a source gas to a deposition chamber and physically and chemically adsorbing the source gas on a semiconductor substrate. Then, the redundant source gas and the physisorbed source gas are purged using a purge gas such as N2. Next, a reactant gas such as O2, H2O, H2O2, and N2O is supplied to the deposition chamber and reacts with the chemisorbed source gas. The redundant reactant gas is also purged using a purge gas. The foregoing steps are repeatedly performed until the thin oxide layer having a predetermined thickness is obtained.
  • Meanwhile, according to the present invention, a dielectric oxide layer may be deposited using only a source gas without a reactant gas such as O2, H2O, H2O2, and N2O. By using the source gas including oxygen atoms, the thin dielectric oxide layer can be obtained without the reactant gas. For example, depositing the dielectric oxide layer using CVD comprises introducing a semiconductor substrate into a deposition chamber, supplying a source gas including oxygen atoms to the deposition chamber, and then heating the semiconductor substrate. Thus, the source gas is thermally decomposed on the semiconductor substrate so as to deposit a stable dielectric oxide layer.
  • Also, in the present invention, depositing a dielectric oxide layer using ALD comprises introducing a semiconductor substrate into a deposition chamber and injecting a source gas including oxygen atoms into the deposition chamber so as to induce chemical and physical adsorption. Here, the source gas is supplied using a bubbler technique or a liquid delivery system (LDS) technique. Once the adsorption is complete, after a predetermined time, an N2 or Ar inert gas is injected into the deposition chamber so as to remove the redundant source gas other than the chemisorbed source gas from the deposition chamber. When the semiconductor substrate is heated, the adsorbed source gas is thermally decomposed to deposit a stable dielectric oxide layer. After a predetermined time, the inside of the deposition chamber is purged using a purge gas so as to remove the residual materials resulting from the reaction. Next, a cycle of injecting a source gas, injecting a purge gas, reaction, and injecting a purge gas is repeated until the dielectric oxide layer having a predetermined thickness is formed.
  • The first dielectric layer 120 is cured (130) in an atmosphere containing oxygen, for example, an ozone or oxygen atmosphere, or using O2 plasma or N2O plasma. The plasma may be an RF plasma of 13.56 MHz or electron cyclotron resonance (ECR). Oxygen atoms generated from an atmosphere containing oxygen penetrate into the dielectric layer and are bonded with a dangling bond. As a result, the curing process 130 enables the first dielectric layer 120 to exhibit stable characteristics and oxygen vacancy to be filled, thus improving electrical properties. The temperature of the curing process 130 may be decided considering the type and the thickness of the deposited first dielectric layer 120 or other process conditions. Generally, the curing process 130 is carried out at a low temperature of approximately 350 to 650° C.
  • The second dielectric layer 140 is also deposited using only a source gas, without a reactant gas, by the same method as the first dielectric layer 120. The second dielectric layer 140 may be formed, for example, of one of Ta2O5, HfO2, ZrO2, Al2O3, TiO2, and a combination thereof using CVD or ALD. The second dielectric layer is deposited at a temperature of 100 to 600° C., like the first dielectric layer 120, while the deposited thickness dt2 ranges from 5 to 3000 Å. Examples of the source gas are the same as those of the first dielectric layer 120.
  • The thickness dt2 of the second dielectric layer 140 should be greater than that dt1 of the first dielectric layer 120 considering the step coverage and facility of the curing process. However, considering the electrical properties of the resulting device, the preferable thickness dt1 of the first dielectric layer 120 may optionally be greater than that dt2 of the second dielectric layer 140. The thicknesses dt1 and dt2 should be decided with all considerations for the step coverage, the facility of the curing process, and the electrical properties.
  • In the present embodiment, the thickness dt1 may be thinner than that St1 of FIG. 2 and the thickness dt2 may be thicker than that St2 of FIG. 2, so that the thickness T1 of the entire dielectric layer, i.e., the sum of the thicknesses dt1 and dt2 of the first and second dielectric layers 120 and 140, can be maintained to be equal to the thickness t1 of the dielectric layer of FIG. 2. Because the entire dielectric layer can be formed to a desired thickness by forming the first dielectric layer to be thinner than St1 of FIG. 2, even if the dielectric layer is deposited on a first electrode having a relatively complicated structure, the step coverage can be improved and yield can be increased. Also, since the dielectric layer is deposited using only a source gas, without a reactant gas such as O2, H2O, H2O2, and N2O, oxidation of a storage node contact plug caused by the reactant gas can be suppressed. The foregoing advantages will be explained in detail through the following embodiments.
    • Embodiment 2
  • FIG. 8 illustrates the first embodiment of present invention, with reference to FIGS. 5 through 7, as applied to the formation of a DRAM capacitor.
  • Specifically, a transistor is formed at an active region of a semiconductor substrate 201, which is defined by shallow trench isolation 203. The transistor includes a source region 205, a drain region 207, and a gate electrode 211 with an intervening gate oxide layer 209. Also, a bit line 213 is connected to the drain region 207, while a storage electrode, i.e., a first electrode 221, is connected to the source region 209 through a storage node contact plug 217 that fills a contact hole formed in an interlayer dielectric (ILD) 215. As described above, the first electrode 221 has the three-dimensional cylinder shape. The first electrode 221 is formed of one of TiN, TaN, W, WN, Al, Cu, Ru, RuO2, Pt, Ir, IrO2, a doped polysilicon, and a combination thereof. Also, the first electrode 221 can be formed using CVD, PVD, or ALD at a temperature of 25 to 1000° C. Next, a cleaning process is carried out to stabilize the interface of the first electrode 221, and then dielectric layers 223 and 224 and a second electrode 225 are formed on the first electrode 221.
  • As described above, the dielectric layers 223 and 224 are deposited using CVD or ALD using only a source gas without a reactant gas. The first dielectric layer 223 is deposited to a relatively thin thickness and is then cured using O3. Next, the second dielectric layer 224 is deposited to provide a predetermined combined dielectric layer thickness, without performing an additional curing process.
  • For example, assuming the temperature of the semiconductor substrate 201 is 430° C. and the pressure of the chamber is 1 Torr, the thickness of the first dielectric layer 223 is 90 Å and a thickness of the second dielectric layer 224 is 60 Å such that the total thickness is 150 Å. The first dielectric layer 223 is cured using 03 at 400° C. with 30 Torr for five minutes. The second electrode 225 is formed by the same method as the first electrode 221. The preferable composition of the first electrode 221/ dielectric layers 223 and 224/second electrode 225 is TiN/Ta2O5/TiN, between which reactivity is so low as to prevent degradation of the capacitor.
  • After forming the first dielectric layer 223, the second dielectric layer 224 is formed to meet the remaining required thickness. In this manner, the first electrode 221 having a complicated cylinder structure, as shown in FIG. 8, is able to satisfy the requirement for improved step coverage. Also, because the dielectric layers 223 and 224 are deposited using only a source gas such as PET containing oxygen atoms, without a reactant gas such as O2, H2O, H2O2, and N2O, oxidation of the storage node contact plug 217 can be prevented.
    • Embodiment 3
  • As described above, an analog capacitor, an RF capacitor, or a high-voltage capacitor requires a thicker dielectric layer than a capacitor used in a stand-alone memory or embedded memory. Therefore, according to the conventional method, the dielectric layer was formed by performing repeated deposition curing processes. However, according to the present invention, even a relatively thick dielectric layer can be formed through a twice-performed deposition process and a one-time curing process. This is described hereinafter with reference to the flowchart of FIG. 5 and the cross-sectional view of FIG. 9.
  • Referring to FIG. 9, a first dielectric layer 320 and a second dielectric layer 340 are formed between a first electrode 310 and a second electrode 350. As mentioned above, the first and second dielectric layers 320 and 340 are deposited using only a source gas, without a reactant gas. The first dielectric layer 320 is cured in an atmosphere containing oxygen, whereas the second dielectric layer 340 is not cured. In an analog capacitor, an RF capacitor, or a high-voltage capacitor, a dielectric layer such as Al2O3 may be applied between the first electrode 310 and first dielectric layer 320, and the dielectric layer such as Al2O3 may be inserted under the second electrode 350 in order to ensure suitable electrical properties.
  • As shown in FIG. 3, in the conventional method, n (n>3) dielectric layers (DL1, DL2, . . . , and DLn) were deposited and n curing processes were performed to obtain the thickness t2 of the dielectric layer. However, in the present embodiment, the entire thickness T2 (i.e., the thickness DT1 of the first dielectric layer+the thickness DT2 of the second dielectric layer), which is equivalent to the thickness t2 of FIG. 3, can be ensured by properly controlling the respective thicknesses DT1 and DT2 of the first and second dielectric layers 320 and 340, without adding any additional deposition and curing processes.
  • As a result, the thick dielectric layer required by the analog capacitor, the RF capacitor, or the high-voltage capacitor can be deposited, thus enabling the process simplification.
  • Example of Experiment
  • Typically, a CVD process uses a source gas together with a reactant gas to cause a reaction. FIG. 10 is a graph illustrating the results of depositing a dielectric layer using only a source gas without a reactant gas when a Ta2O5 dielectric layer is deposited to a thickness of 150 Å using CVD without any curing process, and a comparison of these results to the result of depositing a dielectric layer using a source gas with a reactant gas.
  • Squares ▪ shown on the graph represent a leakage current density in the case where the dielectric layer was deposited using a PET source gas and an O2 reactant gas. Circles ● on the graph represent a leakage current density in the case where the dielectric layer was deposited using only a PET source gas. In both cases, a cylinder-type capacitor, which includes electrodes formed of TiN using metal organic CVD (MOCVD), was formed as shown in FIG. 8.
  • In general, it is assumed that a capacitor formed using a reactant gas exhibits improved electrical properties. However, the results of the present experiment demonstrated that a capacitor formed without a reactant gas exhibits far better electrical properties. It can be inferred that in a structure having a small design rule such as DRAM, the reactant gas acted as an inhibitor to formation of the dielectric layer.
  • Meanwhile, FIG. 11 shows the resulting electrical properties in the case of the reactant-free deposition of the dielectric layer.
  • In FIG. 11, squares ▪ represent measured leakage current density for a device formed according to the conventional method. That is, TiN deposited by MOCVD was used as device electrodes, and to form a Ta2O5 layer, a deposition process was performed twice using an O2 reactant gas and a PET source gas, and, following each deposition process, a curing process was performed, using O3. The first Ta2O5 layer had a thickness of 60 Å and a second Ta2O5 layer had a thickness of 90 Å such that the total thickness is 150 Å. Circles ● represent leakage current density in the case where TiN deposited by MOCVD was used as electrodes and a Ta2O5 layer was deposited to a thickness of 150 Å using only a PET source gas. Here, no curing process is performed.
  • As shown in FIG. 11, when the dielectric layer is formed by reactant-free deposition, though a curing process is not performed, the leakage current caused by a negative applied voltage is substantially equal to that of the conventional method, and the leakage current caused by a positive applied voltage is slightly degraded, thus resulting in excellent electrical properties. Because the leakage current caused by the positive applied voltage affects the initial dielectric layer, as long as the first dielectric layer of the present invention is properly cured, equivalent or better electrical properties can be obtained, as compared with the conventional method.
  • In FIG. 12, squares ▪ represent measured leakage current density for a device formed according to the conventional method. That is, TiN deposited by PVD was used as device electrodes, and to form a Ta2O5 layer, a deposition process was performed twice using an O2 reactant gas and a PET source gas, and, following each deposition process, a curing process was performed using O3. The first Ta2O5 layer had a thickness of 60 Å and the second Ta2O5 layer had a thickness of 90 Å such that the total thickness was 150 Å. Circles ● represent leakage current density in the case where a first Ta2O5 layer was deposited to a thickness of 60 Å using only a PET source gas and is then cured using 03, and a second Ta2O5 layer was deposited thereon to a thickness of 90 Å using only a PET source gas without a curing process. Though the second Ta2O5 layer was not cured, the leakage current density was reduced, as compared to the example of FIG. 11.
    • Embodiment 4
  • FIG. 13 is a schematic top plan view of an apparatus for forming the dielectric layer according to the present invention.
  • Specifically, referring to FIG. 13, the apparatus for forming the dielectric layer comprises a loadlock chamber 405 where a cassette 403, on which semiconductor substrates 401 are loaded, is positioned, a transfer chamber 409 having a unit connected to the loadlock chamber 405 which is capable of loading/unloading a semiconductor substrate 401, for example, a robot arm 407, a first deposition chamber 411 connected to the transfer chamber 409, and a curing chamber 413 connected to the first deposition chamber 411. For example, the curing chamber 413 may be connected to an ozone generator or a plasma generator for generating oxygen radicals. The apparatus further comprises a second deposition chamber 414 connected to the transfer chamber 409.
  • In FIG. 13, the arrows indicate the manner in which the apparatus in forming a dielectric layer. To begin with, the semiconductor substrate 401, where the first electrode is formed, is introduced into the first deposition chamber 411 by the robot arm 407 in Step S10 of FIG. 5. Thus, a first dielectric layer is deposited as shown in Step S20 of FIG. 5. Here, the first dielectric layer is preferably deposited using only a source gas without a reactant gas. Next, the semiconductor substrate 401 is moved into the curing chamber 413 and is cured in an atmosphere containing oxygen, i.e., using one of O3, O2, O2 plasma, N2O plasma, and a combination thereof, according to Step S30 of FIG. 5. Then, the semiconductor substrate 401 is introduced into the second deposition chamber 414. A second dielectric layer is deposited to the remaining thickness on the semiconductor substrate 401 using only a source gas without a reactant gas, according to Step S40 of FIG. 5. The semiconductor substrate 401 is then unloaded to the loadlock chamber 405 without additional curing. Subsequently, a second electrode is formed on the second dielectric layer as shown in Step S50 of FIG. 5. Therefore, according to the present invention, steps from depositing the first dielectric layer to depositing the second dielectric layer can be performed by the use of a single apparatus for forming dielectric layers.
  • While the conventional apparatus requires two or more deposition chambers and curing chambers, the apparatus of the present invention includes only a pair of deposition chambers and a single curing chamber. That is, the structure of the equipment is relatively simple, as compared to the conventional approach. Also, the time required for moving a semiconductor substrate to respective chambers can be shortened, thus reducing the manufacturing costs. Further, because a transfer chamber is shared, the apparatus price is reduced and the space of a clean room can be efficiently used.
  • While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
  • In particular, though a first dielectric layer of the present invention is preferably deposited using only a source gas without a reactant gas, it is also possible to deposit the first dielectric layer using both the source gas and the reactant gas. However, the second dielectric layer should be deposited using only a source gas without a reactant gas.

Claims (8)

1. An apparatus for forming a dielectric layer comprising:
a loadlock chamber including a cassette for receiving a plurality of semiconductor substrates;
a transfer chamber including a robot arm connected to the loadlock chamber for loading and unloading a semiconductor substrate to and from the loadlock chamber;
a first deposition chamber connected to the transfer chamber for depositing a first dielectric layer on the substrate;
a curing chamber connected to the first deposition chamber; and
a second deposition chamber connected to the transfer chamber for depositing a second dielectric layer on the substrate,
wherein a first dielectric layer deposited in the first deposition chamber is cured in the curing chamber and then a second dielectric layer is deposited in the second deposition chamber.
2. The apparatus as claimed in claim 1, wherein the first dielectric layer is deposited using only a source gas without a reactant gas in the first deposition chamber.
3. The apparatus as claimed in claim 1, wherein the second dielectric layer is deposited using only a source gas without a reactant gas in the second deposition chamber.
4. The apparatus as claimed in claim 1, wherein the first dielectric layer deposited in the first deposition chamber is cured in the curing chamber in an atmosphere containing oxygen.
5. The apparatus as claimed in claim 1, wherein the transfer chamber introduces the substrate into the first deposition chamber and the second deposition chamber.
6. The apparatus as claimed in claim 1, wherein the transfer chamber receives the substrate from the second deposition chamber and unloads the substrate to the loadlock chamber without additional curing.
7. The apparatus as claimed in claim 1, wherein the curing chamber is connected to an ozone generator for generating oxygen radicals.
8. The apparatus as claimed in claim 1, wherein the curing chamber is connected to a plasma generator for generating oxygen radicals.
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