US20070161214A1 - High k gate stack on III-V compound semiconductors - Google Patents
High k gate stack on III-V compound semiconductors Download PDFInfo
- Publication number
- US20070161214A1 US20070161214A1 US11/327,675 US32767506A US2007161214A1 US 20070161214 A1 US20070161214 A1 US 20070161214A1 US 32767506 A US32767506 A US 32767506A US 2007161214 A1 US2007161214 A1 US 2007161214A1
- Authority
- US
- United States
- Prior art keywords
- layer
- iii
- compound semiconductor
- semiconducting
- semiconducting layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 150000001875 compounds Chemical class 0.000 title claims abstract description 85
- 239000000463 material Substances 0.000 claims abstract description 101
- 238000000034 method Methods 0.000 claims abstract description 67
- 239000003989 dielectric material Substances 0.000 claims abstract description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 238000011065 in-situ storage Methods 0.000 claims abstract description 19
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 15
- 239000002019 doping agent Substances 0.000 claims description 19
- 238000000137 annealing Methods 0.000 claims description 12
- 238000003795 desorption Methods 0.000 claims description 8
- 230000004913 activation Effects 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 3
- 230000002708 enhancing effect Effects 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 claims 2
- 239000010410 layer Substances 0.000 abstract description 121
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 39
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 6
- 239000002344 surface layer Substances 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 description 15
- 230000008021 deposition Effects 0.000 description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000004020 conductor Substances 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 229910000449 hafnium oxide Inorganic materials 0.000 description 7
- 239000007943 implant Substances 0.000 description 7
- 238000002161 passivation Methods 0.000 description 7
- 230000000737 periodic effect Effects 0.000 description 7
- -1 GaAs compound Chemical class 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 238000005137 deposition process Methods 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 3
- 229910020286 SiOxNy Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000000356 contaminant Substances 0.000 description 3
- 238000011066 ex-situ storage Methods 0.000 description 3
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 3
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 229910005542 GaSb Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- COHDHYZHOPQOFD-UHFFFAOYSA-N arsenic pentoxide Chemical compound O=[As](=O)O[As](=O)=O COHDHYZHOPQOFD-UHFFFAOYSA-N 0.000 description 2
- 238000010420 art technique Methods 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910017109 AlON Inorganic materials 0.000 description 1
- 229910017115 AlSb Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 1
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910004304 SiNy Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- LTBRWBUKPWVGFA-UHFFFAOYSA-N butan-1-olate;hafnium(4+) Chemical compound [Hf+4].CCCC[O-].CCCC[O-].CCCC[O-].CCCC[O-] LTBRWBUKPWVGFA-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000000224 chemical solution deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- CMIHHWBVHJVIGI-UHFFFAOYSA-N gadolinium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Gd+3].[Gd+3] CMIHHWBVHJVIGI-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000000752 ionisation method Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 229910003455 mixed metal oxide Inorganic materials 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000000348 solid-phase epitaxy Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31645—Deposition of Hafnium oxides, e.g. HfO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
- H01L21/02148—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
- The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure including a dielectric material having a dielectric constant of greater than that of silicon dioxide located on a passivated surface of a III-V compound semiconductor in which the passivated surface has electrical properties that are sufficient for high-performance field effect transistor (FET) applications. The present invention also provides a method of fabricating such a semiconductor structure.
- In semiconductor technology, an elemental semiconductor material such as, for example, Si or Ge, is typically used as a substrate in which one or more semiconductor devices including, but not limited to, FETs and capacitors, are formed. Of the various elemental semiconductor materials, Si is the elemental semiconductor of choice due to process and performance benefits that are achieved using such an elemental semiconductor material.
- Alternative semiconductor materials such as, for example, compound semiconductors, are also known which are used for specific market applications. A major class of compound semiconductors are comprised of at least one element from Group IIIA and Group VA of the Periodic Table of Elements. Such compound semiconductors including an element from Group IIIA and VA are often referred to as III-V or III/V compound semiconductors. Illustrative examples of III-V compound semiconductors include, but are not limited to: GaAs, InP, InAs, GaP, InSb, GaSb and GaN.
- The need for alternative semiconductor materials is driven by the growth of markets that require integrated circuit (IC) performance beyond that which Si semiconductors can provide. One key IC performance factor that needs to be achieved is high operating speeds. Wireless and high-speed digital communications, space applications, and consumer markets are developing special niche semiconductor markets that are centered on high speed that can support higher signal frequencies.
- GaAs, which is the most common III-V compound semiconductor material, has greater electron mobility than Si so the majority carriers move faster than in Si. There are also some attributes of a GaAs semiconductor material that reduce parasitic capacitance and signal loses. These result in ICs that are generally faster than those made with silicon. The improved signal speed of GaAs devices permits them to react to high-frequency microwave signals and accurately converts them into electrical signals. As such, products for wireless and high-speed digital communications and high-speed optoelectronic devices are made from GaAs and other III-V compound semiconductors.
- One major disadvantage of a GaAs semiconductor material (as well as the other III-V compound semiconductors) is the lack of a natural oxide. This feature hinders the development of standard metal oxide semiconductor (MOS) devices that require the ability to form a surface dielectric. Moreover, when a dielectric material having a dielectric constant that is greater than silicon dioxide (k greater than 4.0) is deposited on a GaAs semiconductor material that has an unpassivated surface, the interface between the high k dielectric and the GaAs semiconductor material is typically poor, resulting in a high interface state density (on the order of about 1013 cm−2 eV−1 or greater). Because of such a high interface state density, the electrical properties of the dielectric are insufficient for use with high-performance FETs.
- Several known solutions have been proposed, but each have problems/drawbacks associated therewith. One such solution is disclosed, for example by Passlack et al. “Low Dit, Thermodynamically Stable Ga2O3—GaAs Interfaces: Fabrication, Characterization, and Modeling”, IEEE Transactions on Electron Devices, Vol 44, No. 2, p. 214, February 1997 and by M. Hong et al., “Low Interface State Density Oxide-GaAs Structures Fabricated by in situ Molecular Beam Epitaxy”, J. Vac. Sci., Technol. B 14(3), p. 2297, May/June 1996. The prior art technique described in the two aforementioned disclosures involves deposition of a Ga2O3/Gd2O5 oxide on a clean/reconstructed GaAs surface in an ultra-high vacuum using an ultra-low oxygen ambient. This prior art technique has been shown to be successful in unpinning the GaAs/oxide interface, and produces a very low density of interface states. However, it requires a complex dual chamber molecular beam epitaxial (MBE) system which is not suitable for manufacturing. Moreover, Ga2O3 has the problem that it has a relatively low bandgap, and therefore can produce higher leakage than is desirable for scaled MOSFET applications.
- Another solution to the general problem mentioned above is disclosed, for example, in Tiwari et al. “Unpinned GaAs MOS Capacitors and Transistors”, IEEE Electron Device Letters, Vol. 9, No. 9, p. 488, September 1988; D. S. L. Mui et al, “Si3N4/Si/In0.53Ga0.47As Depletion-mode Metal-Insulator-Semiconductor Field Effect Transistors With Improved Stability”, Appl. Phys. Lett., 62 (25), p. 3291, Jun. 21, 1993; Z. Wang et al., “Si3N4/Si/n-GaAs Capacitor with Minimum Interface Density in the 1010 eV−1 cm−2 Range”, Appl. Phys. Lett., 62 (23), p. 2977, Jun. 7, 1993; Z. Wang et al., “Gate Quality Si3N4/Si/n-In0.53Ga0.47As Metal-Insulator-Semiconductor Capacitors”, Appl. Phys. Lett., 61 (15) p. 1826, Oct. 12, 1992; D. S. L. Mui et al. “Investigations of the Si3N4/Si/n-GaAs Insulator-Semiconductor Interface With Low Interface Trap Density”, Appl. Phys. Lett., 60 (20), p. 2511, May 18, 1992; and D. S. L. Mui et al. “Electrical Characteristics of Si3N4/Si/GaAs Metal-Insulator-Semiconductor Capacitor”, Appl. Phys. Lett. 59 (22), p. 2847, Nov. 25, 1991. Specifically, each of the aforesaid articles disclose the deposition of a thin Si layer on top of a GaAs substrate in a MBE chamber after GaAs growth. In some of these disclosures, the Si is deposited in the same chamber as the GaAs using a heated elemental Si source. In other disclosures, a second dual chamber system is employed, and the interfacial Si is deposited using an ECR source, which allows higher deposition rates. Both of these techniques mentioned in the above articles have the problem that an III-V MBE chamber is needed to first produce a high-quality GaAs interface before Si deposition.
- Callegari et al., “Properties of SiO2/Si/GaAs Structures Formed By Solid Phase Epitaxy of amorphous Si on GaAs”, App. Phys. Lett. 58, (22), p. 2540, Jun. 3, 1991 provide a method wherein the GaAs compound semiconductor is subjected to a H-precleaning process prior to deposition, e.g., plasma enhanced chemical vapor deposition (PECVD) of a Si layer. After deposition of the Si layer, SiO2 is formed on the precleaned GaAs surface.
- In addition to the above-mentioned techniques, several techniques have been purposed to passivate a GaAs surface, yet these techniques have not been utilized in conjunction with a high k dielectric. These prior art GaAs passivation techniques include, for example, nitrogen passivation and sulfur passivation. Both of the aforementioned passivation techniques have been shown to unpin the GaAs surface under certain conditions, but it is not clear whether or not such passivation techniques would work in conjunction with a high k dielectric.
- In view of the above, there is a need for providing a method in which a high k dielectric stack can be formed on a surface of a III-V compound semiconductor material with electrical properties sufficient for high-performance FET applications. That is, a method is needed in which the interface between the high k dielectric stack and the III-V compound semiconductor material is of good quality, resulting in low interface state density (on the order of about 1012 cm−2 eV−1 or less). More specifically, a structure including an unpinned III-V compound semiconductor surface is needed.
- The present invention provides a method in which a high k dielectric material having a dielectric constant of greater than that of silicon dioxide can be formed on a surface of a III-V compound semiconductor material with electrical properties sufficient for high-performance FET applications wherein the interface between the high k dielectric material and the III-V compound semiconductor material is of good quality, resulting in a low interface state density (on the order of about 1012 cm−2 eV−1 or less); the unit for the interface state density can also be written as cm−2/eV. That is, the present invention provides a method in which a high k dielectric material is formed on an unpinned, i.e. passivated, surface of a III-V compound semiconductor material. In accordance with the method of the present invention, the surface of the III-V compound semiconductor includes substantially no oxide or other contaminants that would otherwise cause a large interface state density in the structure.
- In accordance with the present invention, the method begins by first subjecting a III-V compound semiconductor material to a cleaning step that is capable of removing any native oxides such as, Ga2O3 or As2O5, from the surface of the III-V compound semiconductor material. This step provides a treated surface that typically remains unpinned. The preclean may be performed by a desorption process or, preferably, by a H plasma process. A semiconducting layer (either amorphous or crystalline) is formed in-situ on the treated surface of the III-V compound semiconductor material. This step, together with the previous precleaning step, provides a structure in which the surface of the III-V compound is passivated. Preferably, the semiconducting layer comprises Si, with amorphous Si being even more highly preferred. At this point of the present invention, the semiconducting layer can optionally be subjected to a nitridation, oxidation or oxynitridation process. That is, the semiconducting layer is optionally converted, completely or partially, into a layer or surface region that is comprised of AOxNy wherein A is a semiconducting material, preferably Si, x is from 0 to 1 and y is from 0 to 1; note x and y can not both be zero at the same time. In accordance with the present invention, an in-situ or ex-situ oxidation, nitridation or oxynitridation process can be used. Next, a dielectric material (or multilayers thereof) that has a dielectric constant that is greater than silicon dioxide is formed on either the semiconducting layer, or the AOxNy layer.
- In general terms, the method of present invention comprises:
- removing native oxides from a III-V compound semiconductor material to provide a treated surface;
- forming a semiconducting layer in-situ on said treated surface of said III-V compound semiconductor material; and
- forming a dielectric material having a dielectric constant that is greater than silicon dioxide on said semiconducting layer.
- In one embodiment of the present invention, the method of present invention comprises:
- removing native oxides from a III-V compound semiconductor material to provide a treated surface;
- forming a semiconducting layer in-situ on said treated surface of said III-V compound semiconductor material;
- converting at least an upper surface region of said semiconducting layer to a region comprised of AOxNy wherein A is a semiconducting material, x is from 0 to 1, y is from 0 to 1 and x and y are not both 0; and
- forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the upper surface region of said semiconducting layer.
- In accordance with the present invention, the converting step may include a complete or partial oxidation, nitridation or oxynitridation process. When complete conversion is achieved, the semiconductor layer is modified to comprise a AOxNy layer, wherein A, x and y are as defined above. In a preferred embodiment, the semiconducting layer is Si which is modified to a SiOxNy layer. In this particular embodiment, the high k dielectric material is formed on a completely modified semiconducting, e.g., SiOxNy, layer. When partial conversion is achieved, an upper surface region of the originally formed semiconducting layer is modified to include a AOxNy surface layer that is located above the remaining semiconducting layer. In this particular embodiment, the dielectric material is formed on the converted upper surface region of the semiconducting layer.
- In a highly preferred embodiment of the present invention, the method includes the steps of:
- subjecting a GaAs compound semiconductor material to a H preclean, said H preclean removes native oxides from a surface of said GaAs compound semiconductor material;
- forming an amorphous Si layer in-situ on said surface of said GaAs compound semiconductor material;
- subjecting said Si layer to a nitridation process to form a silicon nitride layer; and
- forming a Hf-based dielectric on said silicon nitride layer.
- The methods of the present invention described above have has several advantages. First the semiconducting, e.g., Si, layer is excellent at passivating a surface of a III-V compound semiconductor material, particularly a GaAs surface. Secondly, by depositing the semiconducting layer using a high-quality technique such as MBE, the surface can be cleaned (either by desorbing the oxygen at high temperatures, or using a H-plasma preclean), to create a virtually oxygen-free interface. The semiconducting layer thickness can be controlled to high precision as well, and thus be made very thin. If the semiconducting layer is nitridated, in situ, a nitrogen plasma could be used to then convert the semiconducting layer to a semiconducting nitride. Nitride, instead of oxide, formation has the advantage that over nitridation will not cause problems, as generally, nitridation of the GaAs surface does not degrade the electrical characteristics. Over oxidation, on the other hand, can severely degrade the electrical characteristics. Once the nitride is formed, the surface is stable against oxidation, and could be removed and exposed to air, for subsequent high k deposition. A semiconducting nitride also has the advantage of allowing the subsequent HfO2 that is deposited to nucleate amorphous as opposed to polycrystalline, which can improve the electrical properties. The HfO2 could be deposited in situ as well, which would have the advantage that the entire gate stack could be deposited in a single vacuum step. The inventive process has the additional advantage that it does not require a high-temperature step, as the H-preclean, semiconducting layer deposition, optional nitridation, oxidation or oxynitridation and high k deposition all could be performed at a temperature of less than 300° C., which would avoid any contamination or surface degradation problems associated with sublimation of one of the elements of the III-V compound semiconductor material.
- In addition to the general method and other embodiments thereof described above, the present invention also relates to a semiconductor structure which includes a dielectric material located on a passivated surface of a III-V compound semiconductor material. In accordance with this aspect of the present invention, the inventive structure generally includes:
- a III-V compound semiconductor material having a surface that is essentially free of oxides;
- a semiconducting layer located on said surface, wherein an interface is present between the III-V compound semiconductor material and the semiconducting layer that has an interface state density of about 1012 cm−2 eV−1 or less; and
- a dielectric material having a dielectric constant greater than that of silicon dioxide located on said semiconducting layer.
- In some embodiments, the semiconducting layer includes at least a surface region of AOxNy, where A, x and y are as defined above. In such an embodiment, the dielectric material is located on said surface region of AOxNy.
- In yet another embodiment of the present invention, the semiconducting layer of the inventive semiconductor structure is replaced by a AOxNy layer and the dielectric material is located on that replacement layer.
- In a highly preferred embodiment, the semiconductor structure comprises:
- a GaAs compound semiconductor material having a surface that is essentially free of oxides;
- a silicon nitride layer located on said surface, wherein an interface is present between GaAs and the silicon nitride layer that has an interface state density of about 1012 cm−2 eV−1 or less; and
- a Hf-based dielectric material located on said silicon nitride layer.
- In addition to the above, the applicants have determined that the presence of the semiconducting layer acts as a robust cap during the activation of implanted source/drain regions. There is no measurable surface erosion observed in the inventive capped structure even after annealing at temperatures of greater than 800° C. This cap is far superior to conventional caps of SiNx or SiOX where measurable surface erosion occurs after annealing at 800° C. or greater. Accordingly, the present invention provides a method of enhancing the activation of implanted dopants within a III/V compound semiconductor material that includes:
- providing a semiconducting cap layer atop a III/V compound semiconductor that has a surface that is essentially free of oxides, said III/V compound semiconductor including n-type dopants and/or p-type dopants; and
- annealing (typically at 800° C. or greater) the dopants to provide at least one activated dopant region in said III/V compound semiconductor.
- In this particular embodiment of the present invention, the n-type dopants for III/V materials include Si, Ge, an element from Group VIA of the Periodic Table of Elements or any combination thereof, while the p-type dopants include C, an element from Group IIA of the Periodic Table of Elements or any combination thereof. A conventional ion implantation process, gas phase doping or plasma immersion process can be used to introduce the dopants into the III/V compound semiconductor material and the annealing step is performed utilizing conventional conditions that are well-known in the art.
- It should be noted that the term “III-V compound semiconductor material” is used throughout this application to include a semiconductor material that includes at least one element or a mixture of elements from Group IIIA of the Periodic Table of Elements and at least one element or a mixture of elements from Group VA of the Periodic Table of Elements. The III-V compound semiconductor material may be a single layered material or a multilayered material including different III-V compound semiconductors stacked upon each other can be used. In the multilayered embodiment, an upper layer of a III-V compound semiconductor is located on a lower layer of a different III-V compound material, wherein the upper layer has a wider-band gap than that of the lower layer, is used. A III-V layer may also be grown on a IVA elemental semiconductor, e.g., GaP on Si or GaA on Ge or vice a versa.
-
FIGS. 1A-1D are pictorial representations (through cross sectional views) depicting one embodiment of the present invention. - FIGS. 2A-E are pictorial representations (through cross sectional views) depicting another embodiment of the present invention.
-
FIG. 3 is a pictorial representation (through a cross sectional view) depicting a FET that includes the inventive semiconductor structure. -
FIG. 4A is a graph showing the C-V characteristics of a MOS capacitor comprising GaAs/amorphous Si/SiOx/HfO2, after annealing at 700° C. for 1 minute in a nitrogen ambient. -
FIG. 4B is graph showing the interface state density as a function of gate voltage of the MOS capacitor mentioned inFIG. 4A . - The present invention, which provides a high k gate stack on a III-V compound semiconductor material as well as a method of fabricating the same, will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative proposes and, as such, they are not drawn to scale.
- Reference is first made to
FIGS. 1A-1D , which are pictorial representations (through cross sectional views) depicting one embodiment of the present invention. In this particular embodiment, asemiconducting layer 14 is first formed on a treatedsurface 11 of a III-Vcompound semiconductor material 10 and thereafter adielectric material 16 having a dielectric constant of greater than that of silicon dioxide is formed on thesemiconducting layer 14. - Reference is first made to
FIG. 1A which illustrates an initial III-Vcompound semiconductor material 10 that can be used in the present invention. As shown, the initial III-Vcompound semiconductor material 10 hasregion 12 that includes native oxides, atomic Ga or As species and other contaminants such as, for example, C-containing compounds therein. In accordance with the present invention, the initial III-Vcompound semiconductor material 10 used is a semiconductor material that includes at least one element or a mixture of elements from Group IIIA of the Periodic Table of Elements and at least one element or a mixture of elements from Group VA of the Periodic Table of Elements. Illustrative examples of III-V compound semiconductors that can be used asmaterial 10 include, but are not limited to: GaAs, InP, InAs, GaP, InSb, GaSb, GaN, InGaAs, and InAsSb. Preferably the III-V compound semiconductor is one of GaAs optionally including In, or one of InSb optionally including As. - The III-V
compound semiconductor material 10 may be a single layered material (as shown) or a multilayered material (seeFIG. 2A , for example) including different III-V compound semiconductors stacked upon each other. In the multilayered embodiment, an upper layer of a III-V compound semiconductor is located on a lower layer of a different III-V compound material, wherein the upper layer has a wider-band gap than the lower layer. Some examples of such materials include, but are not limited to: an AlGaAs layer atop a InGaAs layer, a InGaP layer located atop a InGaAs layer, InAlAs layer atop a InGaAs layer, or a AlSb layer atop an InAsSb layer. A III-V layer may also be grown on a IVA elemental semiconductor, e.g., GaP on Si or GaA on Ge or vice a versa. - The
region 12 of native oxides and other contaminates typically includes at least an oxide of one of the elements of the initial III-V compound semiconductor material. For example, if the initial III-Vcompound semiconductor material 10 is GaAs,region 12 would include an oxide of Ga and/or an oxide of As. The initial III-Vcompound semiconductor material 10 includes an untreated surface at this point of the present invention which, if used without cleaning and passivated, would result in a structure that is pinned and has a high interface state density (on the order of about 1013 cm−2 eV−1 or greater). -
FIG. 1B shows the III-Vcompound semiconductor material 10 ofFIG. 1A after theregion 12 of native oxides and other contaminates is removed from the material forming a treatedsurface 11. The treatedsurface 11 which contains essentially no oxides and other contaminates is formed by utilizing a desorption process or by utilizing a H plasma precleaning process. By “essentially free of oxide” it is meant that the oxide content is about 10−2 of a monolayer or less. - When a desorption process is used to remove
region 12 forming the treatedsurface 11, the desorption is carried out in vacuum or an inert ambient such as, for example, N2, He, Ar or a mixture thereof, at a temperature of about 600° C. or greater. The desorption is typically performed in the presence of a partial pressure of As wherein a partial pressure equivalent to an incident flux of about 1014 As molecules cm−2 or higher is established. - Although desorption can be used, it is preferred in the present invention that the
region 12 is removed from the III-Vcompound semiconductor material 10 utilizing a H plasma process. The H plasma process includes providing a plasma of hydrogen, H, using a hydrogen source such as, for example, molecular or, more preferably, atomic hydrogen. The hydrogen plasma is a neutral, highly ionized hydrogen gas that consisting of neutral atoms or molecules, positive ions and free electrons. Ionization of the hydrogen source is typically carried out in a reactor chamber in which the ionization process is achieved by subjecting the source to strong DC or AC electromagnetic fields. Alternatively, the ionization of the hydrogen source is performed by bombarding the gate atoms with an appropriate electron source. - In accordance with a preferred embodiment of the present invention, the hydrogen plasma process used to provide the treated
surface 11 is performed at a temperature of about 300° C. or less. - As stated above, this step of the present invention removes the
region 12 including at least the native oxides of the III-V compound semiconductor material from the initial material providing a treatedsurface 11 such as shown, for example, inFIG. 1B . The interface formed at the treated surface located between the III-V compound semiconductor 10 and the semiconductor layer (to be subsequently formed) has a low interface state density of on the order of about 1012 cm−2 eV−1 or less. - The thickness of the treated
surface 11 may vary depending on the technique used in forming the same and the exact conditions employed. Typically, the treatedsurface 11 has a thickness that is about a few monolayers or greater. - After forming the treated
surface 11, asemiconducting layer 14 is formed thereon providing the structure shown, for example, inFIG. 1C . Thesemiconducting layer 14 may be crystalline or, more preferably, amorphous. The term “semiconducting layer” denotes a layer including Si, Ge alloys, SiGe, SiC, SiGeC and the like. Preferably, thesemiconducting layer 14 is comprised of Si. In accordance with the present invention, thesemiconducting layer 14 is formed in-situ in the same reactor chamber as used in providing the treatedsurface 11. This step provides a semiconducting layer that passivates the previously cleaned III-V compound semiconductor material. Thesemiconducting layer 14 is formed by molecular beam epitaxy (MBE), chemical vapor deposition (CD), and other like deposition processes. Preferably, MBE is used in forming thesemiconducting layer 14. - The thickness of the
semiconducting layer 14 may vary depending on the technique used in forming the same. Typically, thesemiconducting layer 14 has a thickness from about 0.5 to about 5 nm, with a thickness from about 0.5 to about 2 nm being even more typical. - In the specific embodiment illustrated, a
dielectric material 16 having a dielectric constant of greater than that of silicon dioxide is formed on the surface of thesemiconducting layer 14. Thedielectric material 16 employed in the present invention comprises any metal oxide or mixed metal oxide that is typically used as a gate dielectric or a capacitor dielectric in semiconductor device manufacturing. Examples of such dielectric materials (which can be referred to as a high k dielectric since they have a dielectric constant of that which is greater than silicon dioxide) include, but are not limited to: Al2O3, AlON, Ta2O5, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, MgO, MgNO, Hf-based diele described in greater detail herein below), and combinations including multilayers thereof. - The term ‘Hf-based dielectric’ is intended herein to include any high k dielectric containing hafiium, Hf. Examples of such Hf-based dielectrics comprise hafnium oxide (HfO2), hafiiium silicate (HfSiOx), Hf silicon oxynitride (HfSiON), HfLaOx, HfLaSiOx, HfLaSiONx, or multilayers thereof. Typically, the Hf-based dielectric is hafnium oxide or hafnium silicate. Hf-based dielectrics typically have a dielectric constant that is greater than about 10.0.
- The physical thickness of the
dielectric material 16 may vary, but typically, thedielectric material 16 has a thickness from about 0.2 to about 20 nm, with a thickness from about 0.5 to about 10 nm being more typical. Thedielectric material 16 may be formed in-situ or ex-situ utilizing any conventional deposition process including, for example, chemical vapor deposition, PECVD, atomic layer deposition, chemical solution deposition, MOCVD, evaporation and other like deposition processes. - In one embodiment of the present invention, the
dielectric material 16 is hafnium oxide that is formed by MOCVD were hafnium-tetrabutoxide (a Hf-precursor) and O2 are used. In such an embodiment, the O2 may be molecular oxygen, or preferably, atomic oxygen is used. The deposition of Hf oxide occurs using a chamber pressure of about 1 Torr or less and a substrate temperature of about 200° C. or greater. In another embodiment of the present invention, thedielectric material 16 is hafnium silicate which is formed by MOCVD using the precursor Hf-tetrabutoxide, O2, and SiH4; (ii) a chamber pressure of about 1 Torr or less; and (iii) a substrate temperature of about 200° C. or greater may also be used. - Reference is now made to
FIGS. 2A-2E which illustrates another embodiment of the present invention. In this embodiment of the present invention, asemiconducting layer 14 is first formed on a treatedsurface 11 of a III-V compound semiconductor material 10 (including top and bottom layers as described above) and thereafter thesemiconducting layer 14 is completely or partially converted into alayer 15 including at least a surface region comprised of AOxNy, wherein A is a semiconducting material, x is 0 to 1, y is 0 to 1 and x and y are both not zero. In the embodiment where complete conversion is achieved,layer 15 is completely comprised of AOxNy. In embodiments where partially conversion is achieved, the upper surface portion oflayer 15 is comprised of AOxNy and the remaining portion oflayer 15 is comprised of the semiconducting material.FIG. 3 shows such an embodiment, wherein 15A is the remaining semiconducting material oflayer FIG. 3 , the remaining semiconducting layer is optional. In either embodiment, the treated surface is passivated with either a AOxNy layer or a material stack comprising, from bottom to top, a semiconducting material and a AOxNy layer. - This embodiment shown in
FIGS. 2A-2E begins by first providing the structure shown inFIG. 2A which includes a III-Vcompound semiconductor material 10 having aregion 12 of native oxides and other contaminants therein. Thesemiconductor material 10 and theregion 12 are the same as described above forFIG. 1A . It is noted that in these drawings, thesemiconductor material 10 is shown as including a top III-Vcompound semiconductor layer 10B that has a wider band gap than that of the lower III-Vcompound semiconductor layer 10A.FIG. 2B illustrates the structure that is formed after removing theregion 12 from the structure and forming the treatedsurface 11 therein. This step of the illustrated embodiment is the same as that described above forFIG. 1B . Next, and as is shown inFIG. 2C , a semiconducting layer 14 (as described above) is formed on the treatedsurface 11. - After forming the
semiconducting layer 14,layer 14 is converted completely or partially converted into alayer 15 that is comprised of at least a surface region including AOxNy wherein A is a semiconducting material, x is 0 to 1, y is 0 to 1 and x and y are both not zero. The resultantstructure including layer 15 is shown, for example, inFIG. 2D . In accordance with this embodiment of the present invention, thesemiconducting layer 14 is subjected to a nitridation, oxidation or oxynitridation process which may be performed in-situ or ex-situ utilizing conventional conditions that are well known in the art. Plasma and thermal techniques are both contemplated herein. In the case ofsemiconducting layer 14 being Si, a SiNy layer can be formed by exposing thesemiconducting layer 14 to atomic nitrogen, with a partial pressure typically in the range of 10−6 to 10−4 Torr, at a temperature in the range of about 200° C. or greater, and a SiOx layer to atomic O, with a partial pressure typically in the range of 10−6 to 10−4 Torr at a temperature in the range of about 200° C. or greater, and a SiOxNy layer can be formed by utilizing a sequential or concurrent combination of these conditions. It is noted that other conditions can be used besides those mentioned herein for this step of the present invention. In accordance with the present invention, it is preferred that this step of the present invention by performed in-situ. The conditions and duration of the converting will determine whether thesemiconducting layer 14 is completely (typically characterized by longer processing times) or partially modified (typically characterized by shorter processing times). - When complete conversion is achieved, the
semiconducting layer 14 is modified to a AOxNy layer, wherein A, x and y are as defined above. When partial conversion is achieved, an upper surface region of the originally formedsemiconducting layer 14 is modified to include a AOxNy surface layer that is located above the remaining semiconducting material. In this particular embodiment, the dielectric material is formed on the converted upper surface region. In such an embodiment, the upper surface region including the AOxNy surface layer has a thickness from about 0.5 to about 8 nm, with a thickness of about 0.5 to about 2 nm being even more typical. -
FIG. 2E illustrates the structure after a dielectric material 16 (as described above) is formed onlayer 15. Notwithstanding partial or complete conversion oflayer 15, thedielectric material 16 is formed on a surface that is comprised of AOxNy. - The material stacks shown in
FIG. 1D or 2E can be used in fabricating a metal oxide semiconductor capacitor (MOSCAP) and/or a MOSFET utilizing conventional processes that are well known in the art. One example of a MOSFET is shown inFIG. 3 ; in thisdrawing reference numeral 10 denotes the III-V compound semiconductor,reference numeral 11 denotes the treated surface,reference numeral 15B denotes the AOxNy layer,reference numeral 15A denotes the remaining semiconducting material of the semiconducting layer;reference numeral 16 denotes the high k dielectric material,reference numeral 18 denotes the gate electrode, andreference numeral 20 denotes the source/drain diffusion regions. In each case, an electrode or an electrode stack is formed on the material stacks shown inFIG. 1D or 2E and thereafter these materials layers are patterned by lithography and etching. - The electrode or electrode stack, which comprises at least one conductive material, is formed utilizing a known deposition process such as, for example, physical vapor deposition, CVD or evaporation. The conductive material used as the electrode includes, but is not limited to: Si-containing materials such as Si or a SiGe alloy layer in either single crystal, polycrystalline or amorphous form. The conductive material may also be a conductive metal or a conductive metal alloy. Combinations of the aforementioned conductive materials are also contemplated herein. Si-containing materials are preferred, with polySi being most preferred. In addition to aforementioned conductive materials, the present invention also contemplates instances wherein the conductor is fully silicided or a stack including a combination of a silicide and Si or SiGe. The silicide is made using a conventional silicidation process well known to those skilled in the art. Fully silicided layers can be formed using a conventional replacement gate process; the details of which are not critical to the practice of the present invention. The blanket layer of conductive material may be doped or undoped. If doped, an in-situ doping deposition process may be employed in forming the same. Alternatively, a doped conductive material can be formed by deposition, ion implantation and annealing. The ion implantation and annealing can occur prior to or after a subsequent etching step that patterns the material stack. The doping of the conductive material will shift the workfunction of the electrode formed. The thickness, i.e., height, of the electrode deposited at this point of the present invention may vary depending on the deposition process employed. Typically, the electrode has a vertical thickness from about 20 to about 180 nm, with a thickness from about 40 to about 150 nm being more typical.
- The MOSCAP formation typically includes forming a thermal, chemical or deposited sacrificial oxide (not shown) on the surface of the III-V compound semiconductor material. Using lithography, the active areas of the capacitor structure are opened in the field oxide by etching. Following the removal of the oxide, the material stack as shown in
FIG. 1D or 2E is formed as described above. Specifically, the material stack is provided, patterned by lithography and etching, and then a gate electrode including dopants is formed on the dielectric stack. In the case of a poly-silicon gate electrode, the dopants are typically P or As, and can be incorporated by implantation with a typical dose in the range of 1×1015 ions/cm2 to 5×1015 ions/cm2, or in situ doping during poly-silicon deposition using dopant precursor species such as AsH3 or PH3. The dopants are activated using an activation anneal that is performed at 900° C. to 1000° C. for about 5 seconds. The MOS cap could also incorporate a metal or metal-alloy stack alone or in combination with a polysilicon gate electrode. In some cases, an anneal step can be performed before or after the deposition of the gate electrode. Said anneal step is typically performed between 500° to 800° C., and is typically performed in a nitrogen ambient. - The MOSFET formation includes first forming isolation regions, such as trench isolation regions, within the III-V compound semiconductor material described above. A sacrificial oxide layer can be formed atop the III-V compound semiconductor material to form the isolation regions. Similar to the MOSCAP and after removing the sacrificial oxide, a material stack as described above is formed. Next, a gate electrode is formed and the material stack is then patterned. Following patterning of the material stack, at least one spacer is typically, but not always, formed on exposed sidewalls of each patterned material stack. The at least one spacer is comprised of an insulator such as an oxide, nitride, oxynitride and/or any combination thereof. The at least one spacer is formed by deposition and etching.
- The width of the at least one spacer must be sufficiently wide such that the source and drain silicide contacts (to be subsequently formed) do not encroach underneath the edges of the patterned material stack. Typically, the source/drain silicide does not encroach underneath the edges of the patterned material stack when the at least one spacer has a width, as measured at the bottom, from about 20 to about 80 nm.
- The patterned material stack can also be passivated at this point of the present invention by subjecting the same to a thermal oxidation, nitridation or oxynitridation process. The passivation step forms a thin layer of passivating material about the material stack. This step may be used instead or in conjunction with the previous step of spacer formation. When used with the spacer formation step, spacer formation occurs after the material stack passivation process.
- Source/drain diffusion regions are then formed into the substrate. The source/drain diffusion regions are formed utilizing ion implantation and an annealing step. Typically, a raised source/drain process is used. The annealing step serves to activate the dopants that were implanted by the previous implant step. The conditions for the ion implantation and annealing are well known to those skilled in the art. The source/drain diffusion regions may also include extension implant regions which are formed prior to source/drain implantation using a conventional extension implant. The extension implant may be followed by an activation anneal, or alternatively the dopants implanted during the extension implant and the source/drain implant can be activated using the same activation anneal cycle. Halo implants are also contemplated herein.
- In some cases, an annealing step as described above can be performed. Further CMOS processing such as formation of silicided contacts (source/drain and gate) as well as formation of BEOL (back-end-of-the-line) interconnect levels with metal interconnects can be formed utilizing processing steps that are well known to those skilled in the art.
- The following example is provided for illustrative purposes and thus it should not be construed to limit the scope of the present application in any way.
- In this example, a MOSCAP was prepared utilizing a semiconductor structure in accordance with the present invention. The inventive structure included, from bottom to top, an atomic-H passivated GaAs substrate, an amorphous Si layer, SiOx and HfO2. The structure was formed utilizing the inventive processing details described above. After formation, a gate electrode was formed thereon and the structure was annealed at 700° C., 1 min., in nitrogen.
-
FIG. 4A shows the CV curves of such a MOSCAP at 1 kHz, 10 kHz, 100 kHz and 1 MHz. Specifically, the CV curves have very low frequency dispersion, which is indicative of low interface state density.FIG. 4B shows the Dit extracted as a function of gate voltage of the same MOSCAP as inFIG. 4A using the frequency-dependent method well known in the art. The results show a minimum Dit value of 6×1011 cm−2/eV, which is over an order of magnitude lower than typically obtained on MOSCAPs with HfO2 directly on an unpassivated GaAs. - While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Claims (23)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/327,675 US20070161214A1 (en) | 2006-01-06 | 2006-01-06 | High k gate stack on III-V compound semiconductors |
US13/607,741 US9805949B2 (en) | 2006-01-06 | 2012-09-09 | High κ gate stack on III-V compound semiconductors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/327,675 US20070161214A1 (en) | 2006-01-06 | 2006-01-06 | High k gate stack on III-V compound semiconductors |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/607,741 Division US9805949B2 (en) | 2006-01-06 | 2012-09-09 | High κ gate stack on III-V compound semiconductors |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070161214A1 true US20070161214A1 (en) | 2007-07-12 |
Family
ID=38233253
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/327,675 Abandoned US20070161214A1 (en) | 2006-01-06 | 2006-01-06 | High k gate stack on III-V compound semiconductors |
US13/607,741 Active 2027-04-12 US9805949B2 (en) | 2006-01-06 | 2012-09-09 | High κ gate stack on III-V compound semiconductors |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/607,741 Active 2027-04-12 US9805949B2 (en) | 2006-01-06 | 2012-09-09 | High κ gate stack on III-V compound semiconductors |
Country Status (1)
Country | Link |
---|---|
US (2) | US20070161214A1 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080242012A1 (en) * | 2007-03-28 | 2008-10-02 | Sangwoo Pae | High quality silicon oxynitride transition layer for high-k/metal gate transistors |
US20100075507A1 (en) * | 2008-09-22 | 2010-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Fabricating a Gate Dielectric for High-K Metal Gate Devices |
US20100123205A1 (en) * | 2008-11-17 | 2010-05-20 | International Business Machines Corporation | Method to prevent surface decomposition of iii-v compound semiconductors |
US20120132913A1 (en) * | 2010-11-29 | 2012-05-31 | International Business Machines Corporation | III-V Compound Semiconductor Material Passivation With Crystalline Interlayer |
US20150011080A1 (en) * | 2013-07-03 | 2015-01-08 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR ELECTRICAL ACTIVATION OF DOPANT SPECIES IN A GaN FILM |
US20150214047A1 (en) * | 2014-01-29 | 2015-07-30 | Renesas Electronics Corporation | Method for Manufacturing Semiconductor Device |
US20170062522A1 (en) * | 2015-08-27 | 2017-03-02 | Intermolecular, Inc. | Combining Materials in Different Components of Selector Elements of Integrated Circuits |
US20170229303A1 (en) * | 2014-11-13 | 2017-08-10 | Applied Materials, Inc. | Method for removing native oxide and residue from a iii-v group containing surface |
US20180053656A1 (en) * | 2016-08-18 | 2018-02-22 | International Business Machines Corporation | Gate-Stack Structure with a Diffusion Barrier Material |
US20180269300A1 (en) * | 2007-02-15 | 2018-09-20 | Sony Corporation | Method for manufacturing insulated gate field effect transistor |
US10720337B2 (en) * | 2018-07-20 | 2020-07-21 | Asm Ip Holding B.V. | Pre-cleaning for etching of dielectric materials |
US10720334B2 (en) | 2018-07-20 | 2020-07-21 | Asm Ip Holding B.V. | Selective cyclic dry etching process of dielectric materials using plasma modification |
CN113964178A (en) * | 2020-07-21 | 2022-01-21 | 格芯(美国)集成电路科技有限公司 | III-V compound semiconductor layer stack with electrical isolation provided by trap rich layer |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9515186B2 (en) | 2014-01-23 | 2016-12-06 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US10259600B2 (en) | 2015-06-19 | 2019-04-16 | Telebrands Corp. | Container sealing device |
US20160368628A1 (en) | 2015-06-19 | 2016-12-22 | Telebrands Corp. | System, device, and method for filling at least one balloon |
US9776744B2 (en) | 2015-06-19 | 2017-10-03 | Telebrands Corp. | Container sealing device |
USD793483S1 (en) | 2015-11-20 | 2017-08-01 | Telebrands Corp. | Device for filling multiple water balloons |
USD793484S1 (en) | 2015-11-20 | 2017-08-01 | Telebrands Corp. | Device for filling multiple water balloons |
USD793485S1 (en) | 2015-11-20 | 2017-08-01 | Telebrands Corp. | Device for filling multiple water balloons |
US10475930B2 (en) * | 2016-08-17 | 2019-11-12 | Samsung Electronics Co., Ltd. | Method of forming crystalline oxides on III-V materials |
Citations (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4490284A (en) * | 1982-09-29 | 1984-12-25 | Dragoco Gerberding & Co. Gmbh | 1,1-Di(C1 -C6 -alkyl)-2-phenyl-ethane derivatives as perfuming ingredients |
US4905163A (en) * | 1988-10-03 | 1990-02-27 | Minnesota Mining & Manufacturing Company | Intelligent optical navigator dynamic information presentation and navigation system |
US5089952A (en) * | 1988-10-07 | 1992-02-18 | International Business Machines Corporation | Method for allowing weak searchers to access pointer-connected data structures without locking |
US5121493A (en) * | 1990-01-19 | 1992-06-09 | Amalgamated Software Of North America, Inc. | Data sorting method |
US5442784A (en) * | 1990-03-16 | 1995-08-15 | Dimensional Insight, Inc. | Data management system for building a database with multi-dimensional search tree nodes |
US5604772A (en) * | 1993-09-13 | 1997-02-18 | U.S. Philips Corporation | Transmission system and modem utilizing coded modulation |
US5613110A (en) * | 1995-01-05 | 1997-03-18 | International Business Machines Corporation | Indexing method and apparatus facilitating a binary search of digital data |
US5696962A (en) * | 1993-06-24 | 1997-12-09 | Xerox Corporation | Method for computerized information retrieval using shallow linguistic analysis |
US5701467A (en) * | 1993-07-07 | 1997-12-23 | European Computer-Industry Research Centre Gmbh | Computer data storage management system and methods of indexing a dataspace and searching a computer memory |
US5778367A (en) * | 1995-12-14 | 1998-07-07 | Network Engineering Software, Inc. | Automated on-line information service and directory, particularly for the world wide web |
US5781773A (en) * | 1995-05-10 | 1998-07-14 | Minnesota Mining And Manufacturing Company | Method for transforming and storing data for search and display and a searching system utilized therewith |
US5873080A (en) * | 1996-09-20 | 1999-02-16 | International Business Machines Corporation | Using multiple search engines to search multimedia data |
US5987446A (en) * | 1996-11-12 | 1999-11-16 | U.S. West, Inc. | Searching large collections of text using multiple search engines concurrently |
US6009422A (en) * | 1997-11-26 | 1999-12-28 | International Business Machines Corporation | System and method for query translation/semantic translation using generalized query language |
US6067552A (en) * | 1995-08-21 | 2000-05-23 | Cnet, Inc. | User interface system and method for browsing a hypertext database |
US6072490A (en) * | 1997-08-15 | 2000-06-06 | International Business Machines Corporation | Multi-node user interface component and method thereof for use in accessing a plurality of linked records |
US6078866A (en) * | 1998-09-14 | 2000-06-20 | Searchup, Inc. | Internet site searching and listing service based on monetary ranking of site listings |
US6078914A (en) * | 1996-12-09 | 2000-06-20 | Open Text Corporation | Natural language meta-search system and method |
US6094652A (en) * | 1998-06-10 | 2000-07-25 | Oracle Corporation | Hierarchical query feedback in an information retrieval system |
US6097294A (en) * | 1999-08-18 | 2000-08-01 | Hilton; David D. | Infant protective safety support with indicating means |
US6098066A (en) * | 1997-06-13 | 2000-08-01 | Sun Microsystems, Inc. | Method and apparatus for searching for documents stored within a document directory hierarchy |
US6133938A (en) * | 1998-03-14 | 2000-10-17 | Sony Corporation Of Japan | Descriptor mechanism for assuring indivisible execution of AV/C operations |
US6185550B1 (en) * | 1997-06-13 | 2001-02-06 | Sun Microsystems, Inc. | Method and apparatus for classifying documents within a class hierarchy creating term vector, term file and relevance ranking |
US6185569B1 (en) * | 1998-06-29 | 2001-02-06 | Microsoft Corporation | Linked data structure integrity verification system which verifies actual node information with expected node information stored in a table |
US6212518B1 (en) * | 1998-02-02 | 2001-04-03 | Fujitsu Limited | System and method for retrieval of data from related databases based upon database association model |
US6226641B1 (en) * | 1997-10-07 | 2001-05-01 | International Business Machines Corporation | Access control for groups of related data items |
US6253188B1 (en) * | 1996-09-20 | 2001-06-26 | Thomson Newspapers, Inc. | Automated interactive classified ad system for the internet |
US6255004B1 (en) * | 1996-11-27 | 2001-07-03 | The Furukawa Electric Co., Ltd. | III-V nitride semiconductor devices and process for the production thereof |
US6292796B1 (en) * | 1999-02-23 | 2001-09-18 | Clinical Focus, Inc. | Method and apparatus for improving access to literature |
US6292894B1 (en) * | 1997-09-08 | 2001-09-18 | Science Applications International Corporation | System, method, and medium for retrieving, organizing, and utilizing networked data |
US20010025304A1 (en) * | 2000-03-09 | 2001-09-27 | The Web Acess, Inc. | Method and apparatus for applying a parametric search methodology to a directory tree database format |
US20010044837A1 (en) * | 2000-03-30 | 2001-11-22 | Iqbal Talib | Methods and systems for searching an information directory |
US6327588B1 (en) * | 1994-10-14 | 2001-12-04 | Saqqara Systems, Inc. | Method and system for executing a guided parametric search |
US20010056460A1 (en) * | 2000-04-24 | 2001-12-27 | Ranjit Sahota | Method and system for transforming content for execution on multiple platforms |
US6421675B1 (en) * | 1998-03-16 | 2002-07-16 | S. L. I. Systems, Inc. | Search engine |
US6421661B1 (en) * | 1998-06-15 | 2002-07-16 | International Business Machines Corporation | Hierarchical query syntax for inquiring and selecting among database objects |
US6424966B1 (en) * | 1998-06-30 | 2002-07-23 | Microsoft Corporation | Synchronizing crawler with notification source |
US6444592B1 (en) * | 2000-06-20 | 2002-09-03 | International Business Machines Corporation | Interfacial oxidation process for high-k gate dielectric process integration |
US6484165B1 (en) * | 1998-04-10 | 2002-11-19 | Requisite Technology, Inc. | Method and system for database manipulation |
US6499033B1 (en) * | 1998-05-09 | 2002-12-24 | Isc, Inc. | Database method and apparatus using hierarchical bit vector index structure |
US6513032B1 (en) * | 1998-10-29 | 2003-01-28 | Alta Vista Company | Search and navigation system and method using category intersection pre-computation |
US6516337B1 (en) * | 1999-10-14 | 2003-02-04 | Arcessa, Inc. | Sending to a central indexing site meta data or signatures from objects on a computer network |
US20030027392A1 (en) * | 2001-08-01 | 2003-02-06 | International Business Machines Corporation | Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics |
US6523021B1 (en) * | 2000-07-31 | 2003-02-18 | Microsoft Corporation | Business directory search engine |
US6523961B2 (en) * | 2000-08-30 | 2003-02-25 | Reflectivity, Inc. | Projection system and mirror elements for improved contrast ratio in spatial light modulators |
US6532094B2 (en) * | 2000-05-31 | 2003-03-11 | Ricoh Company, Ltd. | Optical scanning lens, optical scanning device and image forming apparatus |
US6542593B1 (en) * | 1999-06-02 | 2003-04-01 | Accenture Llp | Rules database server in a hybrid communication system architecture |
US20030091083A1 (en) * | 2001-11-13 | 2003-05-15 | Applied Optoelectronics, Ins. | VCSEL with ion-implanted current-confinement structure |
US6567800B1 (en) * | 1998-10-01 | 2003-05-20 | At&T Corp. | System and method for searching information stored on a network |
US6573197B2 (en) * | 2001-04-12 | 2003-06-03 | International Business Machines Corporation | Thermally stable poly-Si/high dielectric constant material interfaces |
US6631367B2 (en) * | 2000-12-28 | 2003-10-07 | Intel Corporation | Method and apparatus to search for information |
US6664186B1 (en) * | 2000-09-29 | 2003-12-16 | International Business Machines Corporation | Method of film deposition, and fabrication of structures |
US6704729B1 (en) * | 2000-05-19 | 2004-03-09 | Microsoft Corporation | Retrieval of relevant information categories |
US6727134B1 (en) * | 2002-11-05 | 2004-04-27 | Taiwan Semiconductor Manufacturing Company | Method of forming a nitride gate dielectric layer for advanced CMOS devices |
US20040099886A1 (en) * | 2002-11-26 | 2004-05-27 | Howard Rhodes | CMOS imager pixel designs |
US6826597B1 (en) * | 1999-03-17 | 2004-11-30 | Oracle International Corporation | Providing clients with services that retrieve data from data sources that do not necessarily support the format required by the clients |
US20050224800A1 (en) * | 2004-03-31 | 2005-10-13 | Nick Lindert | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US20060001071A1 (en) * | 2004-06-30 | 2006-01-05 | Brask Justin K | Forming high-k dielectric layers on smooth substrates |
US20060022283A1 (en) * | 2004-07-30 | 2006-02-02 | Thomas Shawn G | Interfacial layer for use with high k dielectric materials |
US20060151787A1 (en) * | 2005-01-12 | 2006-07-13 | International Business Machines Corporation | LOW CONCENTRATION SiGe BUFFER DURING STRAINED Si GROWTH OF SSGOI MATERIAL FOR DOPANT DIFFUSION CONTROL AND DEFECT REDUCTION |
US20060189110A1 (en) * | 2005-02-24 | 2006-08-24 | International Business Machines Corporation | Body capacitor for SOI memory description |
US20070148838A1 (en) * | 2005-12-28 | 2007-06-28 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US20070152276A1 (en) * | 2005-12-30 | 2007-07-05 | International Business Machines Corporation | High performance CMOS circuits, and methods for fabricating the same |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100486609B1 (en) * | 2002-12-30 | 2005-05-03 | 주식회사 하이닉스반도체 | Method for fabricating pMOSFET having Ultra Shallow Super-Steep-Retrograde epi-channel formed by Multiple channel doping |
-
2006
- 2006-01-06 US US11/327,675 patent/US20070161214A1/en not_active Abandoned
-
2012
- 2012-09-09 US US13/607,741 patent/US9805949B2/en active Active
Patent Citations (72)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4490284A (en) * | 1982-09-29 | 1984-12-25 | Dragoco Gerberding & Co. Gmbh | 1,1-Di(C1 -C6 -alkyl)-2-phenyl-ethane derivatives as perfuming ingredients |
US4905163A (en) * | 1988-10-03 | 1990-02-27 | Minnesota Mining & Manufacturing Company | Intelligent optical navigator dynamic information presentation and navigation system |
US5089952A (en) * | 1988-10-07 | 1992-02-18 | International Business Machines Corporation | Method for allowing weak searchers to access pointer-connected data structures without locking |
US5121493A (en) * | 1990-01-19 | 1992-06-09 | Amalgamated Software Of North America, Inc. | Data sorting method |
US5442784A (en) * | 1990-03-16 | 1995-08-15 | Dimensional Insight, Inc. | Data management system for building a database with multi-dimensional search tree nodes |
US5696962A (en) * | 1993-06-24 | 1997-12-09 | Xerox Corporation | Method for computerized information retrieval using shallow linguistic analysis |
US5701467A (en) * | 1993-07-07 | 1997-12-23 | European Computer-Industry Research Centre Gmbh | Computer data storage management system and methods of indexing a dataspace and searching a computer memory |
US5604772A (en) * | 1993-09-13 | 1997-02-18 | U.S. Philips Corporation | Transmission system and modem utilizing coded modulation |
US6327588B1 (en) * | 1994-10-14 | 2001-12-04 | Saqqara Systems, Inc. | Method and system for executing a guided parametric search |
US5613110A (en) * | 1995-01-05 | 1997-03-18 | International Business Machines Corporation | Indexing method and apparatus facilitating a binary search of digital data |
US5781773A (en) * | 1995-05-10 | 1998-07-14 | Minnesota Mining And Manufacturing Company | Method for transforming and storing data for search and display and a searching system utilized therewith |
US6067552A (en) * | 1995-08-21 | 2000-05-23 | Cnet, Inc. | User interface system and method for browsing a hypertext database |
US5778367A (en) * | 1995-12-14 | 1998-07-07 | Network Engineering Software, Inc. | Automated on-line information service and directory, particularly for the world wide web |
US6253188B1 (en) * | 1996-09-20 | 2001-06-26 | Thomson Newspapers, Inc. | Automated interactive classified ad system for the internet |
US5873080A (en) * | 1996-09-20 | 1999-02-16 | International Business Machines Corporation | Using multiple search engines to search multimedia data |
US5987446A (en) * | 1996-11-12 | 1999-11-16 | U.S. West, Inc. | Searching large collections of text using multiple search engines concurrently |
US6255004B1 (en) * | 1996-11-27 | 2001-07-03 | The Furukawa Electric Co., Ltd. | III-V nitride semiconductor devices and process for the production thereof |
US6078914A (en) * | 1996-12-09 | 2000-06-20 | Open Text Corporation | Natural language meta-search system and method |
US6098066A (en) * | 1997-06-13 | 2000-08-01 | Sun Microsystems, Inc. | Method and apparatus for searching for documents stored within a document directory hierarchy |
US6185550B1 (en) * | 1997-06-13 | 2001-02-06 | Sun Microsystems, Inc. | Method and apparatus for classifying documents within a class hierarchy creating term vector, term file and relevance ranking |
US6072490A (en) * | 1997-08-15 | 2000-06-06 | International Business Machines Corporation | Multi-node user interface component and method thereof for use in accessing a plurality of linked records |
US6292894B1 (en) * | 1997-09-08 | 2001-09-18 | Science Applications International Corporation | System, method, and medium for retrieving, organizing, and utilizing networked data |
US6226641B1 (en) * | 1997-10-07 | 2001-05-01 | International Business Machines Corporation | Access control for groups of related data items |
US6009422A (en) * | 1997-11-26 | 1999-12-28 | International Business Machines Corporation | System and method for query translation/semantic translation using generalized query language |
US6212518B1 (en) * | 1998-02-02 | 2001-04-03 | Fujitsu Limited | System and method for retrieval of data from related databases based upon database association model |
US6133938A (en) * | 1998-03-14 | 2000-10-17 | Sony Corporation Of Japan | Descriptor mechanism for assuring indivisible execution of AV/C operations |
US6421675B1 (en) * | 1998-03-16 | 2002-07-16 | S. L. I. Systems, Inc. | Search engine |
US6484165B1 (en) * | 1998-04-10 | 2002-11-19 | Requisite Technology, Inc. | Method and system for database manipulation |
US6499033B1 (en) * | 1998-05-09 | 2002-12-24 | Isc, Inc. | Database method and apparatus using hierarchical bit vector index structure |
US6094652A (en) * | 1998-06-10 | 2000-07-25 | Oracle Corporation | Hierarchical query feedback in an information retrieval system |
US6421661B1 (en) * | 1998-06-15 | 2002-07-16 | International Business Machines Corporation | Hierarchical query syntax for inquiring and selecting among database objects |
US6185569B1 (en) * | 1998-06-29 | 2001-02-06 | Microsoft Corporation | Linked data structure integrity verification system which verifies actual node information with expected node information stored in a table |
US6424966B1 (en) * | 1998-06-30 | 2002-07-23 | Microsoft Corporation | Synchronizing crawler with notification source |
US6078866A (en) * | 1998-09-14 | 2000-06-20 | Searchup, Inc. | Internet site searching and listing service based on monetary ranking of site listings |
US6567800B1 (en) * | 1998-10-01 | 2003-05-20 | At&T Corp. | System and method for searching information stored on a network |
US6513032B1 (en) * | 1998-10-29 | 2003-01-28 | Alta Vista Company | Search and navigation system and method using category intersection pre-computation |
US6292796B1 (en) * | 1999-02-23 | 2001-09-18 | Clinical Focus, Inc. | Method and apparatus for improving access to literature |
US6826597B1 (en) * | 1999-03-17 | 2004-11-30 | Oracle International Corporation | Providing clients with services that retrieve data from data sources that do not necessarily support the format required by the clients |
US6542593B1 (en) * | 1999-06-02 | 2003-04-01 | Accenture Llp | Rules database server in a hybrid communication system architecture |
US6097294A (en) * | 1999-08-18 | 2000-08-01 | Hilton; David D. | Infant protective safety support with indicating means |
US6516337B1 (en) * | 1999-10-14 | 2003-02-04 | Arcessa, Inc. | Sending to a central indexing site meta data or signatures from objects on a computer network |
US20020023085A1 (en) * | 2000-03-09 | 2002-02-21 | The Web Access, Inc. | Method and apparatus for performing a research task by interchangeably utilizing a multitude of search methodologies |
US20020016794A1 (en) * | 2000-03-09 | 2002-02-07 | The Web Access, Inc. | Method and apparatus for accessing data within an electronic system by an external system |
US7085766B2 (en) * | 2000-03-09 | 2006-08-01 | The Web Access, Inc. | Method and apparatus for organizing data by overlaying a searchable database with a directory tree structure |
US20020016793A1 (en) * | 2000-03-09 | 2002-02-07 | The Web Access, Inc. | Method and apparatus for notifying a user of new data entered into an electronic system |
US20020004793A1 (en) * | 2000-03-09 | 2002-01-10 | The Web Access, Inc. | Method and apparatus for organizing data by overlaying a searchable database with a directory tree structure |
US20020065812A1 (en) * | 2000-03-09 | 2002-05-30 | The Web Access, Inc. | Method and apparatus for accessing information within an electronic system |
US20020032672A1 (en) * | 2000-03-09 | 2002-03-14 | The Web Access, Inc | Method and apparatus for formatting information within a directory tree structure into an encylopedia-like entry |
US7054875B2 (en) * | 2000-03-09 | 2006-05-30 | The Web Access, Inc. | Method and apparatus for notifying a user of new data entered into an electronic system |
US20020091686A1 (en) * | 2000-03-09 | 2002-07-11 | The Web Access, Inc. | Method and apparatus for performing a research task by interchangeably utilizing a multitude of search methodologies |
US20010025304A1 (en) * | 2000-03-09 | 2001-09-27 | The Web Acess, Inc. | Method and apparatus for applying a parametric search methodology to a directory tree database format |
US20010044837A1 (en) * | 2000-03-30 | 2001-11-22 | Iqbal Talib | Methods and systems for searching an information directory |
US20010056460A1 (en) * | 2000-04-24 | 2001-12-27 | Ranjit Sahota | Method and system for transforming content for execution on multiple platforms |
US6704729B1 (en) * | 2000-05-19 | 2004-03-09 | Microsoft Corporation | Retrieval of relevant information categories |
US6532094B2 (en) * | 2000-05-31 | 2003-03-11 | Ricoh Company, Ltd. | Optical scanning lens, optical scanning device and image forming apparatus |
US6444592B1 (en) * | 2000-06-20 | 2002-09-03 | International Business Machines Corporation | Interfacial oxidation process for high-k gate dielectric process integration |
US6523021B1 (en) * | 2000-07-31 | 2003-02-18 | Microsoft Corporation | Business directory search engine |
US6523961B2 (en) * | 2000-08-30 | 2003-02-25 | Reflectivity, Inc. | Projection system and mirror elements for improved contrast ratio in spatial light modulators |
US6664186B1 (en) * | 2000-09-29 | 2003-12-16 | International Business Machines Corporation | Method of film deposition, and fabrication of structures |
US6631367B2 (en) * | 2000-12-28 | 2003-10-07 | Intel Corporation | Method and apparatus to search for information |
US6573197B2 (en) * | 2001-04-12 | 2003-06-03 | International Business Machines Corporation | Thermally stable poly-Si/high dielectric constant material interfaces |
US20030027392A1 (en) * | 2001-08-01 | 2003-02-06 | International Business Machines Corporation | Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics |
US20030091083A1 (en) * | 2001-11-13 | 2003-05-15 | Applied Optoelectronics, Ins. | VCSEL with ion-implanted current-confinement structure |
US6727134B1 (en) * | 2002-11-05 | 2004-04-27 | Taiwan Semiconductor Manufacturing Company | Method of forming a nitride gate dielectric layer for advanced CMOS devices |
US20040099886A1 (en) * | 2002-11-26 | 2004-05-27 | Howard Rhodes | CMOS imager pixel designs |
US20050224800A1 (en) * | 2004-03-31 | 2005-10-13 | Nick Lindert | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US20060001071A1 (en) * | 2004-06-30 | 2006-01-05 | Brask Justin K | Forming high-k dielectric layers on smooth substrates |
US20060022283A1 (en) * | 2004-07-30 | 2006-02-02 | Thomas Shawn G | Interfacial layer for use with high k dielectric materials |
US20060151787A1 (en) * | 2005-01-12 | 2006-07-13 | International Business Machines Corporation | LOW CONCENTRATION SiGe BUFFER DURING STRAINED Si GROWTH OF SSGOI MATERIAL FOR DOPANT DIFFUSION CONTROL AND DEFECT REDUCTION |
US20060189110A1 (en) * | 2005-02-24 | 2006-08-24 | International Business Machines Corporation | Body capacitor for SOI memory description |
US20070148838A1 (en) * | 2005-12-28 | 2007-06-28 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US20070152276A1 (en) * | 2005-12-30 | 2007-07-05 | International Business Machines Corporation | High performance CMOS circuits, and methods for fabricating the same |
Cited By (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11289581B2 (en) | 2007-02-15 | 2022-03-29 | Sony Corporation | Method for manufacturing insulated gate field effect transistor |
US10505008B2 (en) * | 2007-02-15 | 2019-12-10 | Sony Corporation | Method for manufacturing insulated gate field effect transistor |
US20180269300A1 (en) * | 2007-02-15 | 2018-09-20 | Sony Corporation | Method for manufacturing insulated gate field effect transistor |
US20080242012A1 (en) * | 2007-03-28 | 2008-10-02 | Sangwoo Pae | High quality silicon oxynitride transition layer for high-k/metal gate transistors |
US9711373B2 (en) * | 2008-09-22 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a gate dielectric for high-k metal gate devices |
US20100075507A1 (en) * | 2008-09-22 | 2010-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Fabricating a Gate Dielectric for High-K Metal Gate Devices |
US20100123205A1 (en) * | 2008-11-17 | 2010-05-20 | International Business Machines Corporation | Method to prevent surface decomposition of iii-v compound semiconductors |
US8273649B2 (en) * | 2008-11-17 | 2012-09-25 | International Business Machines Corporation | Method to prevent surface decomposition of III-V compound semiconductors |
US8415772B2 (en) | 2008-11-17 | 2013-04-09 | International Business Machines Corporation | Method to prevent surface decomposition of III-V compound semiconductors |
US8431476B2 (en) | 2008-11-17 | 2013-04-30 | International Business Machines Corporation | Method to prevent surface decomposition of III-V compound semiconductors |
US8524614B2 (en) * | 2010-11-29 | 2013-09-03 | International Business Machines Corporation | III-V compound semiconductor material passivation with crystalline interlayer |
US20120132913A1 (en) * | 2010-11-29 | 2012-05-31 | International Business Machines Corporation | III-V Compound Semiconductor Material Passivation With Crystalline Interlayer |
US8809860B2 (en) | 2010-11-29 | 2014-08-19 | International Business Machines Corporation | III-V compound semiconductor material passivation with crystalline interlayer |
US9337039B2 (en) * | 2013-07-03 | 2016-05-10 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for electrical activation of dopant species in a GaN film |
US20150011080A1 (en) * | 2013-07-03 | 2015-01-08 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR ELECTRICAL ACTIVATION OF DOPANT SPECIES IN A GaN FILM |
TWI642108B (en) * | 2014-01-29 | 2018-11-21 | 日商瑞薩電子股份有限公司 | Method for manufacturing semiconductor device |
US9646824B2 (en) * | 2014-01-29 | 2017-05-09 | Renesas Electronics Corporation | Method for manufacturing semiconductor device |
US20150214047A1 (en) * | 2014-01-29 | 2015-07-30 | Renesas Electronics Corporation | Method for Manufacturing Semiconductor Device |
US10199481B2 (en) | 2014-01-29 | 2019-02-05 | Renesas Electronics Corporation | Method for manufacturing semiconductor device |
US20170229303A1 (en) * | 2014-11-13 | 2017-08-10 | Applied Materials, Inc. | Method for removing native oxide and residue from a iii-v group containing surface |
US10438796B2 (en) * | 2014-11-13 | 2019-10-08 | Applied Materials, Inc. | Method for removing native oxide and residue from a III-V group containing surface |
US20170062522A1 (en) * | 2015-08-27 | 2017-03-02 | Intermolecular, Inc. | Combining Materials in Different Components of Selector Elements of Integrated Circuits |
US9953839B2 (en) * | 2016-08-18 | 2018-04-24 | International Business Machines Corporation | Gate-stack structure with a diffusion barrier material |
US20180053656A1 (en) * | 2016-08-18 | 2018-02-22 | International Business Machines Corporation | Gate-Stack Structure with a Diffusion Barrier Material |
US10720337B2 (en) * | 2018-07-20 | 2020-07-21 | Asm Ip Holding B.V. | Pre-cleaning for etching of dielectric materials |
US10720334B2 (en) | 2018-07-20 | 2020-07-21 | Asm Ip Holding B.V. | Selective cyclic dry etching process of dielectric materials using plasma modification |
TWI780345B (en) * | 2018-07-20 | 2022-10-11 | 荷蘭商Asm Ip 控股公司 | Selective cyclic dry etching process of dielectric materials using plasma modification |
CN113964178A (en) * | 2020-07-21 | 2022-01-21 | 格芯(美国)集成电路科技有限公司 | III-V compound semiconductor layer stack with electrical isolation provided by trap rich layer |
Also Published As
Publication number | Publication date |
---|---|
US9805949B2 (en) | 2017-10-31 |
US20120326212A1 (en) | 2012-12-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9805949B2 (en) | High κ gate stack on III-V compound semiconductors | |
US7446380B2 (en) | Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS | |
US7820552B2 (en) | Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack | |
US7872317B2 (en) | Dual metal gate self-aligned integration | |
US7955917B2 (en) | Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate methods | |
Wu et al. | High-κ dielectrics and advanced channel concepts for Si MOSFET | |
US8575655B2 (en) | Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering | |
KR101166437B1 (en) | Semiconductor Field Effect Transistors and Fabrication Thereof | |
US7521376B2 (en) | Method of forming a semiconductor structure using a non-oxygen chalcogen passivation treatment | |
US20050258491A1 (en) | Threshold and flatband voltage stabilization layer for field effect transistors with high permittivity gate oxides | |
US7303996B2 (en) | High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics | |
US20060102968A1 (en) | Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide | |
US20080164581A1 (en) | Electronic device and process for manufacturing the same | |
US6350311B1 (en) | Method for forming an epitaxial silicon-germanium layer | |
US20090294876A1 (en) | Method for deposition of an ultra-thin electropositive metal-containing cap layer | |
US20140035001A1 (en) | Compound semiconductor structure | |
EP1880409B1 (en) | Method of fabricating a mos device with a high-k or sion gate dielectric | |
US7880241B2 (en) | Low-temperature electrically activated gate electrode and method of fabricating same | |
Shimizu et al. | Electrical properties of ruthenium/metalorganic chemical vapor deposited La-oxide/Si field effect transistors | |
US8809860B2 (en) | III-V compound semiconductor material passivation with crystalline interlayer | |
Young et al. | Perfecting high-κ/Ge and/InGaAs interfaces–push for ultimate CMOS and emerging cryogenic electronic devices | |
Ohmi et al. | Ultrathin HfO x N y gate insulator formation by electron cyclotron resonance Ar/N 2 plasma nitridation of HfO 2 thin films | |
Kambhampati et al. | In-Situ Deposition of High-k Gate Stack on InGaAs and GaAs for Metal-Oxide-Semiconductor Devices with Low Equivalent Oxide Thickness | |
Donnelly¹ et al. | GERMANIUM-ON-SI MOSFETS WITH HFO₂ GATE DIELECTRIC | |
Kambhampati | High-k gate stack on compound semiconductor channel materials for low power, high performance digital logic applications |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FOMPEYRINE, JEAN;KIEWRA, EDWARD W.;KOESTER, STEVEN J.;AND OTHERS;REEL/FRAME:018251/0711;SIGNING DATES FROM 20060406 TO 20060518 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |