US20070145541A1 - Stack type surface acoustic wave package, and method for manufacturing the same - Google Patents
Stack type surface acoustic wave package, and method for manufacturing the same Download PDFInfo
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- US20070145541A1 US20070145541A1 US11/682,583 US68258307A US2007145541A1 US 20070145541 A1 US20070145541 A1 US 20070145541A1 US 68258307 A US68258307 A US 68258307A US 2007145541 A1 US2007145541 A1 US 2007145541A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
- H03H9/1085—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a non-uniform sealing mass covering the non-active sides of the BAW device
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
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- H—ELECTRICITY
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- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/058—Holders; Supports for surface acoustic wave devices
- H03H9/059—Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps
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- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
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- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
- H03H9/1078—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a foil covering the non-active sides of the SAW device
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- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/64—Filters using surface acoustic waves
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- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Definitions
- the step a) comprises printing a conductive pattern on upper ends of the via-holes to be electrically connected to the input and output electrodes, and another conductive pattern on lower ends of the via-holes to be electrically connected to a main board.
- the step c) comprises laminating the resin film formed of a thermosetting material by thermal compression.
- the separating grooves are formed to an extent that the upper surface of the lower wafer is exposed to the outside.
- a plurality of second bare chips 120 are continuously disposed, and separated a predetermined distance from each other on the lower wafer W 1 to form a single chip when being cut.
- a continuous loop-shaped wall is formed to form a shielding wall surrounding the input, output and IDT electrodes 121 , 122 and 123 formed on the upper surface of the lower wafer W 1 .
Abstract
Disclosed herein is a stack type surface acoustic wave package. The surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips. The surface acoustic wave package can prevent deformation due to thermal impact from the outside during a packaging process, enhancing reliability of the product, minimizing the size of the product, and reducing manufacturing costs by reducing the number of components and material costs.
Description
- This application is a divisional of U.S. application Ser. No. 11/217,465, filed Sep. 2, 2005, which claims priority from, Korean Application No. 2005-38093, filed May 6, 2005, the disclosures of which are hereby incorporated by reference herein in their entirety.
- 1. Field of the Invention
- The present invention relates to a stack type surface acoustic wave package, and a method for manufacturing the same. More particularly, the present invention relates to a stack type surface acoustic wave package, which is formed by packaging two piezoelectric single crystal bare chips formed of the same material to face each other through a chip-scale packaging process and a wafer level packaging process, thereby allowing integration of two filters having different frequency bands and high resistance to thermal impact into a single component while reducing a product size, and a method for manufacturing the same.
- 2. Description of the Related Art
- As communication technology has advanced remarkably in recent years, miniaturization, high performance, and multifunctionality are required for mobile communication products. In order to achieve theses requirements, various components, for example, a filter, a duplexer, and the like, used for the mobile communication products are also required to be miniaturized and multi-functionalized.
- As for one example of these components, a surface acoustic wave device comprises a piezoelectric board 1 which is a piezoelectric single crystal bare chip, a pair of Inter-Digital Transducer (IDT)
electrodes 2 facing each other in an interdigitated pattern on the piezoelectric board 1, and input andoutput electrodes IDT electrodes 2, respectively. - When an electric signal is applied through the
input electrode 3, the piezoelectric effect causes piezoelectric distortion to occur corresponding to an overlap length between theIDT electrodes 2, and the piezoelectric distortion generates surface acoustic waves, which are transmitted to the piezoelectric board 1. Then, the surface acoustic waves are converted into an electric signal, and output through theoutput electrode 4. At this time, only the electric signal having a predetermined frequency band determined by various factors, such as distance between theIDT electrodes 2, width or length of theIDT electrodes 2, is filtered out. - As such, the surface acoustic wave device has characteristics determined by the distance between the
IDT electrodes 2, the width or length of theIDT electrodes 2 formed on the piezoelectric board 1 of the surface acoustic wave device. If theIDT electrodes 2 are damaged or have minute foreign substances such as dust attached thereto, the characteristics of the device will be changed. Thus, various package structures are required to protect the electrodes of the surface acoustic wave device from the external environment. - A fundamental structure of a conventional surface acoustic wave package comprises a ceramic wiring board, devices mounted on the board, and a sealing member packaging the devices and the board, as shown in
FIGS. 2 a, 2 b and 2 c. - In
FIG. 2 a, a surface-mount type surfaceacoustic wave package 10 comprises awiring board 11 formed of a plurality of staked ceramic layers, adevice 15 having input, output andIDT electrodes lid 19 mounted on thewiring board 11 to seal thedevice 15 in a cavity formed when the plurality of ceramic layers are stacked to form thewiring board 11, in which thedevice 15 is connected in a wire-bonding manner to via-holes 12 passing through thewiring board 11 via a plurality ofmetal wires 13 such that theelectrodes lid 19 in the cavity. - In
FIG. 2 b, a flip-chip bonding type surfaceacoustic wave package 20 comprises awiring board 21, adevice 25, and alid 29, in which thedevice 25 is connected in a flip chip-bonding manner to via-holes 22 passing through thewiring board 21 via a plurality ofbump balls 23 such thatelectrodes board 21 in a cavity, and in which thedevice 25 is sealed in the cavity on thewring board 21 by thelid 29. - In
FIG. 2 c, a chip-scale packaging type surfaceacoustic wave package 30 comprises awiring board 31, a device 35, and ametal layer 39, in which the device 35 is connected in a flip chip-bonding manner to via-holes 32 passing through thewiring board 31 via a plurality ofbump balls 33 such thatelectrodes wiring board 31, and in which the device 35 mounted above thewiring board 31 is sealed by a laminatedfilm 38 and themetal layer 39 applied to an upper surface of thefilm 38. - The
conventional packages devices wiring boards metal lids boards conventional packages - Meanwhile, in
FIG. 7 , a surfaceacoustic wave package 40 can filter out different frequency bands. The surfaceacoustic wave package 40 is formed by mounting twodevices holes 42 passing therethrough viabump balls 43 in which IDT electrodes of thedevices film 48 and ametal layer 49. - However, since the conventional surface
acoustic wave package 40 has the twodevices devices single wiring board 41, there is a problem in that the overall size of the product is remarkably increased. - Additionally, since the thermal expansion coefficient of the ceramic wiring board is about 7 mm/m2K and the thermal expansion coefficient of the piezoelectric single crystal bare chip is about 15 mm/m2K, there is a difference in thermal expansion coefficient between the materials. Thus, when welding the metallic lid or when wire-bonding or flip-chip bonding the input and output electrodes of the device to the via-holes of the wiring board, thermal impact applied from the outside frequently causes damage, such as separation of the bump ball or a bonding surface between the device and the board.
- The present invention has been made to solve the above problems, and it is an object of the present invention to provide a stack type surface acoustic wave package, which can prevent deformation due to thermal impact from the outside during a packaging process to enhance reliability of a product, and a method for manufacturing the same.
- It is another object of the present invention to provide a stack type surface acoustic wave package, which can minimize the product according to a tendency of miniaturization of the product, and can reduce the number of components and material costs to reduce manufacturing costs, and a method for manufacturing the same.
- In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a stack type surface acoustic wave package, comprising: a first bare chip having a plurality of electrodes formed thereon; a second bare chip having a plurality of electrodes and via-holes formed thereon; a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip; and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips.
- Preferably, the first and second bare chips are piezoelectric single crystal elements, and the plurality of electrodes of the first and second bare chips comprise an input electrode, an output electrode, and IDT electrodes formed on upper surfaces of the piezoelectric elements facing each other, the IDT electrodes formed on the upper surface of the first bare chip being different in length, width, and gap between the IDT electrodes from those of the IDT electrodes formed on the upper surface of the second bare chip.
- Preferably, the connecting portion is a metallic bonding agent interposed between a conductive pad laid on the input and output electrodes of the first bare chip and a conductive pattern electrically connected to the via-holes of the second bare chip.
- Preferably, the connecting portion is a metallic bonding agent interposed between a conductive pad laid on the input and output electrodes of the first bare chip and another conductive pad laid on the via-holes of the second bare chip.
- More preferably, the metallic bonding agent comprises an Au-based stud bump used for supersonic bonding.
- More preferably, the metallic bonding agent comprises an AuSn-based solder bump used for thermal bonding.
- Preferably, the sealing member comprises a resin film laminated from an upper surface of the first bare chip to surround side and upper surfaces of the second bare chip, and a metal layer coated to surround the upper surface of the second bare chip, and side and upper surfaces of the resin film.
- Preferably, the sealing member comprises a continuous metal dam interposed between a lower surface of the first bare chip and an upper surface of the second bare chip, and a metal layer extending from the metal dam to surround side and upper surfaces of the metal dam.
- Preferably, the sealing member is electrically connected to an inner ground terminal to prevent electromagnetic wave from being induced into the package from the outside.
- In accordance with another aspect of the present invention, a method for manufacturing a stack type surface acoustic wave package is provided, comprising the steps of: a) preparing a lower wafer having input, output and IDT electrodes formed on an upper surface thereof, and a plurality of via-holes passing through the lower wafer; b) bonding first bare chips, each having input, output and IDT electrodes formed thereon, to the lower wafer via a metallic bonding agent; c) laminating a resin film on the lower wafer to cover side and upper surfaces of the first bare chips; d) removing the resin film to a predetermined depth along a boundary between the first bare chips to form separating grooves therebetween; e) plating a metal layer of a predetermined thickness on the resin film and the separating grooves; and f) cutting a central portion between the separating grooves plated with the metal layer.
- Preferably, the step a) comprises printing a conductive pattern on upper ends of the via-holes to be electrically connected to the input and output electrodes, and another conductive pattern on lower ends of the via-holes to be electrically connected to a main board.
- Preferably, the step b) comprises flip-chip bonding of the first bare chips to the lower wafer via the metallic bonding agent such that the input and output electrodes, and the IDT electrodes of each first bare chip face the input and output electrodes, and the IDT electrodes of the lower wafer, respectively.
- More preferably, flip-chip bonding of the first bare chips to the lower wafer comprises supersonic bonding by use of stud bumps interposed between a conductive pad laid on the input and output electrodes of each first bare chip and a conductive pattern of the input and output electrodes of the lower wafer.
- More preferably, flip-chip bonding of the first bare chips to the lower wafer comprises thermal bonding by use of AuSn-based solder bumps interposed between a conductive pad laid on the input and output electrodes of each first bare chip and a conductive pattern of the input and output electrodes of the lower wafer.
- Preferably, the step c) comprises laminating the resin film formed of a thermosetting material by thermal compression.
- More preferably, the thermosetting resin film is one selected from a polyimide based film and an epoxy-based film.
- Preferably, at the step d), the separating grooves are formed to an extent that the upper surface of the lower wafer is exposed to the outside.
- Preferably, at the step e), the metal layer is electrically connected to an inner ground terminal to prevent electromagnetic waves from being induced from the outside.
- Preferably, at the step e), the metal layer is plated by an electroplating process.
- In accordance with yet another aspect of the present invention, a method for manufacturing a stack type surface acoustic wave package is provided, comprising the steps of: a) preparing a lower wafer having input, output and IDT electrodes formed on an upper surface thereof, and a plurality of via-holes passing through the lower wafer; b) forming a metal dam to surround the input, output and IDT electrodes of the lower wafer; c) bonding an upper wafer having input, output and IDT electrodes formed thereon onto the lower wafer via a metallic bonding agent; d) forming separating grooves spaced a predetermined from each other and having a predetermined depth on the upper wafer; e) plating a metal layer of a predetermined thickness from the upper surface of the metal dam to cover the upper wafer; and f) dicing a central portion between the separating grooves plated with the metal layer.
- Preferably, the step a) comprises printing a conductive pattern on upper ends of the via-holes to be electrically connected to the input and output electrodes, and another conductive pattern on lower ends of the via-holes to be electrically connected to a main board.
- Preferably, the step b) comprises forming the metallic bonding agent while forming the metal dam on the lower wafer.
- Preferably, at the step b), the metal layer is electrically connected to an inner ground terminal to prevent electromagnetic waves from being induced from the outside after plating the metal layer.
- Preferably, the step c) comprises flip-chip bonding the upper wafer to the lower wafer via the metallic bonding agent such that the input and output electrodes, and the IDT electrodes of the upper wafer face the input and output electrodes, and the IDT electrodes of the lower wafer, respectively.
- More preferably, flip-chip bonding of the upper wafer to the lower wafer comprises supersonic bonding by use of stud bumps interposed between a conductive pad laid on the input and output electrodes of the upper wafer and another conductive pad laid on the input and output electrodes of the lower wafer.
- More preferably, flip-chip bonding of the upper wafer to the lower wafer comprises thermal bonding by use of AuSn-based solder bumps interposed between a conductive pad laid on the input and output electrodes of the upper wafer and another conductive pad laid on the input and output electrodes of the lower wafer.
- Preferably, at the step d), the separating grooves are formed to an extent that the upper surface of the lower wafer is exposed to the outside.
- Preferably, at the step e), the metal layer is plated by an electroplating process.
- The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings:
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FIG. 1 is a perspective view illustrating a surface acoustic wave device in a conventional surface acoustic wave package; -
FIGS. 2 a to 2 c are views illustrating conventional surface acoustic wave packages, in whichFIG. 2 a is a cross-sectional view illustrating a surface-mounting type surface acoustic wave package,FIG. 2 b is a cross-sectional view illustrating a flip-chip type surface acoustic wave package, andFIG. 2 c is a cross-sectional view illustrating a chip-scale package type surface acoustic wave package; -
FIG. 3 is a cross-sectional view illustrating a stack type surface acoustic wave package in accordance with a first embodiment of the present invention; -
FIG. 4 is a cross-sectional view illustrating a stack type surface acoustic wave package in accordance with a second embodiment of the present invention; -
FIGS. 5 a to 5 f are step diagrams illustrating a method for manufacturing the stack type surface acoustic wave package in accordance with the first embodiment of the present invention; -
FIGS. 6 a to 6 f are step diagrams illustrating a method for manufacturing the stack type surface acoustic wave package in accordance with the second embodiment of the present invention; -
FIG. 7 is a cross-sectional view for comparing the conventional surface acoustic wave package and a surface acoustic wave package in accordance with the present invention. - Preferred embodiments will now be described in detail with reference to the accompanying drawings.
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FIGS. 3 and 4 are cross-sectional views illustrating stack type surface acoustic wave packages in accordance with first and second embodiments of the present invention, respectively. As shown inFIGS. 3 and 4 , the surfaceacoustic wave package bare chips bare chips member 140 to protect these components from the external environment. - The first
bare chip 110 is a piezoelectric single crystal device which has aninput electrode 111, anoutput electrode 112, andIDT electrodes 113 formed on an upper surface thereof, and the secondbare chip 120 is another piezoelectric single crystal device which has aninput electrode 121, anoutput electrode 122, andother IDT electrodes 123 formed on an upper surface thereof facing the upper surface of the firstbare chip 110. - Here, the
IDT electrodes 113 of the firstbare chip 110, and theIDT electrodes 123 of the secondbare chip 120 are electrodes having different widths, lengths, and gap between the electrodes to filter out different frequency bands. - A plurality of via-
holes 134 are formed in the secondbare chip 120, and are printed at lower ends thereof with aconductive pattern 135 which will be electrically connected to a main board (not shown). - The connecting
portion 130 is interposed between the input andoutput electrodes bare chip 110 and the input andoutput electrodes bare chip 120 such that the first, second, andIDT electrodes bare chip 110 face the first, second, andIDT electrodes bare chip 120. The connectingportion 130 electrically connects these components to each other. - In
FIG. 3 , the connectingportion 130 can be ametallic bonding agent 131 interposed between aconductive pad 132 laid on the input andoutput electrodes bare chip 110 and aconductive pattern 133 electrically connected to upper ends of the via-holes 134 of the secondbare chip 120. - Alternatively, in
FIG. 4 , the connectingportion 130 can be ametallic bonding agent 131 a interposed between aconductive pad 132 a laid on the input and output electrodes 111 a and 113 a of the firstbare chip 110 and anotherconductive pad 133 a laid on upper ends of the via-holes 134 a of the secondbare chip 120. - Here, the
metallic bonding agent bare chips - The sealing
member 140 forms an air-tight space on an operating surface between the first and secondbare chips bare chips - In
FIG. 3 , the sealingmember 140 comprises athermosetting resin film 141 laminated from an upper surface of the firstbare chip 110 to surround side and upper surfaces of the secondbare chip 120, and ametal layer 142 coated to surround the upper surface of the secondbare chip 141, and side and upper surfaces of theresin film 141. - Alternatively, in
FIG. 4 , the sealingmember 140 comprises acontinuous metal dam 141 a laminated between a lower surface of the firstbare chip 110 and an upper surface of the secondbare chip 120 to surround the electrodes of the secondbare chip 120, and ametal layer 142 a extending from themetal dam 141 a to surround side and upper surfaces of themetal dam 141 a. - Preferably, the
metal layer 142 and themetal dam 141 a of the sealingmember 140 are connected to a ground terminal (not shown) to prevent electromagnetic waves from being induced into the package from the outside. -
FIGS. 5 a to 5 f are step diagrams illustrating a method for manufacturing a stack type surface acoustic wave package according to the first embodiment of the invention. - The surface
acoustic wave package 100 of the present invention is a chip-scale type package manufactured via steps a to f described below. - Step a: Preparing a lower wafer having input, output and IDT electrodes formed on an upper surface thereof, and a plurality of via-holes passing therethrough.
- As shown in
FIG. 5 a, patterns of input, output, andIDT electrodes - Then, a plurality of via-
holes 134 are formed through the lower wafer W1 having theelectrodes holes 134 are printed with aconductive pattern 133 electrically connected to the input andoutput electrodes conductive pattern 135 electrically connected to a main substrate. - As a result, a plurality of second
bare chips 120 are continuously disposed, and separated a predetermined distance from each other on the lower wafer W1 to form a single chip when being cut. - Step b: Bonding first bare chips having input, output and IDT electrodes formed thereon onto the lower wafer via a metallic bonding agent.
- As shown in
FIG. 5 b, after forming theelectrodes holes 134 on the lower wafer W1, firstbare chips 110 having other input, output andIDT electrodes bare chip 110 face the electrodes of the lower wafer W1, respectively. - In this state, a
metallic bonding agent 131 is interposed between aconductive pad 132 laid on the input andoutput electrodes bare chip 110 and theconductive pattern 133 electrically connected to the input andoutput electrodes bare chips 110 and the lower wafer W1 while electrically connecting them. - At this time, flip chip bonding of the first
bare chips 110 to the lower wafer W1 via themetallic bonding agent 131 is performed through a supersonic bonding process using Au-based stud bumps as themetallic bonding agent 131 interposed between theconductive pad 132 laid on the input andoutput electrodes bare chip 110 and theconductive pattern 133 of the input andoutput electrodes - Alternatively, flip-chip bonding of the first bare chip to the lower wafer may be performed by a thermal bonding process using AuSn-based solder bumps as the
metallic bonding agent 131. - At this time, when the stud bumps are used as the
metallic bonding agent 131, a bonding temperature of 120 to 180° C. can enhance bonding force of the bump balls. - Step c: Laminating a resin film on the lower wafer to cover side and upper surfaces of the first bare chip.
- As shown in
FIG. 5 c, a thermosetting resin film is laminated on the lower wafer W1 through thermal compression to cover side and upper surfaces of the firstbare chip 110 mounted on the lower wafer W1. - At this time, preferably, the
thermosetting resin film 141 is one selected from a polyimide based film and an epoxy-based film. Theresin film 141 is provided to form an air-tight space on an operating surface of the surface acoustic wave device via control of fluidity through temperature control between the electrode surfaces of the firstbare chip 110 and the electrode surfaces of the lower wafer W1. - When laminating the
resin film 141, major factors for the laminating step include compressing material, temperature, time, vacuum level, and the like. More specifically, when using the polyimide based film as thethermosetting resin film 141, optimal laminating results can be obtained under the conditions of the laminating process wherein the compressing material has an elasticity in the range of 0.2˜1 MPa, the laminating temperature is in the range of 170˜200° C., the laminating time is in the range of 30 seconds to 2 minutes, and the vacuum level is in the range of 0.5˜1.5 hpa. - Step d: Removing the resin film to a predetermined depth along a boundary between the first bare chips to form separating grooves therebetween.
- As shown in
FIG. 5 d, separating grooves G are formed between the firstbare chips 110 separated a predetermined distance from each other on the lower wafer W1 by grooving thelaminated resin film 141 to a predetermined depth along a boundary at the center between the firstbare chip 110 and another adjacent firstbare chip 110. - At this time, the separating grooves G are preferably formed to an extent that the upper surface of the lower wafer W1 is exposed to the outside. With this structure, it is possible to obtain a stable structure in which a metal layer entirely surrounds an upper surface of the package without exposing the
resin film 141 on a cut surface during a dicing step after the metal layer is plated on the upper surface of the lower wafer W1 exposed through the bottom of the separating grooves G. - Step e: Plating a metal layer of a predetermined depth on the resin film and the separating groove.
- As shown in
FIG. 5 e, ametal layer 142 having a predetermined thickness is plated on theresin film 141 having the separating grooves G, and on the upper surface of the lower wafer W1 exposed through the separating grooves G in order to prevent infiltration of moisture. In this case, themetal layer 142 is naturally brought into integral contact with theresin film 141 and the piezoelectric single crystal of the lower wafer W1 exposed through the separating grooves G, completely preventing the moisture from infiltrating into the air-tight space between the firstbare chip 110 and the lower wafer W1. - Additionally, preferably, the
metal layer 142 plated on theresin film 141 is electrically connected to a ground terminal to prevent electromagnetic wave from being induced from the outside. - Plating of the
metal layer 142 is preferably performed by electroplating after forming a seed metal with a sputter. - Step f: Dicing a central portion of the separating grooves plated with the metal layer.
- As shown in
FIG. 5 f, after plating the metal layer, the lower wafer W1 is cut by dicing the central portion of the bottom of the separating grooves G in a direction perpendicular to the upper surface of the lower wafer W1. As a result, as shown inFIG. 7 , a plurality of stack type surface acoustic wave packages 100 can be manufactured simultaneously, each of which has a stacked structure having the firstbare chip 110 flip-chip bonded on the upper surface of the secondbare chip 120, and has theresin film 141 and themetal layer 142 to protect the first and secondbare chips - A dicing width of the lower wafer W1 is preferably smaller than the width between the separating grooves G.
-
FIGS. 6 a to 6 f are step diagrams illustrating a method for manufacturing a stack type surface acoustic wave package according to a second embodiment of the invention. - A surface
acoustic wave package 100 a of the present invention is manufactured via steps a to f described below. - Step a: Preparing a lower wafer having input, output and IDT electrodes formed on an upper surface thereof, and a plurality of via-holes passing therethrough.
- As shown in
FIG. 6 a, patterns of input, output, andIDT electrodes - Then, a plurality of via-
holes 134 are formed through the lower wafer W1 having theelectrodes holes 134 are printed with aconductive pad 133 a electrically connected to the input andoutput electrodes conductive pattern 135 a electrically connected to a main substrate. - As a result, a plurality of second
bare chips 120 are continuously disposed, and separated a predetermined distance from each other on the lower wafer W1 to form a single chip when being cut. - Step b: Forming a metal dam to surround the input, output and IDT electrodes of the lower wafer.
- As shown in
FIG. 6 b, after forming theelectrodes holes 134 on the lower wafer W1, a continuous loop-shaped wall is formed to form a shielding wall surrounding the input, output andIDT electrodes - Step c: Bonding an upper wafer having input, output and IDT electrodes formed thereon to the lower wafer via a metallic bonding agent.
- As shown in
FIG. 6 c, an upper wafer W2 having other input, output andIDT electrodes - In this state, a
metallic bonding agent 131 a is interposed between aconductive pad 132 a laid on the input andoutput electrodes conductive pad 133 a electrically connected to the input andoutput electrodes - At this time, the upper wafer W2 and the lower wafer W1 must be accurately aligned to each other in order to ensure that the electrodes of the upper wafer W2 correspond to the electrodes of the lower wafers W1 when they are bonded. In this regard, since the piezoelectric single crystal wafer is substantially transparent, aligning of the upper and lower wafers can be easily performed.
- Additionally, the
metal dam 141 a allows an air-tight space to be formed between the upper and lower wafer W2 and W1 in order to completely shield an electrode operating surface from the external environment. - At this time, flip chip bonding of the upper wafer W2 to the lower wafer W1 via the
metallic bonding agent 131 is performed through a supersonic bonding process using Au-based stud bumps as themetallic bonding agent 131 interposed between theconductive pad 132 a laid on the input andoutput electrodes conductive pad 133 a laid on the input andoutput electrodes metallic bonding agent 131. - Additionally, the
metallic bonding agent 131 a may be formed by screen printing, electroless plating or depositing solders on the lower wafer W1 when forming themetal dam 141 a on the lower wafer W1. - At this time, preferably, the
metallic bonding agent 131 a and themetal dam 141 a comprise gold (Au) or Au alloys such as AuSn. - Step d: Forming separating grooves spaced a predetermined from each other and having a predetermined depth on the upper wafer.
- As shown in
FIG. 6 d, separating grooves G having a predetermined depth are formed and separated a predetermined distance from each other on the upper wafer W2 by grooving the upper wafer W2 and themetal dam 141 a such that a plurality of firstbare chips 110 having input, output andIDT electrodes - At this time, the separating grooves G are preferably formed to an extent that the upper surface of the lower wafer W1 is exposed to the outside.
- Step e: Plating a metal layer having a predetermined thickness from the upper surface of the metal dam to cover the upper wafer.
- As shown in
FIG. 6 e, after forming the separating grooves G on the upper wafer W2, ametal layer 142 a having a predetermined thickness is plated on the upper wafer W2 having the separating grooves G, and on the upper surface of the lower wafer W1 exposed through the separating grooves G in order to prevent infiltration of moisture. - In this case, the
metal layer 142 a is naturally brought into integral contact with themetal dam 141 a exposed through the separating grooves G, completely preventing the moisture from infiltrating into the air-tight space between the firstbare chips 110 and the lower wafer W1. - At this time, preferably, after plating the
metal layer 142 a, themetal dam 141 a is electrically connected to a ground terminal to prevent electromagnetic waves from being induced from the outside. - Plating of the
metal layer 142 a is preferably performed by electroplating after forming a seed metal with a sputter. - Step f: Dicing a central portion between the separating grooves plated with the metal layer.
- As shown in
FIG. 6 f, after plating themetal layer 142 a, the lower wafer W1 is cut by dicing the central portion between the separating grooves G in a direction perpendicular to the upper surface of the lower wafer W1. As a result, a plurality of stack type surface acoustic wave packages 100 a can be provided simultaneously, each of which has a stacked structure having the firstbare chip 110 flip-chip bonded to the upper surface of the secondbare chip 120, and has themetal dam 141 a and themetal layer 142 a to protect the first and secondbare chips - A dicing width of the lower wafer W1 is preferably smaller than the width between the separating grooves G.
- As apparent from the above description, since the surface acoustic wave package of the present invention has vertically flip chip bonded first and second bare chips, each having a plurality of electrodes and a sealing member surrounding the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips, a base of the package can be constituted by a transparent piezoelectric single crystal board instead of a ceramic wiring board, thereby reducing the volume of the board and the chip size, and minimizing the overall package size.
- Additionally, according to the invention, since the transparent piezoelectric single crystal board is used, the number of components can be significantly reduced, thereby remarkably reducing material costs.
- Additionally, according to the invention, the first and second bare chips, each having IDT electrodes different in width, length, and gap therebetween from others, are vertically laminated, and filter out different frequency bands to realize multiple frequency bands without change in width, so that the overall size of the package can be remarkably reduced in comparison to the conventional package having longitudinally disposed bare chips.
- Additionally, according to the invention, since the first and second bare chips are made of the piezoelectric single crystals having the same thermal expansion coefficient, they do not suffer deformation caused by temperature variation such as thermal impact from the outside during flip-chip bonding, so that the first and second bare chips can be stably bonded using metal bumps, and provide a structure having high thermal resistance, thereby enhancing product reliability.
- It should be understood that the embodiments and the accompanying drawings have been described for illustrative purposes, and the present invention is limited only by the following claims. Further, those skilled in the art will appreciate that various modifications, additions and substitutions are allowed without departing from the scope and spirit of the invention according to the accompanying claims.
Claims (19)
1. A method for manufacturing a stack type surface acoustic wave package, comprising the steps of:
a) preparing a lower wafer having input, output and IDT electrodes formed on an upper surface thereof, and a plurality of via-holes passing through the lower wafer;
b) bonding first bare chips, each having input, output and IDT electrodes formed thereon, to the lower wafer via a metallic bonding agent;
c) laminating a resin film on the lower wafer to cover side and upper surfaces of the first bare chips;
d) removing the resin film to a predetermined depth along a boundary between the first bare chips to form separating grooves therebetween;
e) plating a metal layer of a predetermined thickness on the resin film and the separating grooves; and
f) cutting a central portion between the separating grooves plated with the metal layer.
2. The method according to claim 1 , wherein the step a) comprises printing a conductive pattern on upper ends of the via-holes to be electrically connected to the input and output electrodes, and another conductive pattern on lower ends of the via-holes to be electrically connected to a main board.
3. The method according to claim 1 , wherein the step b) comprises flip-chip bonding of the first bare chips to the lower wafer via the metallic bonding agent such that the input and output electrodes, and the IDT electrodes of each first bare chip face the input and output electrodes, and the IDT electrodes of the lower wafer, respectively.
4. The method according to claim 3 , wherein flip-chip bonding of the first bare chips to the lower wafer comprises supersonic bonding by use of stud bumps interposed between a conductive pad laid on the input and output electrodes of each first bare chip and a conductive pattern of the input and output electrodes of the lower wafer.
5. The method according to claim 3 , wherein flip-chip bonding of the first bare chips to the lower wafer comprises thermal bonding by use of AuSn-based solder bumps interposed between a conductive pad laid on the input and output electrodes of each first bare chip and a conductive pattern of the input and output electrodes of the lower wafer.
6. The method according to claim 1 , wherein the step c) comprises laminating the resin film formed of a thermosetting material by thermal compression.
7. The method according to claim 6 , wherein the thermosetting resin film is one selected from a polyimide based film and an epoxy-based film.
8. The method according to claim 1 , wherein, at the step d), the separating grooves are formed to an extent that the upper surface of the lower wafer is exposed to the outside.
9. The method according to claim 1 , wherein, at the step e), the metal layer is electrically connected to an inner ground terminal to prevent electromagnetic waves from being induced from the outside.
10. The method according to claim 1 , wherein, at the step e), the metal layer is plated by an electroplating process.
11. A method for manufacturing a stack type surface acoustic wave package, comprising the steps of:
a) preparing a lower wafer having input, output and IDT electrodes formed on an upper surface thereof, and a plurality of via-holes passing through the lower wafer;
b) forming a metal dam to surround the input, output and IDT electrodes of the lower wafer;
c) bonding an upper wafer having input, output and IDT electrodes formed thereon onto the lower wafer via a metallic bonding agent;
d) forming separating grooves spaced a predetermined from each other and having a predetermined depth on the upper wafer;
e) plating a metal layer of a predetermined thickness from the upper surface of the metal dam to cover the upper wafer; and
f) dicing a central portion between the separating grooves plated with the metal layer.
12. The method according to claim 11 , wherein the step a) comprises printing a conductive pattern on upper ends of the via-holes to be electrically connected to the input and output electrodes, and another conductive pattern on lower ends of the via-holes to be electrically connected to a main board.
13. The method according to claim 11 , wherein the step b) comprises forming the metallic bonding agent while forming the metal dam on the lower wafer.
14. The method according to claim 11 , wherein at the step b), the metal layer is electrically connected to an inner ground terminal to prevent electromagnetic waves from being induced from the outside after plating the metal layer.
15. The method according to claim 11 , wherein the step c) comprises flip-chip bonding of the upper wafer to the lower wafer via the metallic bonding agent such that the input and output electrodes, and the IDT electrodes of the upper wafer face the input and output electrodes, and the IDT electrodes of the lower wafer, respectively.
16. The method according to claim 15 , wherein flip-chip bonding of the upper wafer to the lower wafer comprises supersonic bonding by use of stud bumps interposed between a conductive pad laid on the input and output electrodes of the upper wafer and another conductive pad laid on the input and output electrodes of the lower wafer.
17. The method according to claim 15 , wherein flip-chip bonding of the upper wafer to the lower wafer comprises thermal bonding by use of AuSn-based solder bumps interposed between a conductive pad laid on the input and output electrodes of the upper wafer and another conductive pad laid on the input and output electrodes of the lower wafer.
18. The method according to claim 11 , wherein at the step d), the separating grooves are formed to an extent that the upper surface of the lower wafer is exposed to the outside.
19. The method according to claim 11 , wherein, at the step e), the metal layer is plated by an electroplating process.
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US11/217,465 US7336017B2 (en) | 2005-05-06 | 2005-09-02 | Stack type surface acoustic wave package, and method for manufacturing the same |
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US20140332937A1 (en) * | 2007-04-30 | 2014-11-13 | Markus Brunnbauer | Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips |
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US9601475B2 (en) | 2007-04-30 | 2017-03-21 | Intel Deutschland Gmbh | Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips |
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Also Published As
Publication number | Publication date |
---|---|
US20100047949A1 (en) | 2010-02-25 |
KR20060115791A (en) | 2006-11-10 |
US7820468B2 (en) | 2010-10-26 |
KR100691160B1 (en) | 2007-03-09 |
US7336017B2 (en) | 2008-02-26 |
US20060249824A1 (en) | 2006-11-09 |
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