US20070141751A1 - Stackable molded packages and methods of making the same - Google Patents
Stackable molded packages and methods of making the same Download PDFInfo
- Publication number
- US20070141751A1 US20070141751A1 US11/311,579 US31157905A US2007141751A1 US 20070141751 A1 US20070141751 A1 US 20070141751A1 US 31157905 A US31157905 A US 31157905A US 2007141751 A1 US2007141751 A1 US 2007141751A1
- Authority
- US
- United States
- Prior art keywords
- die
- conductive
- packaged
- conductive members
- encapsulant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Definitions
- the present invention relates generally to integrated circuit packages, and more particularly to stackable molded packages and methods of making the same.
- stackable packages often warp resulting in poor reliability of contacts with other packages.
- stackable packages include a substrate and a molded die on top of the substrate.
- the mold covering the die does not cover the entire surface of the substrate.
- the thin substrate which is not supported by the mold in entirety, is more prone to suffer from warpage. This warpage may result from different thermal coefficients of expansion for the substrate and the mold.
- Stackable packages may be stacked in a package-on-package structure and may be interconnected using solder balls.
- FIG. 1 is a top view of an exemplary substrate strip, consistent with one embodiment of the invention
- FIG. 2 is a cross section view of the exemplary substrate strip of FIG. 1 with wire-bonded dies, consistent with one embodiment of the invention
- FIG. 3 is a cross section view of the exemplary substrate strip of FIG. 2 with dams and conductive balls, consistent with one embodiment of the invention
- FIG. 4 is a cross section view of the exemplary substrate strip of FIG. 3 with the encapsulant dispensed between dams, consistent with one embodiment of the invention
- FIG. 5 is a cross section view of an exemplary substrate strip with a flip chip die, consistent with one embodiment of the invention.
- FIG. 6 is a top view of an exemplary top mold chase with vacuum-assisted pad protectors, consistent with one embodiment of the invention.
- FIG. 7 is a cross section view of a substrate inside a mold chase, consistent with one embodiment of the invention.
- FIG. 8 is a cross section view of a substrate with mold injected on top of the substrate, consistent with one embodiment of the invention.
- FIG. 9 is a cross section view of an exemplary stackable package, consistent with one embodiment of the invention.
- FIG. 10 is a top view of an exemplary top mold chase with a conductive ball protection plate, consistent with one embodiment of the invention.
- FIG. 11 is a cross section view of a substrate inside a mold chase, consistent with one embodiment of the invention.
- FIG. 12 is a cross section view of a substrate with mold injected on top of the substrate, consistent with one embodiment of the invention.
- FIG. 13 is a cross section view of another exemplary stackable package, consistent with one embodiment of the invention.
- FIG. 14 is a cross section view of an exemplary package-on-package structure, consistent with one embodiment of the invention.
- FIG. 15 is a cross section view of an exemplary stackable package with a shield, consistent with one embodiment of the invention.
- FIG. 16 is a cross section view of another exemplary package-on-package structure, consistent with one embodiment of the invention.
- an exemplary method for forming a stackable package such as a packaged integrated circuit.
- the exemplary method may include providing a package substrate having a first surface, a first IC die attached to the first surface, a plurality of conductive members on the first surface at least partially surrounding the first IC die and electrically connected to the first IC die, and a dam on the first surface at least partially surrounding the plurality of conductive members.
- the exemplary method may further include performing a surface fill by providing an encapsulant to the first surface of the package substrate wherein the encapsulant surrounds the first IC die and is at least partially contained by the dam and wherein portions of each of the plurality of conductive members remain exposed during the surface fill.
- the method may include providing a package substrate having a first surface, a first IC die attached to the first surface, a plurality of conductive members on the first surface at least partially surrounding the first IC die and electrically connected to the first IC die.
- the method may further include providing a protection plate in physical contact with a top portion of each of the plurality of conductive members.
- the method may further include providing an encapsulant onto the first surface of the package substrate, wherein the encapsulant surrounds the first IC die and each of the plurality of conductive members, and wherein the protection plate remains in physical contact with the top portion of each of the plurality of conductive members during the providing the encapsulant.
- the method may further include removing the protection plate, wherein after removing the protection plate, the top portion of each of the plurality of conductive members remains exposed.
- a packaged integrated circuit may include a first packaged IC having a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant.
- the packaged integrated circuit may further include a second packaged IC stacked onto the first packaged IC, the second packaged IC having at least one IC die and a plurality of conductive members electrically connected to the at least one IC die of the second packaged IC, each conductive member of the plurality of conductive members of the second packaged IC in contact with a corresponding conductive member of the plurality of conductive members of the first packaged IC.
- FIG. 1 is a top view of an exemplary substrate strip, consistent with one embodiment of the invention.
- a substrate strip 10 may be formed, which may include multiple substrate units.
- Substrate strip 10 may include die attach areas 16 , to which die could be attached later.
- Substrate strip 10 may further include bond posts 18 for wire bonding die.
- FIG. 1 shows bond posts 18 for wire bonding die, die may be connected to substrate strip 10 using other techniques, such as flip chip bonding.
- Substrate strip 10 may further include contact pads 20 for connecting stackable packages. Although FIG. 1 shows two rows/columns of contact pads 20 additional or fewer rows/columns may also be used.
- Substrate strip 10 may further include dam bars 12 and 14 .
- Dam bars 12 and 14 may be used to stop the flow of an encapsulant material beyond the periphery of the stackable package. Dam bars 12 and 14 may be formed by depositing solder balls on a copper strip. Alternatively, dam bars 12 and 14 may be formed by depositing any suitable dam bar material, including conductive or non-conductive materials. Furthermore, additional bars, such as bars 13 and 15 may be formed by depositing suitable dam bar material. Bars 13 and 15 may serve as a radio frequency shield for a die attached to die attach areas 16 . Additionally and/or alternatively, bars 13 and 15 may serve to shield the die from interference, such as electromagnetic interference. Also, shown in FIG.
- FIG. 1 is the direction 22 of saw-street along which substrate strip 10 may be singulated.
- FIG. 1 refers to a substrate strip 10 having a row of substrate of units, an array of substrate units with more than one row of substrate units may also be used.
- die 24 may be wire bonded to substrate strip 10 using bond posts 18 and wires 19 .
- FIG. 3 is a cross section view of the exemplary substrate of FIG. 2 with dams, shielding bars, and conductive balls, consistent with one embodiment of the invention.
- dams 26 , shielding supports 31 , and conductive balls 30 may be formed by re-flowing conductive material. Dams 26 (which may be formed using conductive balls), conductive balls 30 , and shielding supports may be preformed and may be attached to respective contact areas.
- FIG. 4 is a cross section view of the exemplary substrate of FIG. 3 with the encapsulant dispensed between dams, consistent with one embodiment of the invention.
- an encapsulant 34 may be dispensed on the top surface of substrate strip 10 using dispensers 32 , for example. Dams 26 may prevent the flow of encapsulant 34 beyond the periphery of the stackable packages. Any conventional encapsulants may be used as part of this step.
- External conductive balls 36 may be formed on a bottom surface of substrate strip 10 . Alternatively, preformed external conductive balls 36 may be attached to the bottom surface of substrate strip 10 .
- flip chip die 38 may also be used as part of stackable packages.
- Encapsulant 34 may act as an underfill between flip chip die 38 and a top surface of substrate strip 10 .
- stackable packages may be singulated. Die may be attached to substrate strip 10 using processes other than wire bonding and flip chip bonding.
- FIG. 6 is a top view of an exemplary top mold chase with vacuum-assisted pad protectors, consistent with one embodiment of the invention, which may be used as part of the molding process.
- Top mold chase 50 may include vacuum-assisted pad protectors 52 located in vacuum housing 51 .
- Vacuum housing 51 may be of the same material as the material of top mold chase 50 .
- inserts could be added to vacuum-assisted pad protectors 52 or to vacuum housing 51 in order to, for example, narrow the area covered by vacuum-assisted pad protectors 52 resulting in a variable pad width.
- Top mold chase 50 may further include a vacuum tube 54 .
- Top mold chase 50 may further include a mold injecting tube 56 . Molding material may be injected using mold injecting tube 56 .
- FIG. 7 a cross section view of a substrate inside a mold chase is shown.
- Substrate 60 including a die 62 attached to it, may be held between top mold chase 50 and bottom mold chase 58 .
- Molding material 64 (shown in FIG. 8 ) may be injected using mold injecting tube 56 .
- Vacuum tube 54 may be used to prevent the molding material from flowing into an area above contact pads 66 .
- a positive pressure may be applied through vacuum-assisted pad protectors 52 to prevent the molding material from flowing into an area above contact pads 66 .
- the application of positive pressure and/or vacuum could be controlled during the molding process to prevent overflow on the contact pads 66 .
- molding material 64 is shown as filling the area between top mold chase 50 and substrate 60 , except the area occupied by die 62 and the area protected by vacuum-assisted pad protectors 52 .
- FIG. 9 is a cross section view of an exemplary stackable package, consistent with one embodiment of the invention.
- Stackable package may include die 62 attached to substrate 60 with molding material 64 on top.
- Stackable package may further include conductive material 68 filled into the area protected by vacuum-assisted pad protectors 52 .
- Conductive material 68 may be filled using conventional processes and then leveled using a solder squeegee, for example.
- Conductive material 68 may be reflowed and the stackable package grinded, if necessary. Solder balls may also be inserted in the area above contact pads 66 , which could then be reflowed to form conductive material 68 .
- external conductive balls 63 may be formed on a bottom surface of substrate 60 for connecting the stackable package to other packages or other components, such as printed circuit boards.
- FIG. 9 shows die 62 as being wire bonded to substrate 60
- die 62 may be attached to substrate 60 using other techniques, such as flip chip bonding.
- stackable packages may be formed using other exemplary mold processes, as well. For example, as described below, a mold chase with a conductive ball protection plate may also be used to form stackable packages.
- a top mold chase 70 may include a conductive ball protection plate 72 .
- Top mold chase 70 may further include a mold injection tube 76 .
- FIG. 11 a cross section view of a substrate 80 inside a mold chase is shown.
- Substrate 80 including a die 82 attached to it, may be held between top mold chase 70 and bottom mold chase 78 .
- Molding material 86 (shown in FIG. 12 ) may be injected using mold injecting tube 76 .
- Alignment indentations 73 formed in conductive ball protection plate 72 may cover the top portion of conductive balls 74 to prevent the flow of molding material 86 on top of conductive balls 74 .
- conductive ball protection plate 72 may be removed subsequent to the injection of molding material, a top portion of conductive balls 74 may remain exposed.
- conductive ball protection plate 72 may be connected to top molding plate 70 using springs 77 .
- Springs 77 may provide pressure to conductive ball protection plate 72 to ensure that conductive ball protection plate 72 is not pushed up by molding material 86 .
- molding material 86 is shown as filling the area between conductive ball protection plate 72 and substrate 80 , except the area occupied by die 82 . Molding material 86 is also shown as an underfill for die 82 .
- FIG. 13 is a cross section view of an exemplary stackable package, consistent with one embodiment of the invention.
- Stackable package may include die 82 attached to substrate 80 with molding material 86 on top.
- Stackable package may further include conductive balls 74 , whose top portion is not covered by molding material 86 and is thus exposed.
- external conductive balls 88 may be formed on a bottom surface of substrate 80 for connecting the stackable package to other packages or other components, such as printed circuit boards.
- FIG. 13 shows die 82 as being flip chip bonded to substrate 80 , die 82 may be attached to substrate 80 using other techniques, such as wire bonding.
- FIG. 14 is a cross section view of an exemplary package-on-package structure 100 , consistent with one embodiment of the invention.
- a package-on-package (POP) structure 100 may be formed by stacking multiple packages.
- POP structure 100 may include a top package 90 over another stackable package.
- Package 90 may include die 92 and die 94 encapsulated in an encapsulant 98 .
- Package 90 may further include connecting pads 96 for connecting package 90 to another package.
- conductive balls 74 may be connected to connecting pads 96 to connect package 90 to another stackable package. Any stackable package described above may be used as part of POP structure 100 .
- a stackable package may also be stacked on top of the stackable package. Furthermore, any number of packages and/or stackable packages may be stacked on top of each other. Each package and/or stackable package may include one or more die. External conductive balls 88 may be formed on a bottom or top surface of any package, as and when necessary.
- FIG. 15 is a cross section view of another exemplary stackable package, consistent with one embodiment of the invention.
- Stackable package may include die 82 attached to substrate 80 with molding material 86 on top.
- Stackable package may further include conductive balls 74 , whose top portion is not covered by molding material 86 and is thus exposed.
- external conductive balls 88 may be formed on a bottom surface of substrate 80 for connecting the stackable package to other packages or other components, such as printed circuit boards.
- FIG. 15 shows die 82 as being flip chip bonded to substrate 80 , die 82 may be attached to substrate 80 using other techniques, such as wire bonding.
- Stackable package may further include contact pads 85 with shielding support, such as contact balls 87 connected to contact pads 85 .
- a shield such as a radio frequency shield or an electromagnetic interference shield may be mounted on top of shielding support/contact balls 87 .
- FIG. 15 shows contact balls 87 as shielding support, other types of shielding support may also be used.
- FIG. 16 is a cross section view of another exemplary package-on-package structure 200 , consistent with one embodiment of the invention.
- a package-on-package (POP) structure 200 may be formed by stacking multiple packages.
- POP structure 200 may include a top package 90 over another stackable package.
- Package 90 may include die 92 and die 94 encapsulated in an encapsulant 98 .
- Package 90 may further include connecting pads 96 for connecting package 90 to another package.
- conductive balls 74 may be connected to connecting pads 96 to connect package 90 to another stackable package. Any stackable package described above may be used as part of POP structure 200 .
- package-on-package structure 200 may include a shield 91 , which may act as a radio frequency shield or an electromagnetic interference shield.
- shield 91 may act as a radio frequency shield or an electromagnetic interference shield.
- contact pads 93 on a top surface of bottom package may be formed, which may then have a shielding support, such as contact balls 95 mounted thereon. Shield 91 may then be attached to contact balls 95 .
- FIG. 16 shows contact balls 95 as shielding support, other types of shielding support may also be used.
- Contact balls 87 and 95 acting as shielding support, may be electrically connected through the substrate to balls 88 which can be grounded to the desired locations.
Abstract
Description
- The present invention relates generally to integrated circuit packages, and more particularly to stackable molded packages and methods of making the same.
- Traditional stackable packages often warp resulting in poor reliability of contacts with other packages. In general, such stackable packages include a substrate and a molded die on top of the substrate. Typically, the mold covering the die does not cover the entire surface of the substrate. In such a stackable package, the thin substrate, which is not supported by the mold in entirety, is more prone to suffer from warpage. This warpage may result from different thermal coefficients of expansion for the substrate and the mold. Stackable packages may be stacked in a package-on-package structure and may be interconnected using solder balls.
- When conventional stackable packages are used in a package-on-package structure, however, warpage of the stackable package may result in poor contacts between stacked packages. Conventionally, this problem has been addressed by increasing the diameter and pitch of the solder balls interconnecting the stacked packages. Increased diameter and pitch of the solder balls, however, results in several problems. For example, use of larger solder balls reduces the area available for the die and the metal routing of the substrate. Furthermore, use of larger solder balls increases the height of the package-on-package structure.
- Thus, there is a need for improved stackable molded packages and methods of making the same.
- The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
-
FIG. 1 is a top view of an exemplary substrate strip, consistent with one embodiment of the invention; -
FIG. 2 is a cross section view of the exemplary substrate strip ofFIG. 1 with wire-bonded dies, consistent with one embodiment of the invention; -
FIG. 3 is a cross section view of the exemplary substrate strip ofFIG. 2 with dams and conductive balls, consistent with one embodiment of the invention; -
FIG. 4 is a cross section view of the exemplary substrate strip ofFIG. 3 with the encapsulant dispensed between dams, consistent with one embodiment of the invention; -
FIG. 5 is a cross section view of an exemplary substrate strip with a flip chip die, consistent with one embodiment of the invention; -
FIG. 6 is a top view of an exemplary top mold chase with vacuum-assisted pad protectors, consistent with one embodiment of the invention; -
FIG. 7 is a cross section view of a substrate inside a mold chase, consistent with one embodiment of the invention; -
FIG. 8 is a cross section view of a substrate with mold injected on top of the substrate, consistent with one embodiment of the invention; -
FIG. 9 is a cross section view of an exemplary stackable package, consistent with one embodiment of the invention; -
FIG. 10 is a top view of an exemplary top mold chase with a conductive ball protection plate, consistent with one embodiment of the invention; -
FIG. 11 is a cross section view of a substrate inside a mold chase, consistent with one embodiment of the invention; -
FIG. 12 is a cross section view of a substrate with mold injected on top of the substrate, consistent with one embodiment of the invention; -
FIG. 13 is a cross section view of another exemplary stackable package, consistent with one embodiment of the invention; -
FIG. 14 is a cross section view of an exemplary package-on-package structure, consistent with one embodiment of the invention; -
FIG. 15 is a cross section view of an exemplary stackable package with a shield, consistent with one embodiment of the invention; and -
FIG. 16 is a cross section view of another exemplary package-on-package structure, consistent with one embodiment of the invention. - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
- In one aspect, an exemplary method for forming a stackable package, such as a packaged integrated circuit is provided. The exemplary method may include providing a package substrate having a first surface, a first IC die attached to the first surface, a plurality of conductive members on the first surface at least partially surrounding the first IC die and electrically connected to the first IC die, and a dam on the first surface at least partially surrounding the plurality of conductive members. The exemplary method may further include performing a surface fill by providing an encapsulant to the first surface of the package substrate wherein the encapsulant surrounds the first IC die and is at least partially contained by the dam and wherein portions of each of the plurality of conductive members remain exposed during the surface fill.
- In another aspect, another exemplary method for forming a packaged integrated circuit is provided. The method may include providing a package substrate having a first surface, a first IC die attached to the first surface, a plurality of conductive members on the first surface at least partially surrounding the first IC die and electrically connected to the first IC die. The method may further include providing a protection plate in physical contact with a top portion of each of the plurality of conductive members. The method may further include providing an encapsulant onto the first surface of the package substrate, wherein the encapsulant surrounds the first IC die and each of the plurality of conductive members, and wherein the protection plate remains in physical contact with the top portion of each of the plurality of conductive members during the providing the encapsulant. The method may further include removing the protection plate, wherein after removing the protection plate, the top portion of each of the plurality of conductive members remains exposed.
- In yet another aspect, a packaged integrated circuit is provided. The packaged integrated circuit may include a first packaged IC having a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. The packaged integrated circuit may further include a second packaged IC stacked onto the first packaged IC, the second packaged IC having at least one IC die and a plurality of conductive members electrically connected to the at least one IC die of the second packaged IC, each conductive member of the plurality of conductive members of the second packaged IC in contact with a corresponding conductive member of the plurality of conductive members of the first packaged IC.
-
FIG. 1 is a top view of an exemplary substrate strip, consistent with one embodiment of the invention. As part of the process of forming stackable packages asubstrate strip 10 may be formed, which may include multiple substrate units.Substrate strip 10 may include dieattach areas 16, to which die could be attached later.Substrate strip 10, may further includebond posts 18 for wire bonding die.FIG. 1 showsbond posts 18 for wire bonding die, die may be connected tosubstrate strip 10 using other techniques, such as flip chip bonding.Substrate strip 10 may further includecontact pads 20 for connecting stackable packages. AlthoughFIG. 1 shows two rows/columns ofcontact pads 20 additional or fewer rows/columns may also be used. -
Substrate strip 10 may further includedam bars Dam bars Dam bars dam bars bars Bars attach areas 16. Additionally and/or alternatively,bars FIG. 1 is thedirection 22 of saw-street along whichsubstrate strip 10 may be singulated. AlthoughFIG. 1 refers to asubstrate strip 10 having a row of substrate of units, an array of substrate units with more than one row of substrate units may also be used. Referring now toFIG. 2 , as part of the process of forming stackable packages, die 24 may be wire bonded tosubstrate strip 10 usingbond posts 18 andwires 19. -
FIG. 3 is a cross section view of the exemplary substrate ofFIG. 2 with dams, shielding bars, and conductive balls, consistent with one embodiment of the invention. As part of this step,dams 26, shielding supports 31, andconductive balls 30 may be formed by re-flowing conductive material. Dams 26 (which may be formed using conductive balls),conductive balls 30, and shielding supports may be preformed and may be attached to respective contact areas. -
FIG. 4 is a cross section view of the exemplary substrate ofFIG. 3 with the encapsulant dispensed between dams, consistent with one embodiment of the invention. As shown, as the next step of forming stackable packages, anencapsulant 34 may be dispensed on the top surface ofsubstrate strip 10 usingdispensers 32, for example.Dams 26 may prevent the flow ofencapsulant 34 beyond the periphery of the stackable packages. Any conventional encapsulants may be used as part of this step. Externalconductive balls 36 may be formed on a bottom surface ofsubstrate strip 10. Alternatively, preformed externalconductive balls 36 may be attached to the bottom surface ofsubstrate strip 10. Referring toFIG. 5 , flip chip die 38 may also be used as part of stackable packages.Encapsulant 34 may act as an underfill between flip chip die 38 and a top surface ofsubstrate strip 10. As part of the final step, stackable packages may be singulated. Die may be attached tosubstrate strip 10 using processes other than wire bonding and flip chip bonding. - Consistent with another embodiment of the invention, stackable packages may also be formed using a molding process.
FIG. 6 is a top view of an exemplary top mold chase with vacuum-assisted pad protectors, consistent with one embodiment of the invention, which may be used as part of the molding process.Top mold chase 50 may include vacuum-assistedpad protectors 52 located invacuum housing 51.Vacuum housing 51 may be of the same material as the material oftop mold chase 50. In addition, although not shown inFIG. 7 , inserts could be added to vacuum-assistedpad protectors 52 or to vacuumhousing 51 in order to, for example, narrow the area covered by vacuum-assistedpad protectors 52 resulting in a variable pad width.Top mold chase 50 may further include avacuum tube 54. Usingvacuum tube 54, the interface between vacuum-assistedpad protectors 52 andcontact pads 66 may be made substantially air-tight and thus preventing flow of any molding material into an area abovecontact pads 66.Top mold chase 50 may further include amold injecting tube 56. Molding material may be injected usingmold injecting tube 56. Referring toFIG. 7 now, a cross section view of a substrate inside a mold chase is shown.Substrate 60, including a die 62 attached to it, may be held betweentop mold chase 50 andbottom mold chase 58. Molding material 64 (shown inFIG. 8 ) may be injected usingmold injecting tube 56.Vacuum tube 54 may be used to prevent the molding material from flowing into an area abovecontact pads 66. By way of another example, instead of applying vacuum through vacuum-assistedpad protectors 52, a positive pressure may be applied through vacuum-assistedpad protectors 52 to prevent the molding material from flowing into an area abovecontact pads 66. The application of positive pressure and/or vacuum could be controlled during the molding process to prevent overflow on thecontact pads 66. Referring further toFIG. 8 ,molding material 64 is shown as filling the area betweentop mold chase 50 andsubstrate 60, except the area occupied bydie 62 and the area protected by vacuum-assistedpad protectors 52. -
FIG. 9 is a cross section view of an exemplary stackable package, consistent with one embodiment of the invention. Stackable package may include die 62 attached tosubstrate 60 withmolding material 64 on top. Stackable package may further includeconductive material 68 filled into the area protected by vacuum-assistedpad protectors 52.Conductive material 68 may be filled using conventional processes and then leveled using a solder squeegee, for example.Conductive material 68 may be reflowed and the stackable package grinded, if necessary. Solder balls may also be inserted in the area abovecontact pads 66, which could then be reflowed to formconductive material 68. Additionally, externalconductive balls 63 may be formed on a bottom surface ofsubstrate 60 for connecting the stackable package to other packages or other components, such as printed circuit boards. AlthoughFIG. 9 shows die 62 as being wire bonded tosubstrate 60, die 62 may be attached tosubstrate 60 using other techniques, such as flip chip bonding. Further, stackable packages may be formed using other exemplary mold processes, as well. For example, as described below, a mold chase with a conductive ball protection plate may also be used to form stackable packages. - As shown in
FIG. 10 , atop mold chase 70 may include a conductiveball protection plate 72.Top mold chase 70 may further include amold injection tube 76. Referring now toFIG. 11 , a cross section view of asubstrate 80 inside a mold chase is shown.Substrate 80, including a die 82 attached to it, may be held betweentop mold chase 70 andbottom mold chase 78. Molding material 86 (shown inFIG. 12 ) may be injected usingmold injecting tube 76.Alignment indentations 73 formed in conductiveball protection plate 72 may cover the top portion ofconductive balls 74 to prevent the flow ofmolding material 86 on top ofconductive balls 74. Thus, after conductiveball protection plate 72 is removed subsequent to the injection of molding material, a top portion ofconductive balls 74 may remain exposed. By way of example, conductiveball protection plate 72 may be connected totop molding plate 70 usingsprings 77.Springs 77 may provide pressure to conductiveball protection plate 72 to ensure that conductiveball protection plate 72 is not pushed up by moldingmaterial 86. Referring further toFIG. 12 ,molding material 86 is shown as filling the area between conductiveball protection plate 72 andsubstrate 80, except the area occupied bydie 82.Molding material 86 is also shown as an underfill fordie 82. -
FIG. 13 is a cross section view of an exemplary stackable package, consistent with one embodiment of the invention. Stackable package may include die 82 attached tosubstrate 80 withmolding material 86 on top. Stackable package may further includeconductive balls 74, whose top portion is not covered by moldingmaterial 86 and is thus exposed. Additionally, externalconductive balls 88 may be formed on a bottom surface ofsubstrate 80 for connecting the stackable package to other packages or other components, such as printed circuit boards. AlthoughFIG. 13 shows die 82 as being flip chip bonded tosubstrate 80, die 82 may be attached tosubstrate 80 using other techniques, such as wire bonding. -
FIG. 14 is a cross section view of an exemplary package-on-package structure 100, consistent with one embodiment of the invention. In general, a package-on-package (POP)structure 100 may be formed by stacking multiple packages. By way of example,POP structure 100 may include atop package 90 over another stackable package.Package 90 may include die 92 and die 94 encapsulated in anencapsulant 98.Package 90 may further include connectingpads 96 for connectingpackage 90 to another package. Thus, as shown inFIG. 14 ,conductive balls 74 may be connected to connectingpads 96 to connectpackage 90 to another stackable package. Any stackable package described above may be used as part ofPOP structure 100. AlthoughFIG. 14 shows a non-stackable package stacked on top of a stackable package, a stackable package may also be stacked on top of the stackable package. Furthermore, any number of packages and/or stackable packages may be stacked on top of each other. Each package and/or stackable package may include one or more die. Externalconductive balls 88 may be formed on a bottom or top surface of any package, as and when necessary. -
FIG. 15 is a cross section view of another exemplary stackable package, consistent with one embodiment of the invention. Stackable package may include die 82 attached tosubstrate 80 withmolding material 86 on top. Stackable package may further includeconductive balls 74, whose top portion is not covered by moldingmaterial 86 and is thus exposed. Additionally, externalconductive balls 88 may be formed on a bottom surface ofsubstrate 80 for connecting the stackable package to other packages or other components, such as printed circuit boards. AlthoughFIG. 15 shows die 82 as being flip chip bonded tosubstrate 80, die 82 may be attached tosubstrate 80 using other techniques, such as wire bonding. Stackable package may further includecontact pads 85 with shielding support, such ascontact balls 87 connected to contactpads 85. Additionally, a shield, such as a radio frequency shield or an electromagnetic interference shield may be mounted on top of shielding support/contact balls 87. AlthoughFIG. 15 shows contact balls 87 as shielding support, other types of shielding support may also be used. -
FIG. 16 is a cross section view of another exemplary package-on-package structure 200, consistent with one embodiment of the invention. In general, a package-on-package (POP)structure 200 may be formed by stacking multiple packages. By way of example,POP structure 200 may include atop package 90 over another stackable package.Package 90 may include die 92 and die 94 encapsulated in anencapsulant 98.Package 90 may further include connectingpads 96 for connectingpackage 90 to another package. Thus, as shown inFIG. 16 ,conductive balls 74 may be connected to connectingpads 96 to connectpackage 90 to another stackable package. Any stackable package described above may be used as part ofPOP structure 200. AlthoughFIG. 16 shows a non-stackable package stacked on top of a stackable package, a stackable package may also be stacked on top of the stackable package. Furthermore, any number of packages and/or stackable packages may be stacked on top of each other. Each package and/or stackable package may include one or more die. Externalconductive balls 88 may be formed on a bottom or top surface of any package, as and when necessary. In addition, package-on-package structure 200 may include ashield 91, which may act as a radio frequency shield or an electromagnetic interference shield. By way of example,contact pads 93 on a top surface of bottom package may be formed, which may then have a shielding support, such ascontact balls 95 mounted thereon.Shield 91 may then be attached to contactballs 95. AlthoughFIG. 16 shows contact balls 95 as shielding support, other types of shielding support may also be used. Contactballs balls 88 which can be grounded to the desired locations. - In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
- Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims (24)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/311,579 US20070141751A1 (en) | 2005-12-16 | 2005-12-16 | Stackable molded packages and methods of making the same |
JP2008545899A JP2009520366A (en) | 2005-12-16 | 2006-11-21 | Multilayer molded package and method for forming the same |
KR1020087014218A KR20080077177A (en) | 2005-12-16 | 2006-11-21 | Stackable molded packages and methods of making the same |
PCT/US2006/061127 WO2007120282A2 (en) | 2005-12-16 | 2006-11-21 | Stackable molded packages and methods of making the same |
TW095143749A TW200802789A (en) | 2005-12-16 | 2006-11-27 | Stackable molded packages and methods of making the same |
US11/968,873 US20080108179A1 (en) | 2005-12-16 | 2008-01-03 | Stackable molded packages and methods of making the same |
US12/567,469 US8044494B2 (en) | 2005-12-16 | 2009-09-25 | Stackable molded packages and methods of making the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/311,579 US20070141751A1 (en) | 2005-12-16 | 2005-12-16 | Stackable molded packages and methods of making the same |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/968,873 Division US20080108179A1 (en) | 2005-12-16 | 2008-01-03 | Stackable molded packages and methods of making the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070141751A1 true US20070141751A1 (en) | 2007-06-21 |
Family
ID=38174159
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/311,579 Abandoned US20070141751A1 (en) | 2005-12-16 | 2005-12-16 | Stackable molded packages and methods of making the same |
US11/968,873 Abandoned US20080108179A1 (en) | 2005-12-16 | 2008-01-03 | Stackable molded packages and methods of making the same |
US12/567,469 Active 2026-01-09 US8044494B2 (en) | 2005-12-16 | 2009-09-25 | Stackable molded packages and methods of making the same |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/968,873 Abandoned US20080108179A1 (en) | 2005-12-16 | 2008-01-03 | Stackable molded packages and methods of making the same |
US12/567,469 Active 2026-01-09 US8044494B2 (en) | 2005-12-16 | 2009-09-25 | Stackable molded packages and methods of making the same |
Country Status (5)
Country | Link |
---|---|
US (3) | US20070141751A1 (en) |
JP (1) | JP2009520366A (en) |
KR (1) | KR20080077177A (en) |
TW (1) | TW200802789A (en) |
WO (1) | WO2007120282A2 (en) |
Cited By (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070166867A1 (en) * | 2006-01-04 | 2007-07-19 | Chow Seng G | Integrated circuit package system with image sensor system |
US20070190690A1 (en) * | 2006-02-14 | 2007-08-16 | Stats Chippac Ltd. | Integrated circuit package system with exposed interconnects |
US20080179729A1 (en) * | 2005-03-31 | 2008-07-31 | Il Kwon Shim | Encapsulant cavity integrated circuit package system |
US20080258289A1 (en) * | 2007-04-23 | 2008-10-23 | Pendse Rajendra D | Integrated circuit package system for package stacking |
JP2009105297A (en) * | 2007-10-25 | 2009-05-14 | Rohm Co Ltd | Resin-encapsulated semiconductor device |
US20090236731A1 (en) * | 2008-03-19 | 2009-09-24 | Seong Bo Shim | Stackable integrated circuit package system |
US7768125B2 (en) | 2006-01-04 | 2010-08-03 | Stats Chippac Ltd. | Multi-chip package system |
US20110204494A1 (en) * | 2010-02-23 | 2011-08-25 | Chi Heejo | Integrated circuit packaging system with shield and method of manufacture thereof |
US20110281403A1 (en) * | 2008-11-17 | 2011-11-17 | Pyxis Systems Integration Pte Ltd | Method For Encapsulating Semiconductor Dies |
US8102032B1 (en) * | 2008-12-09 | 2012-01-24 | Amkor Technology, Inc. | System and method for compartmental shielding of stacked packages |
US20120049348A1 (en) * | 2010-08-31 | 2012-03-01 | Samsung Electronics Co., Ltd. | Package having elastic members for vias, package on package comprising the same, and methods of fabricating the same |
US20120168917A1 (en) * | 2010-12-31 | 2012-07-05 | Samsung Electronics Co., Ltd. | Stack type semiconductor package and method of fabricating the same |
JP2012256935A (en) * | 2012-08-31 | 2012-12-27 | Rohm Co Ltd | Resin sealing type semiconductor device |
FR2977076A1 (en) * | 2011-06-21 | 2012-12-28 | St Microelectronics Grenoble 2 | SEMICONDUCTOR DEVICE WITH ENCAPSULATED ELECTRICAL CONNECTING ELEMENTS AND METHOD FOR MANUFACTURING THE SAME |
US20140027431A1 (en) * | 2012-07-26 | 2014-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage Control in the Packaging of Integrated Circuits |
US20140231984A1 (en) * | 2013-02-21 | 2014-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molding Compound Structure |
US20140247565A1 (en) * | 2013-03-01 | 2014-09-04 | Seiko Epson Corporation | Module, electronic apparatus and moving object |
US20150069606A1 (en) * | 2012-05-03 | 2015-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for Package on Package Devices |
US20150137334A1 (en) * | 2009-10-23 | 2015-05-21 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV |
US20150187734A1 (en) * | 2013-12-30 | 2015-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with Die Stack Including Exposed Molding Underfill |
US20170040293A1 (en) * | 2015-08-03 | 2017-02-09 | Samsung Electronics Co., Ltd. | Printed circuit board (pcb), method of manufacturing the pcb, and method of manufacturing semiconductor package using the pcb |
US9991239B2 (en) | 2014-09-18 | 2018-06-05 | Intel Corporation | Method of embedding WLCSP components in e-WLB and e-PLB |
CN108780790A (en) * | 2017-01-04 | 2018-11-09 | 华为技术有限公司 | A kind of stack package structure and terminal |
US10217702B2 (en) * | 2012-06-21 | 2019-02-26 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SoP fan-out package |
US20210242157A1 (en) * | 2020-01-30 | 2021-08-05 | Stmicroelectronics S.R.L. | Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal |
US11854954B2 (en) | 2020-01-30 | 2023-12-26 | Stmicroelectronics S.R.L. | Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal routed through the integrated circuit |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI322448B (en) * | 2002-10-08 | 2010-03-21 | Chippac Inc | Semiconductor stacked multi-package module having inverted second package |
US20090000815A1 (en) | 2007-06-27 | 2009-01-01 | Rf Micro Devices, Inc. | Conformal shielding employing segment buildup |
US8959762B2 (en) | 2005-08-08 | 2015-02-24 | Rf Micro Devices, Inc. | Method of manufacturing an electronic module |
KR100885419B1 (en) * | 2006-04-26 | 2009-02-24 | 삼성전자주식회사 | Package-On-Package PoP Structure |
JP5185062B2 (en) * | 2008-10-21 | 2013-04-17 | パナソニック株式会社 | Multilayer semiconductor device and electronic device |
KR101461630B1 (en) * | 2008-11-06 | 2014-11-20 | 삼성전자주식회사 | Wafer level chip on chip package, package on package improving solder joint reliability but reducing mounting height and manufacturing method thereof |
US8130512B2 (en) * | 2008-11-18 | 2012-03-06 | Stats Chippac Ltd. | Integrated circuit package system and method of package stacking |
CN102047404B (en) * | 2008-12-16 | 2013-07-10 | 松下电器产业株式会社 | Semiconductor device, flip-chip mounting method and flip-chip mounting apparatus |
JP5193898B2 (en) * | 2009-02-12 | 2013-05-08 | 新光電気工業株式会社 | Semiconductor device and electronic device |
CN101924041B (en) * | 2009-06-16 | 2015-05-13 | 飞思卡尔半导体公司 | Method for assembling stackable semiconductor packaging |
US8148813B2 (en) * | 2009-07-31 | 2012-04-03 | Altera Corporation | Integrated circuit package architecture |
US8390283B2 (en) | 2009-09-25 | 2013-03-05 | Everspin Technologies, Inc. | Three axis magnetic field sensor |
TWI497679B (en) * | 2009-11-27 | 2015-08-21 | Advanced Semiconductor Eng | Semiconductor package and manufacturing method thereof |
EP2506298A1 (en) | 2009-11-27 | 2012-10-03 | Sumitomo Bakelite Company Limited | Production method for electronic device, electronic device, production method for electronic device package, and electronic device package |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8299595B2 (en) * | 2010-03-18 | 2012-10-30 | Stats Chippac Ltd. | Integrated circuit package system with package stacking and method of manufacture thereof |
TWI411075B (en) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | Semiconductor package and manufacturing method thereof |
US8569869B2 (en) * | 2010-03-23 | 2013-10-29 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulation and method of manufacture thereof |
US8518734B2 (en) | 2010-03-31 | 2013-08-27 | Everspin Technologies, Inc. | Process integration of a single chip three axis magnetic field sensor |
US9137934B2 (en) | 2010-08-18 | 2015-09-15 | Rf Micro Devices, Inc. | Compartmentalized shielding of selected components |
US8546193B2 (en) * | 2010-11-02 | 2013-10-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US8835226B2 (en) * | 2011-02-25 | 2014-09-16 | Rf Micro Devices, Inc. | Connection using conductive vias |
US9627230B2 (en) | 2011-02-28 | 2017-04-18 | Qorvo Us, Inc. | Methods of forming a microshield on standard QFN package |
KR101222820B1 (en) | 2011-03-16 | 2013-01-15 | 삼성전기주식회사 | Semiconductor package and manufacturing method of the same |
JP2013069942A (en) * | 2011-09-24 | 2013-04-18 | Denso Corp | Semiconductor device and manufacturing method of the same |
KR101798571B1 (en) | 2012-02-16 | 2017-11-16 | 삼성전자주식회사 | Semiconductor Packages |
US9030841B2 (en) * | 2012-02-23 | 2015-05-12 | Apple Inc. | Low profile, space efficient circuit shields |
TWI590399B (en) * | 2012-04-02 | 2017-07-01 | 矽品精密工業股份有限公司 | Semiconductor package, package substrate and fabrication method thereof |
KR101989516B1 (en) * | 2012-09-24 | 2019-06-14 | 삼성전자주식회사 | Semiconductor package |
JP6016611B2 (en) * | 2012-12-20 | 2016-10-26 | 三菱電機株式会社 | Semiconductor module, manufacturing method thereof and connection method thereof |
US9807890B2 (en) | 2013-05-31 | 2017-10-31 | Qorvo Us, Inc. | Electronic modules having grounded electromagnetic shields |
US9287240B2 (en) * | 2013-12-13 | 2016-03-15 | Micron Technology, Inc. | Stacked semiconductor die assemblies with thermal spacers and associated systems and methods |
KR101844535B1 (en) * | 2013-12-27 | 2018-04-02 | 인텔 코포레이션 | Optoelectronic packaging assemblies |
WO2016117075A1 (en) * | 2015-01-22 | 2016-07-28 | 新電元工業株式会社 | Semiconductor module and method for producing semiconductor module |
KR101712288B1 (en) * | 2015-11-12 | 2017-03-03 | 앰코 테크놀로지 코리아 주식회사 | Package of semiconductor and method for manufacturing the same |
KR101837511B1 (en) * | 2016-04-04 | 2018-03-14 | 주식회사 네패스 | Semiconductor package and method of manufacturing the same |
US20180053753A1 (en) * | 2016-08-16 | 2018-02-22 | Freescale Semiconductor, Inc. | Stackable molded packages and methods of manufacture thereof |
US11502008B2 (en) | 2017-06-30 | 2022-11-15 | Intel Corporation | Dual strip backside metallization for improved alt-FLI plating, KOZ minimization, test enhancement and warpage control |
US11127689B2 (en) | 2018-06-01 | 2021-09-21 | Qorvo Us, Inc. | Segmented shielding using wirebonds |
US11219144B2 (en) | 2018-06-28 | 2022-01-04 | Qorvo Us, Inc. | Electromagnetic shields for sub-modules |
US11114363B2 (en) | 2018-12-20 | 2021-09-07 | Qorvo Us, Inc. | Electronic package arrangements and related methods |
US11515282B2 (en) | 2019-05-21 | 2022-11-29 | Qorvo Us, Inc. | Electromagnetic shields with bonding wires for sub-modules |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5891753A (en) * | 1997-01-24 | 1999-04-06 | Micron Technology, Inc. | Method and apparatus for packaging flip chip bare die on printed circuit boards |
US6707168B1 (en) * | 2001-05-04 | 2004-03-16 | Amkor Technology, Inc. | Shielded semiconductor package with single-sided substrate and method for making the same |
US20040065473A1 (en) * | 2002-10-08 | 2004-04-08 | Siliconware Precision Industries, Ltd., Taiwan | Warpage preventing substrate |
US20040212066A1 (en) * | 2003-04-23 | 2004-10-28 | Advanced Semiconductor Engineering, Inc. | Multi-chips stacked package |
US6815254B2 (en) * | 2003-03-10 | 2004-11-09 | Freescale Semiconductor, Inc. | Semiconductor package with multiple sides having package contacts |
US20050164429A1 (en) * | 2000-06-02 | 2005-07-28 | Kinsman Larry D. | Method for fabricating a chip scale package using wafer level processing |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5153379A (en) * | 1990-10-09 | 1992-10-06 | Motorola, Inc. | Shielded low-profile electronic component assembly |
US5220489A (en) * | 1991-10-11 | 1993-06-15 | Motorola, Inc. | Multicomponent integrated circuit package |
US5311059A (en) * | 1992-01-24 | 1994-05-10 | Motorola, Inc. | Backplane grounding for flip-chip integrated circuit |
US5222014A (en) * | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5405808A (en) * | 1993-08-16 | 1995-04-11 | Lsi Logic Corporation | Fluid-filled and gas-filled semiconductor packages |
US5650659A (en) * | 1995-08-04 | 1997-07-22 | National Semiconductor Corporation | Semiconductor component package assembly including an integral RF/EMI shield |
US5923959A (en) * | 1997-07-23 | 1999-07-13 | Micron Technology, Inc. | Ball grid array (BGA) encapsulation mold |
KR100266693B1 (en) * | 1998-05-30 | 2000-09-15 | 김영환 | Stackable ball grid array semiconductor package and fabrication method thereof |
US6084297A (en) * | 1998-09-03 | 2000-07-04 | Micron Technology, Inc. | Cavity ball grid array apparatus |
TWI322448B (en) * | 2002-10-08 | 2010-03-21 | Chippac Inc | Semiconductor stacked multi-package module having inverted second package |
US7732904B2 (en) * | 2003-10-10 | 2010-06-08 | Interconnect Portfolio Llc | Multi-surface contact IC packaging structures and assemblies |
TWI336502B (en) * | 2006-09-27 | 2011-01-21 | Advanced Semiconductor Eng | Semiconductor package and semiconductor device and the method of making the same |
US7537962B2 (en) * | 2006-12-22 | 2009-05-26 | Stats Chippac Ltd. | Method of fabricating a shielded stacked integrated circuit package system |
US7851894B1 (en) * | 2008-12-23 | 2010-12-14 | Amkor Technology, Inc. | System and method for shielding of package on package (PoP) assemblies |
-
2005
- 2005-12-16 US US11/311,579 patent/US20070141751A1/en not_active Abandoned
-
2006
- 2006-11-21 KR KR1020087014218A patent/KR20080077177A/en not_active Application Discontinuation
- 2006-11-21 WO PCT/US2006/061127 patent/WO2007120282A2/en active Application Filing
- 2006-11-21 JP JP2008545899A patent/JP2009520366A/en active Pending
- 2006-11-27 TW TW095143749A patent/TW200802789A/en unknown
-
2008
- 2008-01-03 US US11/968,873 patent/US20080108179A1/en not_active Abandoned
-
2009
- 2009-09-25 US US12/567,469 patent/US8044494B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5891753A (en) * | 1997-01-24 | 1999-04-06 | Micron Technology, Inc. | Method and apparatus for packaging flip chip bare die on printed circuit boards |
US20050164429A1 (en) * | 2000-06-02 | 2005-07-28 | Kinsman Larry D. | Method for fabricating a chip scale package using wafer level processing |
US6707168B1 (en) * | 2001-05-04 | 2004-03-16 | Amkor Technology, Inc. | Shielded semiconductor package with single-sided substrate and method for making the same |
US20040065473A1 (en) * | 2002-10-08 | 2004-04-08 | Siliconware Precision Industries, Ltd., Taiwan | Warpage preventing substrate |
US6815254B2 (en) * | 2003-03-10 | 2004-11-09 | Freescale Semiconductor, Inc. | Semiconductor package with multiple sides having package contacts |
US20040212066A1 (en) * | 2003-04-23 | 2004-10-28 | Advanced Semiconductor Engineering, Inc. | Multi-chips stacked package |
Cited By (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7855100B2 (en) | 2005-03-31 | 2010-12-21 | Stats Chippac Ltd. | Integrated circuit package system with an encapsulant cavity and method of fabrication thereof |
US8309397B2 (en) | 2005-03-31 | 2012-11-13 | Stats Chippac Ltd. | Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof |
US20080179729A1 (en) * | 2005-03-31 | 2008-07-31 | Il Kwon Shim | Encapsulant cavity integrated circuit package system |
US8021924B2 (en) | 2005-03-31 | 2011-09-20 | Stats Chippac Ltd. | Encapsulant cavity integrated circuit package system and method of fabrication thereof |
US7838899B2 (en) | 2006-01-04 | 2010-11-23 | Stats Chippac Ltd. | Integrated circuit package system with image sensor system |
US20070166867A1 (en) * | 2006-01-04 | 2007-07-19 | Chow Seng G | Integrated circuit package system with image sensor system |
US20100065936A1 (en) * | 2006-01-04 | 2010-03-18 | Seng Guan Chow | Integrated circuit package system with image sensor system |
US8378502B2 (en) | 2006-01-04 | 2013-02-19 | Stats Chippac Ltd. | Integrated circuit package system with image sensor system |
US7723146B2 (en) | 2006-01-04 | 2010-05-25 | Stats Chippac Ltd. | Integrated circuit package system with image sensor system |
US7768125B2 (en) | 2006-01-04 | 2010-08-03 | Stats Chippac Ltd. | Multi-chip package system |
US20110037136A1 (en) * | 2006-01-04 | 2011-02-17 | Seng Guan Chow | Integrated circuit package system with image sensor system |
US8704349B2 (en) | 2006-02-14 | 2014-04-22 | Stats Chippac Ltd. | Integrated circuit package system with exposed interconnects |
US20070190690A1 (en) * | 2006-02-14 | 2007-08-16 | Stats Chippac Ltd. | Integrated circuit package system with exposed interconnects |
US20080258289A1 (en) * | 2007-04-23 | 2008-10-23 | Pendse Rajendra D | Integrated circuit package system for package stacking |
US8409920B2 (en) | 2007-04-23 | 2013-04-02 | Stats Chippac Ltd. | Integrated circuit package system for package stacking and method of manufacture therefor |
JP2009105297A (en) * | 2007-10-25 | 2009-05-14 | Rohm Co Ltd | Resin-encapsulated semiconductor device |
US9484282B2 (en) | 2007-10-25 | 2016-11-01 | Rohm Co., Ltd. | Resin-sealed semiconductor device |
US20090184412A1 (en) * | 2007-10-25 | 2009-07-23 | Rohm Co., Ltd. | Resin-seal type semiconductor device |
US8779570B2 (en) * | 2008-03-19 | 2014-07-15 | Stats Chippac Ltd. | Stackable integrated circuit package system |
US20090236731A1 (en) * | 2008-03-19 | 2009-09-24 | Seong Bo Shim | Stackable integrated circuit package system |
US20110281403A1 (en) * | 2008-11-17 | 2011-11-17 | Pyxis Systems Integration Pte Ltd | Method For Encapsulating Semiconductor Dies |
US8102032B1 (en) * | 2008-12-09 | 2012-01-24 | Amkor Technology, Inc. | System and method for compartmental shielding of stacked packages |
US20150137334A1 (en) * | 2009-10-23 | 2015-05-21 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV |
US9401347B2 (en) * | 2009-10-23 | 2016-07-26 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV |
US8314486B2 (en) * | 2010-02-23 | 2012-11-20 | Stats Chippac Ltd. | Integrated circuit packaging system with shield and method of manufacture thereof |
US20110204494A1 (en) * | 2010-02-23 | 2011-08-25 | Chi Heejo | Integrated circuit packaging system with shield and method of manufacture thereof |
US8274144B2 (en) * | 2010-08-31 | 2012-09-25 | Samsung Electronics Co., Ltd. | Helical springs electrical connecting a plurality of packages |
US20120049348A1 (en) * | 2010-08-31 | 2012-03-01 | Samsung Electronics Co., Ltd. | Package having elastic members for vias, package on package comprising the same, and methods of fabricating the same |
US8952513B2 (en) * | 2010-12-31 | 2015-02-10 | Samsung Electronics Co., Ltd. | Stack type semiconductor package and method of fabricating the same |
US20120168917A1 (en) * | 2010-12-31 | 2012-07-05 | Samsung Electronics Co., Ltd. | Stack type semiconductor package and method of fabricating the same |
FR2977076A1 (en) * | 2011-06-21 | 2012-12-28 | St Microelectronics Grenoble 2 | SEMICONDUCTOR DEVICE WITH ENCAPSULATED ELECTRICAL CONNECTING ELEMENTS AND METHOD FOR MANUFACTURING THE SAME |
USRE49046E1 (en) * | 2012-05-03 | 2022-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for package on package devices |
US20150069606A1 (en) * | 2012-05-03 | 2015-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for Package on Package Devices |
US9373599B2 (en) * | 2012-05-03 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for package on package devices |
US10217702B2 (en) * | 2012-06-21 | 2019-02-26 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SoP fan-out package |
US11432372B2 (en) | 2012-07-26 | 2022-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage control in the packaging of integrated circuits |
US20140027431A1 (en) * | 2012-07-26 | 2014-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage Control in the Packaging of Integrated Circuits |
US9888527B2 (en) | 2012-07-26 | 2018-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Systems for processing semiconductor devices, and methods of processing semiconductor devices |
US10512124B2 (en) | 2012-07-26 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage control in the packaging of integrated circuits |
US9538582B2 (en) * | 2012-07-26 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage control in the packaging of integrated circuits |
JP2012256935A (en) * | 2012-08-31 | 2012-12-27 | Rohm Co Ltd | Resin sealing type semiconductor device |
CN104009007A (en) * | 2013-02-21 | 2014-08-27 | 台湾积体电路制造股份有限公司 | Molding compound structure |
US9406596B2 (en) * | 2013-02-21 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molding compound structure |
US20140231984A1 (en) * | 2013-02-21 | 2014-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molding Compound Structure |
US10867896B2 (en) | 2013-02-21 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molding compound structure |
US10347572B2 (en) | 2013-02-21 | 2019-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molding compound structure |
US9911687B2 (en) | 2013-02-21 | 2018-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molding compound structure |
US9426892B2 (en) * | 2013-03-01 | 2016-08-23 | Seiko Epson Corporation | Module, electronic apparatus and moving object |
US20140247565A1 (en) * | 2013-03-01 | 2014-09-04 | Seiko Epson Corporation | Module, electronic apparatus and moving object |
US9793242B2 (en) * | 2013-12-30 | 2017-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with die stack including exposed molding underfill |
US20150187734A1 (en) * | 2013-12-30 | 2015-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with Die Stack Including Exposed Molding Underfill |
US9991239B2 (en) | 2014-09-18 | 2018-06-05 | Intel Corporation | Method of embedding WLCSP components in e-WLB and e-PLB |
US10147710B2 (en) | 2014-09-18 | 2018-12-04 | Intel Corporation | Method of embedding WLCSP components in E-WLB and E-PLB |
KR102412611B1 (en) | 2015-08-03 | 2022-06-23 | 삼성전자주식회사 | Printed Circuit Board(PCB), method for fabricating the PCB, and method for fabricating semiconductor package using the PCB |
US10068878B2 (en) * | 2015-08-03 | 2018-09-04 | Samsung Electronics Co., Ltd. | Printed circuit board (PCB), method of manufacturing the PCB, and method of manufacturing semiconductor package using the PCB |
US20170040293A1 (en) * | 2015-08-03 | 2017-02-09 | Samsung Electronics Co., Ltd. | Printed circuit board (pcb), method of manufacturing the pcb, and method of manufacturing semiconductor package using the pcb |
CN106409776A (en) * | 2015-08-03 | 2017-02-15 | 三星电子株式会社 | Printed circuit board (PCB), method of manufacturing the PCB, and method of manufacturing semiconductor package using the PCB |
KR20170016154A (en) * | 2015-08-03 | 2017-02-13 | 삼성전자주식회사 | Printed Circuit Board(PCB), method for fabricating the PCB, and method for fabricating semiconductor package using the PCB |
CN108780790A (en) * | 2017-01-04 | 2018-11-09 | 华为技术有限公司 | A kind of stack package structure and terminal |
US20210242157A1 (en) * | 2020-01-30 | 2021-08-05 | Stmicroelectronics S.R.L. | Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal |
US11742311B2 (en) * | 2020-01-30 | 2023-08-29 | Stmicroelectronics S.R.L. | Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal |
US11854954B2 (en) | 2020-01-30 | 2023-12-26 | Stmicroelectronics S.R.L. | Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal routed through the integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2009520366A (en) | 2009-05-21 |
US20080108179A1 (en) | 2008-05-08 |
WO2007120282A2 (en) | 2007-10-25 |
US20100013065A1 (en) | 2010-01-21 |
US8044494B2 (en) | 2011-10-25 |
WO2007120282A3 (en) | 2008-04-10 |
KR20080077177A (en) | 2008-08-21 |
TW200802789A (en) | 2008-01-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8044494B2 (en) | Stackable molded packages and methods of making the same | |
CN106711094B (en) | Semiconductor package and method of manufacturing the same | |
US7326592B2 (en) | Stacked die package | |
US7262074B2 (en) | Methods of fabricating underfilled, encapsulated semiconductor die assemblies | |
US7399658B2 (en) | Pre-molded leadframe and method therefor | |
US6720666B2 (en) | BOC BGA package for die with I-shaped bond pad layout | |
US6885093B2 (en) | Stacked die semiconductor device | |
US20070273019A1 (en) | Semiconductor package, chip carrier structure thereof, and method for fabricating the chip carrier | |
US20030148557A1 (en) | BOC BGA package for die with I-shaped bond pad layout | |
US20070093000A1 (en) | Pre-molded leadframe and method therefor | |
US20070164407A1 (en) | Double encapsulated semiconductor package and manufacturing method thereof | |
US8124459B2 (en) | Bump chip carrier semiconductor package system | |
US20040029318A1 (en) | Semiconductor device having contact prevention spacer | |
US20020173074A1 (en) | Method for underfilling bonding gap between flip-chip and circuit substrate | |
KR20200106001A (en) | Control of sub-charge for double-sided ball grid array packages | |
US9576873B2 (en) | Integrated circuit packaging system with routable trace and method of manufacture thereof | |
CN102104030A (en) | Rebuilt wafer assembly | |
US9761435B1 (en) | Flip chip cavity package | |
KR100922370B1 (en) | Substrate for manufacturing semiconductor package and, method for manufacturing semiconductor package using the same | |
US7763961B2 (en) | Hybrid stacking package system | |
US20090096070A1 (en) | Semiconductor package and substrate for the same | |
US9947605B2 (en) | Flip chip cavity package | |
CN113206071A (en) | Semiconductor package device and method of manufacturing the same | |
KR20040096371A (en) | Molding process in FBGA package | |
KR20070069753A (en) | Semiconductor chip stack package and packaging method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MISTRY, ADDI B.;MANGRUM, MARC A.;PATTEN, DAVID T.;AND OTHERS;REEL/FRAME:017391/0399;SIGNING DATES FROM 20051213 TO 20051216 |
|
AS | Assignment |
Owner name: CITIBANK, N.A. AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 Owner name: CITIBANK, N.A. AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037354/0225 Effective date: 20151207 |