US20070128800A1 - Use of chlorine to fabricate trench dielectric in integrated circuits - Google Patents
Use of chlorine to fabricate trench dielectric in integrated circuits Download PDFInfo
- Publication number
- US20070128800A1 US20070128800A1 US11/671,740 US67174007A US2007128800A1 US 20070128800 A1 US20070128800 A1 US 20070128800A1 US 67174007 A US67174007 A US 67174007A US 2007128800 A1 US2007128800 A1 US 2007128800A1
- Authority
- US
- United States
- Prior art keywords
- chlorine
- liner
- oxide
- silicon oxide
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000000460 chlorine Substances 0.000 title claims abstract description 32
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 title claims abstract description 30
- 229910052801 chlorine Inorganic materials 0.000 title claims abstract description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract 12
- 238000002955 isolation Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 description 16
- 239000000377 silicon dioxide Substances 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 230000003647 oxidation Effects 0.000 description 13
- 238000007254 oxidation reaction Methods 0.000 description 13
- 235000012239 silicon dioxide Nutrition 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 230000015654 memory Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- XSTXAVWGXDQKEL-UHFFFAOYSA-N Trichloroethylene Chemical compound ClC=C(Cl)Cl XSTXAVWGXDQKEL-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- UOCLXMDMGBRAIB-UHFFFAOYSA-N 1,1,1-trichloroethane Chemical compound CC(Cl)(Cl)Cl UOCLXMDMGBRAIB-UHFFFAOYSA-N 0.000 description 1
- WSLDOOZREJYCGB-UHFFFAOYSA-N 1,2-Dichloroethane Chemical group ClCCCl WSLDOOZREJYCGB-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 125000001309 chloro group Chemical group Cl* 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- UBOXGVDOUJQMTN-UHFFFAOYSA-N trichloroethylene Natural products ClCC(Cl)Cl UBOXGVDOUJQMTN-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates to integrated circuits, and more particularly to dielectric formed in trenches in a silicon substrate. Some embodiments are suitable for substrate isolation for integrated circuits.
- FIG. 1 illustrates an intermediate structure in a flash memory fabrication process using shallow trench isolation (STI).
- Silicon dioxide 110 (“pad oxide”) is thermally grown on silicon substrate 120 .
- Silicon nitride 130 is formed on oxide 110 and patterned photolithographically to define substrate isolation trenches 134 to be formed between active areas 140 .
- Oxide 110 and substrate 140 are etched through the openings in nitride 130 to form the isolation trenches.
- Silicon dioxide 150 is deposited to fill the trenches and cover the wafer.
- Oxide 150 is polished by chemical mechanical polishing (CMP) until the top surface of nitride 130 is exposed. A planar top wafer surface is provided.
- CMP chemical mechanical polishing
- Oxide 150 can be etched down ( FIG. 2 ) to achieve a more planar topography in subsequent steps.
- Nitride 130 and pad oxide 110 are etched away ( FIG. 3 ).
- Silicon dioxide 410 (“tunnel oxide”) is thermally grown to a desired thickness (e.g. 9 nm).
- a doped polysilicon layer 510 ( FIG. 5 ) is deposited on oxide layers 410 , 150 to provide the floating gates and is partially patterned.
- Dielectric 520 e.g. a sandwich of silicon dioxide, silicon nitride, silicon dioxide, i.e. ONO
- Doped polysilicon 530 is deposited on ONO 520 .
- Layers 530 , 520 , 510 are patterned together to create wordlines form the layer 530 and to finish the patterning of the floating gate.
- Source/drain regions 610 top view in FIG. 6
- the cross sectional plane of FIG. 5 is marked V-V in FIG. 6 .
- Floating gates 510 are shown with crosses in FIG. 6 .
- Additional layers are deposited and patterned to provide conductive bitlines contacting some of the source/drain regions. See e.g. U.S. Pat. No. 6,265,292 issued Jul. 24, 2001 to Parat et al. and incorporated herein by reference.
- the electric field is undesirably increased at sharp corners 140 C ( FIGS. 4, 5 ) during the circuit operation.
- the growth of tunnel oxide 410 ( FIG. 4 ) is retarded at these corners, so oxide 410 is thinner at the corners than in the middle of the active areas.
- the oxide thinning further increases the electric field at the corners, creating overerase and/or other problems (depending on the memory operation). See U.S. patent application published as no. US 2004/0014269 on Jan. 22, 2004, incorporated herein by reference. It is desirable to round the trench corners 410 C to provide a uniform thickness oxide 410 and reduce the electric field at the corners, as illustrated in FIG. 7 (showing the wafer with rounded corners 410 C at the stage of FIG. 1 ) and in FIG. 8 (the wafer with rounded corners at the stage of FIG. 3 ).
- oxide 150 can be formed by first growing a thin silicon dioxide liner on the trench surface by thermal oxidation. The oxidation rounds the corners 140 C. Then the rest of oxide 150 can be deposited (by a high density plasma process, i.e. HDP, or some other technique). The rounding should be controlled to minimize the active area consumption. If the corners are at the [111] crystallographic plane and the trench sidewalls are at [100], a chlorine source can be used in the liner formation to provide a desired rounding without an undue consumption of the active area. See PCT application published as WO 01/47010 on 28 Jun. 2001 and incorporated herein by reference.
- Some embodiments of the present invention incorporate chlorine into pad oxide 110 . It is well known that chlorine increases oxygen diffusion through silicon dioxide. Chlorine has also been used in silicon dioxide layers, at a concentration of at most three atomic percent, to immobilize metal atoms. In some embodiments of the present invention, chlorine incorporation into pad oxide 110 increases the oxygen diffusion through oxide 110 during the liner formation. This oxygen diffusion increases the oxidation rate at corners 410 C relative to the trench sidewalls, to create a desired rounded corner profile.
- the chlorine concentration in oxide 110 is more than three atomic percent.
- An exemplary range is 5 ⁇ 15 atomic percent. Greater concentrations can also be used. Some embodiments use 5 ⁇ 10 atomic percent of chlorine.
- the oxidation time is shortened to prevent undue consumption of the active area.
- the liner is very thin (3 ⁇ 10 nm in some embodiments).
- a second oxide liner is deposited by chemical vapor deposition (CVD), and then a third liner is thermally grown.
- the CVD liner protects the active areas from excessive oxidation when the third liner is being formed, but the corner rounding can be enhanced during the third liner fabrication.
- chlorine is incorporated into the CVD liner to speed up oxidation of the trench sidewall and bottom surfaces during the third liner fabrication and provide a desired corner profile.
- the CVD liner can be used with or without chlorine incorporation into pad oxide 110 .
- the invention is not limited to the features and advantages described above.
- the invention includes non-memory integrated circuits.
- the corner rounding techniques can be used with trenches other than STI trenches, and the invention is not limited to substrate isolation. Other features are described below.
- the invention is defined by the appended claims.
- FIGS. 1-5 show cross sections of prior art integrated circuits in the process of fabrication.
- FIG. 6 is a plan view of a prior art integrated circuit in the process of fabrication.
- FIGS. 7, 8 show cross sections of prior art integrated circuits in the process of fabrication.
- FIG. 9-14 show cross sections of integrated circuits in the process of fabrication according to some embodiments of the present invention.
- FIG. 9 illustrates initial STI fabrication stages in one embodiment of the present invention.
- Silicon dioxide layer 110 comprising chlorine atoms is formed on silicon wafer 120 .
- the chlorine concentration is more than three atomic percent, or at least 5 atomic percent. A range from 5 to 15 atomic percent is believed to be suitable, and other concentrations are possible.
- oxide 110 is formed by thermal oxidation at 800 ⁇ 1000° C.
- the oxygen flow is 10 ⁇ 5 l/m in (liters per minute).
- the chlorine is provided by hydrogen chloride (HCl) flown at 1 l/min.
- Other possible chlorine sources include the chlorine gas (Cl), TCA (trichloroethane, C 2 H 3 Cl 3 ), TCE (trichloroethylene, C 2 HCl 2 ), dichloroethylene (C 2 H 2 Cl 2 ).
- Other chlorine sources known or to be invented, may also be suitable.
- Oxide 110 can also be formed by CVD.
- dichlorosilane can be used: SiH 2 Cl 2 +2N 2 O ⁇ SiO 2 +2N 2 +2HCl.
- Oxygen is also flown in the reaction chamber, reacting with the hydrogen chloride (HCl) to form chlorine.
- Chlorine is incorporated into the SiO 2 layer 110 .
- Other fabrication techniques, known or to be invented, can also be used.
- An exemplary thickness of oxide 110 is 5 ⁇ 15 nm, but this is not limiting.
- Silicon nitride 130 is formed on oxide 110 by known techniques (e.g. CVD).
- An exemplary thickness of nitride 130 is 100 ⁇ 200 nm, but this is not limiting.
- a photoresist mask (not shown) is formed on nitride 130 and patterned to have openings over the positions of STI trenches 134 .
- Nitride 130 is etched through the openings to form a hard mask for the STI trenches.
- Oxide 110 and silicon 120 are etched through the openings in nitride 130 to form the trenches between active areas 140 .
- the trench depth is 0.3 ⁇ m.
- the trenches have sharp corners 140 C, but this is not necessary. Smoother corners can be obtained by suitably controlling the etch process, as described for example in U.S. patent application publication US 2004/0014269 A1 published Jan. 22, 2004 and incorporated herein by reference.
- the etch can be anisotropic (e.g. RIE).
- the silicon substrate etch can be controlled to provide vertical or sloped sidewalls for the trenches. In some embodiments, the trench sidewalls are at 60 ⁇ 9° to the horizontal. See the aforementioned U.S. publication 2004/0014269 A1 and U.S. Pat. No. 6,265,292.
- the wafer is oxidized to form a silicon dioxide liner 150 . 1 ( FIG. 10 ) on the trenches' silicon surfaces.
- the liner is formed by dry oxidation at 850 ⁇ 1050° C. Other oxidation processes can also be used. Oxygen diffuses through the exposed sidewalls of pad oxide 110 to round the top trench corners 140 C. The bottom corners also become a little rounded.
- the oxidation is shortened to avoid undue consumption of active areas 140 . This is particularly desirable if the active areas are narrow.
- the active area width is 0.065 ⁇ 0.18 ⁇ m, and smaller widths are also possible.
- the liner 150 . 1 is only 3 ⁇ 10 nm thick in some embodiments.
- additional thermal oxide is desirable to provide better isolation and more rounding of the top and bottom corners of the trenches.
- a silicon dioxide liner 150 . 2 ( FIG. 11 ) is formed by CVD on the wafer to protect the active areas.
- layer 150 . 2 incorporates chlorine for control of the top corner profile during the subsequent thermal oxidation.
- An exemplary thickness of layer 150 . 2 is 3 ⁇ 20 nm, and the chlorine concentration is 10 13 ⁇ 10 14 atoms/cm 2 , or 1 ⁇ 10 atomic percent.
- the wafer is oxidized to grow the additional thermal silicon dioxide layer 150 . 3 ( FIG. 12 ) on the trench surface.
- a low oxidation rate is achieved by diluting oxygen in nitrogen or argon to a volume concentration of 10%.
- the oxidation temperature is 900 ⁇ 1050° C.
- the thickness of layer 150 . 3 is 1 ⁇ 5 nm. Other processes are also possible.
- the appropriate values for the thickness of layers 110 , 150 . 1 , 150 . 2 , 150 . 3 and the chlorine concentration in layers 110 , 150 . 2 may depend on the trench and active area dimensions, the fabrication equipment, and desired circuit characteristics. In each case, the appropriate thicknesses and chlorine concentrations can be determined experimentally to obtain the desired corner rounding and thickness uniformity for oxide 410 ( FIG. 14 ).
- silicon dioxide 150 . 4 ( FIG. 13 ) is deposited by HDP to fill the trenches and cover the wafer.
- Oxide layers 150 . 4 , 150 . 2 are polished by CMP to expose the nitride 130 .
- Oxide 150 . 4 , 150 . 2 is etched down (as in FIG. 2 ).
- Nitride 130 and pad oxide 110 are removed.
- Tunnel oxide 410 ( FIG. 14 ) is thermally grown to a desired thickness.
- Layers 510 , 520 , 530 are deposited and patterned as described above, and the doping steps are performed, to form the structure of FIG. 6 .
- the invention is not limited to the embodiments described above.
- the invention is not limited to nonvolatile memories, MOS circuits, or substrate isolation.
- Other embodiments and variations are within the scope of the invention, as defined by the appended claims.
Abstract
Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide liner (150.1) is thermally grown on the trench surfaces. A second silicon oxide liner (150.2) incorporating chlorine is deposited by CVD over the first liner (150.1), and then a third liner (150.3) is thermally grown. The chlorine concentration in the second liner (150.2) and the thickness of the three liners (150.1, 150.2, 150.3) are controlled to improve the corner rounding without consuming too much of the active areas (140).
Description
- The present application is a division of U.S. patent application Ser. No. 11/174,081 filed on Jun. 30, 2005, incorporated herein by reference.
- The present invention relates to integrated circuits, and more particularly to dielectric formed in trenches in a silicon substrate. Some embodiments are suitable for substrate isolation for integrated circuits.
-
FIG. 1 illustrates an intermediate structure in a flash memory fabrication process using shallow trench isolation (STI). Silicon dioxide 110 (“pad oxide”) is thermally grown onsilicon substrate 120.Silicon nitride 130 is formed onoxide 110 and patterned photolithographically to definesubstrate isolation trenches 134 to be formed betweenactive areas 140.Oxide 110 andsubstrate 140 are etched through the openings innitride 130 to form the isolation trenches.Silicon dioxide 150 is deposited to fill the trenches and cover the wafer.Oxide 150 is polished by chemical mechanical polishing (CMP) until the top surface ofnitride 130 is exposed. A planar top wafer surface is provided. -
Oxide 150 can be etched down (FIG. 2 ) to achieve a more planar topography in subsequent steps. Nitride 130 andpad oxide 110 are etched away (FIG. 3 ). Silicon dioxide 410 (“tunnel oxide”) is thermally grown to a desired thickness (e.g. 9 nm). A doped polysilicon layer 510 (FIG. 5 ) is deposited onoxide layers Doped polysilicon 530 is deposited on ONO 520.Layers layer 530 and to finish the patterning of the floating gate. Source/drain regions 610 (top view inFIG. 6 ) are formed on each side of each floating gate. The cross sectional plane ofFIG. 5 is marked V-V inFIG. 6 . Floatinggates 510 are shown with crosses in FIG. 6. Additional layers (not shown) are deposited and patterned to provide conductive bitlines contacting some of the source/drain regions. See e.g. U.S. Pat. No. 6,265,292 issued Jul. 24, 2001 to Parat et al. and incorporated herein by reference. - The electric field is undesirably increased at
sharp corners 140C (FIGS. 4, 5 ) during the circuit operation. In addition, the growth of tunnel oxide 410 (FIG. 4 ) is retarded at these corners, sooxide 410 is thinner at the corners than in the middle of the active areas. The oxide thinning further increases the electric field at the corners, creating overerase and/or other problems (depending on the memory operation). See U.S. patent application published as no. US 2004/0014269 on Jan. 22, 2004, incorporated herein by reference. It is desirable to round the trench corners 410C to provide auniform thickness oxide 410 and reduce the electric field at the corners, as illustrated inFIG. 7 (showing the wafer with rounded corners 410C at the stage ofFIG. 1 ) and inFIG. 8 (the wafer with rounded corners at the stage ofFIG. 3 ). - To round the
corners 140C,oxide 150 can be formed by first growing a thin silicon dioxide liner on the trench surface by thermal oxidation. The oxidation rounds thecorners 140C. Then the rest ofoxide 150 can be deposited (by a high density plasma process, i.e. HDP, or some other technique). The rounding should be controlled to minimize the active area consumption. If the corners are at the [111] crystallographic plane and the trench sidewalls are at [100], a chlorine source can be used in the liner formation to provide a desired rounding without an undue consumption of the active area. See PCT application published as WO 01/47010 on 28 Jun. 2001 and incorporated herein by reference. - Improved corner rounding techniques for flash memories and other integrated circuits are desirable.
- This section summarizes some features of the invention. Other features are described in the subsequent sections. The invention is defined by the appended claims which are incorporated into this section by reference.
- Some embodiments of the present invention incorporate chlorine into
pad oxide 110. It is well known that chlorine increases oxygen diffusion through silicon dioxide. Chlorine has also been used in silicon dioxide layers, at a concentration of at most three atomic percent, to immobilize metal atoms. In some embodiments of the present invention, chlorine incorporation intopad oxide 110 increases the oxygen diffusion throughoxide 110 during the liner formation. This oxygen diffusion increases the oxidation rate at corners 410C relative to the trench sidewalls, to create a desired rounded corner profile. - In some embodiments, the chlorine concentration in
oxide 110 is more than three atomic percent. An exemplary range is 5˜15 atomic percent. Greater concentrations can also be used. Some embodiments use 5˜10 atomic percent of chlorine. - In some embodiments, the oxidation time is shortened to prevent undue consumption of the active area. Hence the liner is very thin (3˜10 nm in some embodiments). After the liner formation, a second oxide liner is deposited by chemical vapor deposition (CVD), and then a third liner is thermally grown. The CVD liner protects the active areas from excessive oxidation when the third liner is being formed, but the corner rounding can be enhanced during the third liner fabrication. In some embodiments, chlorine is incorporated into the CVD liner to speed up oxidation of the trench sidewall and bottom surfaces during the third liner fabrication and provide a desired corner profile. The CVD liner can be used with or without chlorine incorporation into
pad oxide 110. - The invention is not limited to the features and advantages described above. The invention includes non-memory integrated circuits. The corner rounding techniques can be used with trenches other than STI trenches, and the invention is not limited to substrate isolation. Other features are described below. The invention is defined by the appended claims.
-
FIGS. 1-5 show cross sections of prior art integrated circuits in the process of fabrication. -
FIG. 6 is a plan view of a prior art integrated circuit in the process of fabrication. -
FIGS. 7, 8 show cross sections of prior art integrated circuits in the process of fabrication. -
FIG. 9-14 show cross sections of integrated circuits in the process of fabrication according to some embodiments of the present invention. - The embodiments described in this section illustrate but do not limit the invention. The invention is not limited to particular fabrication techniques or numerical values and ranges. The invention is defined by the appended claims.
-
FIG. 9 illustrates initial STI fabrication stages in one embodiment of the present invention.Silicon dioxide layer 110 comprising chlorine atoms is formed onsilicon wafer 120. In some embodiments, the chlorine concentration is more than three atomic percent, or at least 5 atomic percent. A range from 5 to 15 atomic percent is believed to be suitable, and other concentrations are possible. - In one embodiment,
oxide 110 is formed by thermal oxidation at 800˜1000° C. The oxygen flow is 10±5 l/m in (liters per minute). The chlorine is provided by hydrogen chloride (HCl) flown at 1 l/min. Other possible chlorine sources include the chlorine gas (Cl), TCA (trichloroethane, C2H3Cl3), TCE (trichloroethylene, C2HCl2), dichloroethylene (C2H2Cl2). Other chlorine sources, known or to be invented, may also be suitable. -
Oxide 110 can also be formed by CVD. For example, dichlorosilane can be used:
SiH2Cl2+2N2O→SiO2+2N2+2HCl.
Oxygen is also flown in the reaction chamber, reacting with the hydrogen chloride (HCl) to form chlorine. Chlorine is incorporated into the SiO2 layer 110. Other fabrication techniques, known or to be invented, can also be used. An exemplary thickness ofoxide 110 is 5˜15 nm, but this is not limiting. -
Silicon nitride 130 is formed onoxide 110 by known techniques (e.g. CVD). An exemplary thickness ofnitride 130 is 100˜200 nm, but this is not limiting. - A photoresist mask (not shown) is formed on
nitride 130 and patterned to have openings over the positions ofSTI trenches 134.Nitride 130 is etched through the openings to form a hard mask for the STI trenches.Oxide 110 andsilicon 120 are etched through the openings innitride 130 to form the trenches betweenactive areas 140. In some embodiments, the trench depth is 0.3 μm. In some embodiments, the trenches havesharp corners 140C, but this is not necessary. Smoother corners can be obtained by suitably controlling the etch process, as described for example in U.S. patent application publication US 2004/0014269 A1 published Jan. 22, 2004 and incorporated herein by reference. The etch can be anisotropic (e.g. RIE). The silicon substrate etch can be controlled to provide vertical or sloped sidewalls for the trenches. In some embodiments, the trench sidewalls are at 60˜9° to the horizontal. See the aforementioned U.S. publication 2004/0014269 A1 and U.S. Pat. No. 6,265,292. - The wafer is oxidized to form a silicon dioxide liner 150.1 (
FIG. 10 ) on the trenches' silicon surfaces. In some embodiments, the liner is formed by dry oxidation at 850˜1050° C. Other oxidation processes can also be used. Oxygen diffuses through the exposed sidewalls ofpad oxide 110 to round thetop trench corners 140C. The bottom corners also become a little rounded. - In some embodiments, the oxidation is shortened to avoid undue consumption of
active areas 140. This is particularly desirable if the active areas are narrow. In some embodiments, the active area width is 0.065˜0.18 μm, and smaller widths are also possible. The liner 150.1 is only 3˜10 nm thick in some embodiments. - In some embodiments, additional thermal oxide is desirable to provide better isolation and more rounding of the top and bottom corners of the trenches. Before growing the additional thermal oxide however, a silicon dioxide liner 150.2 (
FIG. 11 ) is formed by CVD on the wafer to protect the active areas. In some embodiments, layer 150.2 incorporates chlorine for control of the top corner profile during the subsequent thermal oxidation. An exemplary thickness of layer 150.2 is 3˜20 nm, and the chlorine concentration is 1013˜1014 atoms/cm2, or 1˜10 atomic percent. Other thickness and concentration parameters and also possible, and can be selected experimentally to obtain a desired profile fortop corners 140C and a desired thickness uniformity for subsequently grown tunnel oxide 410 (FIG. 14 ). - The wafer is oxidized to grow the additional thermal silicon dioxide layer 150.3 (
FIG. 12 ) on the trench surface. In some embodiments, a low oxidation rate is achieved by diluting oxygen in nitrogen or argon to a volume concentration of 10%. The oxidation temperature is 900˜1050° C. The thickness of layer 150.3 is 1˜5 nm. Other processes are also possible. - In each case, the appropriate values for the thickness of
layers 110, 150.1, 150.2, 150.3 and the chlorine concentration inlayers 110, 150.2 may depend on the trench and active area dimensions, the fabrication equipment, and desired circuit characteristics. In each case, the appropriate thicknesses and chlorine concentrations can be determined experimentally to obtain the desired corner rounding and thickness uniformity for oxide 410 (FIG. 14 ). - The remaining fabrication processes can be conventional. In one embodiment, silicon dioxide 150.4 (
FIG. 13 ) is deposited by HDP to fill the trenches and cover the wafer. Oxide layers 150.4, 150.2 are polished by CMP to expose thenitride 130. Oxide 150.4, 150.2 is etched down (as inFIG. 2 ).Nitride 130 andpad oxide 110 are removed. Tunnel oxide 410 (FIG. 14 ) is thermally grown to a desired thickness.Layers FIG. 6 . - The invention is not limited to the embodiments described above. The invention is not limited to nonvolatile memories, MOS circuits, or substrate isolation. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.
Claims (8)
1. An integrated circuit comprising:
a silicon substrate having a trench therein;
a first dielectric in the trench, the first dielectric comprising:
a first silicon oxide portion on a surface of the trench; and
a second silicon oxide portion separated from the surface of the trench by the first silicon oxide portion, the second silicon oxide portion comprising chlorine at a higher concentration than the first silicon oxide portion.
2. The integrated circuit of claim 1 wherein the first silicon oxide portion does not comprise chlorine.
3. The integrated circuit of claim 1 wherein the chlorine concentration in the second silicon oxide portion is at least 1 atomic percent.
4. The integrated circuit of claim 3 wherein the chlorine concentration in the second silicon oxide portion is at most 10 atomic percent.
5. The integrated circuit of claim 1 wherein the chlorine concentration in the second silicon oxide portion is at least 1013 atoms/cm2.
6. The integrated circuit of claim 5 wherein the chlorine concentration in the second silicon oxide portion is at most 1014 atoms/cm2.
7. The integrated circuit of claim 1 wherein the first dielectric isolates adjacent active areas of the substrate from each other.
8. The integrated circuit of claim 1 wherein further comprising a transistor active area in the substrate adjacent to the trench.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/671,740 US20070128800A1 (en) | 2005-06-30 | 2007-02-06 | Use of chlorine to fabricate trench dielectric in integrated circuits |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/174,081 US7265015B2 (en) | 2005-06-30 | 2005-06-30 | Use of chlorine to fabricate trench dielectric in integrated circuits |
US11/671,740 US20070128800A1 (en) | 2005-06-30 | 2007-02-06 | Use of chlorine to fabricate trench dielectric in integrated circuits |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/174,081 Division US7265015B2 (en) | 2005-06-30 | 2005-06-30 | Use of chlorine to fabricate trench dielectric in integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070128800A1 true US20070128800A1 (en) | 2007-06-07 |
Family
ID=37590119
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/174,081 Active 2025-11-19 US7265015B2 (en) | 2005-06-30 | 2005-06-30 | Use of chlorine to fabricate trench dielectric in integrated circuits |
US11/671,740 Abandoned US20070128800A1 (en) | 2005-06-30 | 2007-02-06 | Use of chlorine to fabricate trench dielectric in integrated circuits |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/174,081 Active 2025-11-19 US7265015B2 (en) | 2005-06-30 | 2005-06-30 | Use of chlorine to fabricate trench dielectric in integrated circuits |
Country Status (3)
Country | Link |
---|---|
US (2) | US7265015B2 (en) |
CN (1) | CN100433291C (en) |
TW (1) | TWI302361B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080001209A1 (en) * | 2006-06-29 | 2008-01-03 | Cho Eun-Suk | Non-volatile memory device and method of manufacturing the non-volatile memory device |
US8551877B2 (en) * | 2012-03-07 | 2013-10-08 | Tokyo Electron Limited | Sidewall and chamfer protection during hard mask removal for interconnect patterning |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060228492A1 (en) * | 2005-04-07 | 2006-10-12 | Sumco Corporation | Method for manufacturing SIMOX wafer |
KR100673021B1 (en) * | 2005-12-23 | 2007-01-24 | 삼성전자주식회사 | Non-volatile memory devices having floating gate and methods of forming the same |
US8936995B2 (en) * | 2006-03-01 | 2015-01-20 | Infineon Technologies Ag | Methods of fabricating isolation regions of semiconductor devices and structures thereof |
US7737487B2 (en) * | 2008-06-06 | 2010-06-15 | Promos Technologies Pte. Ltd. | Nonvolatile memories with tunnel dielectric with chlorine |
JP6200818B2 (en) * | 2014-01-21 | 2017-09-20 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP2015179729A (en) * | 2014-03-19 | 2015-10-08 | 東京エレクトロン株式会社 | Method for forming silicon oxide film, and device for forming silicon oxide film |
CN105405809B (en) * | 2014-09-12 | 2018-06-19 | 上海格易电子有限公司 | A kind of manufacturing method of flash memory |
US10177185B2 (en) * | 2015-05-07 | 2019-01-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | High dielectric constant dielectric layer forming method, image sensor device, and manufacturing method thereof |
TWI714423B (en) * | 2020-01-08 | 2020-12-21 | 華邦電子股份有限公司 | Semiconductor structure and method of manufacturing the same |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006477A (en) * | 1988-11-25 | 1991-04-09 | Hughes Aircraft Company | Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices |
US5244843A (en) * | 1991-12-17 | 1993-09-14 | Intel Corporation | Process for forming a thin oxide layer |
US6274442B1 (en) * | 1998-07-15 | 2001-08-14 | Advanced Micro Devices, Inc. | Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same |
US20020024119A1 (en) * | 1999-01-08 | 2002-02-28 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6455389B1 (en) * | 2001-06-01 | 2002-09-24 | Kuo-Tai Huang | Method for preventing a by-product ion moving from a spacer |
US6562713B1 (en) * | 2002-02-19 | 2003-05-13 | International Business Machines Corporation | Method of protecting semiconductor areas while exposing a gate |
US20040108524A1 (en) * | 2002-12-09 | 2004-06-10 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
US6956237B2 (en) * | 2002-12-28 | 2005-10-18 | Lg.Philips Lcd Co., Ltd. | Thin film transistor array substrate and method for manufacturing the same |
US7001844B2 (en) * | 2004-04-30 | 2006-02-21 | International Business Machines Corporation | Material for contact etch layer to enhance device performance |
US7005714B2 (en) * | 2003-07-04 | 2006-02-28 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and manufacturing method for the same |
US20070034876A1 (en) * | 1996-12-27 | 2007-02-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US7199063B2 (en) * | 2003-05-08 | 2007-04-03 | Ching-Wei Lin | Process for passivating polysilicon and process for fabricating polysilicon thin film transistor |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6265292B1 (en) * | 1999-07-12 | 2001-07-24 | Intel Corporation | Method of fabrication of a novel flash integrated circuit |
KR100338767B1 (en) * | 1999-10-12 | 2002-05-30 | 윤종용 | Trench Isolation structure and semiconductor device having the same, trench isolation method |
US6150234A (en) | 1999-12-16 | 2000-11-21 | Vlsi Technology, Inc. | Trench-diffusion corner rounding in a shallow-trench (STI) process |
CN1140922C (en) * | 2001-06-18 | 2004-03-03 | 矽统科技股份有限公司 | Method for elimianting leakage current of shallow channel isolation area |
US6566282B2 (en) * | 2001-06-21 | 2003-05-20 | United Microelectronics Corp. | Method of forming a silicon oxide layer |
KR100466195B1 (en) * | 2002-07-18 | 2005-01-13 | 주식회사 하이닉스반도체 | Method for manufacturing flash memory |
US6734082B2 (en) * | 2002-08-06 | 2004-05-11 | Chartered Semiconductor Manufacturing Ltd. | Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape |
-
2005
- 2005-06-30 US US11/174,081 patent/US7265015B2/en active Active
-
2006
- 2006-04-27 CN CNB2006100745429A patent/CN100433291C/en not_active Expired - Fee Related
- 2006-05-03 TW TW095115797A patent/TWI302361B/en active
-
2007
- 2007-02-06 US US11/671,740 patent/US20070128800A1/en not_active Abandoned
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006477A (en) * | 1988-11-25 | 1991-04-09 | Hughes Aircraft Company | Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices |
US5244843A (en) * | 1991-12-17 | 1993-09-14 | Intel Corporation | Process for forming a thin oxide layer |
US20070034876A1 (en) * | 1996-12-27 | 2007-02-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US6274442B1 (en) * | 1998-07-15 | 2001-08-14 | Advanced Micro Devices, Inc. | Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same |
US20020024119A1 (en) * | 1999-01-08 | 2002-02-28 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6455389B1 (en) * | 2001-06-01 | 2002-09-24 | Kuo-Tai Huang | Method for preventing a by-product ion moving from a spacer |
US6562713B1 (en) * | 2002-02-19 | 2003-05-13 | International Business Machines Corporation | Method of protecting semiconductor areas while exposing a gate |
US20040108524A1 (en) * | 2002-12-09 | 2004-06-10 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
US6956237B2 (en) * | 2002-12-28 | 2005-10-18 | Lg.Philips Lcd Co., Ltd. | Thin film transistor array substrate and method for manufacturing the same |
US7199063B2 (en) * | 2003-05-08 | 2007-04-03 | Ching-Wei Lin | Process for passivating polysilicon and process for fabricating polysilicon thin film transistor |
US7005714B2 (en) * | 2003-07-04 | 2006-02-28 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and manufacturing method for the same |
US7001844B2 (en) * | 2004-04-30 | 2006-02-21 | International Business Machines Corporation | Material for contact etch layer to enhance device performance |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080001209A1 (en) * | 2006-06-29 | 2008-01-03 | Cho Eun-Suk | Non-volatile memory device and method of manufacturing the non-volatile memory device |
US8551877B2 (en) * | 2012-03-07 | 2013-10-08 | Tokyo Electron Limited | Sidewall and chamfer protection during hard mask removal for interconnect patterning |
Also Published As
Publication number | Publication date |
---|---|
TW200703553A (en) | 2007-01-16 |
TWI302361B (en) | 2008-10-21 |
CN1893015A (en) | 2007-01-10 |
US20070004136A1 (en) | 2007-01-04 |
US7265015B2 (en) | 2007-09-04 |
CN100433291C (en) | 2008-11-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7265015B2 (en) | Use of chlorine to fabricate trench dielectric in integrated circuits | |
US7745303B2 (en) | Method of manufacturing a semiconductor device and the semiconductor device | |
US7772671B2 (en) | Semiconductor device having an element isolating insulating film | |
US7709346B2 (en) | Semiconductor device with trench gate type transistor and method of manufacturing the same | |
US5872045A (en) | Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation | |
KR100371252B1 (en) | Film Flattening Method in Semiconductor Devices | |
US7176104B1 (en) | Method for forming shallow trench isolation structure with deep oxide region | |
KR20080001413A (en) | Method for manufacturing flash memory device | |
US6667227B1 (en) | Trenched gate metal oxide semiconductor device and method | |
US6537914B1 (en) | Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing | |
JP2008010481A (en) | Semiconductor device, and manufacturing method thereof | |
US20060223280A1 (en) | Method for manufacturing semiconductor device and semiconductor device | |
US6248641B1 (en) | Method of fabricating shallow trench isolation | |
US6744113B2 (en) | Semiconductor device with element isolation using impurity-doped insulator and oxynitride film | |
JP4330671B2 (en) | Manufacturing method of semiconductor device | |
US6180463B1 (en) | Method for fabricating a multi-level mask ROM | |
US6207515B1 (en) | Method of fabricating buried source to shrink chip size in memory array | |
US6387814B1 (en) | Method of fabricating a stringerless flash memory | |
US6828209B1 (en) | Methods for manufacturing a semiconductor device including a trench isolation region | |
US20090321821A1 (en) | Semiconductor device having recess gate and method of fabricating the same | |
KR20050063266A (en) | Method for forming shallow trench isolation in semiconductor device processing | |
US6440819B1 (en) | Method for differential trenching in conjunction with differential fieldox growth | |
US7061128B2 (en) | Semiconductor device and manufacturing method of the same | |
KR100780620B1 (en) | Semiconductor device with recess gate and method for fabricating the same | |
JP2003273207A (en) | Method of manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |