US20070099432A1 - Method for photolithography in semiconductor manufacturing - Google Patents
Method for photolithography in semiconductor manufacturing Download PDFInfo
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- US20070099432A1 US20070099432A1 US11/347,513 US34751306A US2007099432A1 US 20070099432 A1 US20070099432 A1 US 20070099432A1 US 34751306 A US34751306 A US 34751306A US 2007099432 A1 US2007099432 A1 US 2007099432A1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
- G03F7/405—Treatment with inorganic or organometallic reagents after imagewise removal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Definitions
- DOF depth of focus
- An effective DOF will cover all the variations of photoresist. thickness, local substrate topology step height, and wafer center and edge step height differences.
- An effective DOF facilitates manufacturing a semiconductor device within a desired critical dimension (CD) specification with little or no scum or top loss defects.
- photoresist that is thicker than the DOF. For example, if the DOF is less than the thickness of the photoresist layer plus step height variation, scum or CD errors may occur in some of the patterns formed on the semiconductor devices. Therefore, thin layers of photoresist may be desired to counter this problem. Such thin photoresist layers may also be desirable for low dosage exposure tools, such as an e-beam or extreme ultraviolet (EUV) tools, as they may improve resist contrast, resolution, and dissolution. Moreover, for mass production purposes, the combination of thin photoresist layers and low dosage exposure tools can increase the throughput of semiconductor devices.
- EUV extreme ultraviolet
- a thin photoresist layer may adversely affect etching performance if it does not provide sufficient protection during the etch process.
- a two step process may be used. For example, a relatively thin photo sensitive layer may be formed over a thick buffer layer. The photo sensitive layer is developed to form a predefined pattern, and the buffer layer is then etched to correspond to the pattern formed by the photo sensitive layer. The buffer layer then serves as an etch stop layer during etching of the substrate. Accordingly, two removal steps (developing and etching) are needed to reach the substrate prior to etching the substrate.
- FIG. 1 illustrates a method for implementing one embodiment of the present invention during semiconductor manufacturing.
- FIG. 2 is a perspective view of one embodiment of a partial semiconductor device with a photo sensitive layer overlying other layers undergoing manufacturing using the method of FIG. 1 .
- FIG. 3 is a perspective view of the partial semiconductor device of FIG. 2 illustrating a pattern formed on the photosensitive layer.
- FIG. 4 is a perspective view of the partial semiconductor device of FIG. 3 after development of the photo sensitive layer based on the pattern.
- FIG. 5 is a perspective view of the partial semiconductor device of FIG. 4 after the formation of a second layer on the developed photo sensitive layer.
- FIG. 6 is a perspective view of the partial semiconductor device of FIG. 5 after using the second layer as a mask during etching of the layer underlying the developed photo sensitive layer.
- FIG. 7 is a perspective view of the partial semiconductor device of FIG. 6 after removal of the second layer and photo sensitive layer.
- FIG. 8 illustrates a method for implementing another embodiment of the present invention during semiconductor manufacturing.
- FIG. 9 is a perspective view of one embodiment of a partial semiconductor device with a photo sensitive layer overlying other layers undergoing manufacturing using the method of FIG. 8 .
- FIG. 10 is a perspective view of the partial semiconductor device of FIG. 10 after development of the photo sensitive layer based on a pattern.
- FIG. 11 is a perspective view of the partial semiconductor device of FIG. 10 after the formation of a second layer on a seed layer defined by the pattern.
- FIG. 12 is a perspective view of the partial semiconductor device of FIG. 11 after the remaining portions of the photosensitive layer have been removed.
- FIG. 13 is a perspective view of the partial semiconductor device of FIG. 12 after using the second layer as a mask during etching of the layer underlying the developed photo sensitive layer.
- FIG. 14 is a perspective view of the partial semiconductor device of FIG. 13 after removal of the second layer.
- FIG. 15 is a perspective view of another embodiment of the partial semiconductor device of FIG. 9 .
- first and second features are formed in direct contact
- additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
- a method 100 may be used to obtain the benefits of a relatively thin photo sensitive layer while reducing the number of development/etch steps generally needed when using a photo sensitive layer and a buffer/etch stop layer.
- the method 100 is described in conjunction with FIGS. 2-7 , which illustrate one embodiment of a semiconductor device 200 undergoing manufacture using the method 100 . It is understood that the semiconductor device 200 is only one example of a device that may be manufactured using the method 100 , and that other steps (e.g., rinsing) may be performed in addition to the steps described.
- a photo sensitive layer 206 (e.g., a photoresist) is formed on an underlying layer 204 .
- the layer 204 is positioned above another layer 202 .
- the layer 204 may be formed of one or more insulator, conductor, and/or semiconductor layers.
- the layer 204 may be formed of a conductor
- the layer 202 may be formed of an insulator having vias (not shown) that connect the layer 204 to conductive material (not shown) under the layer 202 .
- the layer 204 may be an insulator layer and the layer 202 may be a conductive layer.
- the layer 202 may be absent, and the layer 204 may include an elementary semiconductor material, such as crystal silicon, polycrystalline silicon, amorphous silicon, and/or germanium; a compound semiconductor, such as silicon carbide and/or gallium arsenic; or an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, and/or GaInP.
- the layer 204 may include a bulk semiconductor, such as bulk silicon, and such a bulk semiconductor may include an epi silicon layer. It may also or alternatively include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, or a thin-film transistor (TFT) substrate.
- SOI silicon-on-insulator
- TFT thin-film transistor
- the layer 204 may also or alternatively include a multiple silicon structure or a multilayer compound semiconductor structure.
- the formation of the photo sensitive layer 206 includes the deposition of a resist material (e.g., a positive resist or a negative resist); a polymer layer; and/or any other suitable materials.
- a resist material e.g., a positive resist or a negative resist
- the photo sensitive layer 206 is formed from a positive photoresist material and has a thickness of between 100 and 2000 angstroms.
- the resist material may be deposited and distributed over the surface of the layer 204 by a spin-on coating process and/or other processes.
- the photo sensitive layer 206 may be a chemically amplified resist that employs acid catalysis.
- a pattern 300 is formed on the photo sensitive layer 206 ( FIG. 3 ) and the photo sensitive layer 206 is then developed ( FIG. 4 ).
- the pattern may include lines, spaces, holes (e.g., vias), islands, or any other pattern.
- the photosensitive layer 206 may undergo a development process to form a resist image as a seed layer 400 .
- the resist is selected to be responsive to the photo sensitive material and provide a bond for subsequent process to grow thicker buffer layer from this resist image.
- the seed layer 400 is approximately 100 to 2000 angstroms thick.
- a layer 500 may be formed on the seed layer 400 . It is understood that, in the present embodiment, the layer 500 is formed only on the seed layer 400 and not on the exposed surfaces of the layer 204 .
- the layer 500 may be formed using a variety of methods, and may be thicker and/or harder than the seed layer 400 after formation. As will be described below, the layer 500 may be used as an etch stop layer for a later etching process. Accordingly, the materials used to form the etch stop layer 500 may depend on the composition of the underlying layer to be etched (e.g., the layer 204 ) and the process used to etch the underlying layer.
- the materials forming the etch stop layer 500 may be selected to have a particular composition if the layer 204 is a metal layer etched using a wet etch process, and a different composition if the layer 204 is an oxide layer etched using a dry etch process.
- the layer 500 may be formed by exposing the seed layer 400 to a solution with a PH value of less than 7 or, in another example, with a PH value of 7 or greater.
- the second layer 500 may be developed in a plasma environment using a process such as CVD.
- laser pulse vaporization may be utilized to selectively deposit the layer 500 using the seed layer 400 .
- the layer 500 may be formed by the use of long-chain molecules or long-chain polymer(s) in the Z direction as indicated in FIG. 5 .
- the long-chain molecules or polymers may include one or more carbon nanotubes, one or more ZnO nanotubes, aligned long-chain molecules, one or more aligned long-chain polymers, and/or any other suitable materials.
- the thickness of the second layer 202 may be approximately between about 200 and about 600 nanometers.
- electro-less plating may be used to develop the etch stop layer.
- metal particles may be mixed into the photoresist to provide a metal base for electrode plating.
- the layer 204 is etched using the layer 500 as an etch stop layer.
- the etching process may use one or more etching steps, including dry etching, wet etching, and/or other etching methods.
- etching may be stopped when a desired amount of the layer 204 has been removed and the etching need not remove all of the exposed layer 204 .
- the seed layer 400 and etch stop layer 500 may be removed by wet chemical etch and/or dry etch process.
- an etch stop layer may be formed using a single development/etching step. It is understood that additional steps may be performed in order to complete the semiconductor device 200 . Since those additional steps are known in the art and may vary depending on the specifics of the semiconductor device 200 being formed, they will not be further described herein. Furthermore, it is noted that many variations of the above example are contemplated herein. In one example, instead of utilizing the second layer 204 for etching purposes, it may be used for implanting purposes. In a second example, the second layer 204 may be a separate layer formed over the seed layer 400 . In a third example, the second layer 204 may include the seed layer 400 . Accordingly, a variety of modifications are contemplated by this disclosure.
- a method 800 may be used to obtain the benefits of a relatively thin photo sensitive layer while reducing the number of development/etch steps generally needed when using a photo sensitive layer and a buffer/etch stop layer.
- the method 800 is described in conjunction with FIGS. 9-14 , which illustrate one embodiment of a semiconductor device 900 undergoing manufacture using the method 800 . It is understood that the semiconductor device 900 is only one example of a device that may be manufactured using the method 800 , and that other steps (e.g., rinsing) may be performed in addition to the steps described.
- a photo sensitive layer 906 (e.g., a photoresist) is formed on an underlying layer 904 .
- the layer 904 may be formed of one or more insulator, conductor, and/or semiconductor layers.
- the layer 904 may be formed of a conductor, and the layer 902 may be formed of an insulator having vias (not shown) that connect the layer 904 to conductive material (not shown) under the layer 902 .
- the layer 904 may be an insulator layer and the layer 902 may be a conductive layer.
- the layer 902 may be absent, and the layer 904 may include an elementary semiconductor material, such as crystal silicon, polycrystalline silicon, amorphous silicon, and/or germanium; a compound semiconductor, such as silicon carbide and/or gallium arsenic; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, and/or GaInP.
- the layer 904 may include a bulk semiconductor, such as bulk silicon, and such a bulk semiconductor may include an epi silicon layer. It may also or alternatively include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, or a thin-film transistor (TFT) substrate.
- SOI silicon-on-insulator
- TFT thin-film transistor
- the layer 904 may also or alternatively include a multiple silicon structure or a multilayer compound semiconductor structure.
- the formation of the photo sensitive layer 906 includes the deposition of a resist material (e.g., a positive resist or a negative resist); a polymer layer; and/or any other suitable materials.
- a resist material e.g., a positive resist or a negative resist
- the photo sensitive layer 906 is formed from a negative photoresist material and has a thickness of between about 100 and about 2000 angstroms.
- the resist material may be deposited and distributed over the surface of the layer 904 by a spin-on coating process and/or other processes.
- a pattern. 908 is formed on the photo sensitive layer 906 ( FIG. 9 ) and the photo sensitive layer 906 is then developed ( FIG. 10 ).
- the pattern may include lines, spaces, holes (e.g., vias), islands, or any other pattern. Because the photoresist layer 906 is formed from negative photoresist, the pattern 908 indicates areas where the photoresist is developed in order to be removed. Once removed, openings 1000 expose the metal of the underlying metal layer 904 . After patterning and developing, the layer 904 may undergo a deposit or dip process to form a seed layer 1100 selectively on the exposed portions of the layer 904 ( FIG. 11 ).
- the layer 904 itself may serve as a seed layer, obviating the need for the formation of a seed layer.
- the layer 904 may function as electrode plating and the etch stop layer 1102 may be formed therefrom using known electrode plating processes.
- a layer 1102 may be formed on the seed layer 1100 . It is understood that, in the present embodiment, the layer 1102 is formed only on the seed layer 1100 and not on the exposed surfaces of the layer 906 .
- the layer 1102 may be formed using a variety of methods, and may be thicker and/or harder than the seed layer 1100 after formation. As will be described below, the layer 1102 may be used as an etch stop layer for a later etching process. Accordingly, the materials used to form the etch stop layer 1102 may depend on the composition of the underlying layer to be etched and the process used to etch the underlying layer.
- the layer 1102 may be formed using one or more of a variety of processes, as described previously.
- the photoresist layer 906 and underlying layer 908 may be removed. It is understood that, in some embodiments, the photoresist layer 906 may be removed prior to the formation of the etch stop layer 1102 .
- the layer 904 is etched using the layer 1102 as an etch stop layer.
- the etching process may use one or more etching steps, including dry etching, wet etching, and/or other etching methods.
- etching may be stopped when a desired amount of the layer 904 has been removed and the etching need not remove all of the exposed layer 904 .
- the photoresist layer 906 and layer 904 may be removed in a single etching process.
- the seed layer 1100 and etch stop layer 1102 may be removed to expose the remaining portions of the layer 904 for additional processing steps. Such removal may occur using chemical wet etch or dry etch ashing
- an additional layer 1500 may be included between the photoresist layer 906 and the layer 904 of FIG. 9 .
- the layer 1500 may serve as a seed layer, and exposing a portion of the layer 1500 by developing the photoresist layer 906 may provide the previously described step of forming the seed layer.
- the seed layer 1500 may function as electrode plating and the etch stop layer 1102 may be formed therefrom using known electrode plating processes. Once the etch stop layer 1102 has been formed, the remaining negative photoresist may be removed and the underlying metal and dielectric layers may be etched as previously described.
Abstract
Description
- This application claims priority from U.S. Provisional Patent Application Ser. No. 60/731,828 (Attorney Docket No. 24061.722), filed on Oct. 31, 2005, which is incorporated by reference in its entirety.
- One of the factors involved in the manufacture of semiconductor devices is a depth of focus (DOF) window. Generally, an effective DOF will cover all the variations of photoresist. thickness, local substrate topology step height, and wafer center and edge step height differences. An effective DOF facilitates manufacturing a semiconductor device within a desired critical dimension (CD) specification with little or no scum or top loss defects.
- Problems may occur with photoresist that is thicker than the DOF. For example, if the DOF is less than the thickness of the photoresist layer plus step height variation, scum or CD errors may occur in some of the patterns formed on the semiconductor devices. Therefore, thin layers of photoresist may be desired to counter this problem. Such thin photoresist layers may also be desirable for low dosage exposure tools, such as an e-beam or extreme ultraviolet (EUV) tools, as they may improve resist contrast, resolution, and dissolution. Moreover, for mass production purposes, the combination of thin photoresist layers and low dosage exposure tools can increase the throughput of semiconductor devices.
- However, the use of thin photoresist layers can have drawbacks. For example, a thin photoresist layer may adversely affect etching performance if it does not provide sufficient protection during the etch process. To resolve this problem, a two step process may be used. For example, a relatively thin photo sensitive layer may be formed over a thick buffer layer. The photo sensitive layer is developed to form a predefined pattern, and the buffer layer is then etched to correspond to the pattern formed by the photo sensitive layer. The buffer layer then serves as an etch stop layer during etching of the substrate. Accordingly, two removal steps (developing and etching) are needed to reach the substrate prior to etching the substrate.
- Therefore, what is needed is a new and improved photolithography process to address these drawbacks.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 illustrates a method for implementing one embodiment of the present invention during semiconductor manufacturing. -
FIG. 2 is a perspective view of one embodiment of a partial semiconductor device with a photo sensitive layer overlying other layers undergoing manufacturing using the method ofFIG. 1 . -
FIG. 3 is a perspective view of the partial semiconductor device ofFIG. 2 illustrating a pattern formed on the photosensitive layer. -
FIG. 4 is a perspective view of the partial semiconductor device ofFIG. 3 after development of the photo sensitive layer based on the pattern. -
FIG. 5 is a perspective view of the partial semiconductor device ofFIG. 4 after the formation of a second layer on the developed photo sensitive layer. -
FIG. 6 is a perspective view of the partial semiconductor device ofFIG. 5 after using the second layer as a mask during etching of the layer underlying the developed photo sensitive layer. -
FIG. 7 is a perspective view of the partial semiconductor device ofFIG. 6 after removal of the second layer and photo sensitive layer. -
FIG. 8 illustrates a method for implementing another embodiment of the present invention during semiconductor manufacturing. -
FIG. 9 is a perspective view of one embodiment of a partial semiconductor device with a photo sensitive layer overlying other layers undergoing manufacturing using the method ofFIG. 8 . -
FIG. 10 is a perspective view of the partial semiconductor device ofFIG. 10 after development of the photo sensitive layer based on a pattern. -
FIG. 11 is a perspective view of the partial semiconductor device ofFIG. 10 after the formation of a second layer on a seed layer defined by the pattern. -
FIG. 12 is a perspective view of the partial semiconductor device ofFIG. 11 after the remaining portions of the photosensitive layer have been removed. -
FIG. 13 is a perspective view of the partial semiconductor device ofFIG. 12 after using the second layer as a mask during etching of the layer underlying the developed photo sensitive layer. -
FIG. 14 is a perspective view of the partial semiconductor device ofFIG. 13 after removal of the second layer. -
FIG. 15 is a perspective view of another embodiment of the partial semiconductor device ofFIG. 9 . - It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
- Referring to
FIG. 1 , in one embodiment, amethod 100 may be used to obtain the benefits of a relatively thin photo sensitive layer while reducing the number of development/etch steps generally needed when using a photo sensitive layer and a buffer/etch stop layer. Themethod 100 is described in conjunction withFIGS. 2-7 , which illustrate one embodiment of asemiconductor device 200 undergoing manufacture using themethod 100. It is understood that thesemiconductor device 200 is only one example of a device that may be manufactured using themethod 100, and that other steps (e.g., rinsing) may be performed in addition to the steps described. - Referring to
step 102 and with additional reference toFIG. 2 , a photo sensitive layer 206 (e.g., a photoresist) is formed on anunderlying layer 204. Thelayer 204 is positioned above anotherlayer 202. Thelayer 204 may be formed of one or more insulator, conductor, and/or semiconductor layers. For example, thelayer 204 may be formed of a conductor, and thelayer 202 may be formed of an insulator having vias (not shown) that connect thelayer 204 to conductive material (not shown) under thelayer 202. In another embodiment, thelayer 204 may be an insulator layer and thelayer 202 may be a conductive layer. In still another embodiment, thelayer 202 may be absent, and thelayer 204 may include an elementary semiconductor material, such as crystal silicon, polycrystalline silicon, amorphous silicon, and/or germanium; a compound semiconductor, such as silicon carbide and/or gallium arsenic; or an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, and/or GaInP. Further, thelayer 204 may include a bulk semiconductor, such as bulk silicon, and such a bulk semiconductor may include an epi silicon layer. It may also or alternatively include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, or a thin-film transistor (TFT) substrate. Thelayer 204 may also or alternatively include a multiple silicon structure or a multilayer compound semiconductor structure. - The formation of the photo
sensitive layer 206 includes the deposition of a resist material (e.g., a positive resist or a negative resist); a polymer layer; and/or any other suitable materials. In the present example, the photosensitive layer 206 is formed from a positive photoresist material and has a thickness of between 100 and 2000 angstroms. The resist material may be deposited and distributed over the surface of thelayer 204 by a spin-on coating process and/or other processes. In one example, the photosensitive layer 206 may be a chemically amplified resist that employs acid catalysis. - In
step 104 and with additional reference toFIGS. 3 and 4 , apattern 300 is formed on the photo sensitive layer 206 (FIG. 3 ) and the photosensitive layer 206 is then developed (FIG. 4 ). The pattern may include lines, spaces, holes (e.g., vias), islands, or any other pattern. After patterning, thephotosensitive layer 206 may undergo a development process to form a resist image as aseed layer 400. In the present embodiment, the resist is selected to be responsive to the photo sensitive material and provide a bond for subsequent process to grow thicker buffer layer from this resist image. In the present example, theseed layer 400 is approximately 100 to 2000 angstroms thick. - In
step 106 and with additional reference toFIG. 5 , alayer 500 may be formed on theseed layer 400. It is understood that, in the present embodiment, thelayer 500 is formed only on theseed layer 400 and not on the exposed surfaces of thelayer 204. Thelayer 500 may be formed using a variety of methods, and may be thicker and/or harder than theseed layer 400 after formation. As will be described below, thelayer 500 may be used as an etch stop layer for a later etching process. Accordingly, the materials used to form theetch stop layer 500 may depend on the composition of the underlying layer to be etched (e.g., the layer 204) and the process used to etch the underlying layer. For example, the materials forming theetch stop layer 500 may be selected to have a particular composition if thelayer 204 is a metal layer etched using a wet etch process, and a different composition if thelayer 204 is an oxide layer etched using a dry etch process. - In one example, the
layer 500 may be formed by exposing theseed layer 400 to a solution with a PH value of less than 7 or, in another example, with a PH value of 7 or greater. In still another example, thesecond layer 500 may be developed in a plasma environment using a process such as CVD. In yet another example, laser pulse vaporization may be utilized to selectively deposit thelayer 500 using theseed layer 400. - The
layer 500 may be formed by the use of long-chain molecules or long-chain polymer(s) in the Z direction as indicated inFIG. 5 . For example, the long-chain molecules or polymers may include one or more carbon nanotubes, one or more ZnO nanotubes, aligned long-chain molecules, one or more aligned long-chain polymers, and/or any other suitable materials. It is contemplated that the thickness of thesecond layer 202 may be approximately between about 200 and about 600 nanometers. In still other embodiments, electro-less plating may be used to develop the etch stop layer. Alternatively, metal particles may be mixed into the photoresist to provide a metal base for electrode plating. - Referring to step 108 and with additional reference to
FIG. 6 , thelayer 204 is etched using thelayer 500 as an etch stop layer. The etching process may use one or more etching steps, including dry etching, wet etching, and/or other etching methods. Although thelayer 204 is illustrated as completely etched inFIG. 6 , it is understood that etching may be stopped when a desired amount of thelayer 204 has been removed and the etching need not remove all of the exposedlayer 204. - In
step 110 and with additional reference toFIG. 7 , theseed layer 400 andetch stop layer 500 may be removed by wet chemical etch and/or dry etch process. - Accordingly, using the
method 100, an etch stop layer may be formed using a single development/etching step. It is understood that additional steps may be performed in order to complete thesemiconductor device 200. Since those additional steps are known in the art and may vary depending on the specifics of thesemiconductor device 200 being formed, they will not be further described herein. Furthermore, it is noted that many variations of the above example are contemplated herein. In one example, instead of utilizing thesecond layer 204 for etching purposes, it may be used for implanting purposes. In a second example, thesecond layer 204 may be a separate layer formed over theseed layer 400. In a third example, thesecond layer 204 may include theseed layer 400. Accordingly, a variety of modifications are contemplated by this disclosure. - Referring to
FIG. 8 , in another embodiment, amethod 800 may be used to obtain the benefits of a relatively thin photo sensitive layer while reducing the number of development/etch steps generally needed when using a photo sensitive layer and a buffer/etch stop layer. Themethod 800 is described in conjunction withFIGS. 9-14 , which illustrate one embodiment of asemiconductor device 900 undergoing manufacture using themethod 800. It is understood that thesemiconductor device 900 is only one example of a device that may be manufactured using themethod 800, and that other steps (e.g., rinsing) may be performed in addition to the steps described. - In
step 802 and with additional reference toFIG. 9 , a photo sensitive layer 906 (e.g., a photoresist) is formed on anunderlying layer 904. Thelayer 904 may be formed of one or more insulator, conductor, and/or semiconductor layers. For example, thelayer 904 may be formed of a conductor, and thelayer 902 may be formed of an insulator having vias (not shown) that connect thelayer 904 to conductive material (not shown) under thelayer 902. In another embodiment, thelayer 904 may be an insulator layer and thelayer 902 may be a conductive layer. In still another embodiment, thelayer 902 may be absent, and thelayer 904 may include an elementary semiconductor material, such as crystal silicon, polycrystalline silicon, amorphous silicon, and/or germanium; a compound semiconductor, such as silicon carbide and/or gallium arsenic; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, and/or GaInP. Further, thelayer 904 may include a bulk semiconductor, such as bulk silicon, and such a bulk semiconductor may include an epi silicon layer. It may also or alternatively include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, or a thin-film transistor (TFT) substrate. Thelayer 904 may also or alternatively include a multiple silicon structure or a multilayer compound semiconductor structure. - The formation of the photo
sensitive layer 906 includes the deposition of a resist material (e.g., a positive resist or a negative resist); a polymer layer; and/or any other suitable materials. In the present example, the photosensitive layer 906 is formed from a negative photoresist material and has a thickness of between about 100 and about 2000 angstroms. The resist material may be deposited and distributed over the surface of thelayer 904 by a spin-on coating process and/or other processes. - In
step 804 and with reference toFIGS. 9-11 , a pattern.908 is formed on the photo sensitive layer 906 (FIG. 9 ) and the photosensitive layer 906 is then developed (FIG. 10 ). The pattern may include lines, spaces, holes (e.g., vias), islands, or any other pattern. Because thephotoresist layer 906 is formed from negative photoresist, thepattern 908 indicates areas where the photoresist is developed in order to be removed. Once removed,openings 1000 expose the metal of theunderlying metal layer 904. After patterning and developing, thelayer 904 may undergo a deposit or dip process to form aseed layer 1100 selectively on the exposed portions of the layer 904 (FIG. 11 ). It is understood that, in some embodiments, thelayer 904 itself may serve as a seed layer, obviating the need for the formation of a seed layer. For example, thelayer 904 may function as electrode plating and theetch stop layer 1102 may be formed therefrom using known electrode plating processes. - In
step 806 and with continued reference toFIG. 11 , alayer 1102 may be formed on theseed layer 1100. It is understood that, in the present embodiment, thelayer 1102 is formed only on theseed layer 1100 and not on the exposed surfaces of thelayer 906. Thelayer 1102 may be formed using a variety of methods, and may be thicker and/or harder than theseed layer 1100 after formation. As will be described below, thelayer 1102 may be used as an etch stop layer for a later etching process. Accordingly, the materials used to form theetch stop layer 1102 may depend on the composition of the underlying layer to be etched and the process used to etch the underlying layer. Thelayer 1102 may be formed using one or more of a variety of processes, as described previously. - In
step 808 and with additional reference toFIG. 12 , thephotoresist layer 906 andunderlying layer 908 may be removed. It is understood that, in some embodiments, thephotoresist layer 906 may be removed prior to the formation of theetch stop layer 1102. - In
step 810 and with additional reference toFIG. 13 , thelayer 904 is etched using thelayer 1102 as an etch stop layer. The etching process may use one or more etching steps, including dry etching, wet etching, and/or other etching methods. Although thelayer 904 is illustrated as completely etched inFIG. 13 , it is understood that etching may be stopped when a desired amount of thelayer 904 has been removed and the etching need not remove all of the exposedlayer 904. Furthermore, in some embodiments, it is understood that thephotoresist layer 906 andlayer 904 may be removed in a single etching process. Instep 812 and with additional reference toFIG. 14 , theseed layer 1100 andetch stop layer 1102 may be removed to expose the remaining portions of thelayer 904 for additional processing steps. Such removal may occur using chemical wet etch or dry etch ashing - Referring to
FIG. 15 , in still another embodiment, anadditional layer 1500 may be included between thephotoresist layer 906 and thelayer 904 ofFIG. 9 . In some examples, thelayer 1500 may serve as a seed layer, and exposing a portion of thelayer 1500 by developing thephotoresist layer 906 may provide the previously described step of forming the seed layer. In such an example, theseed layer 1500 may function as electrode plating and theetch stop layer 1102 may be formed therefrom using known electrode plating processes. Once theetch stop layer 1102 has been formed, the remaining negative photoresist may be removed and the underlying metal and dielectric layers may be etched as previously described. - Although only a few exemplary embodiments of this disclosure have been described in details above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Also, features illustrated and discussed above with respect to some embodiments can be combined with features illustrated and discussed above with respect to other embodiments. Accordingly, all such modifications are intended to be included within the scope of this disclosure.
Claims (24)
Priority Applications (6)
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US11/347,513 US7220680B1 (en) | 2005-10-31 | 2006-02-03 | Method for photolithography in semiconductor manufacturing |
NL1031939A NL1031939C2 (en) | 2005-10-31 | 2006-06-01 | Method for photolithography in the manufacture of a semiconductor. |
TW095125726A TWI298514B (en) | 2005-10-31 | 2006-07-13 | Method for photolithography in semiconductor manufacturing |
CN2006100995053A CN1959940B (en) | 2005-10-31 | 2006-07-26 | Forming method of part semiconductor assembly |
KR1020060072598A KR100833120B1 (en) | 2005-10-31 | 2006-08-01 | Method for photolithography in semiconductor manufacturing |
JP2006290632A JP4562716B2 (en) | 2005-10-31 | 2006-10-26 | Photolithography in semiconductor device manufacturing. |
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US73182805P | 2005-10-31 | 2005-10-31 | |
US11/347,513 US7220680B1 (en) | 2005-10-31 | 2006-02-03 | Method for photolithography in semiconductor manufacturing |
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JP (1) | JP4562716B2 (en) |
KR (1) | KR100833120B1 (en) |
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Cited By (2)
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US20080296562A1 (en) * | 2007-05-31 | 2008-12-04 | Murduck James M | Methods and apparatus for fabricating carbon nanotubes and carbon nanotube devices |
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CN106783120B (en) * | 2016-12-13 | 2018-03-27 | 深圳顺络电子股份有限公司 | The preparation method and electronic component of a kind of electrodes of electronic components |
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US7220680B1 (en) | 2007-05-22 |
CN1959940A (en) | 2007-05-09 |
NL1031939C2 (en) | 2008-04-15 |
JP4562716B2 (en) | 2010-10-13 |
KR100833120B1 (en) | 2008-05-28 |
KR20070046703A (en) | 2007-05-03 |
JP2007129217A (en) | 2007-05-24 |
TW200723362A (en) | 2007-06-16 |
CN1959940B (en) | 2011-02-02 |
TWI298514B (en) | 2008-07-01 |
NL1031939A1 (en) | 2007-05-02 |
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