US20070096294A1 - Semiconductor device and manufacturing method of the same - Google Patents

Semiconductor device and manufacturing method of the same Download PDF

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Publication number
US20070096294A1
US20070096294A1 US11/594,077 US59407706A US2007096294A1 US 20070096294 A1 US20070096294 A1 US 20070096294A1 US 59407706 A US59407706 A US 59407706A US 2007096294 A1 US2007096294 A1 US 2007096294A1
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Prior art keywords
wafer
cap
arrayed
semiconductor
semiconductor wafer
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Abandoned
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US11/594,077
Inventor
Osamu Ikeda
Toshiyuki Ohkoda
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to US11/594,077 priority Critical patent/US20070096294A1/en
Publication of US20070096294A1 publication Critical patent/US20070096294A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14806—Structural or functional details thereof
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/924—Active solid-state devices, e.g. transistors, solid-state diodes with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap

Definitions

  • the invention relates to a semiconductor device and a manufacturing method thereof, particularly to a semiconductor device in which devices to be sealed are sealed in a package and a manufacturing method thereof.
  • an MEMS device a device using a micro electromechanical system
  • a CCD charge coupled device
  • an IR sensor a sensor electrically detecting infrared radiation
  • Such electronic devices are formed on a semiconductor chip and packaged.
  • a package includes a can package in which the electronic devices are sealed with a metal cap and a ceramic package in which the electronic devices are sealed with a ceramic cap.
  • a semiconductor chip formed with devices to be sealed such as electronic devices and a cap for sealing the devices to be sealed are independently prepared and then assembled. This makes a mass-manufacturing procedure complex, and accordingly increases a manufacturing cost. Furthermore, a package size becomes large, resulting in an increase in a mounting area of the package on a printed board.
  • the invention provides a semiconductor device and a manufacturing method thereof which simplifies a manufacturing procedure to reduce a manufacturing cost and reduces a package size when electronic devices are packaged.
  • a semiconductor chip formed with devices to be sealed on its front surface is attached with a sealing cap, the devices to be sealed being sealed in a cavity formed of a space between the semiconductor chip and the sealing cap.
  • the device to be sealed is an electronic device such as an MEMS device, an IR sensor, and a CCD, or a micro-sized mechanical device.
  • the semiconductor chip is formed with via-holes penetrating therethrough. These via-holes are formed with embedded electrodes.
  • the embedded electrodes are connected with the devices to be sealed through wiring.
  • the embedded electrodes are connected with electrodes for external connection.
  • a plurality of sealing caps and semiconductor chips of the semiconductor device are formed on wafers, attached to each other, and divided into a plurality of packages. This procedure can simplify a mass-manufacturing procedure, and reduce a manufacturing cost of each of the packages.
  • via-holes are provided penetrating through the semiconductor chip of each of the packages and embedded electrodes are formed therein, so that bump electrodes can be formed on a bottom of the semiconductor chip. This can miniaturize the package and reduce a mounting area of the package on a printed board.
  • a cavity for sealing devices to be sealed is filled with an inert gas or kept vacuum so that life and reliability of the sealed devices can be extended and improved.
  • FIG. 1A is a plan view of a semiconductor device of a first embodiment of the invention
  • FIG. 1B is a cross-sectional view of line X-X of FIG. 1A .
  • FIGS. 2A and 2B are plan views of a semiconductor wafer and a cap arrayed wafer of the first embodiment of the invention.
  • FIGS. 3A, 3B and 3 C are cross-sectional views for explaining a manufacturing method of the semiconductor device of the first embodiment of the invention.
  • FIG. 4A is a plan view of a semiconductor device of a second embodiment of the invention
  • FIG. 4B is a cross-sectional view of line Y-Y of FIG. 4A .
  • FIG. 1A is a plan view of a semiconductor device of this embodiment.
  • FIG. 1B is a cross-sectional view along line X-X of FIG. 1A .
  • a plurality of MEMS devices 11 A as devices to be sealed (e.g., a relay, a condenser, a coil or a motor) is formed in a region SA (indicated by a dotted line) on a front surface of a semiconductor chip 10 A (e.g., silicon chip).
  • This region SA includes the MEMS devices 11 A that function as a single device. That is, these MEMS devices 11 A are electronic and mechanical components of a micro-sized mechanism such as a micro-machine.
  • Wiring 12 (e.g. made of Cu, Al, or Al alloy) connected with these MEMS devices 11 A is formed extending to a periphery of the region SA.
  • the wiring 12 is formed in a procedure of forming the MEMS devices 11 A on the semiconductor chip 10 A, having a thickness of about 1 ⁇ m.
  • a plurality of via-holes 13 is formed right under end portions of the wiring 12 formed extending to the periphery of the region SA, penetrating through the semiconductor chip 10 A.
  • Each of these via-holes 13 is formed with an embedded electrode 14 (e.g., made of Cu, Al or Al alloy) therein.
  • the embedded electrodes 14 are formed by a plating method or a sputtering method, and connected with the wiring 12 of the MEMS devices 11 A. Although the embedded electrodes 14 are completely embedded in the via holes 13 in FIG. 1B , the embedded electrodes 14 can be partially embedded therein by adjusting a plating time or a sputtering time.
  • the embedded electrodes 14 are formed with bump electrodes 15 (e.g. made of solder) on a back surface of the semiconductor chip 10 A. Accordingly, leads of the packaged semiconductor chip 10 A are not necessary to be drawn from sides of the semiconductor chip 10 A, but can be drawn from the bottom of the semiconductor chip 10 A, thereby realizing miniaturization of the package. This can prevent increasing of a mounting area of the package on a printed board.
  • bump electrodes 15 e.g. made of solder
  • the front surface of the semiconductor chip 10 A is attached with a sealing cap 20 A made of a glass, a silicon, a ceramic or a resin.
  • the semiconductor chip lOA and the sealing cap 20 A are attached to each other with an adhesive made of an epoxy resin and the like, with the front surface of the semiconductor chip 10 A and a concave portion 21 A of the sealing cap 20 A (inner surface of the sealing cap 20 A) facing each other.
  • a cavity CV is formed in a space between the front surface of the semiconductor chip 10 A and the concave portion 21 A of the sealing cap 20 A.
  • the MEMS devices 11 A are sealed in this cavity CV.
  • the thickness d of the sealing cap 20 A is approximately several ten to several hundred ⁇ m
  • the height h of the cavity CV is approximately several to several ten ⁇ m, although the embodiment is not limited to these values.
  • the MEMS devices 11 A formed on the front surface of the semiconductor chip 10 A are sealed in the cavity CV which is filled with an inert gas (e.g., N 2 ) or kept vacuum.
  • an inert gas e.g., N 2
  • a surface of the concave portion 21 A can be formed with a metal thin film 22 A having a filter function of blocking or transmitting light having a predetermined wave length. Handling of such a filter made of a metal thin film, which has been difficult to handle with its low strength, can be facilitated by utilizing the cavity CV for forming such a filter 22 A on the surface of the concave portion 21 A of the sealing cap 20 A.
  • FIG. 2A is a plan view of a semiconductor wafer 30 A formed of the plurality of the spurconductor chips 10 A disposed in a matrix.
  • the semiconductor wafer 30 A is made of a semiconductor material such as silicon.
  • the plurality of the semiconductor chips 10 A is partitioned with scribe lines L extending in row and column directions.
  • the MEMS devices 11 A are formed in the region SA, in each of the semiconductor chips 10 A.
  • the wiring 12 is connected with each of the MEMS devices 11 A, extending to the periphery of the region SA.
  • FIG. 2B is a plan view of a cap arrayed wafer 40 A formed of the above described sealing caps 20 A disposed in a matrix.
  • the cap arrayed wafer 40 A is made of a glass, a silicon, a ceramic or a resin. Each of regions partitioned with scribe lines L′ is to face each of the semiconductor chips 10 A when attached thereto. These scribe lines L′ of the cap arrayed wafer 40 A are formed in accordance with the scribe lines L of the semiconductor wafer 30 A. The two wafers 30 A and 40 A are attached so that the scribe lines L′ of the cap arrayed wafer 40 A are aligned with the scribe lines L of the semiconductor wafer 30 A.
  • the concave portions 21 A are formed on the cap arrayed wafer 40 A in the regions corresponding to the regions SA of the semiconductor chips 10 A.
  • the cap arrayed wafer 40 A is made of a glass, a silicon or a ceramic
  • the concave portion 21 A is formed by etching.
  • the cap arrayed wafer 40 A is made of a resin
  • the cap arrayed wafer 40 A is formed by injection molding to have the plurality of the concave portions 21 A.
  • the embedded electrodes 14 and the bump electrodes 15 serving as electrodes for external connection are connected with the MEMS devices through the wiring 12 in the above described semiconductor chips 10 A and the semiconductor wafer 30 A, the embedded electrodes 14 and the bump electrodes 15 can be directly connected with the MEMS devices 11 A without through the wiring 12 . This is applied to a second embodiment described below.
  • the semiconductor wafer 30 A formed with the MEMS devices and the wiring 12 (not shown) on its front surface is prepared.
  • the structure of the semiconductor wafer 30 A is the same as the structure shown in FIG. 2A .
  • the cap arrayed wafer 40 A having the plurality of the concave portion 21 A is prepared.
  • the structure of the cap arrayed wafer 40 A is the same as the structure shown in FIG. 2B .
  • the cap arrayed wafer 40 A is made of a glass or a silicon, the surface of the concave portion 21 A can be formed with the metal thin film 22 A having a filter fuiction of blocking or transmitting light having a predetermined wavelength.
  • the cap arrayed wafer 40 A and the semiconductor wafer 30 A are disposed to face the concave portions 21 A of the cap arrayed wafer 40 A and the front surface of the semiconductor wafer 30 A.
  • the cap arrayed wafer 40 A and the semiconductor wafer 30 A are attached with an adhesive made of an epoxy resin or the like. At this time, each of the concave portions 21 A of the cap arrayed wafer 40 A faces each of the regions SA of the semiconductor wafer 30 A.
  • the cavity CV is formed in a space between each of the concave portions 21 A of the cap arrayed wafer 40 A and the front surface of the semiconductor wafer 30 A, and the MEMS devices 11 A are sealed in this cavity.
  • the cap arrayed wafer 40 A and the semiconductor wafer 30 A are attached in a vacuum atmosphere to maintain the cavity CV in vacuum.
  • the cap arrayed wafer 40 A and the semiconductor wafer 30 A can be attached in an inert gas (e.g., N 2 ) atmosphere to fill the cavity CV with the inert gas.
  • the semiconductor wafer 30 A is ground on its back surface to make a thickness of the semiconductor wafer 30 A several ten to several hundred ⁇ m, for example.
  • this back-grinding can be performed to the cap arrayed wafer 40 A or both the semiconductor wafer 30 A and the cap arrayed wafer 40 A.
  • the plurality of the via-holes 13 is formed penetrating from the back surface to the front surface of the semiconductor wafer 30 A.
  • An etching method or a laser beam irradiating method can be used for forming these via-holes 13 .
  • the embedded electrodes 14 are formed in these via-holes 13 by a plating method or a sputtering method. Furthermore, the embedded electrodes 14 on the back surface of the semiconductor wafer 30 are formed with the bump electrodes 15 (e.g., made of a solder). Although the bump electrodes 15 are formed right under the embedded electrodes 14 in the embodiment shown in FIG. 3C , the bump electrodes 15 can be formed on a back-surface wiring connected with the embedded electrodes 14 .
  • the attached cap arrayed wafer 40 A and semiconductor wafer 30 A are cut along the scribe lines L by a dicing blade or laser beams to be divided into each of packages.
  • the plurality of the packages is formed from the cap arrayed wafer 40 A and the semiconductor wafer 30 A simultaneously, thereby simplifying a mass-manufacturing procedure. This reduces a manufacturing cost of each of the packages.
  • MEMS device 11 A is used as a device to be sealed in the above described embodiment, an electronic device of other kind (e.g. IR, sensor) can be used as a device to be sealed.
  • an electronic device of other kind e.g. IR, sensor
  • FIG. 4A is a plan view of the semiconductor device of this embodiment.
  • FIG. 4B is a cross-sectional view along line Y-Y of FIG. 4A .
  • a CCD 11 B as a device to be sealed is formed in a region SB (indicated by a dotted line) for formation of a device to be sealed on a front surface of a semiconductor chip 10 B.
  • the CCD 11 B is used as, for example, an image sensor.
  • a logic circuit LGC for controlling the CCD 11 B is formed in other region for formation of a device to be sealed, which is adjacent to the region SB, on the semiconductor chip 10 B.
  • Wiring 12 (e.g., made of Cu, Al or Al alloy) connected with the CCD 11 B and its logic circuit LGC is formed extending to a periphery of the region SB and the logic circuit LGC.
  • This wiring 12 is formed in a procedure of forming the CCD 11 B and the logic circuit LGC on the semiconductor chip 10 B, having a thickness of about 1 ⁇ m.
  • a plurality of via-holes 13 is formed right under end portions of the wiring 12 formed extending to the periphery of the region SB, penetrating through the semiconductor chip 10 B.
  • Each of the via-holes 13 is formed with an embedded electrode 14 (e.g., made of Cu, Al or Al alloy).
  • the embedded electrodes 14 are formed by a plating method or a sputtering method, and connected with the wiring 12 of the CCD 11 B and the logic circuit LGC.
  • the embedded electrodes 14 are formed with bump electrodes 15 (e.g., made of solder) on a back surface of the semiconductor chip 10 B. Accordingly, leads of the packaged semiconductor chip 10 B are not necessary to be drawn from sides of the semiconductor chip 10 B, but can be drawn from the bottom of the semiconductor chip 10 B, thereby realizing miniaturization of the package. This can prevent increasing of a mounting area of the package on a printed board.
  • bump electrodes 15 e.g., made of solder
  • a sealing cap 20 B (e.g., made of glass, silicon, or resin) is attached to the front surface of the semiconductor chip 10 B.
  • the semiconductor chip 10 B and the sealing cap 20 B are attached, with the region SB on the front surface of the semiconductor chip 10 B and the concave portion 21 B of the sealing cap 20 B facing each other.
  • a cavity CV is formed in a space between the region SB on the front surface of the semiconductor chip 10 B and the concave portion 21 B of the sealing cap 20 B.
  • the CCD 12 B is sealed in this cavity CV.
  • the CCD 11 B formed on the front surface of the semiconductor chip 10 B is sealed in the cavity CV which is filled with an inert gas or kept in vacuum. This prevents the CCD 11 B from being exposed to air, thereby preventing corrosion or degradation with oxidation thereof. Therefore, life and reliability of the CCD 11 B formed on the semiconductor chip 10 B can be extended and improved.
  • a convex portion (not shown) of the sealing cap 20 B is attached without forming the cavity CV.
  • the CCD 11 B is thus sealed in the cavity CV in order to prevent stresses generated by a difference in coefficient of thermal expansion between a material of the sealing cap 20 B and a material of the semiconductor chip 10 B from affecting the CCD 11 B.
  • the logic circuit LGC is thus attached with the convex portion of the sealing cap 20 B thereon in order to increase an attachment area of the sealing cap 20 B for obtaining high attachment strength.
  • a surface of the concave portion 21 B can be formed with a metal thin film 22 B having a filter function of blocking or transmitting light having a predetermined wave length. Handling of such a filter made of a metal thin film, which has been difficult to handle with its low strength, can be facilitated by utilizing the cavity CV for forming such a filter 22 B on the surface of the concave portion 21 B of the sealing cap 20 B.
  • the semiconductor chips 10 B of this embodiment are partitioned with scribe lines L and disposed in a matrix (not shown), in a similar manner as in the semiconductor wafer 30 A shown in FIG. 2A .
  • the CCDs 11 B are formed in the region SB (corresponding to approximately a half of the regions SA in FIG. 2A ), and the logic circuits LGC (corresponding to approximately another half of the regains SA in FIG. 2A ) are formed in positions adjacent the CCDs 11 B.
  • the wiring 12 (not shown) is connected with each of the CCDs 11 B and the logic circuits LGC, extending to the periphery of the region SB and the region formed with the logic circuit LGC.
  • the sealing caps 20 B of this embodiment are partitioned with scribe lines L′ and disposed in a matrix similarly to the cap arrayed wafer 40 A shown in FIG. 2B (not shown). However, the concave portions 21 B are formed on the cap arrayed wafer 40 A only in regions corresponding to the regions SB (not shown) provided for formation of a device to be sealed of the semiconductor chip 10 B, in each of the regions partitioned by the scribe lines L′.
  • the concave portion 21 B is formed by etching when the cap arrayed wafer 40 A of this embodiment is made of a glass or silicon. Alternatively, the concave portion 21 B can be formed simultaneously when the cap arrayed wafer 40 A is formed by injection molding if the cap arrayed wafer 40 A is made of a resin.
  • the CCD 11 B is used as a device to be sealed in the above described embodiment, an electronic device of other kind can be used as a device to be sealed.

Abstract

This invention miniaturizes a package of a semiconductor device and simplifies a manufacturing procedure to reduce a manufacturing cost. A semiconductor wafer formed of a plurality of semiconductor chips formed with MEMS devices and wiring thereof on front surface thereof and a cap arrayed wafer disposed with a plurality of sealing caps are attached to seal the MEMS devices in cavities between them. Then, a plurality of via-holes is provided penetrating through the semiconductor wafer to form embedded electrodes therein, and bump electrodes are formed thereon. After this procedure, this structure is cut along scribe lines to be divided into each of packages.

Description

    CROSS-REFERENCE OF THE INVENTION
  • This invention is based on Japanese Patent Application No. 2003-161634, the content of which is incorporated herein by reference in its entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention:
  • The invention relates to a semiconductor device and a manufacturing method thereof, particularly to a semiconductor device in which devices to be sealed are sealed in a package and a manufacturing method thereof.
  • 2. Description of the Related Art:
  • In recent years, a device using a micro electromechanical system (hereafter, referred to as an MEMS device), a charge coupled device (hereafter, referred to as a CCD) used as an image sensor and so on, and a sensor electrically detecting infrared radiation (hereafter, referred to as an IR sensor) are being developed.
  • These electronic devices or micro-sized mechanical devices (hereafter, referred to as electronic devices) are formed on a semiconductor chip and packaged. Such a package includes a can package in which the electronic devices are sealed with a metal cap and a ceramic package in which the electronic devices are sealed with a ceramic cap.
  • Relating technologies are disclosed in the Japanese Patent Application Publications Nos. Hei 11-351959, Hei 11-258055 and 2001-13156.
  • In a conventional package, however, a semiconductor chip formed with devices to be sealed such as electronic devices and a cap for sealing the devices to be sealed are independently prepared and then assembled. This makes a mass-manufacturing procedure complex, and accordingly increases a manufacturing cost. Furthermore, a package size becomes large, resulting in an increase in a mounting area of the package on a printed board.
    • SUMMARY OF THE INVENTION
  • The invention provides a semiconductor device and a manufacturing method thereof which simplifies a manufacturing procedure to reduce a manufacturing cost and reduces a package size when electronic devices are packaged.
  • In a semiconductor device of the invention, a semiconductor chip formed with devices to be sealed on its front surface is attached with a sealing cap, the devices to be sealed being sealed in a cavity formed of a space between the semiconductor chip and the sealing cap. Here, the device to be sealed is an electronic device such as an MEMS device, an IR sensor, and a CCD, or a micro-sized mechanical device.
  • The semiconductor chip is formed with via-holes penetrating therethrough. These via-holes are formed with embedded electrodes. The embedded electrodes are connected with the devices to be sealed through wiring. The embedded electrodes are connected with electrodes for external connection.
  • In the invention, a plurality of sealing caps and semiconductor chips of the semiconductor device are formed on wafers, attached to each other, and divided into a plurality of packages. This procedure can simplify a mass-manufacturing procedure, and reduce a manufacturing cost of each of the packages.
  • Furthermore, via-holes are provided penetrating through the semiconductor chip of each of the packages and embedded electrodes are formed therein, so that bump electrodes can be formed on a bottom of the semiconductor chip. This can miniaturize the package and reduce a mounting area of the package on a printed board.
  • Furthermore, a cavity for sealing devices to be sealed is filled with an inert gas or kept vacuum so that life and reliability of the sealed devices can be extended and improved.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a plan view of a semiconductor device of a first embodiment of the invention, and FIG. 1B is a cross-sectional view of line X-X of FIG. 1A.
  • FIGS. 2A and 2B are plan views of a semiconductor wafer and a cap arrayed wafer of the first embodiment of the invention.
  • FIGS. 3A, 3B and 3C are cross-sectional views for explaining a manufacturing method of the semiconductor device of the first embodiment of the invention.
  • FIG. 4A is a plan view of a semiconductor device of a second embodiment of the invention, and FIG. 4B is a cross-sectional view of line Y-Y of FIG. 4A.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Next, a structure of a semiconductor device of a first embodiment of the invention will be described with reference to drawings.
  • FIG. 1A is a plan view of a semiconductor device of this embodiment. FIG. 1B is a cross-sectional view along line X-X of FIG. 1A.
  • A plurality of MEMS devices 11A as devices to be sealed (e.g., a relay, a condenser, a coil or a motor) is formed in a region SA (indicated by a dotted line) on a front surface of a semiconductor chip 10A (e.g., silicon chip). This region SA includes the MEMS devices 11A that function as a single device. That is, these MEMS devices 11A are electronic and mechanical components of a micro-sized mechanism such as a micro-machine.
  • Wiring 12 (e.g. made of Cu, Al, or Al alloy) connected with these MEMS devices 11A is formed extending to a periphery of the region SA. The wiring 12 is formed in a procedure of forming the MEMS devices 11A on the semiconductor chip 10A, having a thickness of about 1 μm.
  • A plurality of via-holes 13 is formed right under end portions of the wiring 12 formed extending to the periphery of the region SA, penetrating through the semiconductor chip 10A. Each of these via-holes 13 is formed with an embedded electrode 14 (e.g., made of Cu, Al or Al alloy) therein. The embedded electrodes 14 are formed by a plating method or a sputtering method, and connected with the wiring 12 of the MEMS devices 11A. Although the embedded electrodes 14 are completely embedded in the via holes 13 in FIG. 1B, the embedded electrodes 14 can be partially embedded therein by adjusting a plating time or a sputtering time.
  • The embedded electrodes 14 are formed with bump electrodes 15 (e.g. made of solder) on a back surface of the semiconductor chip 10A. Accordingly, leads of the packaged semiconductor chip 10A are not necessary to be drawn from sides of the semiconductor chip 10A, but can be drawn from the bottom of the semiconductor chip 10A, thereby realizing miniaturization of the package. This can prevent increasing of a mounting area of the package on a printed board.
  • The front surface of the semiconductor chip 10A is attached with a sealing cap 20A made of a glass, a silicon, a ceramic or a resin. The semiconductor chip lOA and the sealing cap 20A are attached to each other with an adhesive made of an epoxy resin and the like, with the front surface of the semiconductor chip 10A and a concave portion 21A of the sealing cap 20A (inner surface of the sealing cap 20A) facing each other.
  • A cavity CV is formed in a space between the front surface of the semiconductor chip 10A and the concave portion 21A of the sealing cap 20A. The MEMS devices 11A are sealed in this cavity CV. The thickness d of the sealing cap 20A is approximately several ten to several hundred μm, the height h of the cavity CV is approximately several to several ten μm, although the embodiment is not limited to these values.
  • The MEMS devices 11A formed on the front surface of the semiconductor chip 10A are sealed in the cavity CV which is filled with an inert gas (e.g., N2) or kept vacuum. This makes the sealed MEMS devices 11A mechanically protected with the sealing cap 20A, and prevents the MEMS devices 11A from being exposed to air, thereby preventing corrosion or degradation with oxidation thereof. Therefore, life and reliability of the MEMS devices 11A formed on the semiconductor chip 10A can be extended and improved.
  • When the sealing cap 20A is made of a glass or a silicon, a surface of the concave portion 21A can be formed with a metal thin film 22A having a filter function of blocking or transmitting light having a predetermined wave length. Handling of such a filter made of a metal thin film, which has been difficult to handle with its low strength, can be facilitated by utilizing the cavity CV for forming such a filter 22A on the surface of the concave portion 21A of the sealing cap 20A.
  • Next, a description will be made on a structure formed with the above described semiconductor chips 10A and sealing caps 20A with reference to drawings.
  • FIG. 2A is a plan view of a semiconductor wafer 30A formed of the plurality of the seinconductor chips 10A disposed in a matrix.
  • The semiconductor wafer 30A is made of a semiconductor material such as silicon. The plurality of the semiconductor chips 10A is partitioned with scribe lines L extending in row and column directions. The MEMS devices 11A are formed in the region SA, in each of the semiconductor chips 10A.
  • Although not shown, the wiring 12 is connected with each of the MEMS devices 11A, extending to the periphery of the region SA.
  • FIG. 2B is a plan view of a cap arrayed wafer 40A formed of the above described sealing caps 20A disposed in a matrix.
  • The cap arrayed wafer 40A is made of a glass, a silicon, a ceramic or a resin. Each of regions partitioned with scribe lines L′ is to face each of the semiconductor chips 10A when attached thereto. These scribe lines L′ of the cap arrayed wafer 40A are formed in accordance with the scribe lines L of the semiconductor wafer 30A. The two wafers 30A and 40A are attached so that the scribe lines L′ of the cap arrayed wafer 40A are aligned with the scribe lines L of the semiconductor wafer 30A.
  • Furthermore, the concave portions 21A are formed on the cap arrayed wafer 40A in the regions corresponding to the regions SA of the semiconductor chips 10A. When the cap arrayed wafer 40A is made of a glass, a silicon or a ceramic, the concave portion 21A is formed by etching.
  • Alternatively, when the cap arrayed wafer 40A is made of a resin, the cap arrayed wafer 40A is formed by injection molding to have the plurality of the concave portions 21A.
  • Although the embedded electrodes 14 and the bump electrodes 15 serving as electrodes for external connection are connected with the MEMS devices through the wiring 12 in the above described semiconductor chips 10A and the semiconductor wafer 30A, the embedded electrodes 14 and the bump electrodes 15 can be directly connected with the MEMS devices 11A without through the wiring 12. This is applied to a second embodiment described below.
  • Next, a semiconductor device manufacturing method of this embodiment will be described with reference to drawings.
  • As shown in FIG. 3A, the semiconductor wafer 30A formed with the MEMS devices and the wiring 12 (not shown) on its front surface is prepared. The structure of the semiconductor wafer 30A is the same as the structure shown in FIG. 2A.
  • Then, the cap arrayed wafer 40A having the plurality of the concave portion 21A is prepared. The structure of the cap arrayed wafer 40A is the same as the structure shown in FIG. 2B. When the cap arrayed wafer 40A is made of a glass or a silicon, the surface of the concave portion 21A can be formed with the metal thin film 22A having a filter fuiction of blocking or transmitting light having a predetermined wavelength.
  • Then, the cap arrayed wafer 40A and the semiconductor wafer 30A are disposed to face the concave portions 21A of the cap arrayed wafer 40A and the front surface of the semiconductor wafer 30A.
  • Next, as shown in FIG. 3B, the cap arrayed wafer 40A and the semiconductor wafer 30A are attached with an adhesive made of an epoxy resin or the like. At this time, each of the concave portions 21A of the cap arrayed wafer 40A faces each of the regions SA of the semiconductor wafer 30A.
  • That is, the cavity CV is formed in a space between each of the concave portions 21A of the cap arrayed wafer 40A and the front surface of the semiconductor wafer 30A, and the MEMS devices 11A are sealed in this cavity. At this time, the cap arrayed wafer 40A and the semiconductor wafer 30A are attached in a vacuum atmosphere to maintain the cavity CV in vacuum. Alternatively, the cap arrayed wafer 40A and the semiconductor wafer 30A can be attached in an inert gas (e.g., N2) atmosphere to fill the cavity CV with the inert gas.
  • Then, the semiconductor wafer 30A is ground on its back surface to make a thickness of the semiconductor wafer 30A several ten to several hundred μm, for example. Alternatively, this back-grinding can be performed to the cap arrayed wafer 40A or both the semiconductor wafer 30A and the cap arrayed wafer 40A.
  • Next, as shown in FIG. 3C, the plurality of the via-holes 13 is formed penetrating from the back surface to the front surface of the semiconductor wafer 30A. An etching method or a laser beam irradiating method can be used for forming these via-holes 13.
  • The embedded electrodes 14 (e.g., made of Cu, Al or Al alloy) are formed in these via-holes 13 by a plating method or a sputtering method. Furthermore, the embedded electrodes 14 on the back surface of the semiconductor wafer 30 are formed with the bump electrodes 15 (e.g., made of a solder). Although the bump electrodes 15 are formed right under the embedded electrodes 14 in the embodiment shown in FIG. 3C, the bump electrodes 15 can be formed on a back-surface wiring connected with the embedded electrodes 14.
  • After the above procedure, the attached cap arrayed wafer 40A and semiconductor wafer 30A are cut along the scribe lines L by a dicing blade or laser beams to be divided into each of packages.
  • As described above, the plurality of the packages is formed from the cap arrayed wafer 40A and the semiconductor wafer 30A simultaneously, thereby simplifying a mass-manufacturing procedure. This reduces a manufacturing cost of each of the packages.
  • Although the MEMS device 11A is used as a device to be sealed in the above described embodiment, an electronic device of other kind (e.g. IR, sensor) can be used as a device to be sealed.
  • Next, a structure of a semiconductor device of a second embodiment of the invention will be described with reference to drawings.
  • FIG. 4A is a plan view of the semiconductor device of this embodiment. FIG. 4B is a cross-sectional view along line Y-Y of FIG. 4A.
  • A CCD 11B as a device to be sealed is formed in a region SB (indicated by a dotted line) for formation of a device to be sealed on a front surface of a semiconductor chip 10B. The CCD 11B is used as, for example, an image sensor. A logic circuit LGC for controlling the CCD 11B is formed in other region for formation of a device to be sealed, which is adjacent to the region SB, on the semiconductor chip 10B.
  • Wiring 12 (e.g., made of Cu, Al or Al alloy) connected with the CCD 11B and its logic circuit LGC is formed extending to a periphery of the region SB and the logic circuit LGC. This wiring 12 is formed in a procedure of forming the CCD 11B and the logic circuit LGC on the semiconductor chip 10B, having a thickness of about 1 μm.
  • Furthermore, a plurality of via-holes 13 is formed right under end portions of the wiring 12 formed extending to the periphery of the region SB, penetrating through the semiconductor chip 10B. Each of the via-holes 13 is formed with an embedded electrode 14 (e.g., made of Cu, Al or Al alloy). The embedded electrodes 14 are formed by a plating method or a sputtering method, and connected with the wiring 12 of the CCD 11B and the logic circuit LGC.
  • The embedded electrodes 14 are formed with bump electrodes 15 (e.g., made of solder) on a back surface of the semiconductor chip 10B. Accordingly, leads of the packaged semiconductor chip 10B are not necessary to be drawn from sides of the semiconductor chip 10B, but can be drawn from the bottom of the semiconductor chip 10B, thereby realizing miniaturization of the package. This can prevent increasing of a mounting area of the package on a printed board.
  • A sealing cap 20B (e.g., made of glass, silicon, or resin) is attached to the front surface of the semiconductor chip 10B. The semiconductor chip 10B and the sealing cap 20B are attached, with the region SB on the front surface of the semiconductor chip 10B and the concave portion 21B of the sealing cap 20B facing each other.
  • A cavity CV is formed in a space between the region SB on the front surface of the semiconductor chip 10B and the concave portion 21B of the sealing cap 20B. The CCD 12B is sealed in this cavity CV. Here, the CCD 11B formed on the front surface of the semiconductor chip 10B is sealed in the cavity CV which is filled with an inert gas or kept in vacuum. This prevents the CCD 11B from being exposed to air, thereby preventing corrosion or degradation with oxidation thereof. Therefore, life and reliability of the CCD 11B formed on the semiconductor chip 10B can be extended and improved.
  • On the region formed with the logic circuit LGC, a convex portion (not shown) of the sealing cap 20B is attached without forming the cavity CV.
  • The CCD 11B is thus sealed in the cavity CV in order to prevent stresses generated by a difference in coefficient of thermal expansion between a material of the sealing cap 20B and a material of the semiconductor chip 10B from affecting the CCD 11B. On the other hand, the logic circuit LGC is thus attached with the convex portion of the sealing cap 20B thereon in order to increase an attachment area of the sealing cap 20B for obtaining high attachment strength.
  • When the sealing cap 20B is made of a glass or a silicon, a surface of the concave portion 21B can be formed with a metal thin film 22B having a filter function of blocking or transmitting light having a predetermined wave length. Handling of such a filter made of a metal thin film, which has been difficult to handle with its low strength, can be facilitated by utilizing the cavity CV for forming such a filter 22B on the surface of the concave portion 21B of the sealing cap 20B.
  • Next, a structure formed with the plurality of the semiconductor chips 10B and the sealing caps 20B on wafers will be described with reference to FIGS. 2A and 2B.
  • The semiconductor chips 10B of this embodiment are partitioned with scribe lines L and disposed in a matrix (not shown), in a similar manner as in the semiconductor wafer 30A shown in FIG. 2A. However, in this embodiment, the CCDs 11B are formed in the region SB (corresponding to approximately a half of the regions SA in FIG. 2A), and the logic circuits LGC (corresponding to approximately another half of the regains SA in FIG. 2A) are formed in positions adjacent the CCDs 11B. The wiring 12 (not shown) is connected with each of the CCDs 11B and the logic circuits LGC, extending to the periphery of the region SB and the region formed with the logic circuit LGC.
  • The sealing caps 20B of this embodiment are partitioned with scribe lines L′ and disposed in a matrix similarly to the cap arrayed wafer 40A shown in FIG. 2B (not shown). However, the concave portions 21B are formed on the cap arrayed wafer 40A only in regions corresponding to the regions SB (not shown) provided for formation of a device to be sealed of the semiconductor chip 10B, in each of the regions partitioned by the scribe lines L′.
  • The concave portion 21B is formed by etching when the cap arrayed wafer 40A of this embodiment is made of a glass or silicon. Alternatively, the concave portion 21B can be formed simultaneously when the cap arrayed wafer 40A is formed by injection molding if the cap arrayed wafer 40A is made of a resin.
  • The above described semiconductor wafer and cap arrayed wafer of this embodiment are finally divided in each of the packages through the same procedure of the manufacturing method as that of the first embodiment.
  • Although the CCD 11B is used as a device to be sealed in the above described embodiment, an electronic device of other kind can be used as a device to be sealed.

Claims (9)

1-10. (canceled)
11. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor wafer comprising a plurality of device areas that are defined by scribe lines, each of the device areas comprising device elements formed on a surface of the semiconductor wafer;
providing a cap arrayed wafer that includes a plurality of concave portions formed therein;
attaching the semiconductor wafer and the cap arrayed wafer so that the device elements of a device area of the semiconductor wafer are sealed in a corresponding concave portion of the cap arrayed wafer; and
dividing along the scribe lines the attached semiconductor wafer and the cap arrayed wafer into individual packages.
12. the method of claim 11, wherein the device elements of the device area are sealed in vacuum.
13. The method of claim 11, wherein the device elements of the device area are sealed in an inert gas.
14. The method of claim 11, further comprising forming a metal thin film on inner surfaces of the concave portions so as to provide a filter function of blocking or transmitting light having a predetermined wavelength.
15. The method of claim 11, further comprising forming a via-hole in the device area, forming an embedded electrode in the via-holes, and forming a wiring connecting the embedded electrode and at least one of the device elements.
16. The method of claim 11, further comprising back-grinding the semiconductor wafer after attaching the cap arrayed wafer and the semiconductor wafer.
17. The method of claim 11, further comprising back-grinding the cap arrayed wafer after attaching the cap arrayed wafer and the semiconductor wafer.
18. The method of claim 11, further comprising back-grinding the semiconductor wafer and the cap arrayed wafer after attaching the cap arrayed wafer and the semiconductor wafer.
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