US20070020774A1 - Methods of utilizing magnetoresistive memory constructions - Google Patents
Methods of utilizing magnetoresistive memory constructions Download PDFInfo
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- US20070020774A1 US20070020774A1 US11/521,289 US52128906A US2007020774A1 US 20070020774 A1 US20070020774 A1 US 20070020774A1 US 52128906 A US52128906 A US 52128906A US 2007020774 A1 US2007020774 A1 US 2007020774A1
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- conductive line
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
Abstract
The invention includes a method of forming a magnetoresistive memory device having a memory bit stack. The stack includes a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization in reading information from the memory bit. The first conductive line is ohmically connecting with either the first or second magnetic layer. A second conductive line is spaced from the stack by a sufficient distance that the second conductive line is not ohmically connected to the stack, and is configured for utilization in writing information to the memory bit. The invention also includes methods of storing and retrieving information.
Description
- This patent is a divisional application of U.S. patent application Ser. No. 10/915,931, filed Aug. 10, 2004, entitled “Magnetoresistive Memory Devices and Assemblies; and Methods of Storing and Retrieving Information”, naming Hasan Nejad as inventor, which is a divisional application of U.S. patent application Ser. No. 10/418,406, filed Apr. 18, 2003, now U.S. Pat. No. 6,791,870, which is a divisional application of U.S. patent application Ser. No. 10/051,679, filed Jan. 16, 2002, now U.S. Pat. No. 6,735,111.
- The invention pertains to magnetoresistive memory devices, such as, for example, magnetic random access memory (MRAM) devices, and also pertains to methods of storing and retrieving information.
- Numerous types of digital memories are utilized in computer system components, digital processing systems, and other applications for storing and retrieving data. MRAM is a type of digital memory in which digital bits of information comprise alternative states of magnetization of magnetic materials in memory cells. The magnetic materials can be thin ferromagnetic films. Information can be stored and retrieved from the memory devices by inductive sensing to determine a magnetization state of the devices, or by magnetoresistive sensing of the magnetization states of the memory devices. It is noted that the term “magnetoresistive device” characterizes the device and not the access device, and accordingly a magnetoresistive device can be accessed by, for example, either inductive sensing or magnetoresistive sensing methodologies.
- A significant amount of research is currently being invested in magnetic digital memories, such as, for example, MRAM's, because such memories are seen to have significant potential advantages relative to the dynamic random access memory (DRAM) components and static random access memory (SRAM) components that are presently in widespread use. For instance, a problem with DRAM is that it relies on electric charge storage within capacitors. Such capacitors leak electric charge, and must be refreshed at approximately 64-128 millisecond intervals. The constant refreshing of DRAM devices can drain energy from batteries utilized to power the devices, and can lead to problems with lost data since information stored in the DRAM devices is lost when power to the devices is shut down.
- SRAM devices can avoid some of the problems associated with DRAM devices, in that SRAM devices do not require constant refreshing. Further, SRAM devices are typically faster than DRAM devices. However, SRAM devices take up more semiconductor real estate than do DRAM devices. As continuing efforts are made to increase the density of memory devices, semiconductor real estate becomes increasingly valuable. Accordingly, SRAM technologies are difficult to incorporate as standard memory devices in memory arrays.
- MRAM devices have the potential to alleviate the problems associated with DRAM devices and SRAM devices. Specifically, MRAM devices do not require constant refreshing, but instead store data in stable magnetic states. Further, the data stored in MRAM devices will remain within the devices even if power to the devices is shutdown or lost. Additionally, MRAM devices can potentially be formed to utilize less than or equal to the amount of semiconductor real estate associated with DRAM devices, and can accordingly potentially be more economical to incorporate into large memory arrays than are SRAM devices.
- Although MRAM devices have potential to be utilized as digital memory devices, they are currently not widely utilized. Several problems associated with MRAM technologies remain to be addressed. It would be desirable to develop improved MRAM devices.
- In one aspect, the invention encompasses a magnetoresistive memory device. The device includes a memory bit which comprises a stack having a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization in reading information from the memory bit. A second conductive line is spaced from the stack by a greater distance than the first conductive line is spaced from the stack, and is configured for utilization in writing information to the memory bit.
- In one aspect, the invention encompasses a magnetoresistive memory device assembly. The assembly includes an array of individual magnetoresistive memory devices. The devices include memory bits. The individual memory bits comprise a stack of a pair of magnetic layers separated by a non-magnetic layer. A first conductive line is proximate the stack and utilized for reading information from the memory bit. A second conductive line is spaced from the stack by a greater distance than the first conductive line and is configured for utilization in writing information to the memory bit. The first conductive line extends across a first set of several of the individual magnetoresistive memory devices of the array, and the second conductive line also extends across the first set of the individual magnetoresistive memory devices of the array. A first transistor is electrically connected with the first conductive line and accordingly electrically connected with the first set of individual magnetoresistive memory devices. Additionally, a second transistor is electrically connected with the second conductive line, and accordingly electrically connected with the first set of the individual magnetoresistive memory devices of the array.
- In one aspect, the invention encompasses a method of storing and retrieving information. A magnetoresistive memory device is provided. The device comprises a memory stack having a pair of magnetic layers separated by a non-magnetic layer. A first conductive line is provided proximate the stack and utilized for reading information from the memory bit, and a second conductive line is spaced from the stack by a greater distance than the first conductive line and utilized for writing information to the memory bit. The first conductive line is operated at a maximum amperage of from about 500 nanoamps to about 1 microamp during reading of information from the memory bit, and the second conductive line is operated at a maximum amperage of from about 1 milliamp to about 10 milliamps during writing of information to the memory bit.
- Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
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FIG. 1 is a diagrammatic, cross-sectional view of an exemplary magnetoresistive memory device encompassed by the present invention. -
FIG. 2 is a diagrammatic top view of a fragment of a magnetoresistive memory device assembly illustrating an exemplary application of the present invention. - In one aspect, the invention pertains to a novel MRAM device exemplified by a
construction 10 inFIG. 1 .Construction 10 includes asubstrate 12.Substrate 12 can comprise, for example, monocrystalline silicon having various circuit elements (not shown) formed thereover. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. - An electrically
conductive line 14 is supported bysubstrate 12, an electricallyinsulative layer 16 is overline 14, and an electricallyconductive line 18 is over electricallyinsulative layer 16. In the discussion and claims that follow,conductive line 18 can be referred to as a first conductive line, andconductive line 14 can be referred to as a second conductive line.Conductive lines Insulative layer 16 can comprise any of numerous electrically insulative materials, including, for example, silicon dioxide, silicon nitride, and/or so-called low-k materials. - A
memory bit 20 is overconductive line 18, and comprises a stack which includes a first magnetic layer 22, a secondmagnetic layer 24, and anon-magnetic material 26 betweenmagnetic layers 22 and 24.Magnetic layers 22 and 24 ofmemory bit 20 typically comprise one or more of nickel, iron, cobalt, iridium, manganese, platinum and ruthenium. Thenon-magnetic material 26 can comprise either an electrically conductive material (such as copper) in applications in which the MRAM is to be a giant magnetoresistive (GMR) device, or can comprise an electrically insulative material (such as, for example, aluminum oxide (Al2O3) or silicon dioxide), in applications in which the MRAM device is to be a tunnel magnetoresistive (TMR) device.Magnetic layer 24 physically contacts conductiveline 18 in the shown embodiment. - A third
conductive line 28 is provided over the memory bit, and extends in an orthogonal orientation relative to first and secondconductive lines conductive line 28 extends into and out of the page in the shown orientation ofconstruction 10.Conductive line 28 can comprise any of numerous conductive materials, including, for example, metals and metal compositions.Conductive line 28 physical contacts magnetic layer 22 in the shown embodiment. - An electrically
insulative material 30 is provided along sidewalls ofconductive line 28 andmemory bit 20, as well as over a top of secondconductive line 18.Insulative material 30 can comprise any of numerous electrical insulative materials, including, for example, silicon dioxide, silicon nitride, and borophosphosilicate glass (BPSG). - The
magnetic layers 22 and 24 each contain a magnetic moment therein, and inFIG. 1 the magnetic moment within layer 22 is illustrated byarrows 32 while the magnetic moment inlayer 24 is illustrated byarrows 34. Information is stored inmemory bit 20 as a relative orientation of the magnetic moment in layer 22 relative to the magnetic moment inlayer 24. In the shown construction, the magnetic moments are anti-parallel to one another. Another stable orientation of the magnetic moments inlayers 22 and 24 is one in which the moments are parallel to one another. Information can be stored withinbit 20 by considering the anti-parallel orientation of the magnetic moments to correspond to either a “0” or “1” in a two-state memory device, and the parallel orientation to correspond to the other of the “0” and “1”. - Typically, one of the
magnetic layers 22 and 24 has its magnetic orientation pinned within it, so that such orientation does not change during storage and retrieval of information from the memory bit. The other of the magnetic layers has an orientation which is changed during at least the writing of information to the memory bit. Accordingly, an exemplary memory bit can have the shown magnetic orientation within layer 22 fixed, while the orientation withinlayer 24 is varied from a parallel to anti-parallel state as information is stored within the memory bit. -
Conductive lines memory bit 20. More specifically,conductive line 14 is utilized for writing of information tomemory bit 20;conductive line 18 is utilized for reading of information frommemory bit 20; andconductive line 28 is a common line utilized for both the reading and writing operations in preferred embodiments. One aspect of particular embodiments of the present invention is a recognition that a conductive line utilized in a reading operation relative to memory bit 20 (theline 18 ofFIG. 1 ) should be in ohmic electrical contact with the bit to allow sensing of a memory state of the bit (i.e. the relative magnetic orientations within layers 22 and 24). - Another aspect of particular embodiments of the invention is recognition that the conductive line utilized for writing information to
memory bit 20 is preferably not in ohmic electrical contact with the bit. In particular aspects, the conductive line utilized for a writing operation (line 14 of the shown construction) is provided close enough to bit 20 so that a magnetic field from thewrite line 14 overlaps sufficiently with the bit to switch a memory state of the bit (specifically, to switch a magnetic orientation within one of layers 22 and 24), but the line is too far from the bit for ohmic electrical contact with the bit. - In the shown construction,
conductive line 14 is separated frommemory bit 20 by a combined thickness ofconductive line 18 andinsulative material 16. In particular embodiments,layer 18 will have a thickness of from about 100 Angstroms to about 300 Angstroms, andlayer 16 will have a thickness of at least about 100 Angstroms, so thatconductive material 14 is separated frombit 20 by a distance of at least about 200 Angstroms. It is noted that other intervening materials can be provided betweenlayer 14 andmemory bit 20 in addition to, or alternatively to, the shown materials oflayers - While it is possible in theory to accomplish a writing operation to
memory bit 20 utilizingconductive line 14 alone, such is difficult in practice due to physics of attempting to induce a full flip in magnetic orientation of one oflayers 22 and 24 from a single conductive line. Specifically, any defects or inhomogeneities in a magnetic material can cause the magnetic moment to be less than fully flipped, and accordingly a stable orientation will not be achieved. The magnetic moment can then flip back to the original orientation, rather than achieving the new orientation desired by the write operation.Conductive line 28 can simplify the writing operation. Specifically, if current is flowed through conductive line 28 a magnetic orientation can be flipped half-way toward a desired magnetic orientation, and subsequent current flow throughline 14 can readily completely flip the magnetic orientation to the desired orientation. The utilization of a conductive line on top of an MRAM memory bit, and orthogonal to a conductive line utilized for writing to the bit, is typically referred to as a half-select process. -
Conductive line 28 can also be utilized in reading information frommemory bit 20, and will provide an electrical contact on the opposite side of the bit for a reading operation. - The relative amperages provided through
conductive lines conductive line 28 can be maintained to a level of from about 1 milliamp to about 10 milliamps. -
Conductive lines conductive line 18 can comprise numerous conductive materials suitable for carrying relatively low amperages, including, for example, various metals, metal silicides, and conductively doped semiconductive materials, including conductively doped silicon.Conductive lines - In an exemplary application of the present invention, memory bits of the type described with reference to
FIG. 1 are incorporated into a memory array. Anexemplary assembly 50 comprising an array of memory bits is illustrated inFIG. 2 , with the array generally designated by the numeral 52.Assembly 50 comprises asubstrate 54 supporting thearray 52.Substrate 54 can comprise the materials described above with reference tosubstrate 12.Individual memory bits 56 are shown withinarray 52, and designated by “X”. The memory bits can comprise themagnetic layers 22 and 24, andnon-magnetic layer 26 described above with reference toFIG. 1 . - A plurality of
conductive lines 18 are shown crossing througharray 52 along a horizontal direction, and a second plurality ofconductive lines 28 are shown crossing througharray 52 along a vertical direction.Conductive lines FIG. 1 . It is noted that there is no conductive line visible inFIG. 2 that corresponds to theline 14 ofFIG. 1 . Such conductive line would, in typical embodiments, be under theconductive line 18, and accordingly not be visible in the view ofFIG. 2 . - Each of the
conductive lines 18 extends across a set ofindividual memory bits 56 of thearray 52. In the shown construction, eachline 18 extends across a set of five memory bits of the array. Similarly, each of thelines 28 extends across a set of five memory bits of the array. Further, a buried line corresponding to theline 14 ofFIG. 1 , and accordingly utilized for writing to the memory bits, will extend across the same set of five memory bits as does the shownline 18. - Each of the
lines boxes 60 alonglines 18, and withboxes 62 alonglines 28. The circuitry will typically include at least one transistor, and will be utilized for, among other things, maintaining a maximum amperage through the conductive lines within a desired range. Additionally, the lines 14 (not shown inFIG. 2 ) will also have circuitry associated therewith similar to the circuitry illustrated relative toline 18, and utilized for controlling flow of electricity through thelines 14; including, for example, maintaining a maximum amperage withinline 14 to within a desired range. - The
array 52 ofmemory bits 56 comprises a footprint oversubstrate 54 which is designated approximately by a dashedline 70 extending around an outer periphery of the array. Thecircuitry conductive lines conductive line 14, is peripheral to the footprint of such array. Preferably, no transistors are provided within the footprint of the array in order to simplify fabrication of the array and densify the number of bits in the fixed array area. - The number of memory bits within
array 52 can vary depending on the desired application for the array. In particular embodiments, the array will comprise a matrix having 10 rows of bits and 10 columns of bits (a 10×10 matrix of memory bits), and accordingly will comprise 100 memory bits. In another embodiment, the array will comprise a 100×100 matrix of memory bits, and will accordingly comprise 10,000 memory bits. In yet another embodiment, the array will comprise a 1,000×1,000 matrix of memory bits, and accordingly will comprise 1,000,000 memory bits. In particular applications there will be no circuit elements within thefootprint 70 other than memory bits and conductive lines extending between the memory bits, in order to simplify fabrication of the array. - Prior art MRAM constructions typically utilized a single line in ohmic electrical contact with a memory bit for both reading and writing operations (i.e., would utilize the
line 18 ofFIG. 1 for both read and write operations), and difficulties were encountered during writing operations in that breakdown voltages of the barriers in tunnel junctions of the bits would be exceeded. One aspect of the prior art problem was that a low voltage was utilized in transistors associated with a writing operation, which caused the transistors to be operated in the deep linear region of the transistor current-voltage curve with low drive currents. One aspect of the present invention is to utilize a half-select isolated write conductor. The electrical isolation of the write conductor from the memory bit allows the transistors associated with the conductor to be operated in a saturated region, and consequently can reduce transistor width by at least 10 fold relative to prior art constructions. Since approximately 30% to 40% of the die area associated with an MRAM assembly is typically occupied by write transistors, the reduction of the size of the transistors can decrease the die size substantially. - In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
Claims (12)
1-47. (canceled)
48. A method of utilizing a magnetoresistive memory construction, comprising:
providing the magnetoresistive memory construction to include:
a memory bit comprising a stack which includes a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers; the memory bit storing information as a relative orientation of a magnetic moment in the first magnetic layer to a magnetic moment in the second magnetic layer;
a first conductive line proximate the stack and configured for utilization in reading information from the memory bit;
a second conductive line on an opposing side of the first conductive line from the stack and thus spaced from the stack by at least a thickness of the first conductive line combined with any distance by which the first conductive line is spaced from the stack; the second conductive line being configured for utilization in writing information to the memory bit; and
the first and second conductive lines extending longitudinally parallel to one another;
utilizing the first conductive line for reading information from the memory bit, but not in writing information to the memory bit; and
utilizing the second conductive line for writing information to the memory bit, but not in reading information from the memory bit.
49. The method of claim 48 wherein the first conductive line is in ohmic electrical contact with at least one of the magnetic layers of the memory bit, and wherein the second conductive line is not in ohmic electrical contact with either of the magnetic layers of the memory bit.
50. The method of claim 48 wherein the first and second magnetic layers comprise one or more of nickel, iron, cobalt, iridium, manganese, platinum and ruthenium.
51. The method of claim 48 wherein the non-magnetic layer comprises an electrically insulative material.
52. The method of claim 48 wherein the non-magnetic layer comprises an electrically conductive material.
53. The method of claim 48 wherein the first conductive line physically contacts one of the first and second magnetic layers.
54. The method of claim 48 wherein the magnetoresistive memory construction further includes an electrically insulative material between the first and second conductive lines; and wherein the second conductive line is thus spaced from the stack by at least a combined thickness of the electrically insulative material and the first conductive line.
55. The method of claim 54 wherein the electrically insulative material comprises a layer which includes one or both of silicon dioxide and silicon nitride, and which is at least about 100 Å thick.
56. The method of claim 48 wherein the magnetoresistive memory construction further includes a third conductive line proximate the stack; and wherein the third conductive line is utilized in both writing information to the memory bit and reading information from the memory bit.
57. The method of claim 56 wherein the first conductive line physically contacts one of the first and second magnetic layers, and wherein the third conductive line physically contacts the other of the first and second magnetic layers.
58. The method of claim 56 wherein the magnetoresistive memory construction further includes an electrically insulative material between the first and second conductive lines, and wherein:
the first conductive line physically contacts one of the first and second magnetic layers; and
the third conductive line physically contacts the other of the first and second magnetic layers.
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US11/521,289 US20070020774A1 (en) | 2002-01-16 | 2006-09-13 | Methods of utilizing magnetoresistive memory constructions |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US10/051,679 US6735111B2 (en) | 2002-01-16 | 2002-01-16 | Magnetoresistive memory devices and assemblies |
US10/418,406 US6791870B2 (en) | 2002-01-16 | 2003-04-18 | Magnetoresistive memory devices and assemblies; and methods of storing and retrieving information |
US10/915,931 US20050014297A1 (en) | 2002-01-16 | 2004-08-10 | Methods of forming magnetoresistive memory devices and assemblies |
US11/521,289 US20070020774A1 (en) | 2002-01-16 | 2006-09-13 | Methods of utilizing magnetoresistive memory constructions |
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US10/915,931 Division US20050014297A1 (en) | 2002-01-16 | 2004-08-10 | Methods of forming magnetoresistive memory devices and assemblies |
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US20070020774A1 true US20070020774A1 (en) | 2007-01-25 |
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US10/051,679 Expired - Lifetime US6735111B2 (en) | 2002-01-16 | 2002-01-16 | Magnetoresistive memory devices and assemblies |
US10/418,406 Expired - Lifetime US6791870B2 (en) | 2002-01-16 | 2003-04-18 | Magnetoresistive memory devices and assemblies; and methods of storing and retrieving information |
US10/915,931 Abandoned US20050014297A1 (en) | 2002-01-16 | 2004-08-10 | Methods of forming magnetoresistive memory devices and assemblies |
US11/521,289 Abandoned US20070020774A1 (en) | 2002-01-16 | 2006-09-13 | Methods of utilizing magnetoresistive memory constructions |
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US10/051,679 Expired - Lifetime US6735111B2 (en) | 2002-01-16 | 2002-01-16 | Magnetoresistive memory devices and assemblies |
US10/418,406 Expired - Lifetime US6791870B2 (en) | 2002-01-16 | 2003-04-18 | Magnetoresistive memory devices and assemblies; and methods of storing and retrieving information |
US10/915,931 Abandoned US20050014297A1 (en) | 2002-01-16 | 2004-08-10 | Methods of forming magnetoresistive memory devices and assemblies |
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US (4) | US6735111B2 (en) |
EP (1) | EP1466328A2 (en) |
JP (1) | JP4811627B2 (en) |
KR (1) | KR100743328B1 (en) |
CN (1) | CN100437816C (en) |
AU (1) | AU2003210113A1 (en) |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013096334A1 (en) * | 2011-12-19 | 2013-06-27 | Lam Research Corporation | Method of making device |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6735111B2 (en) * | 2002-01-16 | 2004-05-11 | Micron Technology, Inc. | Magnetoresistive memory devices and assemblies |
US6762952B2 (en) * | 2002-05-01 | 2004-07-13 | Hewlett-Packard Development Company, L.P. | Minimizing errors in a magnetoresistive solid-state storage device |
AU2003234403A1 (en) * | 2002-05-16 | 2003-12-02 | Nova Research, Inc. | Methods of fabricating magnetoresistive memory devices |
US7660181B2 (en) * | 2002-12-19 | 2010-02-09 | Sandisk 3D Llc | Method of making non-volatile memory cell with embedded antifuse |
US7800932B2 (en) * | 2005-09-28 | 2010-09-21 | Sandisk 3D Llc | Memory cell comprising switchable semiconductor memory element with trimmable resistance |
US7618850B2 (en) * | 2002-12-19 | 2009-11-17 | Sandisk 3D Llc | Method of making a diode read/write memory cell in a programmed state |
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US8008700B2 (en) * | 2002-12-19 | 2011-08-30 | Sandisk 3D Llc | Non-volatile memory cell with embedded antifuse |
US20070164388A1 (en) * | 2002-12-19 | 2007-07-19 | Sandisk 3D Llc | Memory cell comprising a diode fabricated in a low resistivity, programmed state |
US6818549B2 (en) * | 2003-03-05 | 2004-11-16 | Hewlett-Packard Development Company, L.P. | Buried magnetic tunnel-junction memory cell and methods |
US7172751B2 (en) | 2003-06-13 | 2007-02-06 | Immunomedics, Inc. | D-amino acid peptides |
US7800934B2 (en) * | 2005-09-28 | 2010-09-21 | Sandisk 3D Llc | Programming methods to increase window for reverse write 3D cell |
US8796155B2 (en) * | 2008-12-04 | 2014-08-05 | Micron Technology, Inc. | Methods of fabricating substrates |
KR102023626B1 (en) | 2013-01-25 | 2019-09-20 | 삼성전자 주식회사 | Memory device using spin hall effect and methods of manufacturing and operating the same |
Citations (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5565695A (en) * | 1995-04-21 | 1996-10-15 | Johnson; Mark B. | Magnetic spin transistor hybrid circuit element |
US5665695A (en) * | 1992-02-20 | 1997-09-09 | Binney & Smith Inc. | Surfactant composition and method of making the same |
US6005800A (en) * | 1998-11-23 | 1999-12-21 | International Business Machines Corporation | Magnetic memory array with paired asymmetric memory cells for improved write margin |
US6055179A (en) * | 1998-05-19 | 2000-04-25 | Canon Kk | Memory device utilizing giant magnetoresistance effect |
US6097625A (en) * | 1998-07-16 | 2000-08-01 | International Business Machines Corporation | Magnetic random access memory (MRAM) array with magnetic tunnel junction (MTJ) cells and remote diodes |
US6188615B1 (en) * | 1999-10-29 | 2001-02-13 | Hewlett-Packard Company | MRAM device including digital sense amplifiers |
US6215707B1 (en) * | 2000-04-10 | 2001-04-10 | Motorola Inc. | Charge conserving write method and system for an MRAM |
US6272041B1 (en) * | 2000-08-28 | 2001-08-07 | Motorola, Inc. | MTJ MRAM parallel-parallel architecture |
US6272036B1 (en) * | 1999-12-20 | 2001-08-07 | The University Of Chicago | Control of magnetic direction in multi-layer ferromagnetic devices by bias voltage |
US20010019461A1 (en) * | 2000-03-03 | 2001-09-06 | Rolf Allenspach | Magnetic millipede for ultra high density magnetic storage |
US20010026471A1 (en) * | 2000-03-23 | 2001-10-04 | Masashi Michijima | Magnetic memory element, magnetic memory and manufacturing method of magnetic memory |
US20010038548A1 (en) * | 2000-05-03 | 2001-11-08 | Perner Frederick A. | Write circuit for large MRAM arrays |
US20020001223A1 (en) * | 2000-06-30 | 2002-01-03 | Yoshiaki Saito | Solid-state magnetic memory |
US20020006058A1 (en) * | 1999-12-16 | 2002-01-17 | Kentaro Nakajima | Magnetic memory device |
US20020037595A1 (en) * | 2000-09-28 | 2002-03-28 | Keiji Hosotani | Semiconductor memory device utilizing tunnel magneto resistive effects and method for manufacturing the same |
US20020044481A1 (en) * | 2000-10-17 | 2002-04-18 | Mitsubishi Denki Kabushiki Kaisha | Thin film magnetic memory device capable of easily controlling a data write current |
US6381170B1 (en) * | 1993-10-01 | 2002-04-30 | Gary A. Prinz | Ultra high density, non-volatile ferromagnetic random access memory |
US6385083B1 (en) * | 2001-08-01 | 2002-05-07 | Hewlett-Packard Company | MRAM device including offset conductors |
US6385082B1 (en) * | 2000-11-08 | 2002-05-07 | International Business Machines Corp. | Thermally-assisted magnetic random access memory (MRAM) |
US20020057593A1 (en) * | 2000-11-14 | 2002-05-16 | Mitsubishi Denki Kabushiki Kaisha | Thin film magnetic memory device having a highly integrated memory array |
US20020064069A1 (en) * | 1999-03-19 | 2002-05-30 | Bernd Goebel | Memory cell configuration and method for fabricating it |
US6421270B1 (en) * | 2000-12-29 | 2002-07-16 | Amic Technology (Taiwan) Inc. | Magneto-resistive random access memory |
US20020109167A1 (en) * | 2000-12-28 | 2002-08-15 | Kang Chang Yong | Memory device and method of fabrication thereof |
US6436526B1 (en) * | 1999-06-17 | 2002-08-20 | Matsushita Electric Industrial Co., Ltd. | Magneto-resistance effect element, magneto-resistance effect memory cell, MRAM and method for performing information write to or read from the magneto-resistance effect memory cell |
US6535416B1 (en) * | 1999-06-18 | 2003-03-18 | Nve Corporation | Magnetic memory coincident thermal pulse data storage |
US6555858B1 (en) * | 2000-11-15 | 2003-04-29 | Motorola, Inc. | Self-aligned magnetic clad write line and its method of formation |
US6556473B2 (en) * | 2000-07-27 | 2003-04-29 | Kabushiki Kaisha Toshiba | Magnetic memory with reduced write current |
US20030128578A1 (en) * | 2002-01-10 | 2003-07-10 | Perner Frederick A. | Magnetoresistive random access memory (MRAM) with on-chip automatic determination of optimized write current method and apparatus |
US20030156448A1 (en) * | 2000-09-22 | 2003-08-21 | Mitsubishi Denki Kabushiki Kaisha | Magnetic thin-film memory device for quick and stable reading data |
US6649960B1 (en) * | 2001-02-16 | 2003-11-18 | Maxtor Corporation | Synthetic free layer structure for MRAM devices |
US6687178B1 (en) * | 2001-02-23 | 2004-02-03 | Western Digital (Fremont), Inc. | Temperature dependent write current source for magnetic tunnel junction MRAM |
US6721203B1 (en) * | 2001-02-23 | 2004-04-13 | Western Digital (Fremont), Inc. | Designs of reference cells for magnetic tunnel junction (MTJ) MRAM |
US6791870B2 (en) * | 2002-01-16 | 2004-09-14 | Micron Technology, Inc. | Magnetoresistive memory devices and assemblies; and methods of storing and retrieving information |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4493690A (en) * | 1983-01-20 | 1985-01-15 | Rockwell International Corporation | Cam activated anti-dog-ear device |
US6611405B1 (en) | 1999-09-16 | 2003-08-26 | Kabushiki Kaisha Toshiba | Magnetoresistive element and magnetic memory device |
EP1143537A1 (en) | 1999-09-27 | 2001-10-10 | Matsushita Electric Industrial Co., Ltd. | Magnetoresistance effect memory device and method for producing the same |
KR100366702B1 (en) * | 2000-02-03 | 2003-01-08 | 삼성전자 주식회사 | Magnetic random access memory with circuits for write and read using magnetic tunnel junction (MTJ) devices |
DE10118197C2 (en) * | 2001-04-11 | 2003-04-03 | Infineon Technologies Ag | Integrated magnetoresistive semiconductor memory device and method for describing the same |
ATE461657T1 (en) | 2001-06-22 | 2010-04-15 | Abbeymoor Medical Inc | URETHRAL PROFILING DEVICE |
FR2832542B1 (en) * | 2001-11-16 | 2005-05-06 | Commissariat Energie Atomique | MAGNETIC DEVICE WITH MAGNETIC TUNNEL JUNCTION, MEMORY AND METHODS OF WRITING AND READING USING THE DEVICE |
-
2002
- 2002-01-16 US US10/051,679 patent/US6735111B2/en not_active Expired - Lifetime
-
2003
- 2003-01-02 EP EP03731884A patent/EP1466328A2/en not_active Ceased
- 2003-01-02 CN CNB038057549A patent/CN100437816C/en not_active Expired - Lifetime
- 2003-01-02 WO PCT/US2003/000120 patent/WO2003063169A2/en active Application Filing
- 2003-01-02 AU AU2003210113A patent/AU2003210113A1/en not_active Abandoned
- 2003-01-02 JP JP2003562938A patent/JP4811627B2/en not_active Expired - Lifetime
- 2003-01-02 KR KR1020047011035A patent/KR100743328B1/en active IP Right Grant
- 2003-01-13 TW TW092100598A patent/TW588352B/en not_active IP Right Cessation
- 2003-04-18 US US10/418,406 patent/US6791870B2/en not_active Expired - Lifetime
-
2004
- 2004-08-10 US US10/915,931 patent/US20050014297A1/en not_active Abandoned
-
2006
- 2006-09-13 US US11/521,289 patent/US20070020774A1/en not_active Abandoned
Patent Citations (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5665695A (en) * | 1992-02-20 | 1997-09-09 | Binney & Smith Inc. | Surfactant composition and method of making the same |
US6381170B1 (en) * | 1993-10-01 | 2002-04-30 | Gary A. Prinz | Ultra high density, non-volatile ferromagnetic random access memory |
US5565695A (en) * | 1995-04-21 | 1996-10-15 | Johnson; Mark B. | Magnetic spin transistor hybrid circuit element |
US6055179A (en) * | 1998-05-19 | 2000-04-25 | Canon Kk | Memory device utilizing giant magnetoresistance effect |
US6097625A (en) * | 1998-07-16 | 2000-08-01 | International Business Machines Corporation | Magnetic random access memory (MRAM) array with magnetic tunnel junction (MTJ) cells and remote diodes |
US6005800A (en) * | 1998-11-23 | 1999-12-21 | International Business Machines Corporation | Magnetic memory array with paired asymmetric memory cells for improved write margin |
US6579729B2 (en) * | 1999-03-19 | 2003-06-17 | Infineon Technologies Ag | Memory cell configuration and method for fabricating it |
US20020064069A1 (en) * | 1999-03-19 | 2002-05-30 | Bernd Goebel | Memory cell configuration and method for fabricating it |
US6436526B1 (en) * | 1999-06-17 | 2002-08-20 | Matsushita Electric Industrial Co., Ltd. | Magneto-resistance effect element, magneto-resistance effect memory cell, MRAM and method for performing information write to or read from the magneto-resistance effect memory cell |
US6535416B1 (en) * | 1999-06-18 | 2003-03-18 | Nve Corporation | Magnetic memory coincident thermal pulse data storage |
US6188615B1 (en) * | 1999-10-29 | 2001-02-13 | Hewlett-Packard Company | MRAM device including digital sense amplifiers |
US6473336B2 (en) * | 1999-12-16 | 2002-10-29 | Kabushiki Kaisha Toshiba | Magnetic memory device |
US20020006058A1 (en) * | 1999-12-16 | 2002-01-17 | Kentaro Nakajima | Magnetic memory device |
US6272036B1 (en) * | 1999-12-20 | 2001-08-07 | The University Of Chicago | Control of magnetic direction in multi-layer ferromagnetic devices by bias voltage |
US20010019461A1 (en) * | 2000-03-03 | 2001-09-06 | Rolf Allenspach | Magnetic millipede for ultra high density magnetic storage |
US20010026471A1 (en) * | 2000-03-23 | 2001-10-04 | Masashi Michijima | Magnetic memory element, magnetic memory and manufacturing method of magnetic memory |
US6215707B1 (en) * | 2000-04-10 | 2001-04-10 | Motorola Inc. | Charge conserving write method and system for an MRAM |
US20010038548A1 (en) * | 2000-05-03 | 2001-11-08 | Perner Frederick A. | Write circuit for large MRAM arrays |
US20020001223A1 (en) * | 2000-06-30 | 2002-01-03 | Yoshiaki Saito | Solid-state magnetic memory |
US6556473B2 (en) * | 2000-07-27 | 2003-04-29 | Kabushiki Kaisha Toshiba | Magnetic memory with reduced write current |
US6272041B1 (en) * | 2000-08-28 | 2001-08-07 | Motorola, Inc. | MTJ MRAM parallel-parallel architecture |
US20030156448A1 (en) * | 2000-09-22 | 2003-08-21 | Mitsubishi Denki Kabushiki Kaisha | Magnetic thin-film memory device for quick and stable reading data |
US20020037595A1 (en) * | 2000-09-28 | 2002-03-28 | Keiji Hosotani | Semiconductor memory device utilizing tunnel magneto resistive effects and method for manufacturing the same |
US20020044481A1 (en) * | 2000-10-17 | 2002-04-18 | Mitsubishi Denki Kabushiki Kaisha | Thin film magnetic memory device capable of easily controlling a data write current |
US6385082B1 (en) * | 2000-11-08 | 2002-05-07 | International Business Machines Corp. | Thermally-assisted magnetic random access memory (MRAM) |
US20020057593A1 (en) * | 2000-11-14 | 2002-05-16 | Mitsubishi Denki Kabushiki Kaisha | Thin film magnetic memory device having a highly integrated memory array |
US6555858B1 (en) * | 2000-11-15 | 2003-04-29 | Motorola, Inc. | Self-aligned magnetic clad write line and its method of formation |
US20020109167A1 (en) * | 2000-12-28 | 2002-08-15 | Kang Chang Yong | Memory device and method of fabrication thereof |
US6421270B1 (en) * | 2000-12-29 | 2002-07-16 | Amic Technology (Taiwan) Inc. | Magneto-resistive random access memory |
US6649960B1 (en) * | 2001-02-16 | 2003-11-18 | Maxtor Corporation | Synthetic free layer structure for MRAM devices |
US6687178B1 (en) * | 2001-02-23 | 2004-02-03 | Western Digital (Fremont), Inc. | Temperature dependent write current source for magnetic tunnel junction MRAM |
US6721203B1 (en) * | 2001-02-23 | 2004-04-13 | Western Digital (Fremont), Inc. | Designs of reference cells for magnetic tunnel junction (MTJ) MRAM |
US6385083B1 (en) * | 2001-08-01 | 2002-05-07 | Hewlett-Packard Company | MRAM device including offset conductors |
US20030128578A1 (en) * | 2002-01-10 | 2003-07-10 | Perner Frederick A. | Magnetoresistive random access memory (MRAM) with on-chip automatic determination of optimized write current method and apparatus |
US6791870B2 (en) * | 2002-01-16 | 2004-09-14 | Micron Technology, Inc. | Magnetoresistive memory devices and assemblies; and methods of storing and retrieving information |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013096334A1 (en) * | 2011-12-19 | 2013-06-27 | Lam Research Corporation | Method of making device |
US8895323B2 (en) | 2011-12-19 | 2014-11-25 | Lam Research Corporation | Method of forming a magnetoresistive random-access memory device |
Also Published As
Publication number | Publication date |
---|---|
KR100743328B1 (en) | 2007-07-26 |
TW588352B (en) | 2004-05-21 |
AU2003210113A1 (en) | 2003-09-02 |
JP4811627B2 (en) | 2011-11-09 |
US20030205726A1 (en) | 2003-11-06 |
US20050014297A1 (en) | 2005-01-20 |
CN100437816C (en) | 2008-11-26 |
WO2003063169B1 (en) | 2004-03-25 |
KR20040073569A (en) | 2004-08-19 |
CN1643612A (en) | 2005-07-20 |
JP2006507656A (en) | 2006-03-02 |
WO2003063169A3 (en) | 2003-12-31 |
EP1466328A2 (en) | 2004-10-13 |
US20030133323A1 (en) | 2003-07-17 |
WO2003063169A2 (en) | 2003-07-31 |
US6735111B2 (en) | 2004-05-11 |
US6791870B2 (en) | 2004-09-14 |
TW200307942A (en) | 2003-12-16 |
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