US20060282604A1 - Methods and apparatus for processing graphics data using multiple processing circuits - Google Patents

Methods and apparatus for processing graphics data using multiple processing circuits Download PDF

Info

Publication number
US20060282604A1
US20060282604A1 US11/139,733 US13973305A US2006282604A1 US 20060282604 A1 US20060282604 A1 US 20060282604A1 US 13973305 A US13973305 A US 13973305A US 2006282604 A1 US2006282604 A1 US 2006282604A1
Authority
US
United States
Prior art keywords
graphics
graphics processing
integrated
processing
discrete
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/139,733
Inventor
Grigori Temkine
Oleg Drapkin
Gordon Caruk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ATI Technologies ULC
Original Assignee
ATI Technologies ULC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATI Technologies ULC filed Critical ATI Technologies ULC
Priority to US11/139,733 priority Critical patent/US20060282604A1/en
Assigned to ATI TECHNOLOGIES INC. reassignment ATI TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DRAPKIN, OLEG, TEMKINE, GRIGORI, CARUK, GORDON
Publication of US20060282604A1 publication Critical patent/US20060282604A1/en
Assigned to ATI TECHNOLOGIES ULC reassignment ATI TECHNOLOGIES ULC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: ATI TECHNOLOGIES INC.
Priority to US13/924,958 priority patent/US9424622B2/en
Priority to US15/229,679 priority patent/US9865030B2/en
Priority to US15/864,234 priority patent/US20190012760A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2210/00—Indexing scheme for image generation or computer graphics
    • G06T2210/52—Parallel processing

Definitions

  • the present disclosure relates to methods and apparatus for processing video graphics data using multiple processors and, more particularly, to processing video graphics data using a combination of integrated graphics processing circuitry and discrete graphics processing circuitry.
  • video graphics data that is to be processed from an application running on a processor may either be processed by integrated or discrete graphics processing circuitry.
  • Integrated graphics processing circuitry is typically circuitry integrated in a bridge circuit connected to the processor system bus, otherwise known as a “Northbridge.”
  • Discrete processing circuitry is typically an external graphics processing unit that connects to the Northbridge via an interconnect utilizing an interconnect standard such as AGP, PCI, or PCI Express.
  • AGP AGP, PCI, or PCI Express
  • FIG. 1 illustrates a typical computer architecture known in the art utilizing this type of parallel processing.
  • a main processor 102 such as a CPU or any other processing device is connected to a bridge circuit 104 via a system bus 106 .
  • the bridge circuit 104 which may be a Northbridge, includes an integrated graphics processing circuitry 108 , which may be used for video graphics processing if an external graphics processing unit is not connected to the bridge circuit 104 .
  • An example of a known Northbridge circuit utilizing an integrated graphics processing circuitry is ATI's Mobility Radeon® 9100 IGP integrated graphics processor sold by ATI Technologies, Inc. of Markham, Ontario, Canada.
  • the architecture of FIG. 1 also illustrates at least two external or discrete graphics processing units 110 and 112 connected to the bridge circuit 104 via respective interconnects 114 and 116 .
  • These interconnects 114 and 116 may comprise any known standard bus including AGP, PCI or PCI Express.
  • the discrete graphics processing units 110 and 112 may be configured such that one processing unit connects through the other processing unit to the bridge circuit 104 . This is shown, for example, by dashed line connection 117 , where interconnect 116 would not be present (also indicated by the dashing line 116 ).
  • a graphics job refers to a number of tasks, such as graphics processing or display operations, that are performed in conjunction to produce a display.
  • a graphics job could include multiple tasks such as vertex processing, 3D rendering, and driving the display that are performed in conjunction with one another to produce a display.
  • FIG. 1 illustrates an example of a conventional computer system architecture including integrated graphics processing as well as discrete graphics processing.
  • FIG. 2 illustrates a computer architecture according to an example of the present disclosure.
  • FIG. 3 illustrates a flow diagram of a method for achieving multiple graphics processing according to an example of the present disclosure.
  • a bridge circuit includes an integrated graphics processing circuit configured to process graphics data.
  • the bridge circuit also includes an interface operable according to a standard to interface with a discrete graphics processing circuit.
  • a controller which may be implemented with hardware, firmware or software, is also included and configured to detect when the external graphics processing circuit is connected to the interface and to cause the integrated graphics processing circuit to process at least a portion of the graphics data in conjunction with operation of the discrete graphics processing circuit, which processes another portion of the graphics data.
  • the portions of the data are each associated with respective processing functions.
  • processing graphics data or “to process graphics data” (or similar terms related to processing graphics data) may be tasks performed in a graphics job, as defined previously, and may include tasks performing calculations. Also included in these terms (i.e., processing graphics data, etc.) is the displaying of graphics data, whether or not displaying necessarily requires calculations.
  • the previously unutilized circuitry of the Northbridge is utilized, thus reducing the need for further external or discrete graphics processing units, thereby reducing system cost.
  • graphics tasks are split between the external and internal graphics processing units, less memory can be provided with the external graphics processing unit, which can greatly reduce the system cost.
  • the external graphics processing unit can be delegated to handle computationally intensive, latency insensitive, or low memory bandwidth tasks.
  • the integrated graphics processing circuitry is performing some of the graphics processing tasks, which were previously performed by a discrete graphics processing unit, the external graphics processing circuit will not require as much interconnect bandwidth and therefore will not need to utilize as many PCI Express lanes in the interface. Thus, a less expensive component can be built to perform these tasks.
  • FIG. 2 illustrates an example of an architecture 200 according to the present disclosure.
  • Architecture 200 includes a processor 202 such as a central processing unit or any other processor.
  • the processor is connected to a bridge circuit 204 , which is typically a Northbridge via a system bus 206 .
  • the Northbridge 204 in FIG. 2 includes an integrated graphics processing circuitry 208 configured to process video graphics data, such as data received from an application running on the processor 202 .
  • the circuit includes a main external graphics processing unit 210 connected to the Northbridge 204 with a standard interface 212 , such as AGP, PCI or PCI Express.
  • interface 212 will be assumed to operate according to PCI Express.
  • the main GPU drives external display media 214 , which may include one or more monitors, cell phone or PDA displays, or printers. It is noted that, an alternate connection from the Northbridge circuit 204 to the display media 214 may be utilized for display of data processed by circuitry 208 as indicated by dashed lined 216 .
  • the bridge circuit 204 includes a controller 218 , which may, or may not, have synchronization capabilities.
  • 218 may be a set of independent data paths.
  • 218 may be implemented as software, firmware, or hardware.
  • controller 218 is used to ensure the processing circuitry 208 remains functional when an external GPU 210 is connected to an interface 219 , which may be a PCI Express Interface, connecting the Northbridge 204 to the external GPU 210 .
  • controller 218 may establish separate data paths for the integrated graphics processing circuitry 208 and the discrete graphics processor 210 for each to independently access at least one of the system processing circuitry (e.g, CPU 202 ) and the system memory (e.g., memory 220 ). This independent access ensures that the graphics processing circuitry may remain enabled and capable of processing data when the external GPU 210 is connected. Therefore both GPUs ( 208 and 210 ) may be cooperatively used to process graphics information for the graphics job.
  • the system processing circuitry e.g, CPU 202
  • system memory e.g., memory 220
  • processing and frame buffer control which may be performed either in controller 218 , as shown, or processing circuitry 208 , or in software, is used to direct which tasks each of the different processing circuitries 208 and 210 will perform and also to control frame buffer delivery of processed video graphics data to the display media 214 .
  • FIG. 3 illustrates a flow diagram of an operational aspect of the system 200 .
  • the flow diagram 300 begin at an initialization block 302 .
  • a discrete graphics processor is connected to the bridge 204 as illustrated in block 304 .
  • this initialization may also include detection of the discrete graphics processor (e.g., processor 210 ) to the bridge 204 . This detection may be performed either by software running within processing circuitry 208 of the Northbridge 204 or by software run by the central processing unit 202 directing the Northbridge with information passed via the system bus 206 . Additionally, one of ordinary skill in the art will appreciate that the controller 218 may receive an acknowledgement of this detection.
  • the control of the integrated graphics processing circuitry 208 ensures that the circuitry 208 is not disabled according to conventional operation, but is kept active, or in the case where the system is booting up, initialization and enablement of the circuitry 208 is performed. This part of the process is illustrated in block 306 .
  • the flow then proceeds to block 308 where parallel graphics processing (i.e., processing performed in conjunction) is performed using both the integrated processing circuit 208 and the discrete processing circuitry 210 . After this operation, flow continues as illustrated in block 310 . It is noted that the operation in block 308 of FIG. 3 is a continuous, on-going operation performed as long as parallel graphics processing is being effected.
  • the controller 218 or the driver may divide processing tasks between circuitry 208 and circuitry 210 .
  • the types of tasks may be divided where the integrated graphics processing circuitry 208 performs calculating vertexes, whereas the discrete graphics processing unit 210 performs rendering.
  • tasks such as the 2D engine and 3D engine may be divided between the circuitry 208 and 210 .
  • the display could be driven by 208 and most, or all, of the graphics calculations would be performed by the discrete graphics processing unit 210 .
  • processing tasks may be allocated by the synchronization controller 218 based on determining the currently available processing resources of the integrated circuitry 208 and external circuitry 210 .
  • typical integrated graphics processing circuitry has less capacity and performance than discrete graphics processors. Accordingly, tasks which do not have high performance requirements, such as 2D rendering, could be given preference for processing by the integrated graphics whereas 3D processing would be performed by the discrete graphics processor 210 .
  • the discrete graphics has limited memory resources, tasks with considerable memory needs could be given preference for processing by the integrated graphics processor, whereas tasks that require less memory resources are given to the discrete graphics processor.
  • PCI Express bus 212 may be optimized by performing processing tasks with the integrated graphics processing circuit 208 that may be simply “pass through” the main graphics processor 210 without any further processing, thus minimizing the utilization of the PCI Express bus 212 as information is sent from the processing circuitry 208 to the external processor 210 to be displayed by the display media 214 .
  • processed video graphics data may be sent directly from the processing circuitry 208 via an interface on the Northbridge and a connection 216 to the display media 214 in order reduce utilization of resources of the PCI Express bus 212 .
  • the disclosed methods and apparatus afford cost reduction by utilizing extant processing resources typically found on a Northbridge circuit, which previously were wasted when an external graphics processing unit was connected to the Northbridge. Additionally, the number of external interfaces from the bridge circuit 204 is reduced as only one external or discrete graphics processing circuit 210 is utilized, while providing multiple, parallel graphics processing, as illustrated in the example of FIG. 2 .
  • a further feature of the presently disclosed methods and apparatus is that the dividing of the full range of tasks for the graphics job between the internal and external graphics processing units affords the graphics subsystem the ability to tune the processing to utilize the available resources for maximum efficiency.
  • the various tasks for each graphics job are distributed to the graphics processing units that can process them while using the least amount of system resources in the least amount of time.
  • An example of this optimization is PCI Express. Since PCI Express requires equal numbers of downstream and upstream circuits, circuits may not be dynamically allocated from upstream to downstream data transmission. Thus, by performing certain processing tasks which require many bytes of system memory for each byte of data produced with the integrated graphics processing circuitry, less transmission from the Northbridge to the external graphics processor will be required.
  • the disclosed processor, circuits or graphic processor(s) may process information and/or output information in any suitable color space including but not limited to Y,U,V, RGB, YPbPr or CMYK (cyan, magenta, yellow, black) color spaces. Suitable considerations should be taken into account when converting from RGB to CMYK or vice versa or between any two color spaces. For example, as is known, the ink type, paper type, brightness settings, and other factors should be considered in converting from or to RGB space and CMYK space as a color displayed on a display screen may be different from that output by a color printing operation.
  • CMYK color space relates particularly to subtractive color technologies, where adding more color takes a pixel or dot closer to black, just as RGB relates to additive color technologies (where adding more color takes a pixel or dot closer to white).
  • pixel information, or dot color information may be processed and/or output for any suitable display medium including electronic display screens or for printers on display medium such as paper, film or any other suitable article.

Abstract

Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Description

    TECHNICAL FIELD
  • The present disclosure relates to methods and apparatus for processing video graphics data using multiple processors and, more particularly, to processing video graphics data using a combination of integrated graphics processing circuitry and discrete graphics processing circuitry.
    • BACKGROUND
  • In typical computer architectures, video graphics data that is to be processed from an application running on a processor, for example, may either be processed by integrated or discrete graphics processing circuitry. Integrated graphics processing circuitry is typically circuitry integrated in a bridge circuit connected to the processor system bus, otherwise known as a “Northbridge.” Discrete processing circuitry is typically an external graphics processing unit that connects to the Northbridge via an interconnect utilizing an interconnect standard such as AGP, PCI, or PCI Express. In order to further increase the processing resources for video graphics processing, it is also known to utilize one or more discrete graphics processing units working in parallel, all of which are connected to the Northbridge via standard interconnects.
  • FIG. 1 illustrates a typical computer architecture known in the art utilizing this type of parallel processing. As shown, a main processor 102, such as a CPU or any other processing device is connected to a bridge circuit 104 via a system bus 106. As shown, the bridge circuit 104, which may be a Northbridge, includes an integrated graphics processing circuitry 108, which may be used for video graphics processing if an external graphics processing unit is not connected to the bridge circuit 104. An example of a known Northbridge circuit utilizing an integrated graphics processing circuitry is ATI's Mobility Radeon® 9100 IGP integrated graphics processor sold by ATI Technologies, Inc. of Markham, Ontario, Canada.
  • The architecture of FIG. 1 also illustrates at least two external or discrete graphics processing units 110 and 112 connected to the bridge circuit 104 via respective interconnects 114 and 116. These interconnects 114 and 116 may comprise any known standard bus including AGP, PCI or PCI Express. Additionally, the discrete graphics processing units 110 and 112 may be configured such that one processing unit connects through the other processing unit to the bridge circuit 104. This is shown, for example, by dashed line connection 117, where interconnect 116 would not be present (also indicated by the dashing line 116).
  • Currently when an add-in card, such as GPU 110 is plugged into an AGP, PCI or PCI Express slot connected to the Northbridge circuit 104, the processing circuitry 108 in the Northbridge 104 is not utilized and only the external graphics processing unit, such as GPU 110 is used to perform processing of graphics data. Accordingly, the resources of the integrated graphics processing circuitry 108 are usually not utilized and, thus, wasted.
  • Moreover, as discussed previously, it is known to employ parallel processors, such as GPU 110 and GPU 112 in order to increase the processing capacity and band width of the system 100 in order to deliver processed video and graphics to display media 118, which may include one or more monitors, PDA displays, cell phone displays or printers. Although the utilization of multiple graphics processing units (e.g., 110, 112) increases the system processing capacity, existing processing circuitry 108, as mentioned above, cannot be applied to the same graphics job, and potentially is unused when one or more external or discrete processing units are connected to the Northbridge circuit 104. It is noted that a graphics job, for purposes of this application, refers to a number of tasks, such as graphics processing or display operations, that are performed in conjunction to produce a display. For example, a graphics job could include multiple tasks such as vertex processing, 3D rendering, and driving the display that are performed in conjunction with one another to produce a display.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates an example of a conventional computer system architecture including integrated graphics processing as well as discrete graphics processing.
  • FIG. 2 illustrates a computer architecture according to an example of the present disclosure.
  • FIG. 3 illustrates a flow diagram of a method for achieving multiple graphics processing according to an example of the present disclosure.
    • DETAILED DESCRIPTION OF THE PRESENT EXAMPLES
  • The present disclosure relates to methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics data. The bridge circuit also includes an interface operable according to a standard to interface with a discrete graphics processing circuit. A controller, which may be implemented with hardware, firmware or software, is also included and configured to detect when the external graphics processing circuit is connected to the interface and to cause the integrated graphics processing circuit to process at least a portion of the graphics data in conjunction with operation of the discrete graphics processing circuit, which processes another portion of the graphics data. The portions of the data are each associated with respective processing functions.
  • It is noted that the terms “processing graphics data” or “to process graphics data” (or similar terms related to processing graphics data) may be tasks performed in a graphics job, as defined previously, and may include tasks performing calculations. Also included in these terms (i.e., processing graphics data, etc.) is the displaying of graphics data, whether or not displaying necessarily requires calculations.
  • By using the internal graphics processing circuitry of a Northbridge circuit as one of the graphics controllers in a dual graphics controller architecture, the previously unutilized circuitry of the Northbridge is utilized, thus reducing the need for further external or discrete graphics processing units, thereby reducing system cost. Moreover, because graphics tasks are split between the external and internal graphics processing units, less memory can be provided with the external graphics processing unit, which can greatly reduce the system cost. For example, if the system is configured such that the internal graphics processing unit handles real time clients, which require careful control over latency and memory usage, the external graphics processing unit can be delegated to handle computationally intensive, latency insensitive, or low memory bandwidth tasks.
  • Additionally, by using the integrated graphics of the Northbridge, fewer external interfaces are required on the Northbridge circuit, further reducing the cost of the system. Moreover, in a system utilizing PCI Express, in particular, the downstream load over the PCI Express bus is potentially reduced in contrast to a dual discrete graphics processing system due to the above mentioned reduction in link bandwidth. That is, the integrated graphics processing circuitry is performing some of the graphics processing tasks, which were previously performed by a discrete graphics processing unit, the external graphics processing circuit will not require as much interconnect bandwidth and therefore will not need to utilize as many PCI Express lanes in the interface. Thus, a less expensive component can be built to perform these tasks.
  • FIG. 2 illustrates an example of an architecture 200 according to the present disclosure. Architecture 200 includes a processor 202 such as a central processing unit or any other processor. The processor is connected to a bridge circuit 204, which is typically a Northbridge via a system bus 206. Similar to the conventional system illustrated in FIG. 1, the Northbridge 204 in FIG. 2 includes an integrated graphics processing circuitry 208 configured to process video graphics data, such as data received from an application running on the processor 202. Additionally, the circuit includes a main external graphics processing unit 210 connected to the Northbridge 204 with a standard interface 212, such as AGP, PCI or PCI Express. For purposes of the disclosed examples, interface 212 will be assumed to operate according to PCI Express.
  • Typically, the main GPU drives external display media 214, which may include one or more monitors, cell phone or PDA displays, or printers. It is noted that, an alternate connection from the Northbridge circuit 204 to the display media 214 may be utilized for display of data processed by circuitry 208 as indicated by dashed lined 216.
  • In order to maintain operation of integrated graphics processing circuitry, such as circuitry 208, when an external or discrete graphics processing unit is connected to the Northbridge 204, the bridge circuit 204 includes a controller 218, which may, or may not, have synchronization capabilities. 218 may be a set of independent data paths. 218 may be implemented as software, firmware, or hardware. In particular, controller 218 is used to ensure the processing circuitry 208 remains functional when an external GPU 210 is connected to an interface 219, which may be a PCI Express Interface, connecting the Northbridge 204 to the external GPU 210. More particularly, controller 218 may establish separate data paths for the integrated graphics processing circuitry 208 and the discrete graphics processor 210 for each to independently access at least one of the system processing circuitry (e.g, CPU 202) and the system memory (e.g., memory 220). This independent access ensures that the graphics processing circuitry may remain enabled and capable of processing data when the external GPU 210 is connected. Therefore both GPUs (208 and 210) may be cooperatively used to process graphics information for the graphics job.
  • Additionally, processing and frame buffer control, which may be performed either in controller 218, as shown, or processing circuitry 208, or in software, is used to direct which tasks each of the different processing circuitries 208 and 210 will perform and also to control frame buffer delivery of processed video graphics data to the display media 214. This affords the system 200 the capability of off-loading processing from the external GPU to the processing circuitry 208 on the Northbridge 204.
  • FIG. 3 illustrates a flow diagram of an operational aspect of the system 200. The flow diagram 300 begin at an initialization block 302. Next, a discrete graphics processor is connected to the bridge 204 as illustrated in block 304. It is noted that this initialization may also include detection of the discrete graphics processor (e.g., processor 210) to the bridge 204. This detection may be performed either by software running within processing circuitry 208 of the Northbridge 204 or by software run by the central processing unit 202 directing the Northbridge with information passed via the system bus 206. Additionally, one of ordinary skill in the art will appreciate that the controller 218 may receive an acknowledgement of this detection.
  • Once the detection information is received by the controller 218, the control of the integrated graphics processing circuitry 208 ensures that the circuitry 208 is not disabled according to conventional operation, but is kept active, or in the case where the system is booting up, initialization and enablement of the circuitry 208 is performed. This part of the process is illustrated in block 306. The flow then proceeds to block 308 where parallel graphics processing (i.e., processing performed in conjunction) is performed using both the integrated processing circuit 208 and the discrete processing circuitry 210. After this operation, flow continues as illustrated in block 310. It is noted that the operation in block 308 of FIG. 3 is a continuous, on-going operation performed as long as parallel graphics processing is being effected.
  • The particular methods in which the frame buffer controller 218, or the software driver, direct processing of video graphics data received from an application are varied and numerous. According to one example, the controller 218 or the driver may divide processing tasks between circuitry 208 and circuitry 210. For example, the types of tasks may be divided where the integrated graphics processing circuitry 208 performs calculating vertexes, whereas the discrete graphics processing unit 210 performs rendering. In yet another example, tasks such as the 2D engine and 3D engine may be divided between the circuitry 208 and 210. In yet another example, the display could be driven by 208 and most, or all, of the graphics calculations would be performed by the discrete graphics processing unit 210. Although these examples are given, the different tasks allocated between multiple processors, and the methods of dividing or allocating tasks between the integrated circuitry and discrete circuitry are not limited to these and may include any other suitable methods that may be contemplated by those skilled in the art.
  • Further, it is contemplated that the processing tasks may be allocated by the synchronization controller 218 based on determining the currently available processing resources of the integrated circuitry 208 and external circuitry 210. For example, typical integrated graphics processing circuitry has less capacity and performance than discrete graphics processors. Accordingly, tasks which do not have high performance requirements, such as 2D rendering, could be given preference for processing by the integrated graphics whereas 3D processing would be performed by the discrete graphics processor 210. In the case where the discrete graphics has limited memory resources, tasks with considerable memory needs could be given preference for processing by the integrated graphics processor, whereas tasks that require less memory resources are given to the discrete graphics processor. Additionally, the utilization of PCI Express bus 212 may be optimized by performing processing tasks with the integrated graphics processing circuit 208 that may be simply “pass through” the main graphics processor 210 without any further processing, thus minimizing the utilization of the PCI Express bus 212 as information is sent from the processing circuitry 208 to the external processor 210 to be displayed by the display media 214. Alternatively, processed video graphics data may be sent directly from the processing circuitry 208 via an interface on the Northbridge and a connection 216 to the display media 214 in order reduce utilization of resources of the PCI Express bus 212.
  • As mentioned previously, the disclosed methods and apparatus afford cost reduction by utilizing extant processing resources typically found on a Northbridge circuit, which previously were wasted when an external graphics processing unit was connected to the Northbridge. Additionally, the number of external interfaces from the bridge circuit 204 is reduced as only one external or discrete graphics processing circuit 210 is utilized, while providing multiple, parallel graphics processing, as illustrated in the example of FIG. 2.
  • A further feature of the presently disclosed methods and apparatus is that the dividing of the full range of tasks for the graphics job between the internal and external graphics processing units affords the graphics subsystem the ability to tune the processing to utilize the available resources for maximum efficiency. The various tasks for each graphics job are distributed to the graphics processing units that can process them while using the least amount of system resources in the least amount of time. An example of this optimization is PCI Express. Since PCI Express requires equal numbers of downstream and upstream circuits, circuits may not be dynamically allocated from upstream to downstream data transmission. Thus, by performing certain processing tasks which require many bytes of system memory for each byte of data produced with the integrated graphics processing circuitry, less transmission from the Northbridge to the external graphics processor will be required.
  • It will be recognized that all or some of the disclosed operations may be useful as applied to printers or other devices. For example, the disclosed processor, circuits or graphic processor(s) may process information and/or output information in any suitable color space including but not limited to Y,U,V, RGB, YPbPr or CMYK (cyan, magenta, yellow, black) color spaces. Suitable considerations should be taken into account when converting from RGB to CMYK or vice versa or between any two color spaces. For example, as is known, the ink type, paper type, brightness settings, and other factors should be considered in converting from or to RGB space and CMYK space as a color displayed on a display screen may be different from that output by a color printing operation.
  • The CMYK color space relates particularly to subtractive color technologies, where adding more color takes a pixel or dot closer to black, just as RGB relates to additive color technologies (where adding more color takes a pixel or dot closer to white). As such, if desired, pixel information, or dot color information, may be processed and/or output for any suitable display medium including electronic display screens or for printers on display medium such as paper, film or any other suitable article.
  • The above-detailed description of the examples has been presented for the purposes of illustration and description and not by limitation. It is therefore contemplated that the present application covers any additional modifications, variations or equivalents that fall within the spirit and scope of the basic underlying principles disclosed above and the appended claims.

Claims (11)

1. A method comprising:
coupling discrete graphics processing configured to process graphics data with a bridge circuit having integrated graphics processing; and
processing at least a portion of the graphics data with the integrated graphics processing in the bridge circuit and processing at least another portion of the data with the discrete graphics processor unit, the portions of the data being associated with respective graphics tasks of a graphics job.
2. The method as defined in claim 1, further comprising:
enabling functionality of the integrated graphics processing whenever the discrete graphics processing is coupled with the bridge circuit.
3. The method as defined in claim 2, wherein enabling functionality of the integrated processing includes:
establishing separate data paths enabling the integrated graphics processing and the discrete graphics processing to independently access system resources.
4. A method for processing at least one graphics job comprising:
processing at least one task of a graphics job using integrated graphics processing circuitry in the bridge circuit; and
processing at least another task of the graphics job using a discrete graphics processor unit.
5. The method as defined in claim 4, further comprising:
enabling functionality of the integrated graphics processing circuitry whenever the discrete graphics processing is coupled with the integrated graphics processing circuitry.
6. The method as defined in claim 5, wherein enabling functionality of the integrated processing circuitry includes:
establishing separate data paths enabling the integrated graphics processing circuitry and the discrete graphics processor to independently access at least one of system processing circuitry and system memory.
7. A bridge circuit comprising:
an integrated graphics processing circuit configured to process graphics jobs from an application run on a processor;
an interface operable to interface with a discrete graphics processing circuit;
a controller configured to detect when a discrete graphics processing circuit is coupled to the interface and to cause the integrated graphics processing circuit to be operable to process at least one task of a graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process at least one other task of the graphics job.
8. The bridge circuit as defined in claim 7, wherein the controller is further configured to enable functionality of the integrated processing circuitry whenever a discrete graphics processor is coupled to the bridge circuit.
9. The bridge circuit as defined in claim 8, wherein the controller is further configured to establish separate data paths enabling the integrated graphics processing circuit and the discrete graphics processor to independently access at least one of system processing circuitry and a system memory.
10. A graphics processing circuit comprising:
a first graphics processing circuitry configured to process graphics jobs from an application and to couple with an interface operable to interface with at least a second graphics processing circuitry; and
a controller responsive to the coupling of the second external graphics processing circuitry to the interface and configured to cause the first graphics processing circuitry to be operable to process at least a task of a graphics job in conjunction with operation of the second graphics processing circuitry that is operable to process at least one other task of the graphics job.
11. The graphics processing circuit as defined in claim 10, wherein the controller is further configured to enable functionality of the first graphics processing circuitry whenever the second graphics processing circuitry is coupled to the first graphics processing circuitry.
US11/139,733 2005-05-27 2005-05-27 Methods and apparatus for processing graphics data using multiple processing circuits Abandoned US20060282604A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US11/139,733 US20060282604A1 (en) 2005-05-27 2005-05-27 Methods and apparatus for processing graphics data using multiple processing circuits
US13/924,958 US9424622B2 (en) 2005-05-27 2013-06-24 Methods and apparatus for processing graphics data using multiple processing circuits
US15/229,679 US9865030B2 (en) 2005-05-27 2016-08-05 Methods and apparatus for processing graphics data using multiple processing circuits
US15/864,234 US20190012760A1 (en) 2005-05-27 2018-01-08 Methods and apparatus for processing graphics data using multiple processing circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/139,733 US20060282604A1 (en) 2005-05-27 2005-05-27 Methods and apparatus for processing graphics data using multiple processing circuits

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/924,958 Continuation US9424622B2 (en) 2005-05-27 2013-06-24 Methods and apparatus for processing graphics data using multiple processing circuits

Publications (1)

Publication Number Publication Date
US20060282604A1 true US20060282604A1 (en) 2006-12-14

Family

ID=37525377

Family Applications (4)

Application Number Title Priority Date Filing Date
US11/139,733 Abandoned US20060282604A1 (en) 2005-05-27 2005-05-27 Methods and apparatus for processing graphics data using multiple processing circuits
US13/924,958 Active US9424622B2 (en) 2005-05-27 2013-06-24 Methods and apparatus for processing graphics data using multiple processing circuits
US15/229,679 Active US9865030B2 (en) 2005-05-27 2016-08-05 Methods and apparatus for processing graphics data using multiple processing circuits
US15/864,234 Abandoned US20190012760A1 (en) 2005-05-27 2018-01-08 Methods and apparatus for processing graphics data using multiple processing circuits

Family Applications After (3)

Application Number Title Priority Date Filing Date
US13/924,958 Active US9424622B2 (en) 2005-05-27 2013-06-24 Methods and apparatus for processing graphics data using multiple processing circuits
US15/229,679 Active US9865030B2 (en) 2005-05-27 2016-08-05 Methods and apparatus for processing graphics data using multiple processing circuits
US15/864,234 Abandoned US20190012760A1 (en) 2005-05-27 2018-01-08 Methods and apparatus for processing graphics data using multiple processing circuits

Country Status (1)

Country Link
US (4) US20060282604A1 (en)

Cited By (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050270988A1 (en) * 2004-06-04 2005-12-08 Dehaemer Eric Mechanism of dynamic upstream port selection in a PCI express switch
US20060125833A1 (en) * 2004-12-10 2006-06-15 Wen-Chi Hung Image display device and method thereof
US20070162624A1 (en) * 2005-12-12 2007-07-12 Tamasi Anthony M System and method for configurable digital communication
US20070263004A1 (en) * 2006-05-12 2007-11-15 Xgi Technology Inc. Plug-in graphics module architecture
US20090037633A1 (en) * 2007-07-31 2009-02-05 Solomon Mark C Graphics processor in a docking station
US7499051B1 (en) 2005-04-29 2009-03-03 Adobe Systems Incorporated GPU assisted 3D compositing
EP2034400A2 (en) 2007-09-06 2009-03-11 Dell Products, L.P. System and method for an information handling system having an external graphics processor system for operating multiple monitors
US20090138647A1 (en) * 2007-11-26 2009-05-28 Hagita Yasuharu Bus switch, electronic equipment, and data transfer method
US7598952B1 (en) 2005-04-29 2009-10-06 Adobe Systems Incorporatted Three-dimensional image compositing on a GPU utilizing multiple transformations
US7777748B2 (en) 2003-11-19 2010-08-17 Lucid Information Technology, Ltd. PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applications
US7793029B1 (en) 2005-05-17 2010-09-07 Nvidia Corporation Translation device apparatus for configuring printed circuit board connectors
US7796130B2 (en) 2003-11-19 2010-09-14 Lucid Information Technology, Ltd. PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation
US7808504B2 (en) 2004-01-28 2010-10-05 Lucid Information Technology, Ltd. PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications
US7827333B1 (en) * 2008-02-04 2010-11-02 Nvidia Corporation System and method for determining a bus address on an add-in card
US7886094B1 (en) * 2005-06-15 2011-02-08 Nvidia Corporation Method and system for handshaking configuration between core logic components and graphics processors
US20110063302A1 (en) * 2009-09-16 2011-03-17 Nvidia Corporation Compression for co-processing techniques on heterogeneous graphics processing units
US7961194B2 (en) 2003-11-19 2011-06-14 Lucid Information Technology, Ltd. Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
US20110157189A1 (en) * 2009-12-31 2011-06-30 Nvidia Corporation Shared buffer techniques for heterogeneous hybrid graphics
US20110169840A1 (en) * 2006-12-31 2011-07-14 Lucid Information Technology, Ltd Computing system employing a multi-gpu graphics processing and display subsystem supporting single-gpu non-parallel (multi-threading) and multi-gpu application-division parallel modes of graphics processing operation
US8021193B1 (en) 2005-04-25 2011-09-20 Nvidia Corporation Controlled impedance display adapter
US8035641B1 (en) 2007-11-28 2011-10-11 Adobe Systems Incorporated Fast depth of field simulation
US8085273B2 (en) 2003-11-19 2011-12-27 Lucid Information Technology, Ltd Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
WO2012050560A1 (en) * 2010-10-11 2012-04-19 Hewlett-Packard Development Company, L.P. First and second software stacks and discrete and integrated graphics processing units
US8284207B2 (en) 2003-11-19 2012-10-09 Lucid Information Technology, Ltd. Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operations
US8395619B1 (en) * 2008-10-02 2013-03-12 Nvidia Corporation System and method for transferring pre-computed Z-values between GPUs
US8412872B1 (en) * 2005-12-12 2013-04-02 Nvidia Corporation Configurable GPU and method for graphics processing using a configurable GPU
US8427496B1 (en) 2005-05-13 2013-04-23 Nvidia Corporation Method and system for implementing compression across a graphics bus interconnect
US8497865B2 (en) 2006-12-31 2013-07-30 Lucid Information Technology, Ltd. Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS
US20140028689A1 (en) * 2011-12-16 2014-01-30 Sing Hook Arther Teng Method, apparatus, and system for expanding graphical processing via an external display-data i/o port
US8704275B2 (en) 2004-09-15 2014-04-22 Nvidia Corporation Semiconductor die micro electro-mechanical switch management method
US8711156B1 (en) 2004-09-30 2014-04-29 Nvidia Corporation Method and system for remapping processing elements in a pipeline of a graphics processing unit
US8711161B1 (en) 2003-12-18 2014-04-29 Nvidia Corporation Functional component compensation reconfiguration system and method
US8724483B2 (en) 2007-10-22 2014-05-13 Nvidia Corporation Loopback configuration for bi-directional interfaces
US8732644B1 (en) 2003-09-15 2014-05-20 Nvidia Corporation Micro electro mechanical switch system and method for testing and configuring semiconductor functional circuits
US20140152674A1 (en) * 2012-12-03 2014-06-05 Samsung Electronics Co., Ltd. Electronic apparatus, external apparatus and method of controlling the same
US8768642B2 (en) 2003-09-15 2014-07-01 Nvidia Corporation System and method for remotely configuring semiconductor functional circuits
US8775997B2 (en) 2003-09-15 2014-07-08 Nvidia Corporation System and method for testing and configuring semiconductor functional circuits
US8780122B2 (en) 2009-09-16 2014-07-15 Nvidia Corporation Techniques for transferring graphics data from system memory to a discrete GPU
US9331869B2 (en) 2010-03-04 2016-05-03 Nvidia Corporation Input/output request packet handling techniques by a device specific kernel mode driver
EP3016074A1 (en) * 2014-10-22 2016-05-04 Samsung Electronics Co., Ltd Hybrid rendering apparatus and method
US9424622B2 (en) 2005-05-27 2016-08-23 Ati Technologies Ulc Methods and apparatus for processing graphics data using multiple processing circuits
US9591309B2 (en) 2012-12-31 2017-03-07 Nvidia Corporation Progressive lossy memory compression
US9607407B2 (en) 2012-12-31 2017-03-28 Nvidia Corporation Variable-width differential memory compression
US20170091981A1 (en) * 2010-05-29 2017-03-30 Intel Corporation Non-volatile storage for graphics hardware
US20170140570A1 (en) * 2015-11-13 2017-05-18 Intel Corporation Facilitating efficeint centralized rendering of viewpoint-agnostic graphics workloads at computing devices
US20170235700A1 (en) * 2008-10-03 2017-08-17 Advanced Micro Devices, Inc. Peripheral component
US9947070B2 (en) * 2016-09-08 2018-04-17 Dell Products L.P. GPU that passes PCIe via displayport for routing to a USB type-C connector
US9977756B2 (en) 2008-10-03 2018-05-22 Advanced Micro Devices, Inc. Internal bus architecture and method in multi-processor systems
US10157492B1 (en) 2008-10-02 2018-12-18 Nvidia Corporation System and method for transferring pre-computed Z-values between GPUS
CN111007998A (en) * 2019-12-24 2020-04-14 联想(北京)有限公司 Processing method, system and electronic equipment
CN111612684A (en) * 2019-02-22 2020-09-01 环达电脑(上海)有限公司 Electronic device and control method thereof
US11347673B2 (en) * 2017-09-30 2022-05-31 Intel Corporation Method, apparatus, system for thunderbolt-based display topology for dual graphics systems
US20220187898A1 (en) * 2006-12-31 2022-06-16 Google Llc Apparatus and method for power management of a computing system
US11423588B2 (en) 2019-11-05 2022-08-23 Adobe Inc. Color transforms using static shaders compiled at initialization

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140328018A1 (en) * 2013-05-03 2014-11-06 Nvidia Corporation Fanless notebook computer structure providing enhanced graphics performance and form factor
US20150332426A1 (en) * 2014-05-16 2015-11-19 Hon Hai Precision Industry Co., Ltd. Transformable computing device with parallel processing cpus and discrete gpu
US10861126B1 (en) * 2019-06-21 2020-12-08 Intel Corporation Asynchronous execution mechanism

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862156A (en) * 1984-05-21 1989-08-29 Atari Corporation Video computer system including multiple graphics controllers and associated method
US5185858A (en) * 1989-12-01 1993-02-09 Megatek Corporation Image priority video switch
US5712664A (en) * 1993-10-14 1998-01-27 Alliance Semiconductor Corporation Shared memory graphics accelerator system
US5799204A (en) * 1995-05-01 1998-08-25 Intergraph Corporation System utilizing BIOS-compatible high performance video controller being default controller at boot-up and capable of switching to another graphics controller after boot-up
US6028643A (en) * 1997-09-03 2000-02-22 Colorgraphic Communications Corporation Multiple-screen video adapter with television tuner
US6424320B1 (en) * 1999-06-15 2002-07-23 Ati International Srl Method and apparatus for rendering video
US20030188075A1 (en) * 1999-12-20 2003-10-02 Peleg Alex D. CPU expandability bus
US20050190190A1 (en) * 2004-02-27 2005-09-01 Nvidia Corporation Graphics device clustering with PCI-express
US20060028478A1 (en) * 2004-04-23 2006-02-09 Nvidia Corporation Point-to-point bus bridging without a bridge controller

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2097954A1 (en) 1992-06-30 1993-12-31 Eric Youngman Nubus dual display card
AT405459B (en) 1992-12-09 1999-08-25 Freiherr Von Leonhardi Vertrie DETECTION AND RECORDING DEVICE
US5793996A (en) * 1995-05-03 1998-08-11 Apple Computer, Inc. Bridge for interconnecting a computer system bus, an expansion bus and a video frame buffer
US6025840A (en) 1995-09-27 2000-02-15 Cirrus Logic, Inc. Circuits, systems and methods for memory mapping and display control systems using the same
US6104417A (en) * 1996-09-13 2000-08-15 Silicon Graphics, Inc. Unified memory computer architecture with dynamic graphics memory allocation
US6611272B1 (en) * 1998-07-02 2003-08-26 Microsoft Corporation Method and apparatus for rasterizing in a hierarchical tile order
US6275240B1 (en) * 1999-05-27 2001-08-14 Intel Corporation Method and apparatus for maintaining load balance on a graphics bus when an upgrade device is installed
US6760031B1 (en) * 1999-12-31 2004-07-06 Intel Corporation Upgrading an integrated graphics subsystem
US6630936B1 (en) * 2000-09-28 2003-10-07 Intel Corporation Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (BLT) in parallel
US7663633B1 (en) * 2004-06-25 2010-02-16 Nvidia Corporation Multiple GPU graphics system for implementing cooperative graphics instruction execution
US7466316B1 (en) * 2004-12-14 2008-12-16 Nvidia Corporation Apparatus, system, and method for distributing work to integrated heterogeneous processors
US7372465B1 (en) * 2004-12-17 2008-05-13 Nvidia Corporation Scalable graphics processing for remote display
US7586492B2 (en) * 2004-12-20 2009-09-08 Nvidia Corporation Real-time display post-processing using programmable hardware
US20060282604A1 (en) 2005-05-27 2006-12-14 Ati Technologies, Inc. Methods and apparatus for processing graphics data using multiple processing circuits

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862156A (en) * 1984-05-21 1989-08-29 Atari Corporation Video computer system including multiple graphics controllers and associated method
US5185858A (en) * 1989-12-01 1993-02-09 Megatek Corporation Image priority video switch
US5712664A (en) * 1993-10-14 1998-01-27 Alliance Semiconductor Corporation Shared memory graphics accelerator system
US5799204A (en) * 1995-05-01 1998-08-25 Intergraph Corporation System utilizing BIOS-compatible high performance video controller being default controller at boot-up and capable of switching to another graphics controller after boot-up
US6028643A (en) * 1997-09-03 2000-02-22 Colorgraphic Communications Corporation Multiple-screen video adapter with television tuner
US6100936A (en) * 1997-09-03 2000-08-08 Colorgraphic Communications Corporation Multiple-screen video adapter with television tuner
US6424320B1 (en) * 1999-06-15 2002-07-23 Ati International Srl Method and apparatus for rendering video
US20030188075A1 (en) * 1999-12-20 2003-10-02 Peleg Alex D. CPU expandability bus
US20050190190A1 (en) * 2004-02-27 2005-09-01 Nvidia Corporation Graphics device clustering with PCI-express
US20060028478A1 (en) * 2004-04-23 2006-02-09 Nvidia Corporation Point-to-point bus bridging without a bridge controller

Cited By (110)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8872833B2 (en) 2003-09-15 2014-10-28 Nvidia Corporation Integrated circuit configuration system and method
US8732644B1 (en) 2003-09-15 2014-05-20 Nvidia Corporation Micro electro mechanical switch system and method for testing and configuring semiconductor functional circuits
US8768642B2 (en) 2003-09-15 2014-07-01 Nvidia Corporation System and method for remotely configuring semiconductor functional circuits
US8775112B2 (en) 2003-09-15 2014-07-08 Nvidia Corporation System and method for increasing die yield
US8775997B2 (en) 2003-09-15 2014-07-08 Nvidia Corporation System and method for testing and configuring semiconductor functional circuits
US8788996B2 (en) 2003-09-15 2014-07-22 Nvidia Corporation System and method for configuring semiconductor functional circuits
US7843457B2 (en) 2003-11-19 2010-11-30 Lucid Information Technology, Ltd. PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores supported on a plurality of graphics cards and said bridge chip during the running of a graphics application
US8754894B2 (en) 2003-11-19 2014-06-17 Lucidlogix Software Solutions, Ltd. Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications
US8629877B2 (en) 2003-11-19 2014-01-14 Lucid Information Technology, Ltd. Method of and system for time-division based parallelization of graphics processing units (GPUs) employing a hardware hub with router interfaced between the CPU and the GPUs for the transfer of geometric data and graphics commands and rendered pixel data within the system
US9584592B2 (en) 2003-11-19 2017-02-28 Lucidlogix Technologies Ltd. Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications
US7777748B2 (en) 2003-11-19 2010-08-17 Lucid Information Technology, Ltd. PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applications
US7944450B2 (en) 2003-11-19 2011-05-17 Lucid Information Technology, Ltd. Computing system having a hybrid CPU/GPU fusion-type graphics processing pipeline (GPPL) architecture
US7796130B2 (en) 2003-11-19 2010-09-14 Lucid Information Technology, Ltd. PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation
US7796129B2 (en) 2003-11-19 2010-09-14 Lucid Information Technology, Ltd. Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC bus
US7800610B2 (en) 2003-11-19 2010-09-21 Lucid Information Technology, Ltd. PC-based computing system employing a multi-GPU graphics pipeline architecture supporting multiple modes of GPU parallelization dymamically controlled while running a graphics application
US7800611B2 (en) 2003-11-19 2010-09-21 Lucid Information Technology, Ltd. Graphics hub subsystem for interfacing parallalized graphics processing units (GPUs) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC bus
US7800619B2 (en) 2003-11-19 2010-09-21 Lucid Information Technology, Ltd. Method of providing a PC-based computing system with parallel graphics processing capabilities
US7940274B2 (en) 2003-11-19 2011-05-10 Lucid Information Technology, Ltd Computing system having a multiple graphics processing pipeline (GPPL) architecture supported on multiple external graphics cards connected to an integrated graphics device (IGD) embodied within a bridge circuit
US7808499B2 (en) 2003-11-19 2010-10-05 Lucid Information Technology, Ltd. PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router
US8284207B2 (en) 2003-11-19 2012-10-09 Lucid Information Technology, Ltd. Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operations
US7812846B2 (en) 2003-11-19 2010-10-12 Lucid Information Technology, Ltd PC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation
US8134563B2 (en) 2003-11-19 2012-03-13 Lucid Information Technology, Ltd Computing system having multi-mode parallel graphics rendering subsystem (MMPGRS) employing real-time automatic scene profiling and mode control
US8125487B2 (en) 2003-11-19 2012-02-28 Lucid Information Technology, Ltd Game console system capable of paralleling the operation of multiple graphic processing units (GPUS) employing a graphics hub device supported on a game console board
US9405586B2 (en) 2003-11-19 2016-08-02 Lucidlogix Technologies, Ltd. Method of dynamic load-balancing within a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization
US8085273B2 (en) 2003-11-19 2011-12-27 Lucid Information Technology, Ltd Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US7961194B2 (en) 2003-11-19 2011-06-14 Lucid Information Technology, Ltd. Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
US8711161B1 (en) 2003-12-18 2014-04-29 Nvidia Corporation Functional component compensation reconfiguration system and method
US7808504B2 (en) 2004-01-28 2010-10-05 Lucid Information Technology, Ltd. PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications
US8754897B2 (en) 2004-01-28 2014-06-17 Lucidlogix Software Solutions, Ltd. Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem
US7812844B2 (en) 2004-01-28 2010-10-12 Lucid Information Technology, Ltd. PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application
US7812845B2 (en) 2004-01-28 2010-10-12 Lucid Information Technology, Ltd. PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application
US9659340B2 (en) 2004-01-28 2017-05-23 Lucidlogix Technologies Ltd Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem
US7834880B2 (en) 2004-01-28 2010-11-16 Lucid Information Technology, Ltd. Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US20050270988A1 (en) * 2004-06-04 2005-12-08 Dehaemer Eric Mechanism of dynamic upstream port selection in a PCI express switch
US8704275B2 (en) 2004-09-15 2014-04-22 Nvidia Corporation Semiconductor die micro electro-mechanical switch management method
US8723231B1 (en) 2004-09-15 2014-05-13 Nvidia Corporation Semiconductor die micro electro-mechanical switch management system and method
US8711156B1 (en) 2004-09-30 2014-04-29 Nvidia Corporation Method and system for remapping processing elements in a pipeline of a graphics processing unit
US20060125833A1 (en) * 2004-12-10 2006-06-15 Wen-Chi Hung Image display device and method thereof
US10867364B2 (en) 2005-01-25 2020-12-15 Google Llc System on chip having processing and graphics units
US10614545B2 (en) 2005-01-25 2020-04-07 Google Llc System on chip having processing and graphics units
US11341602B2 (en) 2005-01-25 2022-05-24 Google Llc System on chip having processing and graphics units
US8021193B1 (en) 2005-04-25 2011-09-20 Nvidia Corporation Controlled impedance display adapter
US8021194B2 (en) 2005-04-25 2011-09-20 Nvidia Corporation Controlled impedance display adapter
US8063900B1 (en) 2005-04-29 2011-11-22 Adobe Systems Incorporated GPU assisted 3D compositing
US7598952B1 (en) 2005-04-29 2009-10-06 Adobe Systems Incorporatted Three-dimensional image compositing on a GPU utilizing multiple transformations
US7499051B1 (en) 2005-04-29 2009-03-03 Adobe Systems Incorporated GPU assisted 3D compositing
US8427496B1 (en) 2005-05-13 2013-04-23 Nvidia Corporation Method and system for implementing compression across a graphics bus interconnect
US7793029B1 (en) 2005-05-17 2010-09-07 Nvidia Corporation Translation device apparatus for configuring printed circuit board connectors
US9424622B2 (en) 2005-05-27 2016-08-23 Ati Technologies Ulc Methods and apparatus for processing graphics data using multiple processing circuits
US9865030B2 (en) 2005-05-27 2018-01-09 Ati Technologies Ulc Methods and apparatus for processing graphics data using multiple processing circuits
US7886094B1 (en) * 2005-06-15 2011-02-08 Nvidia Corporation Method and system for handshaking configuration between core logic components and graphics processors
US8417838B2 (en) * 2005-12-12 2013-04-09 Nvidia Corporation System and method for configurable digital communication
US20070162624A1 (en) * 2005-12-12 2007-07-12 Tamasi Anthony M System and method for configurable digital communication
US8412872B1 (en) * 2005-12-12 2013-04-02 Nvidia Corporation Configurable GPU and method for graphics processing using a configurable GPU
US20070263004A1 (en) * 2006-05-12 2007-11-15 Xgi Technology Inc. Plug-in graphics module architecture
US10838480B2 (en) * 2006-12-31 2020-11-17 Google Llc Apparatus and method for power management of a computing system
US20200159310A1 (en) * 2006-12-31 2020-05-21 Google Llc Apparatus and method for power management of a computing system
US10120433B2 (en) * 2006-12-31 2018-11-06 Google Llc Apparatus and method for power management of a computing system
US20190129496A1 (en) * 2006-12-31 2019-05-02 Google Llc Apparatus and method for power management of a computing system
US20220187898A1 (en) * 2006-12-31 2022-06-16 Google Llc Apparatus and method for power management of a computing system
US20160162013A1 (en) * 2006-12-31 2016-06-09 Lucidlogix Technologies Ltd. Apparatus and method for power management of a computing system
US20110169840A1 (en) * 2006-12-31 2011-07-14 Lucid Information Technology, Ltd Computing system employing a multi-gpu graphics processing and display subsystem supporting single-gpu non-parallel (multi-threading) and multi-gpu application-division parallel modes of graphics processing operation
US10545565B2 (en) * 2006-12-31 2020-01-28 Google Llc Apparatus and method for power management of a computing system
US11372469B2 (en) * 2006-12-31 2022-06-28 Google Llc Apparatus and method for power management of a multi-gpu computing system
US8497865B2 (en) 2006-12-31 2013-07-30 Lucid Information Technology, Ltd. Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS
US11714476B2 (en) * 2006-12-31 2023-08-01 Google Llc Apparatus and method for power management of a computing system
US9275430B2 (en) * 2006-12-31 2016-03-01 Lucidlogix Technologies, Ltd. Computing system employing a multi-GPU graphics processing and display subsystem supporting single-GPU non-parallel (multi-threading) and multi-GPU application-division parallel modes of graphics processing operation
US20090037633A1 (en) * 2007-07-31 2009-02-05 Solomon Mark C Graphics processor in a docking station
US7827340B2 (en) * 2007-07-31 2010-11-02 Hewlett-Packard Development Company, L.P. Graphics processor in a docking station
EP2034400A2 (en) 2007-09-06 2009-03-11 Dell Products, L.P. System and method for an information handling system having an external graphics processor system for operating multiple monitors
EP2034400A3 (en) * 2007-09-06 2010-03-10 Dell Products, L.P. System and method for an information handling system having an external graphics processor system for operating multiple monitors
US8724483B2 (en) 2007-10-22 2014-05-13 Nvidia Corporation Loopback configuration for bi-directional interfaces
US20090138647A1 (en) * 2007-11-26 2009-05-28 Hagita Yasuharu Bus switch, electronic equipment, and data transfer method
US8035641B1 (en) 2007-11-28 2011-10-11 Adobe Systems Incorporated Fast depth of field simulation
US7827333B1 (en) * 2008-02-04 2010-11-02 Nvidia Corporation System and method for determining a bus address on an add-in card
US8395619B1 (en) * 2008-10-02 2013-03-12 Nvidia Corporation System and method for transferring pre-computed Z-values between GPUs
US10157492B1 (en) 2008-10-02 2018-12-18 Nvidia Corporation System and method for transferring pre-computed Z-values between GPUS
US10467178B2 (en) * 2008-10-03 2019-11-05 Advanced Micro Devices, Inc. Peripheral component
US9977756B2 (en) 2008-10-03 2018-05-22 Advanced Micro Devices, Inc. Internal bus architecture and method in multi-processor systems
US20180314670A1 (en) * 2008-10-03 2018-11-01 Ati Technologies Ulc Peripheral component
US20170235700A1 (en) * 2008-10-03 2017-08-17 Advanced Micro Devices, Inc. Peripheral component
US8773443B2 (en) * 2009-09-16 2014-07-08 Nvidia Corporation Compression for co-processing techniques on heterogeneous graphics processing units
US8780122B2 (en) 2009-09-16 2014-07-15 Nvidia Corporation Techniques for transferring graphics data from system memory to a discrete GPU
US20110063302A1 (en) * 2009-09-16 2011-03-17 Nvidia Corporation Compression for co-processing techniques on heterogeneous graphics processing units
US20110157189A1 (en) * 2009-12-31 2011-06-30 Nvidia Corporation Shared buffer techniques for heterogeneous hybrid graphics
US9111325B2 (en) * 2009-12-31 2015-08-18 Nvidia Corporation Shared buffer techniques for heterogeneous hybrid graphics
US9331869B2 (en) 2010-03-04 2016-05-03 Nvidia Corporation Input/output request packet handling techniques by a device specific kernel mode driver
US10573054B2 (en) * 2010-05-29 2020-02-25 Intel Corporation Non-volatile storage for graphics hardware
US20170091981A1 (en) * 2010-05-29 2017-03-30 Intel Corporation Non-volatile storage for graphics hardware
US20130207984A1 (en) * 2010-10-11 2013-08-15 Craig A. Walrath First And Second Software Stacks And Discrete And Integrated Graphics Processing Units
WO2012050560A1 (en) * 2010-10-11 2012-04-19 Hewlett-Packard Development Company, L.P. First and second software stacks and discrete and integrated graphics processing units
US9269122B2 (en) * 2010-10-11 2016-02-23 Hewlett-Packard Development Company, L.P. First and second software stacks and discrete and integrated graphics processing units
CN103988190A (en) * 2011-12-16 2014-08-13 英特尔公司 Method, apparatus, and system for expanding graphical processing via external display-data i/o port
US20140028689A1 (en) * 2011-12-16 2014-01-30 Sing Hook Arther Teng Method, apparatus, and system for expanding graphical processing via an external display-data i/o port
US20140152674A1 (en) * 2012-12-03 2014-06-05 Samsung Electronics Co., Ltd. Electronic apparatus, external apparatus and method of controlling the same
US10445853B2 (en) 2012-12-03 2019-10-15 Samsung Electronics Co., Ltd. Electronic apparatus, external apparatus and method of controlling the same
CN108196628A (en) * 2012-12-03 2018-06-22 三星电子株式会社 Electronic system
US10181174B2 (en) 2012-12-03 2019-01-15 Samsung Electronics Co., Ltd. Electronic apparatus, external apparatus and method of controlling the same
US9898798B2 (en) 2012-12-03 2018-02-20 Samsung Electronics Co., Ltd. Electronic apparatus, external apparatus and method of controlling the same
US10650485B2 (en) 2012-12-03 2020-05-12 Samsung Electronics Co., Ltd. Electronic apparatus, external apparatus and method of controlling the same
US9640137B2 (en) * 2012-12-03 2017-05-02 Samsung Electronics Co., Ltd. Electronic apparatus, external apparatus and method of controlling the same
US9607407B2 (en) 2012-12-31 2017-03-28 Nvidia Corporation Variable-width differential memory compression
US9591309B2 (en) 2012-12-31 2017-03-07 Nvidia Corporation Progressive lossy memory compression
EP3016074A1 (en) * 2014-10-22 2016-05-04 Samsung Electronics Co., Ltd Hybrid rendering apparatus and method
US20170140570A1 (en) * 2015-11-13 2017-05-18 Intel Corporation Facilitating efficeint centralized rendering of viewpoint-agnostic graphics workloads at computing devices
US9947070B2 (en) * 2016-09-08 2018-04-17 Dell Products L.P. GPU that passes PCIe via displayport for routing to a USB type-C connector
US11347673B2 (en) * 2017-09-30 2022-05-31 Intel Corporation Method, apparatus, system for thunderbolt-based display topology for dual graphics systems
CN111612684A (en) * 2019-02-22 2020-09-01 环达电脑(上海)有限公司 Electronic device and control method thereof
US11423588B2 (en) 2019-11-05 2022-08-23 Adobe Inc. Color transforms using static shaders compiled at initialization
CN111007998A (en) * 2019-12-24 2020-04-14 联想(北京)有限公司 Processing method, system and electronic equipment

Also Published As

Publication number Publication date
US9865030B2 (en) 2018-01-09
US20140035936A1 (en) 2014-02-06
US20160364834A1 (en) 2016-12-15
US9424622B2 (en) 2016-08-23
US20190012760A1 (en) 2019-01-10

Similar Documents

Publication Publication Date Title
US9865030B2 (en) Methods and apparatus for processing graphics data using multiple processing circuits
US20080030510A1 (en) Multi-GPU rendering system
US8947432B2 (en) Accelerated rendering with temporally interleaved details
US5799204A (en) System utilizing BIOS-compatible high performance video controller being default controller at boot-up and capable of switching to another graphics controller after boot-up
KR101121595B1 (en) Picture processing using a hybrid system configuration
US8781260B2 (en) Compositing in multiple video processing unit (VPU) systems
US7721118B1 (en) Optimizing power and performance for multi-processor graphics processing
US8400457B2 (en) Dynamic load balancing in multiple video processing unit (VPU) systems
US7663635B2 (en) Multiple video processor unit (VPU) memory mapping
US8681160B2 (en) Synchronizing multiple cards in multiple video processing unit (VPU) systems
US7372465B1 (en) Scalable graphics processing for remote display
US9448766B2 (en) Interconnected arithmetic logic units
WO2013024753A1 (en) Display system, host device and display device
US20060267991A1 (en) Antialiasing system and method
JP2002510106A (en) Datapath Clock Skew Management in Dynamic Power Management Environment
US8085274B2 (en) Video data compression
KR20130040251A (en) Techniques to control display activity
US8384722B1 (en) Apparatus, system and method for processing image data using look up tables
US20140281603A1 (en) System, method, and computer program product for allowing a head to enter a reduced power mode
US20060238964A1 (en) Display apparatus for a multi-display card and displaying method of the same
CN1319028C (en) Image correction system and method, and computer readable storage medium
US8890876B1 (en) Microprocessor including a display interface in the microprocessor
GB2421159A (en) Multiple graphics processing units
JP2003280850A (en) High speed printer and high speed printing method using the printer
JP2006323754A (en) Display device and method of multi-display card

Legal Events

Date Code Title Description
AS Assignment

Owner name: ATI TECHNOLOGIES INC., CANADA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TEMKINE, GRIGORI;DRAPKIN, OLEG;CARUK, GORDON;REEL/FRAME:016495/0783;SIGNING DATES FROM 20050722 TO 20050726

AS Assignment

Owner name: ATI TECHNOLOGIES ULC, CANADA

Free format text: CHANGE OF NAME;ASSIGNOR:ATI TECHNOLOGIES INC.;REEL/FRAME:023759/0426

Effective date: 20061025

STCB Information on status: application discontinuation

Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION