|Publication number||US20060266997 A1|
|Application number||US 11/498,521|
|Publication date||30 Nov 2006|
|Filing date||3 Aug 2006|
|Priority date||9 Aug 2001|
|Also published as||US7138649, US20030227013, WO2003105221A1|
|Publication number||11498521, 498521, US 2006/0266997 A1, US 2006/266997 A1, US 20060266997 A1, US 20060266997A1, US 2006266997 A1, US 2006266997A1, US-A1-20060266997, US-A1-2006266997, US2006/0266997A1, US2006/266997A1, US20060266997 A1, US20060266997A1, US2006266997 A1, US2006266997A1|
|Inventors||Matthew Currie, Anthony Lochtefeld, Eugene Fitzgerald|
|Original Assignee||Amberwave Systems Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (1), Classifications (13), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to semiconductor structures and particularly to semiconductor structures formed on strained semiconductor layers.
The recent development of silicon (Si) substrates with strained layers has increased the options available for design and fabrication of field-effect transistors (FETs). Enhanced performance of n-type metal-oxide-semiconductor (NMOS) transistors has been demonstrated with heterojunction metal-oxide-semiconductor field effect transistors (MOSFETs) built on substrates having strained silicon and relaxed silicon-germanium (SiGe) layers. Tensilely-strained silicon greatly enhances electron mobilities. NMOS devices with strained silicon surface channels, therefore, have improved performance with higher switching speeds. Hole mobilities are enhanced in tensilely-strained silicon as well, but to a lesser extent for strain levels less than approximately 1.5%. Equivalent enhancement of p-type metal-oxide-semiconductor (PMOS) device performance, therefore, in such surface-channel devices presents a challenge.
A structure that incorporates a compressively strained SiGe layer in tandem with a tensilely strained Si layer can provide greatly enhanced electron and hole mobilities. In this structure, electron transport typically occurs within a surface tensilely strained Si channel and hole transport occurs within the compressively strained SiGe layer below the Si layer. To support the fabrication of NMOS transistors as well as PMOS transistors on this structure, the surface tensilely strained Si layer has a typical thickness of 50-200 Ångstroms (Å) for providing a channel for conduction of electrons. If this layer is thinner than 50 Å, the beneficial mobility enhancement is significantly reduced because the electrons are no longer completely confined within the strained Si layer. Although some NMOS devices are operational with a strained silicon surface channel of only 50 Å, even this strained silicon layer thickness may be too thick to allow modulation of p-type carriers in a buried SiGe layer by an operating voltage applied to the gate of a PMOS transistor.
Complementary metal-oxide silicon (CMOS) circuit design is simplified if carrier mobilities are enhanced equally for both NMOS and PMOS devices. In conventional silicon-based devices, electron mobilities are approximately two times greater than hole mobilities. As noted, electron mobilities have been substantially increased with strained silicon. Methods for equally increasing hole and electron mobilities by forming dual-channel NMOS and PMOS devices on the same substrate are problematic, in part because of different surface strained-silicon thickness requirements for the two types of devices.
In a dual-channel CMOS structure, electron transport takes place in a surface channel, e.g., a strained silicon layer with a thickness greater than 5 nanometers (nm). Hole transport occurs either in a buried channel, such as a buried compressed SiGe channel, or in both the strained silicon surface layer and the buried compressed SiGe layer. Hole mobility in this type of structure is improved because of a reduction in hole scattering due to sub-band splitting, and because of a reduction in hole effective mass, both of which are associated with transport in strained SiGe and strained Si.
In a MOSFET, having carriers such as holes close to the gate improves switching speeds. A thinned strained silicon layer above a PMOS channel facilitates control of hole transport by a voltage applied to a gate above the PMOS channel. If the strained silicon layer over the PMOS channel is too thick, the majority of carriers will be pulled closer to the surface from the buried channel. This configuration will result in a lack of device performance enhancement by the buried channel. Selectively thinning the strained silicon layer above a PMOS channel while maintaining a greater strained silicon thickness as an NMOS channel enables better control of hole transport in p-channel devices while simultaneously providing an adequate channel for electron transport in n-channel devices.
In an aspect, the invention features a semiconductor structure having a surface layer having strained silicon disposed over a substrate, the surface layer including a first region having a first thickness and a second region having a second thickness, the first thickness being less than the second thickness. The structure also includes a gate dielectric disposed over a portion of at least the first region of the surface layer.
One or more of the following features may also be included. The gate dielectric layer may be disposed over a portion of the second region of the surface layer. The gate dielectric layer thickness may be approximately 10-100 Å. The first thickness may be approximately 7-20 Å.
In another aspect, the invention features a semiconductor structure having a surface layer with strained silicon disposed over a substrate. A portion of the surface layer has a minimum thickness necessary for growing a silicon dioxide layer having satisfactory integrity.
One or more of the following features may also be included. The minimum surface layer thickness may be approximately 10-20 Å. The surface layer may be disposed over the underlying layer and the underlying layer may induce strain in the surface layer. The underlying layer may include germanium and/or silicon. The underlying layer may be disposed over an insulator layer.
In yet another aspect, a surface layer including strained silicon is disposed over a substrate, the surface layer including a first region having a first thickness and a second region having a second thickness, the first thickness being less than the second thickness. The first region has a first source and a first drain, with the first source and the first drain including a first type of dopant. The second region has a second source and a second drain, with the second source and the second drain including a second type of dopant.
One or more of the following features may also be included. The surface layer may include tensilely strained silicon. The first type of dopant may be p-type and the second type of dopant may be n-type. The substrate may include a region under compressive strain sharing an interface with the surface layer, the tensilely strained surface layer enhancing mobility of electrons and the compressively strained substrate region enhancing mobility of holes. A gate may be disposed above the surface layer, with the first thickness being sufficiently small such that application of an operating voltage to the gate modulates movement of charge carriers within the compressively strained substrate region, and a majority of the charge carriers populate the compressively strained substrate region. An insulator may be provided between the gate and the surface layer. The compressively strained substrate region may include silicon and/or germanium.
In another aspect, the invention features a method for forming a semiconductor structure. The method includes providing a substrate having a surface layer disposed thereon, the surface layer including strained silicon. A sacrificial layer is selectively formed in a portion of the surface layer. The sacrificial layer is selectively removed to define a first region of the surface layer having a first thickness proximate a second region of the surface layer having a second thickness, with the first thickness being less than the second thickness.
One or more of the following features may also be included. Prior to forming the sacrificial layer, a masking layer may be formed over the surface layer, and a portion of the masking layer removed to expose the portion of the surface layer. The sacrificial layer may subsequently be selectively formed in the portion of the surface layer exposed by the masking layer. Forming the masking layer may include forming a masking silicon nitride layer. Forming the masking layer may also include forming a pad silicon dioxide layer prior to forming the masking silicon nitride layer. A first source and a first drain may be formed in the first region of the surface layer, the first source and the first drain including a first type of dopant. A second source and a second drain may be formed in the second region of the surface layer, the second source and the second drain including a second type of dopant. The first type of dopant may be n-type and the second type of dopant may be p-type. The surface layer may be disposed over a relaxed layer. The relaxed layer may comprise germanium and/or silicon.
Like referenced features identify common features in corresponding drawings.
A gate dielectric layer 48 is formed on a top surface 50 of strained silicon surface layer 18. Gate dielectric layer 48 is, for example, a gate oxide with satisfactory integrity having a thickness T10 of approximately 10-100 Å. In an embodiment, gate dielectric layer 48 thickness T10 is approximately 15 Å. If the initial thickness T9 of thinned strained silicon surface layer first region 41 is 15 Å after removal of sacrificial layer 44 (see
During operation of PMOS transistor 59, an operating voltage bias 52 v is applied to first gate 52. The operating voltage 52 v modulates the movement of charge carriers in PMOS transistor 59. More specifically, charge carriers 67, e.g., holes travel through a compressed channel 66 in compressed SiGe layer 16 from first source 56 to first drain 58. The compressive strain of compressed SiGe layer 16 enhances the mobility of holes. Final thickness T11 of strained silicon surface layer first region 41 is sufficiently small so that the operating voltage 52 v applied to first gate 52 can modulate the movement of charge carriers 67 within compressed SiGe layer 16, and without drawing a majority of the charge carriers into tensilely strained silicon surface layer first region 41 between first source 56 and first drain 58. The majority of carriers 67 remain in compressed channel 66 in compressed SiGe layer 16, thereby retaining the benefits of enhanced performance resulting from greater carrier mobilities.
During operation of NMOS transistor 64, an operating voltage 54 v is applied to second gate 54. Charge carriers 67, e.g., electrons travel through a strained channel 68 in strained silicon surface layer second region 47 from second source 60 to second drain 62. The strain of surface layer 18 enhances the mobility of electrons, and final thickness T12 of strained silicon surface layer second region 47 is sufficiently high to confine the electrons in channel 68.
A dual-channel CMOS device 70 includes PMOS transistor 59 and NMOS transistor 64. In PMOS transistor 58, thinner thickness T11 of strained silicon surface layer first region 41 allows modulation of carriers 67, e.g., holes, in compressed channel 66 by bias 52 v applied to first gate 52. In adjacent NMOS transistor 64, thicker thickness T12 of strained silicon surface layer second region 47 provides an adequate volume for confinement of carriers 67, e.g. electrons, in strained channel 68.
While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the following claims. For example, the described semiconductor structures can be fabricated on a substrate without a graded SiGe layer. PMOS well formation can be performed either before or after patterning of pad oxide and masking nitride layers, either before or after the formation of the sacrificial oxide, and either before or after the removal of the sacrificial oxide. Masking nitride can be removed by a wet etch, such as by a heated phosphoric acid bath. Strained silicon layer can be selectively thinned by methods other than growth of a sacrificial oxide, such as by etching.
It is noted that various processing sequences such as cleaning steps can remove a thickness of exposed strained silicon. The final thickness of thinned strained silicon surface layer first region and the final thickness of strained silicon surface layer region may, therefore, be affected by these additional process steps. These steps can be taken into consideration when calculating appropriate initial and final strained silicon thicknesses to obtain desired final thicknesses after the gate dielectric layer is formed.
Gate dielectric can be a material that is deposited, e.g., a high-k dielectric. In this embodiment, the exposed strained silicon layer will not be consumed during the gate dielectric formation process.
An NMOS device can be formed in a region having a thinner strained silicon layer than the strained silicon layer thickness in a region where a PMOS device is formed. First source and first drain can be n-type, and second source and second drain can be p-type. PMOS and NMOS devices can be fabricated on various alternative substrates, using methods described above.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US20050151164 *||7 Mar 2005||14 Jul 2005||Amberwave Systems Corporation||Enhancement of p-type metal-oxide-semiconductor field effect transistors|
|U.S. Classification||257/19, 257/E27.064, 257/E21.618|
|International Classification||H01L21/8238, H01L31/00, H01L21/8234, H01L27/092|
|Cooperative Classification||H01L21/823412, H01L21/823807, H01L27/0922|
|European Classification||H01L21/8238C, H01L21/8234C, H01L27/092D|
|9 Jan 2007||AS||Assignment|
Owner name: AMBERWAVE SYSTEMS CORPORATION, NEW HAMPSHIRE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CURRIE, MATTHEW T.;LOCHTEFELD, ANTHONY J.;FITZGERALD, EUGENE A.;REEL/FRAME:018732/0405
Effective date: 20020913
|13 Jan 2010||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,T
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMBERWAVE SYSTEMS CORPORATION;REEL/FRAME:023775/0111
Effective date: 20091122