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Publication numberUS20060266997 A1
Publication typeApplication
Application numberUS 11/498,521
Publication date30 Nov 2006
Filing date3 Aug 2006
Priority date9 Aug 2001
Also published asUS7138649, US20030227013, WO2003105221A1
Publication number11498521, 498521, US 2006/0266997 A1, US 2006/266997 A1, US 20060266997 A1, US 20060266997A1, US 2006266997 A1, US 2006266997A1, US-A1-20060266997, US-A1-2006266997, US2006/0266997A1, US2006/266997A1, US20060266997 A1, US20060266997A1, US2006266997 A1, US2006266997A1
InventorsMatthew Currie, Anthony Lochtefeld, Eugene Fitzgerald
Original AssigneeAmberwave Systems Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods for forming semiconductor structures with differential surface layer thicknesses
US 20060266997 A1
Abstract
A semiconductor structure having a substrate with a surface layer including strained silicon. The surface layer has a first region with a first thickness less than a second thickness of a second region. A gate dielectric layer is disposed over a portion of at least the first surface layer region.
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Claims(20)
1.-24. (canceled)
25. A method for forming a semiconductor structure, the method comprising the steps of:
providing a substrate having a surface layer disposed thereon, the surface layer comprising strained silicon;
selectively forming a sacrificial layer in a portion of the surface layer; and
substantially removing the sacrificial layer to define a first region of the surface layer having a first thickness and a second region of the surface layer having a second thickness,
wherein the first thickness is less than the second thickness.
26. The method of claim 25 further comprising:
prior to forming the sacrificial layer, forming a masking layer over the surface layer; and
removing a portion of the masking layer to expose the portion of the surface layer,
wherein the sacrificial layer is subsequently selectively formed in the portion of the surface layer exposed by the masking layer.
27. The method of claim 26, wherein forming the masking layer comprises forming a masking silicon nitride layer.
28. The method of claim 27, wherein forming the masking layer comprises forming a pad silicon dioxide layer prior to forming the masking silicon nitride layer.
29. The method of claim 25 further comprising:
forming a first source and a first drain in the first region of the surface layer, the first source and the first drain including a first type of dopant; and
forming a second source and a second drain in the second region of the surface layer, the second source and the second drain including a second type of dopant.
30. The method of claim 29, wherein the first type of dopant is n-type and the second type of dopant is p-type.
31. The method of claim 29, wherein the first type of dopant is p-type and the second type of dopant is n-type.
32. The method of claim 25, wherein the surface layer is disposed over a relaxed layer.
33. The method of claim 32, wherein the relaxed layer comprises germanium.
34. The method of claim 32, wherein the relaxed layer comprises silicon.
35. The method of claim 25, wherein the surface layer is disposed over an insulator layer.
36. The method of claim 25, wherein the surface layer is disposed over a compressively strained layer.
37. The method of claim 36, wherein the compressively strained layer comprises SiGe.
38. The method of claim 36, wherein the compressively strained layer is disposed over an insulator layer.
39. The method of claim 25 further comprising forming a gate dielectric over the first and second regions of the surface layer.
40. The method of claim 39, wherein forming the gate dielectric comprises oxidation.
41. The method of claim 39, wherein forming the gate dielectric comprises deposition.
42. The method of claim 41, wherein the gate dielectric comprises a high-k dielectric.
43. The method of claim 25, wherein providing the substrate comprises wafer bonding.
Description
    FIELD OF THE INVENTION
  • [0001]
    The present invention relates generally to semiconductor structures and particularly to semiconductor structures formed on strained semiconductor layers.
  • BACKGROUND
  • [0002]
    The recent development of silicon (Si) substrates with strained layers has increased the options available for design and fabrication of field-effect transistors (FETs). Enhanced performance of n-type metal-oxide-semiconductor (NMOS) transistors has been demonstrated with heterojunction metal-oxide-semiconductor field effect transistors (MOSFETs) built on substrates having strained silicon and relaxed silicon-germanium (SiGe) layers. Tensilely-strained silicon greatly enhances electron mobilities. NMOS devices with strained silicon surface channels, therefore, have improved performance with higher switching speeds. Hole mobilities are enhanced in tensilely-strained silicon as well, but to a lesser extent for strain levels less than approximately 1.5%. Equivalent enhancement of p-type metal-oxide-semiconductor (PMOS) device performance, therefore, in such surface-channel devices presents a challenge.
  • [0003]
    A structure that incorporates a compressively strained SiGe layer in tandem with a tensilely strained Si layer can provide greatly enhanced electron and hole mobilities. In this structure, electron transport typically occurs within a surface tensilely strained Si channel and hole transport occurs within the compressively strained SiGe layer below the Si layer. To support the fabrication of NMOS transistors as well as PMOS transistors on this structure, the surface tensilely strained Si layer has a typical thickness of 50-200 Ångstroms (Å) for providing a channel for conduction of electrons. If this layer is thinner than 50 Å, the beneficial mobility enhancement is significantly reduced because the electrons are no longer completely confined within the strained Si layer. Although some NMOS devices are operational with a strained silicon surface channel of only 50 Å, even this strained silicon layer thickness may be too thick to allow modulation of p-type carriers in a buried SiGe layer by an operating voltage applied to the gate of a PMOS transistor.
  • [0004]
    Complementary metal-oxide silicon (CMOS) circuit design is simplified if carrier mobilities are enhanced equally for both NMOS and PMOS devices. In conventional silicon-based devices, electron mobilities are approximately two times greater than hole mobilities. As noted, electron mobilities have been substantially increased with strained silicon. Methods for equally increasing hole and electron mobilities by forming dual-channel NMOS and PMOS devices on the same substrate are problematic, in part because of different surface strained-silicon thickness requirements for the two types of devices.
  • SUMMARY
  • [0005]
    In a dual-channel CMOS structure, electron transport takes place in a surface channel, e.g., a strained silicon layer with a thickness greater than 5 nanometers (nm). Hole transport occurs either in a buried channel, such as a buried compressed SiGe channel, or in both the strained silicon surface layer and the buried compressed SiGe layer. Hole mobility in this type of structure is improved because of a reduction in hole scattering due to sub-band splitting, and because of a reduction in hole effective mass, both of which are associated with transport in strained SiGe and strained Si.
  • [0006]
    In a MOSFET, having carriers such as holes close to the gate improves switching speeds. A thinned strained silicon layer above a PMOS channel facilitates control of hole transport by a voltage applied to a gate above the PMOS channel. If the strained silicon layer over the PMOS channel is too thick, the majority of carriers will be pulled closer to the surface from the buried channel. This configuration will result in a lack of device performance enhancement by the buried channel. Selectively thinning the strained silicon layer above a PMOS channel while maintaining a greater strained silicon thickness as an NMOS channel enables better control of hole transport in p-channel devices while simultaneously providing an adequate channel for electron transport in n-channel devices.
  • [0007]
    In an aspect, the invention features a semiconductor structure having a surface layer having strained silicon disposed over a substrate, the surface layer including a first region having a first thickness and a second region having a second thickness, the first thickness being less than the second thickness. The structure also includes a gate dielectric disposed over a portion of at least the first region of the surface layer.
  • [0008]
    One or more of the following features may also be included. The gate dielectric layer may be disposed over a portion of the second region of the surface layer. The gate dielectric layer thickness may be approximately 10-100 Å. The first thickness may be approximately 7-20 Å.
  • [0009]
    In another aspect, the invention features a semiconductor structure having a surface layer with strained silicon disposed over a substrate. A portion of the surface layer has a minimum thickness necessary for growing a silicon dioxide layer having satisfactory integrity.
  • [0010]
    One or more of the following features may also be included. The minimum surface layer thickness may be approximately 10-20 Å. The surface layer may be disposed over the underlying layer and the underlying layer may induce strain in the surface layer. The underlying layer may include germanium and/or silicon. The underlying layer may be disposed over an insulator layer.
  • [0011]
    In yet another aspect, a surface layer including strained silicon is disposed over a substrate, the surface layer including a first region having a first thickness and a second region having a second thickness, the first thickness being less than the second thickness. The first region has a first source and a first drain, with the first source and the first drain including a first type of dopant. The second region has a second source and a second drain, with the second source and the second drain including a second type of dopant.
  • [0012]
    One or more of the following features may also be included. The surface layer may include tensilely strained silicon. The first type of dopant may be p-type and the second type of dopant may be n-type. The substrate may include a region under compressive strain sharing an interface with the surface layer, the tensilely strained surface layer enhancing mobility of electrons and the compressively strained substrate region enhancing mobility of holes. A gate may be disposed above the surface layer, with the first thickness being sufficiently small such that application of an operating voltage to the gate modulates movement of charge carriers within the compressively strained substrate region, and a majority of the charge carriers populate the compressively strained substrate region. An insulator may be provided between the gate and the surface layer. The compressively strained substrate region may include silicon and/or germanium.
  • [0013]
    In another aspect, the invention features a method for forming a semiconductor structure. The method includes providing a substrate having a surface layer disposed thereon, the surface layer including strained silicon. A sacrificial layer is selectively formed in a portion of the surface layer. The sacrificial layer is selectively removed to define a first region of the surface layer having a first thickness proximate a second region of the surface layer having a second thickness, with the first thickness being less than the second thickness.
  • [0014]
    One or more of the following features may also be included. Prior to forming the sacrificial layer, a masking layer may be formed over the surface layer, and a portion of the masking layer removed to expose the portion of the surface layer. The sacrificial layer may subsequently be selectively formed in the portion of the surface layer exposed by the masking layer. Forming the masking layer may include forming a masking silicon nitride layer. Forming the masking layer may also include forming a pad silicon dioxide layer prior to forming the masking silicon nitride layer. A first source and a first drain may be formed in the first region of the surface layer, the first source and the first drain including a first type of dopant. A second source and a second drain may be formed in the second region of the surface layer, the second source and the second drain including a second type of dopant. The first type of dopant may be n-type and the second type of dopant may be p-type. The surface layer may be disposed over a relaxed layer. The relaxed layer may comprise germanium and/or silicon.
  • BRIEF DESCRIPTION OF DRAWINGS
  • [0015]
    FIGS. 1-8 are a series of schematic cross-sectional views of a semiconductor substrate illustrating a process for fabricating a semiconductor structure on the substrate; and
  • [0016]
    FIGS. 9-10 are schematic cross-sectional views of an alternative embodiment of a semiconductor structure fabricated on a substrate.
  • [0017]
    Like referenced features identify common features in corresponding drawings.
  • DETAILED DESCRIPTION
  • [0018]
    Referring to FIG. 1, which illustrates a structure amenable to use with the present invention, a substrate 10 is made of a semiconductor, such as silicon. Several layers collectively indicated at 11 are formed on substrate 10. In particular, a graded SiGe layer 12 is disposed over substrate 10. Graded SiGe layer 12 has a grading rate of, for example, 10% Ge per micron of thickness, and a thickness T1 of, for example, 2-5 microns. A relaxed SiGe layer 14 is disposed over graded SiGe layer 12. Relaxed SiGe layer 14 contains, for example, 20-50% Ge and has a thickness T2 of, e.g., 0.2-2 microns. A compressed SiGe layer 16, under compressive strain, is disposed over relaxed SiGe layer 14. Compressed SiGe layer 16 has a Ge content higher than the Ge content of relaxed SiGe layer 14. Compressed SiGe layer 16 contains, for example, 40-100% Ge and has a thickness T3 of, e.g., 10-200 Ångstroms (Å). In an embodiment, compressed SiGe layer 16 thickness T3 is approximately 100 Å. A tensilely strained silicon surface layer 18 is disposed over compressed SiGe layer 16, sharing an interface 19 with compressed SiGe layer 16. Strained silicon surface layer 18 has a starting thickness T4 of, for example, 50-300 Å. In an embodiment, starting thickness T4 is approximately 200 Å. A suitable substrate 10 with layers 11 can be readily obtained from, e.g., IQE Silicon Compounds, Ltd., UK.
  • [0019]
    Referring to FIG. 2, a first masking layer 20, such as a pad silicon dioxide layer, hereinafter referred to as pad oxide 20, is deposited over strained silicon surface layer 18 by a deposition method such as low-pressure chemical vapor deposition (LPCVD). Pad oxide 20 has a thickness T5 of, e.g., 100 Å. Subsequently, a second masking layer 22, such as a masking silicon nitride layer, hereinafter referred to as masking nitride 22, is deposited over pad oxide 20 by a deposition method such as plasma enhanced chemical vapor deposition (PECVD). Masking nitride 22 has a thickness T6 of, for example, 500-1000 Å.
  • [0020]
    Referring to FIG. 3, a photoresist layer is deposited over a top surface 24 of masking nitride 22 and patterned to form a photoresist mask 26. Photoresist mask 26 exposes top surface 24 of a first portion 28 of masking nitride 22 disposed over a first region 30 of substrate 10 and layers 11. A device such as a PMOS transistor will be formed in first region 30 with subsequent processing (see, e.g., PMOS transistor 59 in FIG. 8). Photoresist mask 26 covers top surface 24 of a second portion 32 of masking nitride 22 disposed over a second region 34 of substrate 10 and layers 11, including strained silicon surface layer 18. A device, such as an NMOS transistor, will be formed in second region 34 with subsequent processing (see, e.g., NMOS transistor 64 in FIG. 8).
  • [0021]
    Referring to FIG. 3 and also to FIG. 4, first masking nitride portion 28 and a first portion 38 of pad oxide 20 underneath first masking nitride portion 28 are both removed, leaving behind second masking nitride portion 32 and a second portion 40 of pad oxide 20 that are protected by photoresist mask 26. Specifically, exposed first masking nitride portion 28 may be removed by a removal process such as a reactive ion etch (RIE) using gases such as a combination of nitrogen trifluoride, ammonia, and oxygen, or a combination of hydrogen bromide, chlorine, and oxygen. First pad oxide portion 38 may be removed by a wet etch that is selective to silicon, such as a hydrofluoric acid etch. The removal of pad oxide portion 38 exposes a portion 41 of strained silicon surface layer 18. Ions are introduced into areas not covered by photoresist mask 26, including first region 30, to form a well 36, defined, for purposes of illustration, by the boundary 36 b. For example, n-type ions, such as phosphorus, are implanted to form well 36 for a PMOS transistor. The dosage and energy of the phosphorus ion implantation is, for example, 400 keV with 1.51013 atoms/cm2. After the selective removal of first portions 28, 38 of masking nitride 22 and pad oxide 20 and the formation of well 36, photoresist mask 26 is removed by a stripping process such as a dry strip in an oxygen plasma.
  • [0022]
    Referring to FIG. 5, a sacrificial layer 44 is formed on portion 41 of strained silicon surface layer 18. Sacrificial layer 44 is, for example, silicon dioxide grown by thermal oxidation. Thermal oxidation parameters may include, for example, an oxygen ambient at atmospheric pressure at 900 C. for 30 minutes. In an alternative embodiment, sacrificial layer 44 is silicon dioxide grown using a mixture of oxygen and hydrogen. During formation of sacrificial layer 44, this layer consumes a part of the thickness of portion 41 of strained silicon surface layer 18 in region 30. In an embodiment in which sacrificial layer 44 is silicon dioxide, sacrificial layer 44 typically builds up to a thickness T7 of slightly more than twice a thickness T8 of strained silicon surface layer 18 that is removed in region 30 by the growth of sacrificial layer 44. For example, if strained silicon surface layer 18 has a starting thickness T4 of 200 Å, and thinned first region 41 of strained silicon surface layer 18 with an initial thickness T9 of, for example, 20 Å, is desired in first region 30, a thickness T8 of 180 Å of strained silicon surface layer 18 needs to be removed in first region 30. This strained silicon thickness T8 can be consumed by growing sacrificial layer 44 having thickness T7 of approximately 400 Å.
  • [0023]
    Referring to FIG. 5 and also to FIG. 6, portion 32 of masking nitride layer 22 in region 34 is removed by, for example, an RIE process. Subsequently, portion 40 of pad oxide 20 and substantially all of sacrificial layer 44 are removed with an oxide etch selective to silicon, such as a hydrofluoric acid etch. The removal of sacrificial layer 44 exposes thinned first region 41 of strained silicon surface layer 18 with initial thickness T9 disposed over first substrate region 30. Thinned strained silicon surface layer first region 41 is proximate a second (unthinned) region 47 of strained silicon surface layer 18 in second substrate region 34. Initial thickness T9 of thinned surface layer first region 41 is less than starting thickness T4 of surface layer second region 47, which remains substantially unmodified. Initial thickness T9 is selected to be relatively thin so as to, in a PMOS transistor, facilitate control by a gate voltage of hole transport in SiGe layer 16 and possibly in strained silicon surface layer 18 (see, e.g., PMOS transistor 59 in FIG. 8). Referring still to FIGS. 5 and 6 and also to FIG. 7, initial thickness T9 of strained silicon surface layer 18 also has a minimum limit. Strained silicon surface layer 18, including both thinned first region 41 and unthinned second region 47, must be thick enough to enable subsequent growth of a gate dielectric 48, such as a gate oxide, having satisfactory integrity. For purposes hereof, a gate oxide with satisfactory integrity is one that has, for example, a relatively low interface state density, e.g., less than 11011 eV−1 cm−2, and/or a relatively low leakage current, e.g., <10 nanoamperes/square micrometer (nA/μm2) to 1 microampere/square micron (μA/μm ) or even 10 μA/μm2, preferably approximately 10-100 nA/μm2 at 100 C. In some preferred embodiments, the leakage current may range from approximately 10-100 nA/μm2. Thermal oxidation of SiGe or deposition of oxide films on SiGe results in high interface state density (>11011−11012 eV−1 cm−2). High interface state density at the semiconductor-insulator interface leads to undesirable shifts in threshold voltage and in extreme cases unacceptably large subthreshold slope. It is preferable, therefore, to grow gate oxide layers on silicon, rather than on SiGe. A thin gate oxide layer with satisfactory integrity can be grown on strained silicon surface layer 18 having a thickness T9 of approximately 10-20 Å. In an embodiment, strained silicon surface layer 18 thickness T9 is approximately 15 Å. Gate oxide, when grown on silicon, consumes a silicon thickness equal to approximately one-half of the thickness of the gate oxide grown. Leaving a margin for error, initial thickness T9 of thinned strained silicon surface layer 41 can therefore be approximately 15 Å when the desired gate dielectric thickness is approximately 15 Å. Alternatively, T9 can be selected as the final desired thickness, and gate dielectric layer 48 can be deposited rather than grown.
  • [0024]
    A gate dielectric layer 48 is formed on a top surface 50 of strained silicon surface layer 18. Gate dielectric layer 48 is, for example, a gate oxide with satisfactory integrity having a thickness T10 of approximately 10-100 Å. In an embodiment, gate dielectric layer 48 thickness T10 is approximately 15 Å. If the initial thickness T9 of thinned strained silicon surface layer first region 41 is 15 Å after removal of sacrificial layer 44 (see FIGS. 5 and 6), thinned strained silicon surface layer 41 has a lower final thickness T11 after growth of dielectric layer 48; once again, an oxide layer grown on strained silicon surface layer 18 typically builds up to a thickness of slightly more than twice a thickness of strained silicon surface layer 18 that is removed in region 30 by the growth of the oxide layer. Thinned strained silicon surface layer first region 41 final thickness T11 is, for example, less than 10 Å when gate dielectric layer 48 has a thickness T10 of approximately 15 Å and thinned strained silicon surface layer first region 41 initial thickness T9 is 15 Å. Second strained silicon surface layer region 47 is also thinner after gate dielectric layer 48 growth. If strained silicon surface layer region 47 initial thickness T4 is 200 Å (see FIG. 1), after growth of gate dielectric layer 48 with thickness T10 of, e.g., 15 Å, strained silicon surface layer region 47 final thickness T12 is approximately 192 Å.
  • [0025]
    Referring to FIG. 8, a conducting layer, such as doped polysilicon, is deposited over gate dielectric layer 48. The conducting layer is patterned by, for example, photolithography and etching, to define a first gate 52 in first region 30 and a second gate 54 in second region 34. First gate 52 is, for example, a gate for a PMOS transistor 59 and second gate 54 is, for example, a gate for an NMOS transistor 64. A first source 56 and a first drain 58 (defined for purposes of illustration, by the interior boundaries) are formed in first region 30, proximate first gate 52. First source 56 and first drain 58 can be formed by the implantation of p-type ions, such as boron. PMOS transistor 59 includes first source 56, first drain 58, first gate 52 and a first dielectric layer portion 48 a. A second source 60 and a second drain 62 are formed in second region 34, proximate second gate 54. Second source 60 and second drain 62 can be formed by the implantation of n-type ions, such as phosphorus. NMOS transistor 64 includes second source 60, second drain 62, second gate 54, and a second dielectric layer portion 48 b.
  • [0026]
    During operation of PMOS transistor 59, an operating voltage bias 52 v is applied to first gate 52. The operating voltage 52 v modulates the movement of charge carriers in PMOS transistor 59. More specifically, charge carriers 67, e.g., holes travel through a compressed channel 66 in compressed SiGe layer 16 from first source 56 to first drain 58. The compressive strain of compressed SiGe layer 16 enhances the mobility of holes. Final thickness T11 of strained silicon surface layer first region 41 is sufficiently small so that the operating voltage 52 v applied to first gate 52 can modulate the movement of charge carriers 67 within compressed SiGe layer 16, and without drawing a majority of the charge carriers into tensilely strained silicon surface layer first region 41 between first source 56 and first drain 58. The majority of carriers 67 remain in compressed channel 66 in compressed SiGe layer 16, thereby retaining the benefits of enhanced performance resulting from greater carrier mobilities.
  • [0027]
    During operation of NMOS transistor 64, an operating voltage 54 v is applied to second gate 54. Charge carriers 67, e.g., electrons travel through a strained channel 68 in strained silicon surface layer second region 47 from second source 60 to second drain 62. The strain of surface layer 18 enhances the mobility of electrons, and final thickness T12 of strained silicon surface layer second region 47 is sufficiently high to confine the electrons in channel 68.
  • [0028]
    A dual-channel CMOS device 70 includes PMOS transistor 59 and NMOS transistor 64. In PMOS transistor 58, thinner thickness T11 of strained silicon surface layer first region 41 allows modulation of carriers 67, e.g., holes, in compressed channel 66 by bias 52 v applied to first gate 52. In adjacent NMOS transistor 64, thicker thickness T12 of strained silicon surface layer second region 47 provides an adequate volume for confinement of carriers 67, e.g. electrons, in strained channel 68.
  • [0029]
    Referring to FIG. 9, in an embodiment, an alternative layer structure 111 is provided on a substrate 100. Substrate 100 is a semiconductor, such as silicon. An insulator layer 120 is disposed over substrate 100. Insulator layer 120 is made of an insulating material such as glass or silicon dioxide, and has a thickness T13 of, e.g., 500-1500 Å. A relaxed SiGe layer 140 is disposed over insulator layer 120. Relaxed SiGe layer 140 contains, for example, 30% Ge and has a thickness T14 of, e.g., 500 Å. A compressed SiGe layer 160 is disposed over relaxed SiGe layer 140. Compressed SiGe layer 160 contains, for example, 60% Ge and has a thickness T15 within a range of, e.g., 20-200 Å. In an embodiment, compressed SiGe layer 160 thickness T15 is 100 Å. A strained silicon surface layer 180 is disposed over compressed SiGe layer 160. Strained silicon surface layer 180 has a thickness T16 within a range of, for example, 50-200 Å. In an embodiment, strained silicon surface layer 180 thickness T16 is 150 Å. A suitable substrate 100 with layers 111, also called a SiGe-on-insulator (SGOI) substrate, can be produced using a combination of wafer bonding and ultrahigh vacuum chemical vapor deposition, as described, for example, by Cheng, et al., PCT Application No. PCT/JUS01/41680, International Publication Number WO 02/15244 A2, 2002, incorporated herein by reference, and Cheng et al., Journal of Electronic Materials, Vol. 30, No. 12, 2001, incorporated herein by reference. Relaxed SiGe layer 140 is optional. In an alternative embodiment, compressed SiGe layer 160 and strained silicon surface layer 180 can be provided directly onto insulator layer 120 by, e.g., wafer bonding.
  • [0030]
    Referring to FIG. 10, strained silicon surface layer 180 is selectively thinned by, e.g., formation of a sacrificial oxide (not shown), as described above with reference to FIGS. 2-6. Strained silicon surface layer 180 has a first region 200 with a thickness T17, that is less than a thickness T18 of a second region 210 of strained silicon surface layer 180. Substrate 100 with layers 111 is subsequently processed, as described above with reference to FIGS. 7-8, to form, for example, a PMOS transistor (not shown) in first region 220 with thinned strained silicon surface layer 200 and an NMOS transistor (not shown) in second region 230.
  • [0031]
    While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the following claims. For example, the described semiconductor structures can be fabricated on a substrate without a graded SiGe layer. PMOS well formation can be performed either before or after patterning of pad oxide and masking nitride layers, either before or after the formation of the sacrificial oxide, and either before or after the removal of the sacrificial oxide. Masking nitride can be removed by a wet etch, such as by a heated phosphoric acid bath. Strained silicon layer can be selectively thinned by methods other than growth of a sacrificial oxide, such as by etching.
  • [0032]
    It is noted that various processing sequences such as cleaning steps can remove a thickness of exposed strained silicon. The final thickness of thinned strained silicon surface layer first region and the final thickness of strained silicon surface layer region may, therefore, be affected by these additional process steps. These steps can be taken into consideration when calculating appropriate initial and final strained silicon thicknesses to obtain desired final thicknesses after the gate dielectric layer is formed.
  • [0033]
    Gate dielectric can be a material that is deposited, e.g., a high-k dielectric. In this embodiment, the exposed strained silicon layer will not be consumed during the gate dielectric formation process.
  • [0034]
    An NMOS device can be formed in a region having a thinner strained silicon layer than the strained silicon layer thickness in a region where a PMOS device is formed. First source and first drain can be n-type, and second source and second drain can be p-type. PMOS and NMOS devices can be fabricated on various alternative substrates, using methods described above.
  • [0035]
    The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4497683 *3 May 19825 Feb 1985At&T Bell LaboratoriesProcess for producing dielectrically isolated silicon devices
US4692992 *25 Jun 198615 Sep 1987Rca CorporationMethod of forming isolation regions in a semiconductor device
US4920076 *15 Apr 198824 Apr 1990The United States Of America As Represented By The United States Department Of EnergyMethod for enhancing growth of SiO2 in Si by the implantation of germanium
US4990979 *27 Apr 19895 Feb 1991Eurosil Electronic GmbhNon-volatile memory cell
US5079447 *20 Mar 19907 Jan 1992Integrated Device TechnologyBiCMOS gates with improved driver stages
US5089872 *27 Apr 199018 Feb 1992North Carolina State UniversitySelective germanium deposition on silicon and resulting structures
US5241197 *13 Sep 199131 Aug 1993Hitachi, Ltd.Transistor provided with strained germanium layer
US5242847 *27 Jul 19927 Sep 1993North Carolina State University At RaleighSelective deposition of doped silion-germanium alloy on semiconductor substrate
US5291439 *12 Sep 19911 Mar 1994International Business Machines CorporationSemiconductor memory cell and memory array with inversion layer
US5312766 *7 Feb 199217 May 1994National Semiconductor CorporationMethod of providing lower contact resistance in MOS transistors
US5327375 *2 Mar 19935 Jul 1994Eliyahou HarariDRAM cell utilizing novel capacitor
US5442205 *9 Aug 199315 Aug 1995At&T Corp.Semiconductor heterostructure devices with strained semiconductor layers
US5523592 *1 Feb 19944 Jun 1996Hitachi, Ltd.Semiconductor optical device, manufacturing method for the same, and opto-electronic integrated circuit using the same
US5534713 *20 May 19949 Jul 1996International Business Machines CorporationComplementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5596527 *13 Feb 199521 Jan 1997Nippon Steel CorporationElectrically alterable n-bit per cell non-volatile memory with reference cells
US5617351 *5 Jun 19951 Apr 1997International Business Machines CorporationThree-dimensional direct-write EEPROM arrays and fabrication methods
US5739567 *8 Nov 199414 Apr 1998Wong; Chun Chiu D.Highly compact memory device with nonvolatile vertical transistor memory cell
US5777347 *18 Jul 19977 Jul 1998Hewlett-Packard CompanyVertical CMOS digital multi-valued restoring logic device
US5780922 *27 Nov 199614 Jul 1998The Regents Of The University Of CaliforniaUltra-low phase noise GE MOSFETs
US5786612 *16 Apr 199628 Jul 1998Mitsubishi Denki Kabushiki KaishaSemiconductor device comprising trench EEPROM
US5792679 *30 Aug 199311 Aug 1998Sharp Microelectronics Technology, Inc.Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant
US5808344 *4 Feb 199715 Sep 1998International Business Machines CorporationSingle-transistor logic and CMOS inverters
US5891769 *27 Feb 19986 Apr 1999Motorola, Inc.Method for forming a semiconductor device having a heteroepitaxial layer
US5906951 *30 Apr 199725 May 1999International Business Machines CorporationStrained Si/SiGe layers on insulator
US5951757 *6 May 199714 Sep 1999The United States Of America As Represented By The Secretary Of The NavyMethod for making silicon germanium alloy and electric device structures
US6013134 *18 Feb 199811 Jan 2000International Business Machines CorporationAdvance integrated chemical vapor deposition (AICVD) for semiconductor devices
US6058044 *9 Dec 19982 May 2000Kabushiki Kaisha ToshibaShielded bit line sensing scheme for nonvolatile semiconductor memory
US6059895 *13 May 19999 May 2000International Business Machines CorporationStrained Si/SiGe layers on insulator
US6096590 *30 Jun 19981 Aug 2000International Business Machines CorporationScalable MOS field effect transistor
US6107653 *23 Jun 199822 Aug 2000Massachusetts Institute Of TechnologyControlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US6111267 *4 May 199829 Aug 2000Siemens AktiengesellschaftCMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer
US6117750 *21 Dec 199812 Sep 2000France TelecomProcess for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively
US6204529 *27 Aug 199920 Mar 2001Hsing Lan Lung8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate
US6207977 *21 Oct 199827 Mar 2001Interuniversitaire MicroelektronicaVertical MISFET devices
US6228694 *28 Jun 19998 May 2001Intel CorporationMethod of increasing the mobility of MOS transistors by use of localized stress regions
US6235568 *22 Jan 199922 May 2001Intel CorporationSemiconductor device having deposited silicon regions and a method of fabrication
US6249022 *22 Oct 199919 Jun 2001United Microelectronics Corp.Trench flash memory with nitride spacers for electron trapping
US6251755 *22 Apr 199926 Jun 2001International Business Machines CorporationHigh resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe
US6266278 *8 Aug 200024 Jul 2001Sandisk CorporationDual floating gate EEPROM cell array with steering gates shared adjacent cells
US6281532 *28 Jun 199928 Aug 2001Intel CorporationTechnique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6339232 *20 Sep 200015 Jan 2002Kabushika Kaisha ToshibaSemiconductor device
US6350993 *12 Mar 199926 Feb 2002International Business Machines CorporationHigh speed composite p-channel Si/SiGe heterostructure for field effect devices
US6399970 *16 Sep 19974 Jun 2002Matsushita Electric Industrial Co., Ltd.FET having a Si/SiGeC heterojunction channel
US6407406 *29 Jun 199918 Jun 2002Kabushiki Kaisha ToshibaSemiconductor device and method of manufacturing the same
US6413636 *2 Dec 19992 Jul 2002Mark A. AndrewsProtective yarn
US6437375 *5 Jun 200020 Aug 2002Micron Technology, Inc.PD-SOI substrate with suppressed floating body effect and method for its fabrication
US6555839 *16 May 200129 Apr 2003Amberwave Systems CorporationBuried channel strained silicon FET using a supply layer created through ion implantation
US6563152 *29 Dec 200013 May 2003Intel CorporationTechnique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
US6583437 *19 Mar 200124 Jun 2003Kabushiki Kaisha ToshibaSemiconductor device and method of manufacturing the same
US6593191 *16 May 200115 Jul 2003Amberwave Systems CorporationBuried channel strained silicon FET using a supply layer created through ion implantation
US6593625 *3 Apr 200215 Jul 2003International Business Machines CorporationRelaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6593641 *16 Jul 200115 Jul 2003Amberwave Systems CorporationRelaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6600170 *17 Dec 200129 Jul 2003Advanced Micro Devices, Inc.CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
US6603156 *31 Mar 20015 Aug 2003International Business Machines CorporationStrained silicon on insulator structures
US6605498 *29 Mar 200212 Aug 2003Intel CorporationSemiconductor transistor having a backfilled channel material
US6620664 *7 Feb 200216 Sep 2003Sharp Laboratories Of America, Inc.Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same
US6677192 *16 Jul 200113 Jan 2004Amberwave Systems CorporationMethod of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits
US6693641 *25 May 200017 Feb 2004Intel CorporationCalculating display mode values
US6703648 *29 Oct 20029 Mar 2004Advanced Micro Devices, Inc.Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
US6703688 *16 Jul 20019 Mar 2004Amberwave Systems CorporationRelaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723661 *16 Jul 200120 Apr 2004Amberwave Systems CorporationRelaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6724008 *16 Jul 200120 Apr 2004Amberwave Systems CorporationRelaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6730551 *2 Aug 20024 May 2004Massachusetts Institute Of TechnologyFormation of planar strained layers
US6737670 *7 Mar 200318 May 2004Massachusetts Institute Of TechnologySemiconductor substrate structure
US6743684 *11 Oct 20021 Jun 2004Texas Instruments IncorporatedMethod to produce localized halo for MOS transistor
US6759695 *11 Sep 20036 Jul 2004Sharp Laboratories Of America, Inc.Integrated circuit metal oxide semiconductor transistor
US6861318 *23 Jul 20031 Mar 2005Intel CorporationSemiconductor transistor having a stressed channel
US6885084 *23 Jul 200326 Apr 2005Intel CorporationSemiconductor transistor having a stressed channel
US6916694 *28 Aug 200312 Jul 2005International Business Machines CorporationStrained silicon-channel MOSFET using a damascene gate process
US6916727 *21 Jun 200212 Jul 2005Massachusetts Institute Of TechnologyEnhancement of P-type metal-oxide-semiconductor field effect transistors
US6921913 *4 Mar 200326 Jul 2005Taiwan Semiconductor Manufacturing Co., Ltd.Strained-channel transistor structure with lattice-mismatched zone
US7001837 *17 Jan 200321 Feb 2006Advanced Micro Devices, Inc.Semiconductor with tensile strained substrate and method of making the same
US7033869 *13 Jan 200425 Apr 2006Advanced Micro DevicesStrained silicon semiconductor on insulator MOSFET
US7083998 *1 Jul 20041 Aug 2006International Business Machines CorporationSi/SiGe optoelectronic integrated circuits
US7161206 *8 Dec 20049 Jan 2007Samsung Electronics Co., Ltd.Non-volatile memory devices
US7163853 *9 Feb 200516 Jan 2007Taiwan Semiconductor Manufacturing Company, Ltd.Method of manufacturing a capacitor and a metal gate on a semiconductor device
US7176537 *23 May 200513 Feb 2007Taiwan Semiconductor Manufacturing Company, Ltd.High performance CMOS with metal-gate and Schottky source/drain
US7238989 *11 Aug 20053 Jul 2007Taiwan Semiconductor Manufacturing Company, Ltd.Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
US7402493 *20 Nov 200622 Jul 2008Samsung Electronics Co., Ltd.Method for forming non-volatile memory devices
US20010003364 *8 Dec 200014 Jun 2001Sony CorporationSemiconductor and fabrication method thereof
US20020063292 *29 Nov 200030 May 2002Mark ArmstrongCMOS fabrication process utilizing special transistor orientation
US20020100942 *19 Jun 20011 Aug 2002Fitzgerald Eugene A.CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020125471 *4 Dec 200112 Sep 2002Fitzgerald Eugene A.CMOS inverter circuits utilizing strained silicon surface channel MOSFETS
US20020125497 *16 Jul 200112 Sep 2002Fitzgerald Eugene A.Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US20030013323 *14 Jun 200216 Jan 2003Richard HammondMethod of selective removal of SiGe alloys
US20030052334 *18 Jun 200220 Mar 2003Lee Minjoo L.Structure and method for a high-speed semiconductor device
US20030057439 *9 Aug 200227 Mar 2003Fitzgerald Eugene A.Dual layer CMOS devices
US20040007724 *12 Jul 200215 Jan 2004Anand MurthyProcess for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
US20040014276 *16 Jul 200222 Jan 2004Murthy Anand S.Method of making a semiconductor transistor
US20040026765 *6 Jun 200312 Feb 2004Amberwave Systems CorporationSemiconductor devices having strained dual channel layers
US20040119101 *23 Dec 200224 Jun 2004Gerhard SchromContact layout for MOSFETs under tensile strain
US20050017236 *18 Aug 200427 Jan 2005Hitachi, Ltd.Semiconductor device and semiconductor substrate
US20050151164 *7 Mar 200514 Jul 2005Amberwave Systems CorporationEnhancement of p-type metal-oxide-semiconductor field effect transistors
US20060071285 *29 Sep 20046 Apr 2006Suman DattaInducing strain in the channels of metal gate transistors
US20070032009 *6 Oct 20068 Feb 2007Amberwave Systems CorporationSemiconductor devices having strained dual channel layers
US20070072354 *20 Oct 200629 Mar 2007Massachusetts Institute Of TechnologyStructures with planar strained layers
US20070080409 *12 Oct 200512 Apr 2007Seliskar John JMixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof
US20080128747 *23 Oct 20075 Jun 2008Lee Minjoo LSTRUCTURE AND METHOD FOR A HIGH-SPEED SEMICONDUCTOR DEVICE HAVING A Ge CHANNEL LAYER
US20080206961 *22 Jan 200828 Aug 2008Hitachi, Ltd.Semiconductor device and semiconductor substrate
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US843633623 Oct 20077 May 2013Massachusetts Institute Of TechnologyStructure and method for a high-speed semiconductor device having a Ge channel layer
US20050151164 *7 Mar 200514 Jul 2005Amberwave Systems CorporationEnhancement of p-type metal-oxide-semiconductor field effect transistors
US20080128747 *23 Oct 20075 Jun 2008Lee Minjoo LSTRUCTURE AND METHOD FOR A HIGH-SPEED SEMICONDUCTOR DEVICE HAVING A Ge CHANNEL LAYER
Classifications
U.S. Classification257/19, 257/E27.064, 257/E21.618
International ClassificationH01L21/8238, H01L31/00, H01L21/8234, H01L27/092
Cooperative ClassificationH01L21/823412, H01L21/823807, H01L27/0922
European ClassificationH01L21/8238C, H01L21/8234C, H01L27/092D
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