US20060261445A1 - Integrated circuit device with treated perimeter edge - Google Patents
Integrated circuit device with treated perimeter edge Download PDFInfo
- Publication number
- US20060261445A1 US20060261445A1 US11/461,031 US46103106A US2006261445A1 US 20060261445 A1 US20060261445 A1 US 20060261445A1 US 46103106 A US46103106 A US 46103106A US 2006261445 A1 US2006261445 A1 US 2006261445A1
- Authority
- US
- United States
- Prior art keywords
- perimeter
- die
- planar
- integrated circuit
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000000463 material Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000007547 defect Effects 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 16
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 229910003460 diamond Inorganic materials 0.000 claims 1
- 239000010432 diamond Substances 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 229910052594 sapphire Inorganic materials 0.000 claims 1
- 239000010980 sapphire Substances 0.000 claims 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 1
- 229910010271 silicon carbide Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 43
- 238000000227 grinding Methods 0.000 abstract description 17
- 238000005498 polishing Methods 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 235000012431 wafers Nutrition 0.000 description 23
- 238000000429 assembly Methods 0.000 description 7
- 230000000712 assembly Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011044 quartzite Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02076—Cleaning after the substrates have been singulated
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/974—Substrate surface preparation
Definitions
- the present invention is directed to an improved integrated circuit die and a process for forming the die, the process including the further manufacturing step of grinding, polishing or otherwise treating one or more of the perimeter edges of an individual die.
- the invention enhances the further integrated circuit process and assembly steps to produce a more durable die of either a smaller size or having a denser circuitry with more circuitry per unit volume of die substrate material.
Abstract
An integrated circuit die and method of fabricating the same. The method comprises further grinding, polishing or otherwise treating one or more perimeter edges of an individual circuit die. The perimeter edges are treated to remove a substantial portion of the remaining substrate material layer or scribe therefrom without exposing the active circuitry of the die. The process reduces the overall length and width dimensions of a die producing a smaller circuit die without reducing the amount of circuitry on the die.
Description
- This application is a divisional of U.S. application Ser. No. 09/785,006, filed Feb. 16, 2001, which is a continuation of U.S. application Ser. No. 09/137,521, filed Aug. 20, 1998, now issued as U.S. Pat. No. 6,215,172, which is division of U.S. application Ser. No. 08/795,693, filed Feb. 4, 1997, now issued as U.S. Pat. No. 6,127,245, which applications are incorporated herein by reference.
- The present invention relates generally to the manufacturing of integrated circuits and in particular the present invention relates to a grinding technique for preparing integrated circuit dies for further assembly process steps.
- Fabrication of integrated circuit assemblies involves a complicated process including many steps. Depending on the desired product, the steps may vary from manufacturer to manufacturer and vary for different types of circuits. The basic process includes producing an ingot of a substrate material such as silicon having a highly crystalline structure. The ingot is cut into a number of thin wafers which are further ground and polished producing smooth and flat surfaces and smooth edges preferably free from defects such as notches, chips or other surface flaws.
- Each wafer is then subjected to a number of intricate process steps to form a plurality of the integrated circuit patterns on one side defining an active circuitry surface. Each wafer is divided or cut into a large number of circuit dies which will eventually be added to integrated circuit assemblies during further process steps. Each die is precisely cut from the wafer to leave a layer of substrate material or scribe on the edges of the dies. Individual dies may be back ground to remove some of the substrate from the inactive surface. The scribe material is left on the edges to protect the active circuitry from damage during further processing steps and to prevent short circuits between the die and another active circuit or lead.
- Today's rapidly advancing technology is producing a need for ever smaller and more densely packed circuits and circuitry. The smaller circuits make producing functional and flawless circuits more difficult. There is a continuing need to improve the process to provide a flawless, high quality integrated circuit having more active circuits and to do so in a smaller package.
- For the reasons stated above, and for other reasons stated below, which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved process of manufacturing integrated circuits which are smaller in size and more reliable than conventionally manufactured components.
-
FIG. 1 is a schematic depiction of the typical steps involved in a conventional integrated circuit manufacturing process; -
FIG. 2 is a top plan view of an integrated circuit die prior to undergoing the grinding technique of the invention; -
FIG. 3 is a top plan view of the integrated circuit die ofFIG. 2 after undergoing the grinding technique of the invention; -
FIG. 4 is an elevated perspective view of an integrated circuit assembly including the die ofFIG. 3 prior to encapsulation of the assembly in plastic; -
FIG. 5 is an elevated perspective view of the integrated circuit assembly ofFIG. 4 after encapsulation; and -
FIG. 6 is a side view of an integrated circuit die having bi-level edges produced using grinding techniques of the invention. - In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present inventions is to be defined only by the appended claims.
- The basic process for fabricating integrated circuits is known in the art and is illustrated in the simple schematic representation of
FIG. 1 . An ingot of silicon crystal is produced by refining a raw material, such as quartzite, by a complex multi-stage process to produce an electronic grade polysilicon substance. The substance is used to grow single crystal silicon ingots by one of several known processes. The silicon crystal ingot is then sliced into a number of very thin wafers producing the starting substrate for an integrated circuit. - Each wafer is then ground, polished or otherwise treated to produce very smooth, flat substrate surfaces and smooth, flawless edges. One process typically used to finish or treat the wafers is known as chemical mechanical planarization or CMP which is well understood in the art. Each wafer is then individually processed through a number of steps to form the active circuit patterns on one surface of the wafer. These steps may include adding or depositing material on the wafer, masking out a pattern on the wafer, etching a pattern on the wafer and other methods well known in the art. At the time of this writing, for example, a typical wafer may be about 150-200 mm (6-8 in) in diameter and about 0.25-0.50 mm (10-20 mils or 0.01-0.02 in) thick.
- The wafers are then evaluated to locate and identify any flawed or damaged circuits. The wafers may then, as an option, be further tested to determine which individual dies are “known good dies” as known to those skilled in the art. Once the active circuitry is formed, the wafer is sawed or diced into a number of integrated circuit dies. The functional dies are then picked off of the wafer and used to produce integrated circuit assemblies. The dies are bonded to a circuit substrate material, leads are attached or formed and connected to the circuitry, and the entire assembly is then further encapsulated in a plastic material to produce a final integrated circuit assembly. The present invention is directed to an improved integrated circuit die and a process for forming the die, the process including the further manufacturing step of grinding, polishing or otherwise treating one or more of the perimeter edges of an individual die. The invention enhances the further integrated circuit process and assembly steps to produce a more durable die of either a smaller size or having a denser circuitry with more circuitry per unit volume of die substrate material.
- Referring now to the drawings,
FIG. 2 illustrates a top plan view of an integrated circuit die after it has been cut or sawed from a silicon wafer.FIG. 3 illustrates the integrated circuit die after undergoing the additional manufacturing process steps of the invention. As shown inFIG. 2 , circuit die 10 includesactive circuitry 12 embedded in the silicon material and formed in layers on anactive surface 14 of the die. Die 10 further includes a bottom or inactive surface 16 (shown inFIG. 6 ) opposite the active surface which abuts a surface of asubstrate 17 to which the die is bonded in a later process step.FIGS. 4 and 5 illustrate an integrated circuit assembly prior to encapsulation (FIG. 4 ) and after encapsulation in plastic (FIG. 5 ). Die 10 also includes at least oneperimeter edge 18 and will likely include four such edges. As illustrated inFIG. 4 , a typicalintegrated circuit die 10 is generally rectangular. - As shown in
FIG. 2 , theactive circuitry 12 of die 10 terminates inboard from eachperimeter edge 18 of the die. The circuitry terminates at alast metal interconnect 20 defining the outer active circuitry limits for the die. A layer ofremaining scribe material 22 is purposely left protecting theactive circuitry 12 on theperimeter edges 18 to prevent open or short circuits and malfunctions within the circuitry and to protect the circuitry from damage during further process and assembly steps. As noted previously, back grinding the die to reduce and flatten the substrate material layer on theinactive surface 16 is known. - As is illustrated in
FIG. 2 , the unused buffer of silicon or scribe 22 typically has a microscopically rough surface forming a plurality of chips, nicks orother irregularities 24 on the surface and edges of the die. The depth and frequency of these irregularities will depend on many parameters in the formation of the die. Particularly, the sharpness of the blades used to saw each wafer from the ingot of silicon material and to saw each die from a particular wafer has an effect. Other factors which affect the surface quality of the die include the temperature of the blade coolant utilized during the cutting operations and also the speed of the rotating saw blade. - One problem caused by the
irregularities 24 on the perimeter edges 18 of the die is that they produce weak points in the silicon or other substrate material. The weak points may ultimately form cracks in the substrate material as the die undergoes further process and assembly steps. A crack in the die may produce unwanted open or short circuits or otherwise damage theactive circuitry 12 rendering the die non-functional or defective. - An additional problem with the remaining
scribe 22 is that it inherently increases the width and length dimensions of each die 10. Another problem with a conventional integrated circuit die as shown inFIG. 2 is that the perimeter edges 18 do not have an extremely flat finish which is highly desirable in known good die applications. Additionally, some substrate materials used to produce integrated circuits such as gallium arsenide or GaAs are more susceptible to surface flaws and edge damage than other substrate materials. -
FIG. 3 illustrates integrated circuit die 10 after undergoing the additional steps of the invention. The layer of remainingscribe 22 as it was prior to reduction is illustrated in phantom view inFIG. 3 (and also inFIG. 6 which is discussed below). The invention involves further removing the layer of remainingscribe 22 on the die and also increasing the smoothness and flatness of the perimeter edges 18 of a die. After separating a wafer into a plurality of dies, each die is further ground or polished by the process of the invention to remove a substantial amount of the remainingscribe 22 and reduce or eliminate anyirregularities 24 in theedges 18. Thus, a die which has a smaller length and width and which has much smoother and flatter edges is produced. - As an illustrative example, a die may have a layer of material on each edge which is about 25-50 μm (1-2 mils) thick. This will increase both the length and the width of a die about 50-100 μm (2-4 mils). The process of the invention is intended to remove most of this layer of material, leaving only enough material to prevent exposure of the active circuitry of the die. A size reduction of nearly 100 μm in length and width may be quite significant in some applications.
- Reducing or eliminating
irregularities 24 eliminates or at least substantially reduces the possibility of cracks forming in the unused substrate material surrounding the die during further process and assembly steps. Thus, the occurrence of cracks and open or short circuits in the active circuitry of the die is also prevented or substantially reduced. - Additionally, removing most of the remaining scribe and reducing the size of the die allows for one of two conditions to be used to significantly improve integrated circuit assemblies. The invention may be utilized to produce a slightly smaller die having the identical circuit density. Typically, very precise design constraints exist for the outer dimensions of integrated circuit assemblies and also for the minimum amount of plastic encapsulating material required to surround an integrated circuit. In some cases, the integrated circuit die size is nearly as large as the size limit of the final package design criteria, leaving little room for the encapsulating plastic material. By removing scribe material via the process of the invention, more encapsulation material may be added without increasing the size of the assembly. Thus, a particular die having the desired circuitry may be utilized in a package where it would have otherwise been too large.
- Another embodiment of the present invention is illustrated in
FIG. 6 . A die 50 is shown having bi-level perimeter edges 52 and 54. Thebi-level edge 52 is formed by polishing or grinding down oneportion 56 of the side edge to reduce the layer of material of that portion. The remaining portion ofedge 52 has been left as initially formed on the die producing the stepped or dual thicknessbi-level edge 52.Bi-level edge 54 is produced by grinding or polishing an entire edge to reduce the layer of scribe material to afirst level 58 and then further grinding oneportion 60 of the edge more than the remaining portion of the same edge.Bi-level edge 54 includes the preferred benefit of having the entirety of each edge subjected to the process of the invention and not just a portion of each edge. - The additional step of grinding or polishing an integrated circuit die 10 according to the invention may be performed using one of several known processes and methods. For illustration purposes, the CMP process will be briefly described. A circuit die may be held by a carrier and forced against a rotary grinding disc or polishing pad. The pad or disc is typically impregnated with a chemical or abrasive slurry which contacts the die edge to remove a portion of the scribe from the
edges 18 as the pad or disc rotates. Alternatively, a mechanical gripping device such as a “tweezer” type device may be used to hold the die with anedge 18 adjacent the polishing pad or grinding disc. As will be evident to those skilled in the art, the invention is not to be limited to a particular process of performing the grinding technique of the invention, but only to the steps as described for further removing some of the remaining scribe from the edges and surfaces of an integrated circuit die. - The problems with present wafer manufacturing technology and other problems are addressed by the present invention and which will be understood by reading and studying the specification. A method of producing an integrated circuit die of improved reliability, durability and dimensional characteristics is described, which is useful in the process of fabricating integrated circuit assemblies and the like.
- In particular, one method of an embodiment of the invention adds an additional step to the conventional manufacturing process for integrated circuits. A die which has been cut from a wafer is further ground, polished or otherwise treated to remove a portion of the remaining substrate or scribe layer on at least a portion of the edge of the die. Another method of an embodiment of the invention includes further grinding or polishing the entire perimeter edge of a particular die to remove a portion of the remaining scribe layer thereon. Another method of an embodiment of the invention includes the additional step of grinding or polishing a bi-level edge on at least a portion of the perimeter edge of a die. The bi-level edge may be produced in one of two ways. Some of the remaining scribe material may be removed from part of the die's perimeter edge to produce the bi-level edge. Alternatively, the entire edge may be partly ground or polished and then further grinding or polishing a portion of the scribe to produce the bi-level edge. This method creates a bi-level or stepped edge on the die. Such a bi-level edge may be produced on the entire perimeter edge or just a portion of the perimeter edge.
- The methods disclosed produce an integrated circuit die which is slightly smaller in length and width than a conventionally produced die. The method further produces a die which is less susceptible to damage such as edge chipping or die cracking. A chip in the edge of a die produces a weak point in its edge which may cause the die to crack during further processing or assembly steps. Such a flaw or chip may also cause a short or otherwise damage the active circuitry of the die.
- The invention may be utilized to produce a slightly smaller die having the same circuit capacity as a die which has not undergone the process of the invention. A smaller die may be useful in applications where one previously would have been too large taking up too much space within an integrated circuit assembly. Alternatively, the invention may be used to produce a die having increased circuit capacity with no size increase. In particular, some electronic packages require integrated circuit assemblies of a particular maximum size including the plastic encapsulation material. A die which has had most of the remaining scribe removed from the edges saves length and width permitting a die having more circuit capacity to be used within an application without increasing the size of the assembly.
- Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof
Claims (21)
1. An integrated circuit die cut from a wafer of substrate material, said die comprising:
an active surface having a circuit pattern formed thereon;
an inactive surface opposite said active surface;
at least one perimeter edge;
a layer of remaining substrate material on said at least one perimeter edge; and
wherein at least a portion of said layer of remaining substrate material is removed from said at least one perimeter edge of said integrated circuit die.
2. The integrated circuit die of claim 1 , further including a bi-level step on said at least one perimeter edge.
3. The integrated circuit die of claim 1 , further including a perimeter edge surface substantially perpendicular to at least one of the active and inactive surface and entirely contained within the remaining substrate material, the perimeter edge surface having a polished surface containing minimal defects and cut marks, and having at least one portion of the perimeter edge surface within five microns of at least one portion of the circuit pattern formed on the active surface.
4. The integrated circuit die of claim 1 , wherein said substrate includes at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, epitaxial silicon, silicon on sapphire, silicon on insulator, germanium, silicon-germanium, gallium-arsenide, a III-V compound, silicon carbide, and diamond.
5. A known good integrated circuit die cut from a wafer of substrate material to a first length and first width, said die comprising:
an active surface having a circuit pattern formed thereon;
an inactive surface opposite said active surface;
at least one perimeter edge;
a layer of remaining substrate material on said at least one perimeter edge; and
wherein at least a portion of said layer of remaining substrate material removed from said at least one perimeter edge of said integrated circuit die results in a second length and a second width less than the first length and first width.
6. The known good integrated circuit die of claim 5 , further including a perimeter edge surface substantially perpendicular to the active surface and entirely contained within the remaining substrate material, the perimeter edge surface having a polished smooth surface containing minimal defects and cut marks, and having at least one portion of the perimeter edge surface within five microns of at least one portion of the circuit pattern formed on the active surface.
7. The known good integrated circuit die of claim 6 , wherein said perimeter edge has a bi-level step with an upper portion of the perimeter having a portion within five microns of the circuit pattern, and a lower portion having a larger extent and being further horizontally and vertically from the circuit pattern.
8. An integrated circuit assembly comprising a known good integrated circuit die cut from a wafer of substrate material and being mounted to a base, said die and said base encapsulated in a plastic material, wherein said known good integrated circuit die comprises:
an active surface having a circuit pattern formed thereon;
an inactive surface opposite said active surface;
at least one perimeter edge;
a layer of remaining substrate material on said at least one perimeter edge; and
wherein at least a portion of said layer of remaining substrate material is removed from said at least one perimeter edge of said integrated circuit die.
9. The integrated circuit assembly of claim 8 , further including a perimeter edge surface perpendicular to at least one of the active and inactive surface and entirely contained within the remaining substrate material, the perimeter edge surface having a polished smooth surface having at least one portion of the perimeter edge surface within five microns of at least one portion of the circuit pattern formed on the active surface.
10. The integrated circuit assembly of claim 9 , wherein said perimeter edge has a bi-level step with an upper portion of the perimeter having a portion within five microns of the circuit pattern, and a lower portion having a larger extent and being further horizontally and vertically from the circuit pattern.
11. A semiconductor die, comprising:
a substrate that is one of cut and sawed from a semiconductor wafer, having a first planar surface having a first pair of orthogonal dimensions, having a first region with active circuitry thereon having a second pair of orthogonal dimensions smaller than the first pair, surrounded by an unused buffer area second region having a first width from an edge of the substrate to an edge of the first region;
a second planar surface opposite the first planar surface; and
one or more planar perimeter side surfaces disposed in the second region, each planar perimeter side surface extending continuously perpendicular from the first planar surface to the second planar surface.
12. The semiconductor die of claim 11 , wherein each planar perimeter side surface of the semiconductor die comprises a flat polished smooth surface with a top portion of each individual planar perimeter side surface disposed in the second region and having a first width of less than five microns from an edge of the first region to an edge of the substrate.
13. The semiconductor die of claim 11 , wherein the semiconductor die has a substantially rectangular shape.
14. The semiconductor die of claim 11 , wherein the second region is substantially crystal defect free, and the one or more planar perimeter side surfaces disposed in the second region are smooth as an unused portion of the top surface of the semiconductor wafer.
15. A semiconductor die, comprising:
a planar surface having a first region with active circuitry thereon surrounded by an unused buffer area second region;
a plurality of perimeter side surfaces disposed in the second region, each having two portions extending perpendicular to the planar surface and having at least one portion disposed parallel to, but displaced vertically from the planar surface; and
a top portion of an upper one of the two perpendicular portions disposed within five microns of an edge of a portion of the active circuitry of the first region.
16. The semiconductor die as recited in claim 15 , wherein the semiconductor die comprises a shape having four substantially right angles.
17. The semiconductor die as recited in claim 15 , wherein a side surface of the upper one of the two perpendicular portions has a substantially flat surface with a smoothness equivalent to the surface smoothness of an unused portion of the top planar surface.
18. A semiconductor die comprising:
a substrate having a substantially flat and smooth top planar surface having a first region with active circuitry thereon surrounded by a second region;
a substantially flat bottom planar surface opposite the first planar surface;
four perimeter sides disposed in the second region extending between the top planar surface and the bottom planar surface;
each perimeter side having two offset perimeter planar surfaces perpendicular to the top planar surface, where the two offset perimeter planar surfaces are substantially parallel to each other and offset in a horizontal direction from one another;
each perimeter side having a top one of the two offset perimeter planar surfaces extending from the top planar surface to an intermediate point, the bottom one of the two offset perimeter planar surfaces extending from the bottom planar surface to the intermediate point, and each of the offset perimeter planar surfaces is connected to the other by a third surface oriented in a horizontal direction at the intermediate point and parallel to the top planar surface.
19. The semiconductor die as recited in claim 18 , wherein a top edge portion of the top of the two offset perimeter planar surfaces is disposed in the second region within approximately 5 microns of an edge of the first region.
20. The semiconductor die as recited in claim 18 , wherein a top one of the two offset perimeter planar surfaces has a flat surface with a surface variation smoothness equivalent to the surface smoothness of an unused portion of the top planar surface.
21. The semiconductor die as recited in claim 18 , wherein both a top and a bottom one of the two offset perimeter planar surfaces has a flat surface with a surface variation smoothness equivalent to the surface smoothness of an unused portion of the top planar surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/461,031 US20060261445A1 (en) | 1997-02-04 | 2006-07-31 | Integrated circuit device with treated perimeter edge |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/795,693 US6127245A (en) | 1997-02-04 | 1997-02-04 | Grinding technique for integrated circuits |
US09/137,521 US6215172B1 (en) | 1997-02-04 | 1998-08-20 | Grinding technique for integrated circuits |
US09/785,006 US20010004544A1 (en) | 1997-02-04 | 2001-02-16 | Grinding technique for integrated circuits |
US11/461,031 US20060261445A1 (en) | 1997-02-04 | 2006-07-31 | Integrated circuit device with treated perimeter edge |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/785,006 Division US20010004544A1 (en) | 1997-02-04 | 2001-02-16 | Grinding technique for integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060261445A1 true US20060261445A1 (en) | 2006-11-23 |
Family
ID=25166211
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/795,693 Expired - Fee Related US6127245A (en) | 1997-02-04 | 1997-02-04 | Grinding technique for integrated circuits |
US09/137,521 Expired - Fee Related US6215172B1 (en) | 1997-02-04 | 1998-08-20 | Grinding technique for integrated circuits |
US09/785,006 Abandoned US20010004544A1 (en) | 1997-02-04 | 2001-02-16 | Grinding technique for integrated circuits |
US11/461,031 Abandoned US20060261445A1 (en) | 1997-02-04 | 2006-07-31 | Integrated circuit device with treated perimeter edge |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/795,693 Expired - Fee Related US6127245A (en) | 1997-02-04 | 1997-02-04 | Grinding technique for integrated circuits |
US09/137,521 Expired - Fee Related US6215172B1 (en) | 1997-02-04 | 1998-08-20 | Grinding technique for integrated circuits |
US09/785,006 Abandoned US20010004544A1 (en) | 1997-02-04 | 2001-02-16 | Grinding technique for integrated circuits |
Country Status (1)
Country | Link |
---|---|
US (4) | US6127245A (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6127245A (en) * | 1997-02-04 | 2000-10-03 | Micron Technology, Inc. | Grinding technique for integrated circuits |
JP2002043412A (en) * | 2000-07-24 | 2002-02-08 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
US6686225B2 (en) | 2001-07-27 | 2004-02-03 | Texas Instruments Incorporated | Method of separating semiconductor dies from a wafer |
US6541352B2 (en) | 2001-07-27 | 2003-04-01 | Texas Instruments Incorporated | Semiconductor die with contoured bottom surface and method for making same |
JP4072522B2 (en) * | 2004-07-12 | 2008-04-09 | エルピーダメモリ株式会社 | Semiconductor device and manufacturing method thereof |
TWI269392B (en) * | 2005-03-03 | 2006-12-21 | Advanced Semiconductor Eng | Die structure of package and method of manufacturing the same |
TWI309880B (en) * | 2006-09-11 | 2009-05-11 | Siliconware Precision Industries Co Ltd | Semiconductor chip and package structure and fabrication method thereof |
US7973472B2 (en) * | 2009-04-15 | 2011-07-05 | Global Oled Technology Llc | Display device with polygonal chiplets |
US8283742B2 (en) * | 2010-08-31 | 2012-10-09 | Infineon Technologies, A.G. | Thin-wafer current sensors |
US8862648B2 (en) | 2011-05-24 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fast filter calibration apparatus |
US9318405B2 (en) | 2014-05-01 | 2016-04-19 | Qualcomm Incorporated | Wafer level package without sidewall cracking |
KR102442622B1 (en) | 2017-08-03 | 2022-09-13 | 삼성전자주식회사 | Semiconductor device package |
Citations (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3152939A (en) * | 1960-08-12 | 1964-10-13 | Westinghouse Electric Corp | Process for preparing semiconductor members |
US3545325A (en) * | 1969-02-28 | 1970-12-08 | Aerojet General Co | Cutting apparatus |
US3689803A (en) * | 1971-03-30 | 1972-09-05 | Ibm | Integrated circuit structure having a unique surface metallization layout |
US3839781A (en) * | 1971-04-21 | 1974-10-08 | Signetics Corp | Method for discretionary scribing and breaking semiconductor wafers for yield improvement |
US3953919A (en) * | 1974-01-18 | 1976-05-04 | The Lucas Electrical Company Limited | Method of manufacturing semi-conductor devices |
US4542397A (en) * | 1984-04-12 | 1985-09-17 | Xerox Corporation | Self aligning small scale integrated circuit semiconductor chips to form large area arrays |
US4604161A (en) * | 1985-05-02 | 1986-08-05 | Xerox Corporation | Method of fabricating image sensor arrays |
US4804641A (en) * | 1985-09-30 | 1989-02-14 | Siemens Aktiengesellschaft | Method for limiting chippage when sawing a semiconductor wafer |
US4814296A (en) * | 1987-08-28 | 1989-03-21 | Xerox Corporation | Method of fabricating image sensor dies for use in assembling arrays |
US5128282A (en) * | 1991-11-04 | 1992-07-07 | Xerox Corporation | Process for separating image sensor dies and the like from a wafer that minimizes silicon waste |
US5151389A (en) * | 1990-09-10 | 1992-09-29 | Rockwell International Corporation | Method for dicing semiconductor substrates using an excimer laser beam |
US5196378A (en) * | 1987-12-17 | 1993-03-23 | Texas Instruments Incorporated | Method of fabricating an integrated circuit having active regions near a die edge |
US5231683A (en) * | 1991-10-11 | 1993-07-27 | United Technologies Corporation | Attaching optical fibers to integrated optic chips |
US5266528A (en) * | 1991-09-17 | 1993-11-30 | Fujitsu Limited | Method of dicing semiconductor wafer with diamond and resin blades |
US5314844A (en) * | 1991-03-04 | 1994-05-24 | Kabushiki Kaisha Toshiba | Method for dicing a semiconductor wafer |
US5408739A (en) * | 1993-05-04 | 1995-04-25 | Xerox Corporation | Two-step dieing process to form an ink jet face |
US5426073A (en) * | 1988-10-07 | 1995-06-20 | Fujitsu Limited | Method of fabricating semiconductor devices using an intermediate grinding step |
US5477062A (en) * | 1991-12-13 | 1995-12-19 | Yamaha Corporation | Semiconductor wafer |
US5706176A (en) * | 1996-07-22 | 1998-01-06 | Xerox Corporation | Butted chip array with beveled chips |
US5718615A (en) * | 1995-10-20 | 1998-02-17 | Boucher; John N. | Semiconductor wafer dicing method |
US5739067A (en) * | 1995-12-07 | 1998-04-14 | Advanced Micro Devices, Inc. | Method for forming active devices on and in exposed surfaces of both sides of a silicon wafer |
US5747365A (en) * | 1996-08-01 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for preparing semiconductor chip as SEM specimen |
US5786266A (en) * | 1994-04-12 | 1998-07-28 | Lsi Logic Corporation | Multi cut wafer saw process |
US5786632A (en) * | 1993-10-14 | 1998-07-28 | Micron Technology, Inc. | Semiconductor package |
US5786237A (en) * | 1994-08-22 | 1998-07-28 | International Business Machines Corporation | Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips |
US5803797A (en) * | 1996-11-26 | 1998-09-08 | Micron Technology, Inc. | Method and apparatus to hold intergrated circuit chips onto a chuck and to simultaneously remove multiple intergrated circuit chips from a cutting chuck |
US5816899A (en) * | 1996-07-22 | 1998-10-06 | Buehler, Ltd. | Micro precise polishing apparatus |
US5851137A (en) * | 1995-06-05 | 1998-12-22 | Minnesota Mining And Manufacturing Company | Coater die edge finishing method |
US5899743A (en) * | 1995-03-13 | 1999-05-04 | Komatsu Electronic Metals Co., Ltd. | Method for fabricating semiconductor wafers |
US5964030A (en) * | 1994-06-10 | 1999-10-12 | Vlsi Technology, Inc. | Mold flow regulating dam ring |
US5986340A (en) * | 1996-05-02 | 1999-11-16 | National Semiconductor Corporation | Ball grid array package with enhanced thermal and electrical characteristics and electronic device incorporating same |
US6040235A (en) * | 1994-01-17 | 2000-03-21 | Shellcase Ltd. | Methods and apparatus for producing integrated circuit devices |
US6064114A (en) * | 1997-12-01 | 2000-05-16 | Motorola, Inc. | Semiconductor device having a sub-chip-scale package structure and method for forming same |
US6117347A (en) * | 1996-07-10 | 2000-09-12 | Nec Corporation | Method of separating wafers into individual die |
US6215172B1 (en) * | 1997-02-04 | 2001-04-10 | Micron Technology, Inc. | Grinding technique for integrated circuits |
US6287949B1 (en) * | 1994-06-20 | 2001-09-11 | Fujitsu Limited | Multi-chip semiconductor chip module |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0567599A (en) * | 1991-09-06 | 1993-03-19 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
EP0637840A1 (en) * | 1993-08-05 | 1995-02-08 | AT&T Corp. | Integrated circuit with active devices under bond pads |
US5839781A (en) * | 1997-12-04 | 1998-11-24 | Knape; Ronnie D. | Lawn chair rocker base system |
-
1997
- 1997-02-04 US US08/795,693 patent/US6127245A/en not_active Expired - Fee Related
-
1998
- 1998-08-20 US US09/137,521 patent/US6215172B1/en not_active Expired - Fee Related
-
2001
- 2001-02-16 US US09/785,006 patent/US20010004544A1/en not_active Abandoned
-
2006
- 2006-07-31 US US11/461,031 patent/US20060261445A1/en not_active Abandoned
Patent Citations (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3152939A (en) * | 1960-08-12 | 1964-10-13 | Westinghouse Electric Corp | Process for preparing semiconductor members |
US3545325A (en) * | 1969-02-28 | 1970-12-08 | Aerojet General Co | Cutting apparatus |
US3689803A (en) * | 1971-03-30 | 1972-09-05 | Ibm | Integrated circuit structure having a unique surface metallization layout |
US3839781A (en) * | 1971-04-21 | 1974-10-08 | Signetics Corp | Method for discretionary scribing and breaking semiconductor wafers for yield improvement |
US3953919A (en) * | 1974-01-18 | 1976-05-04 | The Lucas Electrical Company Limited | Method of manufacturing semi-conductor devices |
US4542397A (en) * | 1984-04-12 | 1985-09-17 | Xerox Corporation | Self aligning small scale integrated circuit semiconductor chips to form large area arrays |
US4604161A (en) * | 1985-05-02 | 1986-08-05 | Xerox Corporation | Method of fabricating image sensor arrays |
US4804641A (en) * | 1985-09-30 | 1989-02-14 | Siemens Aktiengesellschaft | Method for limiting chippage when sawing a semiconductor wafer |
US4814296A (en) * | 1987-08-28 | 1989-03-21 | Xerox Corporation | Method of fabricating image sensor dies for use in assembling arrays |
US5196378A (en) * | 1987-12-17 | 1993-03-23 | Texas Instruments Incorporated | Method of fabricating an integrated circuit having active regions near a die edge |
US5426073A (en) * | 1988-10-07 | 1995-06-20 | Fujitsu Limited | Method of fabricating semiconductor devices using an intermediate grinding step |
US5151389A (en) * | 1990-09-10 | 1992-09-29 | Rockwell International Corporation | Method for dicing semiconductor substrates using an excimer laser beam |
US5314844A (en) * | 1991-03-04 | 1994-05-24 | Kabushiki Kaisha Toshiba | Method for dicing a semiconductor wafer |
US5266528A (en) * | 1991-09-17 | 1993-11-30 | Fujitsu Limited | Method of dicing semiconductor wafer with diamond and resin blades |
US5231683A (en) * | 1991-10-11 | 1993-07-27 | United Technologies Corporation | Attaching optical fibers to integrated optic chips |
US5128282A (en) * | 1991-11-04 | 1992-07-07 | Xerox Corporation | Process for separating image sensor dies and the like from a wafer that minimizes silicon waste |
US5477062A (en) * | 1991-12-13 | 1995-12-19 | Yamaha Corporation | Semiconductor wafer |
US5408739A (en) * | 1993-05-04 | 1995-04-25 | Xerox Corporation | Two-step dieing process to form an ink jet face |
US5786632A (en) * | 1993-10-14 | 1998-07-28 | Micron Technology, Inc. | Semiconductor package |
US6040235A (en) * | 1994-01-17 | 2000-03-21 | Shellcase Ltd. | Methods and apparatus for producing integrated circuit devices |
US5786266A (en) * | 1994-04-12 | 1998-07-28 | Lsi Logic Corporation | Multi cut wafer saw process |
US5964030A (en) * | 1994-06-10 | 1999-10-12 | Vlsi Technology, Inc. | Mold flow regulating dam ring |
US6287949B1 (en) * | 1994-06-20 | 2001-09-11 | Fujitsu Limited | Multi-chip semiconductor chip module |
US5786237A (en) * | 1994-08-22 | 1998-07-28 | International Business Machines Corporation | Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips |
US5899743A (en) * | 1995-03-13 | 1999-05-04 | Komatsu Electronic Metals Co., Ltd. | Method for fabricating semiconductor wafers |
US5851137A (en) * | 1995-06-05 | 1998-12-22 | Minnesota Mining And Manufacturing Company | Coater die edge finishing method |
US5718615A (en) * | 1995-10-20 | 1998-02-17 | Boucher; John N. | Semiconductor wafer dicing method |
US5739067A (en) * | 1995-12-07 | 1998-04-14 | Advanced Micro Devices, Inc. | Method for forming active devices on and in exposed surfaces of both sides of a silicon wafer |
US5986340A (en) * | 1996-05-02 | 1999-11-16 | National Semiconductor Corporation | Ball grid array package with enhanced thermal and electrical characteristics and electronic device incorporating same |
US6117347A (en) * | 1996-07-10 | 2000-09-12 | Nec Corporation | Method of separating wafers into individual die |
US5816899A (en) * | 1996-07-22 | 1998-10-06 | Buehler, Ltd. | Micro precise polishing apparatus |
US5706176A (en) * | 1996-07-22 | 1998-01-06 | Xerox Corporation | Butted chip array with beveled chips |
US5747365A (en) * | 1996-08-01 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for preparing semiconductor chip as SEM specimen |
US5803797A (en) * | 1996-11-26 | 1998-09-08 | Micron Technology, Inc. | Method and apparatus to hold intergrated circuit chips onto a chuck and to simultaneously remove multiple intergrated circuit chips from a cutting chuck |
US5913104A (en) * | 1996-11-26 | 1999-06-15 | Micron Technology, Inc. | Method and apparatus to hold integrated circuit chips onto a chuck and to simultaneously remove multiple integrated circuit chips from a cutting chuck |
US6215172B1 (en) * | 1997-02-04 | 2001-04-10 | Micron Technology, Inc. | Grinding technique for integrated circuits |
US20010004544A1 (en) * | 1997-02-04 | 2001-06-21 | Micron Technology, Inc. | Grinding technique for integrated circuits |
US6064114A (en) * | 1997-12-01 | 2000-05-16 | Motorola, Inc. | Semiconductor device having a sub-chip-scale package structure and method for forming same |
Also Published As
Publication number | Publication date |
---|---|
US20010004544A1 (en) | 2001-06-21 |
US6127245A (en) | 2000-10-03 |
US6215172B1 (en) | 2001-04-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20060261445A1 (en) | Integrated circuit device with treated perimeter edge | |
US4588473A (en) | Semiconductor wafer process | |
US6699774B2 (en) | Wafer splitting method using cleavage | |
US7135384B2 (en) | Semiconductor wafer dividing method and apparatus | |
US5622875A (en) | Method for reclaiming substrate from semiconductor wafers | |
US6852012B2 (en) | Cluster tool systems and methods for in fab wafer processing | |
EP0678904A1 (en) | Multicut wafer saw process | |
US6338805B1 (en) | Process for fabricating semiconductor wafers with external gettering | |
US6376335B1 (en) | Semiconductor wafer manufacturing process | |
JP2006222453A (en) | Silicon wafer, method for manufacturing the same, and soi wafer | |
KR100572556B1 (en) | Method for Processing a Semiconductor Wafer Including Back Side Grinding | |
JPH04276645A (en) | Dicing method of compound semiconductor wafer | |
US6933211B2 (en) | Semiconductor device whose semiconductor chip has chamfered backside surface edges and method of manufacturing the same | |
KR20010092732A (en) | Method of processing semiconductor wafers to build in back surface damage | |
JPH06275713A (en) | Semiconductor wafer, semiconductor chip and dicing method therefor | |
EP0813931B1 (en) | Method of manufacturing semiconductor wafer | |
JP2588326B2 (en) | Method for manufacturing semiconductor wafer | |
US6264535B1 (en) | Wafer sawing/grinding process | |
JP3803214B2 (en) | Manufacturing method of semiconductor device | |
JP7135352B2 (en) | Semiconductor device manufacturing method | |
US20010023082A1 (en) | Grind and single wafer etch process to remove metallic contamination in silicon wafers | |
KR100289403B1 (en) | Semiconductor package manufacturing method | |
JP4151155B2 (en) | Manufacturing method of notched compound semiconductor wafer | |
JPS62243332A (en) | Processing of semiconductor wafer | |
WO2001054178A1 (en) | Semiconductor wafer manufacturing process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION |