US20060243973A1 - Thin film diode integrated with chalcogenide memory cell - Google Patents
Thin film diode integrated with chalcogenide memory cell Download PDFInfo
- Publication number
- US20060243973A1 US20060243973A1 US11/476,763 US47676306A US2006243973A1 US 20060243973 A1 US20060243973 A1 US 20060243973A1 US 47676306 A US47676306 A US 47676306A US 2006243973 A1 US2006243973 A1 US 2006243973A1
- Authority
- US
- United States
- Prior art keywords
- layer
- diode
- glass
- forming
- chalcogenide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000015654 memory Effects 0.000 title claims abstract description 90
- 150000004770 chalcogenides Chemical class 0.000 title claims 11
- 239000010409 thin film Substances 0.000 title description 2
- 239000005387 chalcogenide glass Substances 0.000 claims abstract description 61
- 230000004888 barrier function Effects 0.000 claims abstract description 48
- 229910052709 silver Inorganic materials 0.000 claims abstract description 24
- 239000004332 silver Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 2
- 239000004020 conductor Substances 0.000 abstract description 68
- 239000011521 glass Substances 0.000 abstract description 52
- 238000009792 diffusion process Methods 0.000 abstract description 43
- QIHHYQWNYKOHEV-UHFFFAOYSA-N 4-tert-butyl-3-nitrobenzoic acid Chemical compound CC(C)(C)C1=CC=C(C(O)=O)C=C1[N+]([O-])=O QIHHYQWNYKOHEV-UHFFFAOYSA-N 0.000 abstract description 34
- 229910021645 metal ion Inorganic materials 0.000 abstract description 20
- 239000003792 electrolyte Substances 0.000 abstract description 19
- -1 silver ions Chemical class 0.000 abstract description 18
- 230000037361 pathway Effects 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 229910052797 bismuth Inorganic materials 0.000 abstract description 6
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 abstract description 6
- 210000004027 cell Anatomy 0.000 description 54
- 229910052721 tungsten Inorganic materials 0.000 description 24
- 239000010937 tungsten Substances 0.000 description 24
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 14
- 239000011669 selenium Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 239000011810 insulating material Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000010561 standard procedure Methods 0.000 description 7
- 210000005056 cell body Anatomy 0.000 description 6
- 210000001787 dendrite Anatomy 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 239000005380 borophosphosilicate glass Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000003491 array Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000010416 ion conductor Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- HTRSGQGJZWBDSW-UHFFFAOYSA-N [Ge].[Se] Chemical compound [Ge].[Se] HTRSGQGJZWBDSW-UHFFFAOYSA-N 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
- H01L29/247—Amorphous materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/685—Hi-Lo semiconductor devices, e.g. memory devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
- H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/066—Patterning of the switching material by filling of openings, e.g. damascene method
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8825—Selenides, e.g. GeSe
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/10—Resistive cells; Technology aspects
- G11C2213/11—Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
Definitions
- This invention relates generally to a method of manufacture for memory devices in integrated circuits and more particularly to programmable conductor memory arrays comprising glass electrolyte elements.
- DRAM dynamic random access memory
- Non-volatile memories do not need frequent refresh cycles to preserve their stored information, so they consume less power than volatile memories and can operate in an environment where the power is not always on. There are many applications where non-volatile memories are preferred or required, such as in cell phones or in control systems of automobiles.
- Non-volatile memories include magnetic random access memories (MRAMs), erasable programmable read only memories (EPROMs) and variations thereof.
- MRAMs magnetic random access memories
- EPROMs erasable programmable read only memories
- the programmable conductor cell of Kozicki et al. (also referred to by Kozicki et al. as a “metal dendrite memory”) comprises a glass ion conductor, such as a chalcogenide-metal ion glass and a plurality of electrodes disposed at the surface of the fast ion conductor and spaced a distance apart from one another.
- the glass/ion element shall be referred to herein as a “glass electrolyte,” or, more generally, “cell body.”
- a non-volatile conductive pathway (considered a sidewall “dendrite” by Kozicki et al.) grows from the cathode through or along the cell body towards the anode, shorting the electrodes and allowing current flow.
- the dendrite stops growing when the voltage is removed.
- the dendrite shrinks, re-dissolving metal ions into the cell body, when the voltage polarity is reversed.
- the programmable conductor cell In a binary mode, the programmable conductor cell has two states; a fully-grown dendrite or shorted state that can be read as a 1, and a state wherein the dendrite does not short out the electrodes that can be read as a 0, or vice versa. It is also possible to arrange variable resistance or capacitance devices with multiple states.
- the recent trends in memory arrays generally have been to form first a via, then fill it with a memory storage element (e.g., capacitor) and etch back. It is simple to isolate individual memory cells in this way.
- Programmable memory cells also have been fabricated using this so-called container configuration, wherein the electrodes and cell body layers are deposited into a via that has been etched into an insulating layer. Metal diffusion in the course of growing and shrinking the conductive pathway is confined by the via wall.
- the memory cell can be formed in a number of array designs. For example, in a cross-point circuit design, memory elements are formed between upper and lower conductive lines at intersections.
- vias are formed in an insulating layer and filled with the memory cell bodies, such as metal-doped glass electrolyte or glass fast ion diffusion (GFID) elements.
- GFID glass fast ion diffusion
- the device comprises at least a first diode element, a glass electrolyte element over the first diode element, and a top electrode in contact with the glass electrolyte element.
- the glass electrolyte element has metal ions mixed or dissolved therein and is able to selectively form a conductive pathway under the influence of an applied voltage.
- a memory device comprising an integrated diode and programmable conductor memory cell wherein both the diode and the memory cell comprise a chalcogenide glass.
- an integrated programmable conductor memory cell and diode device comprises a first polysilicon layer with a first conductivity type doping, a layer of germanium selenide glass containing metal ions over the first polysilicon layer and a top electrode over the layer of germaniumselenide glass.
- the device can further comprise a silicon substrate region having a second conductivity type doping, opposite to the first conductivity type doping, wherein the silicon substrate region is in direct contact with the first polysilicon layer.
- a method of fabricating a PCRAM comprises forming an insulating layer with an array of vias, providing at least one diode element in each via and providing a chalcogenide glass memory element over the diode element in each via.
- the chalcogenide glass memory element has metal ions therein and is capable of selectively forming a conductive pathway under the influence of an applied voltage.
- a method for making a PCRAM cell with an integrated thin film diode in a via comprises providing a diffusion barrier material at a bottom of the via, depositing a first chalcogenide glass to fill the via, etching the first chalcogenide glass back to form a recess in the via, doping the first chalcogenide glass to a predetermined depth after etching, forming a mixture of a second chalcogenide glass and a first conductive material to fill the via after doping and depositing a second conductive material over the mixture.
- FIG. 1 is a cross section of a partially fabricated integrated circuit, showing a via in a silicon nitride layer over a bottom conducting line.
- FIG. 2 shows the via of FIG. 1 after filling the via with germanium selenide (Ge—Se) glass.
- FIG. 3 shows the filled via of FIG. 2 after etching back to recess the Ge—Se glass into the via.
- FIG. 4 shows the Ge—Se glass in the via of FIG. 3 after ion implanting to dope a top portion of the Ge—Se layer.
- FIG. 5 shows the Ge—Se layer of FIG. 4 after an additional layer of Ge—Se glass has been deposited to fill the via.
- FIG. 6A shows the filled via of FIG. 5 after planarization to make the Ge—Se and the surrounding silicon nitride coplanar and subsequent metal deposition and patterning to make a top electrode, in accordance with one embodiment of the present invention.
- FIG. 6B shows the structure of FIG. 6A after formation of a top conductor.
- FIG. 7A shows the filled via of FIG. 5 after deposition of a metal layer over the Ge—Se glass, in accordance with another embodiment of the present invention.
- FIG. 7B shows the structure of FIG. 7A after patterning and etching the metal layer and the Ge—Se overlayer.
- FIG. 7C shows the structure of FIG. 7B after formation of a top conducting line.
- FIG. 8 is a cross section showing another embodiment of the invention wherein an integrated programmable conductor memory cell and diode device comprises a Ge—Se doped layer extending down to a bottom conducting line and overlaid by an undoped layer of Ge—Se glass.
- FIG. 9 is a cross section showing another embodiment of the invention wherein a diode comprises a p+ polysilicon layer and an n+ polysilicon layer, integrated with a programmable conductor memory cell.
- FIG. 10 is a cross section showing another embodiment of the invention wherein two integrated programmable conductor memory cell and diode devices are shown.
- a silicon nitride layer having two vias has been formed directly on a silicon substrate.
- the diodes comprise the underlying p + region of the substrate and n + polysilicon layers at the bottom of the vias.
- FIG. 11 is a cross section showing an alternative arrangement of the embodiment of FIG. 10 wherein first n + polysilicon layers are formed in contact with an underlying p + region of the substrate, and then narrower programmable conductor memory cells are formed in vias in a silicon nitride layer to land on the top surfaces of the diode structures.
- a simple diode comprises two diode elements, or sides of opposite conductivity type, in contact with each another, which form a p-n junction at their interface. More complex structures can be made from multiple diode elements.
- diode connected in series with each memory cell in an array. This allows for discrete switching of the memory cell as a certain level of forward bias is needed to overcome the diode barrier. Above that voltage, current flows easily through the diode. This diode barrier prevents accidental switching of the memory element. It is further desirable that the diode be “leaky,” that is, that it allow a small amount of conduction when reverse biased to allow a trickle current for reading the memory cell state.
- an integrated programmable conductor memory cell and diode device is defined as a device that incorporates both a programmable conductor memory cell and a diode so that they function together, without intervening electrical devices or lines, although layers such as optional diffusion barriers (described below) can intervene.
- layers such as optional diffusion barriers (described below) can intervene.
- a programmable conductor memory element comprises a glass electroltyte element, such as a chalcogenide glass element with metal ions mixed or dissolved therein, which is capable of forming a conductive pathway along or through the glass element under the influence of an applied voltage.
- the extent of the conductive pathway depends upon applied voltage and time; the higher the voltage, the faster the growth rate; and the longer the time, the greater the extent of the conductive pathway.
- the conductive pathway stops growing when the voltage is removed.
- the conductive pathway shrinks, re-dissolving metal ions into the cell body, when the voltage polarity is reversed.
- FIG. 1 is a cross-section drawing showing a structure for a portion of a memory array from which many embodiments of the current invention can be constructed.
- a bottom conducting line 10 overlies a substrate 8 .
- the substrate 8 may be a simple silicon wafer or it may contain up to several layers of integrated circuit devices and insulating layers; typically, an insulating layer intervenes between the conducting line 10 of a cross-point array and a lower semiconductor layer (e.g., top portion of a silicon wafer or an epitaxial layer thereover).
- the bottom conducting line 10 extends from side to side in the plane of the page and continues on past the edges of the page. For the memory array, there are a series of conducting lines parallel to the one 10 shown lying over the substrate 8 .
- the bottom conducting line 10 may comprise any conducting material suitable for integrated circuit manufacture, such as aluminum, copper, or combinations thereof.
- the bottom conducting line 10 comprises tungsten and acts as a bottom electrode for devices that will be fabricated over and in contact with the line 10 .
- an additional layer (not shown) comprising a diffusion barrier, preferably tungsten or tungsten nitride, is deposited over the bottom conducting line 10 .
- a layer of an insulating material 12 has been deposited over the bottom conducting line 10 .
- the insulating layer 12 has a thickness between about 25 nm and 150 nm, more preferably between about 35 nm and 75 nm, most preferably, between about 40 nm and 60 nm.
- the insulating material 12 may be any insulating material that does not interact adversely with the materials used in the programmable conductor memory cell and that has enough structural integrity to support a cell formed in a via therein. Suitable materials include oxides and nitrides.
- the insulating layer 12 comprises silicon nitride. Using standard techniques, an array of vias is patterned and etched into the insulating layer 12 .
- the vias are positioned so that their bottom surfaces expose a bottom conducting line (or a diffusion barrier layer thereover).
- One via 14 that exposes the bottom conducting line 10 is shown in FIG. 1 .
- the width of the via 14 is preferably between about 100 nm and 180 nm, more preferably between about 120 nm and 140 nm. It is in vias such as the one shown in FIG. 1 that the programmable conductor memory cells of many preferred embodiments can be constructed.
- FIG. 2 shows the structure of FIG. 1 after deposition of a chalcogenide glass 16 , preferably a germanium selenide (Ge—Se) glass, such as Ge 2 Se 8 or Ge 25 Se 75 , to overfill the via 14 .
- a chalcogenide glass 16 preferably a germanium selenide (Ge—Se) glass, such as Ge 2 Se 8 or Ge 25 Se 75 .
- the chalcogenide glass may be deposited by any of a number of methods including sputtering and evaporating.
- the chalcogenide glass layer 16 is etched back to form a recess in the via 14 , leaving only a portion 18 of chalcogenide glass remaining in the via 14 .
- the chalcogenide glass is etched back using an isotropic etch, such as a CF 4 dry etch or a tetramethyl ammonium hydroxide (TMAH) wet etch.
- TMAH tetramethyl ammonium hydroxide
- FIG. 4 shows the structure of FIG. 3 after doping a layer 20 of the chalcogenide glass portion 18 in the via 14 to a predetermined depth.
- the depth of the doped layer 20 is between about 10 nm and 20 nm.
- doping comprises processing at a temperature less than about 340° C. and to a concentration of between about 0.1 atomic % and 1.0 atomic %. More preferably, doping comprises ion implantation with a species such as bismuth or lead. In the illustrated embodiment, the ion implantation is performed at an energy between about 20 keV and 30 keV at a dose between about 1 ⁇ 10 13 atoms/cm 2 and 1 ⁇ 10 14 atoms/cm 2 .
- Germanium-selenium or germanium selenide (also referred to as “Ge—Se” herein) is a p-type semiconductor. Doping germanium selenide with bismuth or lead changes the conductivity from p-type to n-type. Thus in the structure of FIG. 4 , the bottom, undoped germanium selenide portion 18 and the doped layer 20 have opposite conductivity types and comprise a p-n junction diode.
- this layer 22 forms a programmable conductor memory cell and preferably comprises a germanium selenide glass, such as Ge 2 Se 8 or Ge 25 Se 75 , with a conductive material, such as metal ions, preferably silver ions, mixed or dissolved therein.
- the layer 22 is formed by co-sputtering Ge—Se glass, such as from a pressed powder target, and silver.
- the Ge—Se glass may be deposited first and then the silver ions diffused therein, such as by photodissolution, as is known in the art of programmable conductor memory cell fabrication.
- the concentration of silver in the chalcogenide glass memory element is between about 20 atomic % and 32 atomic %, more preferably, between about 29 atomic % and 31 atomic %.
- the skilled artisan can, however, arrive at a desired ratio within or outside these ranges through routine experimentation.
- FIGS. 6A-6B There are two illustrated embodiments for completing the integrated programmable conductor memory cell and diode device as described thus far.
- One embodiment is shown in FIGS. 6A-6B .
- the other is shown in FIGS. 7A-7C .
- FIG. 6A the structure of FIG. 5 has been planarized, leaving a programmable conductor chalcogenide glass memory element 24 with metal ions mixed or dissolved therein filling the recess in the via and level with the top surface of the insulating layer 12 .
- a layer of a conducting material preferably from Group IB or Group IIB, more preferably, silver, has been deposited over the chalcogenide glass element 24 and the insulating layer 12 .
- the thickness of the conducting layer is between about 50 nm and 100 nm.
- the conducting layer has been patterned and etched using standard methods to form a top electrode 26 for the integrated programmable conductor memory cell and diode device.
- a diffusion barrier (not shown), such as tungsten nitride, is deposited over the chalcogenide glass element 24 before forming the top electrode 26 .
- a diffusion barrier may also be deposited over the top electrode 26 .
- the top electrode 26 is a multi-layered structure that includes a diffusion barrier layer as one of its components.
- top conducting line 28 extending into and out of the plane of the paper.
- the top conducting line 28 comprises tungsten and connects a row of integrated programmable conductor memory cell and diode devices in the memory array.
- Tungsten also has the advantage of acting as a diffusion barrier for chalcogenide glass species.
- FIG. 6B is a cross-section view of an integrated programmable conductor memory cell and diode device in a via that shows the structure of an illustrated embodiment.
- the device comprises a first diode element 18 , having a first conductivity type, a glass electrolyte element 24 having metal ions, such as silver, therein over the first diode element 18 and a top electrode 26 in contact with the glass electrolyte element 24 .
- the structure further comprises a second diode element 20 , having a second conductivity type, between the first diode element 18 and the glass electrolyte element 24 .
- the diode elements 18 , 20 and the programmable conductor memory cell or glass electrolyte element 24 all comprise a chalcogenide glass, such as Ge—Se glass.
- the first diode element 18 is not intentionally doped and is naturally p-type.
- the second diode element 20 contains an n-type dopant such as bismuth or lead.
- a diffusion barrier layer (not shown) comprising titanium between the second diode element 20 and the glass electrolyte element 24 .
- the first diode element 18 is in electrical contact with the bottom conducting line 10 .
- a portion of the bottom conducting line 10 that is directly below and in electrical contact with the first diode element 18 forms a bottom electrode for the integrated programmable conductor memory cell and diode device.
- the thickness of the diffusion barrier layer is between about 10 nm and 40 nm.
- Materials for the diffusion barrier layers include titanium, tungsten and tungsten nitride.
- a layer of a conducting material 30 preferably from Group IB or Group IIB, more preferably silver, has been deposited over the chalcogenide glass layer 22 .
- the thickness of the conducting layer is between about 50 nm and 100 nm.
- both the conducting layer and the chalcogenide glass layer have been patterned and etched to form a programmable conductor chalcogenide glass memory element 32 with metal ions mixed or dissolved therein and an electrode 34 for the integrated programmable conductor memory cell and diode device.
- top conducting line 28 extending into and out of the plane of the page.
- the top conducting line 28 comprises tungsten and connects a row of integrated programmable conductor memory cell and diode devices in the memory array.
- FIG. 7C is a cross-section view of an integrated programmable conductor memory cell and diode device in a via that shows the structure of an illustrated embodiment.
- the device comprises a first diode element 18 , having a first conductivity type, a glass electrolyte element 32 having metal ions, such as silver, mixed or dissolved therein over the first diode element 18 and a top electrode 34 in contact with the glass electrolyte element 32 .
- the structure further comprises a second diode element 20 , having a second conductivity type, between the first diode element 18 and the glass electrolyte element 32 .
- the diode elements 18 , 20 and the programmable conductor memory cell or glass electrolyte element 32 all comprise a chalcogenide glass, such as Ge—Se glass.
- the first diode element 18 is not intentionally doped, and is naturally p-type.
- the second diode element 20 contains an n-type dopant such as bismuth or lead.
- a diffusion barrier layer (not shown) comprising titanium between the second diode element 20 and the glass electrolyte element 24 .
- the thickness of the diffusion barrier layer is between about 10 nm and 40 nm.
- Materials for the diffusion barrier layers include titanium, tungsten and tungsten nitride.
- the entire thickness of the chalcogenide glass portion 18 is doped. This embodiment is shown in FIG. 8 .
- the doped chalcogenide glass layer 36 extends down to the bottom conducting line 10 or a diffusion barrier layer thereover (not shown) and forms the first diode element.
- processing proceeds much as described for the embodiment in FIGS. 5, 6A and 6 B.
- Another chalcogenide glass layer is deposited, overfilling the via.
- the structure is planarized, leaving the chalcogenide glass layer 38 with metal ions therein filling the recess in the via and level with the top surface of the insulating layer 12 .
- This layer 38 functions both as the second diode element in contact with the first diode element 36 and as the programmable conductor memory element and preferably comprises a germanium selenide glass, such as Ge 2 Se 8 or Ge 25 Se 75 , with a conductive material, such as metal ions, preferably silver ions, mixed or dissolved therein.
- a layer of a conducting material preferably from Group IB or Group IIB, more preferably, silver, is deposited over the chalcogenide glass element 38 and the insulating layer 12 .
- the thickness of the conducting layer is between about 50 nm and 100 nm.
- the conducting layer is patterned and etched to form a top electrode 26 for the integrated programmable conductor memory cell and diode device.
- a diffusion barrier (not shown), such as tungsten nitride, is deposited over the chalcogenide glass element 38 before forming the top electrode 26 .
- a diffusion barrier may be deposited over the top electrode 26 .
- the top electrode 26 is a multi-layered structure that includes a diffusion barrier layer as one of its components.
- a second conducting layer is deposited, patterned and etched to form a top conducting line 28 extending into and out of the plane of the page.
- the top conducting line 28 comprises tungsten and connects a row of integrated programmable conductor memory cell and diode devices in the memory array.
- Tungsten also has the advantage of acting as a diffusion barrier for chalcogenide glass species.
- FIG. 8 is a cross-section view of an integrated programmable conductor memory cell and diode device in a via that shows the structure of an illustrated embodiment.
- the integrated PCRAM (memory and diode device) 36 , 38 is formed in a via in an insulating layer 12 , preferably silicon nitride.
- a conducting line 10 comprising a metal such as tungsten, extends along the bottom of the via and off the edges of the page.
- the first layer of chalcogenide glass 36 has n-type doping from a dopant such as bismuth or lead.
- a second layer of chalcogenide glass 38 infused with silver, is in contact with the first layer of chalcogenide glass 36 .
- the chalcogenide glass is Ge 2 Se 8 or Ge 25 Se 75 .
- the two layers 36 , 38 comprise a p-n junction, and the second layer 38 functions also as a programmable conductor memory element.
- a top electrode layer 26 lies over the second chalcogenide glass layer 38 and may comprise silver.
- a conducting line 28 extending into and out of the page is in contact with the electrode 26 .
- the conducting line 28 comprises tungsten and acts also as a diffusion barrier.
- a separate diffusion barrier layer (not shown) is used either below or above the electrode 26 .
- FIG. 1 Another embodiment of the invention can be described starting with the structure of FIG. 1 .
- a bottom conducting line 10 overlies a substrate 8 .
- an array of vias is patterned and etched into the insulating layer 12 .
- One via 14 is shown in FIG. 1 . It is in this via that the programmable conductor memory cell of this embodiment will be constructed.
- a layer of tungsten silicide 40 is deposited at the bottom of the via.
- a first diode element 42 preferably comprising a doped polysilicon layer having a first type conductivity, is deposited over the tungsten silicide layer 40 .
- a second diode element 44 preferably comprising a doped polysilicon layer having a second type conductivity, opposite to the first type conductivity, is deposited over the first diode element 42 .
- the two polysilicon layers 42 , 44 having opposite conductivity types, form a polysilicon diode.
- a diffusion barrier layer 46 preferably comprising tungsten nitride, is deposited over the second diode element 44 .
- a chalcogenide glass element 48 preferably a germanium selenide glass with metal ions, preferably silver ions, mixed or dissolved therein, is formed by depositing the glass over the diffusion barrier layer 46 and then planarizing the glass layer to make it level with the top surface of the insulating layer 12 .
- a layer of a conducting material preferably from Group IB or Group IIB, more preferably, silver, has been deposited over the chalcogenide glass element 48 and the insulating layer 12 .
- the thickness of the conducting layer is between about 50 nm and 100 nm.
- the conducting layer has been patterned and etched using standard methods to form a top electrode 26 for the integrated programmable conductor memory cell and polysilicon diode device.
- a diffusion barrier (not shown), more preferably, tungsten nitride, is deposited over the chalcogenide glass element 48 before forming the top electrode 26 .
- a conducting line may be provided as described above with reference to FIGS. 6B and 7C .
- FIG. 9 is a cross-section view of an integrated programmable conductor memory cell and diode device that shows the structure of an illustrated embodiment.
- the first polysilicon layer 42 having a first conductivity type doping, lies in a via in an insulating layer 12 .
- There is a second polysilicon layer 44 having a second conductivity type doping, opposite to the first conductivity type, between the first polysilicon layer 42 and a diffusion barrier layer 46 .
- the first polysilicon layer 42 may have p-type doping
- the second polysilicon layer 44 may have n-type doping.
- There is a layer of germanium selenide glass 48 containing metal ions, over the diffusion barrier layer 46 .
- There is a top electrode 26 over the germanium selenide glass 48 may comprise both a conducting layer and a diffusion barrier layer.
- a silicon substrate 8 is shown with a region 52 doped to have a first type conductivity, preferaby p + .
- the region 52 forms the first diode element.
- a layer of an insulating material 12 has been deposited over the substrate 8 .
- the insulating layer 12 has a thickness between about 50 nm and 150 nm, more preferably between about 95 nm and 105 nm.
- the insulating material 12 may be any insulating material that does not interact adversely with the materials used in the programmable conductor memory cell or in the diode and that has enough structural integrity to support a cell formed in a via therein. Suitable materials include oxides and nitrides.
- the insulating layer 12 comprises silicon nitride. Using standard techniques, an array of vias is patterned and etched into the insulating layer 12 . Two such vias, containing integrated programmable conductor memory cell and diode devices are shown in FIG. 10 .
- a polysilicon layer 54 having a second conductivity type, preferably n + , opposite to the first conductivity type of the doped region 52 , is deposited into the via in contact with the doped region 52 of the substrate 8 .
- Polysilicon layer 54 forms the second diode elements and, together with doped region 52 , forms p-n junction diodes.
- Diffusion barrier layers 56 are deposited over the second diode elements 54 .
- Chalcogenide glass elements 58 preferably germanium selenide glass with metal ions, preferably silver ions, mixed or dissolved therein, are formed by depositing the glass over the diffusion barrier layers 56 and then planarizing the glass to make it level with the top surface of the insulating layer 12 .
- a layer of a conducting material preferably from Group IB or Group IIB, more preferably, silver, is deposited over the chalcogenide glass elements 58 and the insulating layer 12 .
- the thickness of the conducting layer is between about 50 nm and 100 nm.
- the conducting layer is patterned and etched using standard methods to form top electrodes 26 for the integrated programmable conductor memory cell and polysilicon diode devices 58 , 52 , 54 .
- a diffusion barrier (not shown), more preferably, tungsten nitride, is deposited over the chalcogenide glass elements 58 before forming the top electrodes 26 .
- a conducting line 28 extending into and out of the page, is in contact with the electrode 26 .
- a conductive plug 60 preferably comprising polysilicon or a metal such as tungsten, makes contact to the doped silicon substrate region 52 and to conducting line 62 , thus providing electrical connections for the integrated programmable conductor memory cell and diode device of FIG. 10 .
- Conducting line 62 is insulated from conducting line 28 by layer 64 , preferably comprising BPSG (borophosphosilicate glass).
- a silicon substrate 8 is shown with a region 52 doped to have a first conductivity type, preferably p + .
- the region 52 forms the first diode elements for integrated programmable conductor memory cell and diode devices.
- a layer of polysilicon with conductivity, preferably n + , opposite to the conductivity of the doped region 52 of the substrate 8 is deposited.
- the polysilicon layer is patterned and etched to form the second diode elements 54 .
- a diffusion barrier layer such as tungsten, tungsten nitride or titanium, is deposited onto the polysilicon layer and then patterned and etched with the polysilicon layer, thus forming diffusion barrier layers 56 over the second diode elements 54 .
- a layer of material 64 preferably silicon nitride, is deposited conformally onto the second diode elements 54 and diffusion barrier layers 56 to act as an etch stop for a subsequent chemical-mechanical planarization step.
- An insulating layer 66 preferably comprising silicon oxide formed from TEOS, is deposited to a thickness that at least covers the top surface of layer 64 .
- Chemical-mechanical planarization is performed until the top portions of layer 64 are exposed to make a flat top surface for silicon oxide layer 66 .
- the exposed portions of layer 64 are patterned and etched to expose at least a portion of a top surface of the diffusion barrier layer 56 .
- a layer of insulating material 12 preferably silicon nitride, is deposited over the silicon oxide layer 66 .
- the layer 12 is patterned and etched to form vias down through layer 64 and onto diffusion barrier layer 56 .
- a chalcogenide glass layer is deposited, overfilling the vias.
- the chalcogenide glass forms the programmable conductor memory cells 58 and preferably comprises a germanium selenide glass, such as Ge 2 Se 8 or Ge 25 Se 75 , with a conductive material, such as metal ions, preferably silver ions, mixed or dissolved therein.
- the glass is formed by co-sputtering Ge—Se glass, such as from a pressed powder target, and silver.
- the Ge—Se glass may be deposited first and then the silver ions diffused therein, such as by photodissolution, as is known in the art of programmable conductor memory cell fabrication.
- the concentration of silver in the chalcogenide glass memory element is between about 20 atomic % and 36 atomic %, more preferably, between about 29 atomic % and 32 atomic %.
- a layer of a conducting material 27 preferably from Group IB or Group IIB, more preferably silver, is deposited over the chalcogenide glass layer 58 .
- the thickness of the conducting layer is between about 50 nm and 100 nm.
- Both the conducting layer 27 and the chalcogenide glass layer 58 are patterned and etched to form programmable conductor chalcogenide glass memory elements 58 with metal ions mixed or dissolved therein and electrodes and conducting lines 27 for the memory cells 58 .
- a layer of insulating material 64 preferably comprising BPSG (borophosphosilicate glass), is deposited over the conducting lines 27 and planarized.
- a via is etched through insulating layers 64 , 12 and 66 , down to expose a portion of the doped region 52 of the substrate 8 .
- the via is filled with conducting material, preferably polysilicon or a metal such as tungsten, thus forming a conductive plug 60 that makes contact to the doped silicon substrate region 52 .
- a conductive line preferably comprising aluminum or copper, is formed over the BPSG 64 and makes contact with the conductive plug 60 , and thus to the diodes in the integrated programmable conductor memory cell and diode devices.
Abstract
An integrated programmable conductor memory cell and diode device in an integrated circuit comprises a diode and a glass electrolyte element, the glass electrolyte element having metal ions mixed or dissolved therein and being able to selectively form a conductive pathway under the influence of an applied voltage. In one embodiment, both the diode and the memory cell comprise a chalcogenide glass, such as germanium selenide (e.g., Ge2Se8 or Ge25Se75). The first diode element comprises a chalcogenide glass layer having a first conductivity type, the second diode element comprises a chalcogenide glass layer doped with an element such as bismuth and having a second conductivity type opposite to the first conductivity type and the memory cell comprises a chalcogenide glass element with silver ions therein. In another embodiment, the diode comprises silicon and there is a diffusion barrier layer between the diode and the chalcogenide glass memory element. Methods of fabricating integrated programmable conductor memory cell and diode devices are also disclosed.
Description
- This invention relates generally to a method of manufacture for memory devices in integrated circuits and more particularly to programmable conductor memory arrays comprising glass electrolyte elements.
- The digital memory most commonly used in computers and computer system components is the dynamic random access memory (DRAM), wherein voltage stored in capacitors represents digital bits of information. Electric power must be supplied to the capacitors to maintain the information because, without frequent refresh cycles, the stored charge dissipates, and the information is lost. Memories that require constant power are known as volatile memories.
- Non-volatile memories do not need frequent refresh cycles to preserve their stored information, so they consume less power than volatile memories and can operate in an environment where the power is not always on. There are many applications where non-volatile memories are preferred or required, such as in cell phones or in control systems of automobiles. Non-volatile memories include magnetic random access memories (MRAMs), erasable programmable read only memories (EPROMs) and variations thereof.
- Another type of non-volatile memory is the programmable conductor or programmable metallization memory cell, which is described by Kozicki et al. in (U.S. Pat. No. 5,761,115; No. 5,914,893; and No. 6,084,796) and is included by reference herein. The programmable conductor cell of Kozicki et al. (also referred to by Kozicki et al. as a “metal dendrite memory”) comprises a glass ion conductor, such as a chalcogenide-metal ion glass and a plurality of electrodes disposed at the surface of the fast ion conductor and spaced a distance apart from one another. The glass/ion element shall be referred to herein as a “glass electrolyte,” or, more generally, “cell body.”
- When a voltage is applied to the anode and the cathode, a non-volatile conductive pathway (considered a sidewall “dendrite” by Kozicki et al.) grows from the cathode through or along the cell body towards the anode, shorting the electrodes and allowing current flow. The dendrite stops growing when the voltage is removed. The dendrite shrinks, re-dissolving metal ions into the cell body, when the voltage polarity is reversed. In a binary mode, the programmable conductor cell has two states; a fully-grown dendrite or shorted state that can be read as a 1, and a state wherein the dendrite does not short out the electrodes that can be read as a 0, or vice versa. It is also possible to arrange variable resistance or capacitance devices with multiple states.
- The recent trends in memory arrays generally have been to form first a via, then fill it with a memory storage element (e.g., capacitor) and etch back. It is simple to isolate individual memory cells in this way. Programmable memory cells also have been fabricated using this so-called container configuration, wherein the electrodes and cell body layers are deposited into a via that has been etched into an insulating layer. Metal diffusion in the course of growing and shrinking the conductive pathway is confined by the via wall. The memory cell can be formed in a number of array designs. For example, in a cross-point circuit design, memory elements are formed between upper and lower conductive lines at intersections. When forming a programmable conductor array with the glass electrolyte elements similar to those of Kozicki et al., vias are formed in an insulating layer and filled with the memory cell bodies, such as metal-doped glass electrolyte or glass fast ion diffusion (GFID) elements.
- Accordingly, a need exists for improved methods and structures for forming integrated programmable conductor memory arrays.
- An integrated programmable conductor memory cell and diode device in an integrated circuit is provided. The device comprises at least a first diode element, a glass electrolyte element over the first diode element, and a top electrode in contact with the glass electrolyte element. The glass electrolyte element has metal ions mixed or dissolved therein and is able to selectively form a conductive pathway under the influence of an applied voltage.
- In accordance with one aspect of the present invention, a memory device, comprising an integrated diode and programmable conductor memory cell is provided wherein both the diode and the memory cell comprise a chalcogenide glass.
- In one embodiment, an integrated programmable conductor memory cell and diode device is provided. The device comprises a first polysilicon layer with a first conductivity type doping, a layer of germanium selenide glass containing metal ions over the first polysilicon layer and a top electrode over the layer of germaniumselenide glass. The device can further comprise a silicon substrate region having a second conductivity type doping, opposite to the first conductivity type doping, wherein the silicon substrate region is in direct contact with the first polysilicon layer.
- In accordance with another aspect of the invention, a method of fabricating a PCRAM (programmable conductor random access memory) is provided. The method comprises forming an insulating layer with an array of vias, providing at least one diode element in each via and providing a chalcogenide glass memory element over the diode element in each via. The chalcogenide glass memory element has metal ions therein and is capable of selectively forming a conductive pathway under the influence of an applied voltage.
- In yet another aspect of the invention, a method for making a PCRAM cell with an integrated thin film diode in a via is provided. The method comprises providing a diffusion barrier material at a bottom of the via, depositing a first chalcogenide glass to fill the via, etching the first chalcogenide glass back to form a recess in the via, doping the first chalcogenide glass to a predetermined depth after etching, forming a mixture of a second chalcogenide glass and a first conductive material to fill the via after doping and depositing a second conductive material over the mixture.
- These and other aspects of the invention will be readily understood by the skilled artisan in view of the detailed description of the preferred embodiments below and the appended drawings, which are meant to illustrate and not to limit the invention, and in which:
-
FIG. 1 is a cross section of a partially fabricated integrated circuit, showing a via in a silicon nitride layer over a bottom conducting line. -
FIG. 2 shows the via ofFIG. 1 after filling the via with germanium selenide (Ge—Se) glass. -
FIG. 3 shows the filled via ofFIG. 2 after etching back to recess the Ge—Se glass into the via. -
FIG. 4 shows the Ge—Se glass in the via ofFIG. 3 after ion implanting to dope a top portion of the Ge—Se layer. -
FIG. 5 shows the Ge—Se layer ofFIG. 4 after an additional layer of Ge—Se glass has been deposited to fill the via. -
FIG. 6A shows the filled via ofFIG. 5 after planarization to make the Ge—Se and the surrounding silicon nitride coplanar and subsequent metal deposition and patterning to make a top electrode, in accordance with one embodiment of the present invention. -
FIG. 6B shows the structure ofFIG. 6A after formation of a top conductor. -
FIG. 7A shows the filled via ofFIG. 5 after deposition of a metal layer over the Ge—Se glass, in accordance with another embodiment of the present invention. -
FIG. 7B shows the structure ofFIG. 7A after patterning and etching the metal layer and the Ge—Se overlayer. -
FIG. 7C shows the structure ofFIG. 7B after formation of a top conducting line. -
FIG. 8 is a cross section showing another embodiment of the invention wherein an integrated programmable conductor memory cell and diode device comprises a Ge—Se doped layer extending down to a bottom conducting line and overlaid by an undoped layer of Ge—Se glass. -
FIG. 9 is a cross section showing another embodiment of the invention wherein a diode comprises a p+ polysilicon layer and an n+ polysilicon layer, integrated with a programmable conductor memory cell. -
FIG. 10 is a cross section showing another embodiment of the invention wherein two integrated programmable conductor memory cell and diode devices are shown. A silicon nitride layer having two vias has been formed directly on a silicon substrate. The diodes comprise the underlying p+ region of the substrate and n+ polysilicon layers at the bottom of the vias. -
FIG. 11 is a cross section showing an alternative arrangement of the embodiment ofFIG. 10 wherein first n+ polysilicon layers are formed in contact with an underlying p+ region of the substrate, and then narrower programmable conductor memory cells are formed in vias in a silicon nitride layer to land on the top surfaces of the diode structures. - A simple diode comprises two diode elements, or sides of opposite conductivity type, in contact with each another, which form a p-n junction at their interface. More complex structures can be made from multiple diode elements.
- It is desirable to have a diode connected in series with each memory cell in an array. This allows for discrete switching of the memory cell as a certain level of forward bias is needed to overcome the diode barrier. Above that voltage, current flows easily through the diode. This diode barrier prevents accidental switching of the memory element. It is further desirable that the diode be “leaky,” that is, that it allow a small amount of conduction when reverse biased to allow a trickle current for reading the memory cell state.
- For the purpose of this disclosure, an integrated programmable conductor memory cell and diode device is defined as a device that incorporates both a programmable conductor memory cell and a diode so that they function together, without intervening electrical devices or lines, although layers such as optional diffusion barriers (described below) can intervene. Several embodiments are discussed comprising various configurations wherein a programmable conductor memory cell and diode elements are arranged to perform this function.
- The aforementioned needs are satisfied by the preferred embodiments of the present invention, which provide integrated programmable conductor memory cells and diode devices and methods for making the same. The advantages of the embodiments will become more fully apparent from the following description taken in conjunction with the accompanying drawings.
- Reference will now be made to the drawings wherein like numerals refer to like parts throughout. The figures have not been drawn to scale.
- A programmable conductor memory element comprises a glass electroltyte element, such as a chalcogenide glass element with metal ions mixed or dissolved therein, which is capable of forming a conductive pathway along or through the glass element under the influence of an applied voltage. The extent of the conductive pathway depends upon applied voltage and time; the higher the voltage, the faster the growth rate; and the longer the time, the greater the extent of the conductive pathway. The conductive pathway stops growing when the voltage is removed. The conductive pathway shrinks, re-dissolving metal ions into the cell body, when the voltage polarity is reversed.
-
FIG. 1 is a cross-section drawing showing a structure for a portion of a memory array from which many embodiments of the current invention can be constructed. Abottom conducting line 10 overlies asubstrate 8. Thesubstrate 8 may be a simple silicon wafer or it may contain up to several layers of integrated circuit devices and insulating layers; typically, an insulating layer intervenes between the conductingline 10 of a cross-point array and a lower semiconductor layer (e.g., top portion of a silicon wafer or an epitaxial layer thereover). Thebottom conducting line 10 extends from side to side in the plane of the page and continues on past the edges of the page. For the memory array, there are a series of conducting lines parallel to the one 10 shown lying over thesubstrate 8. Thebottom conducting line 10 may comprise any conducting material suitable for integrated circuit manufacture, such as aluminum, copper, or combinations thereof. Preferably, thebottom conducting line 10 comprises tungsten and acts as a bottom electrode for devices that will be fabricated over and in contact with theline 10. In one arrangement, an additional layer (not shown) comprising a diffusion barrier, preferably tungsten or tungsten nitride, is deposited over thebottom conducting line 10. - A layer of an insulating
material 12 has been deposited over thebottom conducting line 10. Preferably, the insulatinglayer 12 has a thickness between about 25 nm and 150 nm, more preferably between about 35 nm and 75 nm, most preferably, between about 40 nm and 60 nm. The insulatingmaterial 12 may be any insulating material that does not interact adversely with the materials used in the programmable conductor memory cell and that has enough structural integrity to support a cell formed in a via therein. Suitable materials include oxides and nitrides. Preferably, the insulatinglayer 12 comprises silicon nitride. Using standard techniques, an array of vias is patterned and etched into the insulatinglayer 12. The vias are positioned so that their bottom surfaces expose a bottom conducting line (or a diffusion barrier layer thereover). One via 14 that exposes thebottom conducting line 10 is shown inFIG. 1 . The width of the via 14 is preferably between about 100 nm and 180 nm, more preferably between about 120 nm and 140 nm. It is in vias such as the one shown inFIG. 1 that the programmable conductor memory cells of many preferred embodiments can be constructed. -
FIG. 2 shows the structure ofFIG. 1 after deposition of achalcogenide glass 16, preferably a germanium selenide (Ge—Se) glass, such as Ge2Se8 or Ge25Se75, to overfill the via 14. The chalcogenide glass may be deposited by any of a number of methods including sputtering and evaporating. - As shown in
FIG. 3 , thechalcogenide glass layer 16 is etched back to form a recess in the via 14, leaving only aportion 18 of chalcogenide glass remaining in the via 14. The chalcogenide glass is etched back using an isotropic etch, such as a CF4 dry etch or a tetramethyl ammonium hydroxide (TMAH) wet etch. -
FIG. 4 shows the structure ofFIG. 3 after doping alayer 20 of thechalcogenide glass portion 18 in the via 14 to a predetermined depth. In one embodiment, the depth of the dopedlayer 20 is between about 10 nm and 20 nm. Preferably, doping comprises processing at a temperature less than about 340° C. and to a concentration of between about 0.1 atomic % and 1.0 atomic %. More preferably, doping comprises ion implantation with a species such as bismuth or lead. In the illustrated embodiment, the ion implantation is performed at an energy between about 20 keV and 30 keV at a dose between about 1×1013 atoms/cm2 and 1×1014 atoms/cm2. - Germanium-selenium or germanium selenide (also referred to as “Ge—Se” herein) is a p-type semiconductor. Doping germanium selenide with bismuth or lead changes the conductivity from p-type to n-type. Thus in the structure of
FIG. 4 , the bottom, undopedgermanium selenide portion 18 and the dopedlayer 20 have opposite conductivity types and comprise a p-n junction diode. - In
FIG. 5 , anotherchalcogenide glass layer 22 has been deposited, overfilling the via. Thislayer 22 forms a programmable conductor memory cell and preferably comprises a germanium selenide glass, such as Ge2Se8 or Ge25Se75, with a conductive material, such as metal ions, preferably silver ions, mixed or dissolved therein. In one embodiment, thelayer 22 is formed by co-sputtering Ge—Se glass, such as from a pressed powder target, and silver. In other embodiments the Ge—Se glass may be deposited first and then the silver ions diffused therein, such as by photodissolution, as is known in the art of programmable conductor memory cell fabrication. Preferably, the concentration of silver in the chalcogenide glass memory element is between about 20 atomic % and 32 atomic %, more preferably, between about 29 atomic % and 31 atomic %. The skilled artisan can, however, arrive at a desired ratio within or outside these ranges through routine experimentation. - There are two illustrated embodiments for completing the integrated programmable conductor memory cell and diode device as described thus far. One embodiment is shown in
FIGS. 6A-6B . The other is shown inFIGS. 7A-7C . - In
FIG. 6A , the structure ofFIG. 5 has been planarized, leaving a programmable conductor chalcogenideglass memory element 24 with metal ions mixed or dissolved therein filling the recess in the via and level with the top surface of the insulatinglayer 12. A layer of a conducting material, preferably from Group IB or Group IIB, more preferably, silver, has been deposited over thechalcogenide glass element 24 and the insulatinglayer 12. Preferably, the thickness of the conducting layer is between about 50 nm and 100 nm. The conducting layer has been patterned and etched using standard methods to form atop electrode 26 for the integrated programmable conductor memory cell and diode device. In one aspect of the invention, a diffusion barrier (not shown), such as tungsten nitride, is deposited over thechalcogenide glass element 24 before forming thetop electrode 26. A diffusion barrier may also be deposited over thetop electrode 26. Another possibility is that thetop electrode 26 is a multi-layered structure that includes a diffusion barrier layer as one of its components. - In
FIG. 6B , another conducting layer has been deposited, patterned and etched to form atop conducting line 28 extending into and out of the plane of the paper. Preferably thetop conducting line 28 comprises tungsten and connects a row of integrated programmable conductor memory cell and diode devices in the memory array. Tungsten also has the advantage of acting as a diffusion barrier for chalcogenide glass species. -
FIG. 6B is a cross-section view of an integrated programmable conductor memory cell and diode device in a via that shows the structure of an illustrated embodiment. The device comprises afirst diode element 18, having a first conductivity type, aglass electrolyte element 24 having metal ions, such as silver, therein over thefirst diode element 18 and atop electrode 26 in contact with theglass electrolyte element 24. The structure further comprises asecond diode element 20, having a second conductivity type, between thefirst diode element 18 and theglass electrolyte element 24. In the illustrated embodiment, thediode elements glass electrolyte element 24 all comprise a chalcogenide glass, such as Ge—Se glass. Thefirst diode element 18 is not intentionally doped and is naturally p-type. Thesecond diode element 20 contains an n-type dopant such as bismuth or lead. Preferably there is a diffusion barrier layer (not shown) comprising titanium between thesecond diode element 20 and theglass electrolyte element 24. Thefirst diode element 18 is in electrical contact with thebottom conducting line 10. A portion of thebottom conducting line 10 that is directly below and in electrical contact with thefirst diode element 18 forms a bottom electrode for the integrated programmable conductor memory cell and diode device. - There may also be a diffusion barrier layer (not shown) below the
first diode element 18 and a diffusion barrier layer over thechalcogenide glass element 24. In one embodiment, the thickness of the diffusion barrier layer is between about 10 nm and 40 nm. Materials for the diffusion barrier layers include titanium, tungsten and tungsten nitride. - In the second illustrated embodiment for completing the structure of
FIG. 5 , as shown inFIG. 7A , a layer of a conductingmaterial 30, preferably from Group IB or Group IIB, more preferably silver, has been deposited over thechalcogenide glass layer 22. Preferably, the thickness of the conducting layer is between about 50 nm and 100 nm. InFIG. 7B , both the conducting layer and the chalcogenide glass layer have been patterned and etched to form a programmable conductor chalcogenideglass memory element 32 with metal ions mixed or dissolved therein and anelectrode 34 for the integrated programmable conductor memory cell and diode device. - In
FIG. 7C , another conducting layer has been deposited, patterned and etched to form atop conducting line 28 extending into and out of the plane of the page. Preferably thetop conducting line 28 comprises tungsten and connects a row of integrated programmable conductor memory cell and diode devices in the memory array. -
FIG. 7C is a cross-section view of an integrated programmable conductor memory cell and diode device in a via that shows the structure of an illustrated embodiment. The device comprises afirst diode element 18, having a first conductivity type, aglass electrolyte element 32 having metal ions, such as silver, mixed or dissolved therein over thefirst diode element 18 and atop electrode 34 in contact with theglass electrolyte element 32. The structure further comprises asecond diode element 20, having a second conductivity type, between thefirst diode element 18 and theglass electrolyte element 32. In one embodiment, thediode elements glass electrolyte element 32 all comprise a chalcogenide glass, such as Ge—Se glass. Thefirst diode element 18 is not intentionally doped, and is naturally p-type. Thesecond diode element 20 contains an n-type dopant such as bismuth or lead. Preferably there is a diffusion barrier layer (not shown) comprising titanium between thesecond diode element 20 and theglass electrolyte element 24. - There may also be a diffusion barrier layer (not shown) below the
first diode element 18 and a diffusion barrier layer over thechalcogenide glass element 32. In one embodiment, the thickness of the diffusion barrier layer is between about 10 nm and 40 nm. Materials for the diffusion barrier layers include titanium, tungsten and tungsten nitride. - In another embodiment of the current invention and with reference again to
FIG. 4 , the entire thickness of thechalcogenide glass portion 18 is doped. This embodiment is shown inFIG. 8 . The dopedchalcogenide glass layer 36 extends down to thebottom conducting line 10 or a diffusion barrier layer thereover (not shown) and forms the first diode element. Hereinafter, processing proceeds much as described for the embodiment inFIGS. 5, 6A and 6B. - Another chalcogenide glass layer is deposited, overfilling the via. The structure is planarized, leaving the
chalcogenide glass layer 38 with metal ions therein filling the recess in the via and level with the top surface of the insulatinglayer 12. Thislayer 38 functions both as the second diode element in contact with thefirst diode element 36 and as the programmable conductor memory element and preferably comprises a germanium selenide glass, such as Ge2Se8 or Ge25Se75, with a conductive material, such as metal ions, preferably silver ions, mixed or dissolved therein. A layer of a conducting material, preferably from Group IB or Group IIB, more preferably, silver, is deposited over thechalcogenide glass element 38 and the insulatinglayer 12. Preferably, the thickness of the conducting layer is between about 50 nm and 100 nm. Using standard methods, the conducting layer is patterned and etched to form atop electrode 26 for the integrated programmable conductor memory cell and diode device. - In one aspect of the invention, a diffusion barrier (not shown), such as tungsten nitride, is deposited over the
chalcogenide glass element 38 before forming thetop electrode 26. Alternatively, a diffusion barrier may be deposited over thetop electrode 26. Another possibility is that thetop electrode 26 is a multi-layered structure that includes a diffusion barrier layer as one of its components. A second conducting layer is deposited, patterned and etched to form atop conducting line 28 extending into and out of the plane of the page. Preferably thetop conducting line 28 comprises tungsten and connects a row of integrated programmable conductor memory cell and diode devices in the memory array. Tungsten also has the advantage of acting as a diffusion barrier for chalcogenide glass species. -
FIG. 8 is a cross-section view of an integrated programmable conductor memory cell and diode device in a via that shows the structure of an illustrated embodiment. The integrated PCRAM (memory and diode device) 36, 38 is formed in a via in an insulatinglayer 12, preferably silicon nitride. A conductingline 10 comprising a metal such as tungsten, extends along the bottom of the via and off the edges of the page. There may be first diffusion barrier layer (not shown) between the conductingline 10 and the first layer ofchalcogenide glass 36. - The first layer of
chalcogenide glass 36 has n-type doping from a dopant such as bismuth or lead. A second layer ofchalcogenide glass 38, infused with silver, is in contact with the first layer ofchalcogenide glass 36. In one arrangement, the chalcogenide glass is Ge2Se8 or Ge25Se75. The twolayers second layer 38 functions also as a programmable conductor memory element. Atop electrode layer 26 lies over the secondchalcogenide glass layer 38 and may comprise silver. A conductingline 28, extending into and out of the page is in contact with theelectrode 26. In one aspect of the invention, the conductingline 28 comprises tungsten and acts also as a diffusion barrier. In another aspect of the invention, a separate diffusion barrier layer (not shown) is used either below or above theelectrode 26. Another embodiment of the invention can be described starting with the structure ofFIG. 1 . As discussed above, abottom conducting line 10 overlies asubstrate 8. Using standard techniques, an array of vias is patterned and etched into the insulatinglayer 12. One via 14 is shown inFIG. 1 . It is in this via that the programmable conductor memory cell of this embodiment will be constructed. - With reference to
FIG. 9 , a layer oftungsten silicide 40 is deposited at the bottom of the via. Afirst diode element 42, preferably comprising a doped polysilicon layer having a first type conductivity, is deposited over thetungsten silicide layer 40. Asecond diode element 44, preferably comprising a doped polysilicon layer having a second type conductivity, opposite to the first type conductivity, is deposited over thefirst diode element 42. The twopolysilicon layers - A
diffusion barrier layer 46, preferably comprising tungsten nitride, is deposited over thesecond diode element 44. Achalcogenide glass element 48, preferably a germanium selenide glass with metal ions, preferably silver ions, mixed or dissolved therein, is formed by depositing the glass over thediffusion barrier layer 46 and then planarizing the glass layer to make it level with the top surface of the insulatinglayer 12. A layer of a conducting material, preferably from Group IB or Group IIB, more preferably, silver, has been deposited over thechalcogenide glass element 48 and the insulatinglayer 12. Preferably, the thickness of the conducting layer is between about 50 nm and 100 nm. The conducting layer has been patterned and etched using standard methods to form atop electrode 26 for the integrated programmable conductor memory cell and polysilicon diode device. Preferably a diffusion barrier (not shown), more preferably, tungsten nitride, is deposited over thechalcogenide glass element 48 before forming thetop electrode 26. Finally, although not shown inFIG. 9 , a conducting line may be provided as described above with reference toFIGS. 6B and 7C . -
FIG. 9 is a cross-section view of an integrated programmable conductor memory cell and diode device that shows the structure of an illustrated embodiment. Thefirst polysilicon layer 42, having a first conductivity type doping, lies in a via in an insulatinglayer 12. There is asecond polysilicon layer 44, having a second conductivity type doping, opposite to the first conductivity type, between thefirst polysilicon layer 42 and adiffusion barrier layer 46. For example, thefirst polysilicon layer 42 may have p-type doping, and thesecond polysilicon layer 44 may have n-type doping. There is a layer ofgermanium selenide glass 48, containing metal ions, over thediffusion barrier layer 46. There is atop electrode 26 over thegermanium selenide glass 48. Thetop electrode 26 may comprise both a conducting layer and a diffusion barrier layer. - Another aspect of the invention can be described with reference to
FIG. 10 . Asilicon substrate 8 is shown with aregion 52 doped to have a first type conductivity, preferaby p+. Theregion 52 forms the first diode element. - A layer of an insulating
material 12 has been deposited over thesubstrate 8. Preferably the insulatinglayer 12 has a thickness between about 50 nm and 150 nm, more preferably between about 95 nm and 105 nm. The insulatingmaterial 12 may be any insulating material that does not interact adversely with the materials used in the programmable conductor memory cell or in the diode and that has enough structural integrity to support a cell formed in a via therein. Suitable materials include oxides and nitrides. Preferably the insulatinglayer 12 comprises silicon nitride. Using standard techniques, an array of vias is patterned and etched into the insulatinglayer 12. Two such vias, containing integrated programmable conductor memory cell and diode devices are shown inFIG. 10 . - A
polysilicon layer 54, having a second conductivity type, preferably n+, opposite to the first conductivity type of the dopedregion 52, is deposited into the via in contact with the dopedregion 52 of thesubstrate 8.Polysilicon layer 54 forms the second diode elements and, together with dopedregion 52, forms p-n junction diodes. - Diffusion barrier layers 56, preferably comprising tungsten nitride, are deposited over the
second diode elements 54.Chalcogenide glass elements 58, preferably germanium selenide glass with metal ions, preferably silver ions, mixed or dissolved therein, are formed by depositing the glass over the diffusion barrier layers 56 and then planarizing the glass to make it level with the top surface of the insulatinglayer 12. A layer of a conducting material, preferably from Group IB or Group IIB, more preferably, silver, is deposited over thechalcogenide glass elements 58 and the insulatinglayer 12. Preferably, the thickness of the conducting layer is between about 50 nm and 100 nm. The conducting layer is patterned and etched using standard methods to formtop electrodes 26 for the integrated programmable conductor memory cell andpolysilicon diode devices chalcogenide glass elements 58 before forming thetop electrodes 26. - A conducting
line 28, extending into and out of the page, is in contact with theelectrode 26. Aconductive plug 60, preferably comprising polysilicon or a metal such as tungsten, makes contact to the dopedsilicon substrate region 52 and to conductingline 62, thus providing electrical connections for the integrated programmable conductor memory cell and diode device ofFIG. 10 . Conductingline 62 is insulated from conductingline 28 bylayer 64, preferably comprising BPSG (borophosphosilicate glass). - Another aspect of the invention can be described with reference to
FIG. 11 . Asilicon substrate 8 is shown with aregion 52 doped to have a first conductivity type, preferably p+. Theregion 52 forms the first diode elements for integrated programmable conductor memory cell and diode devices. - A layer of polysilicon with conductivity, preferably n+, opposite to the conductivity of the doped
region 52 of thesubstrate 8 is deposited. The polysilicon layer is patterned and etched to form thesecond diode elements 54. Preferably, a diffusion barrier layer, such as tungsten, tungsten nitride or titanium, is deposited onto the polysilicon layer and then patterned and etched with the polysilicon layer, thus forming diffusion barrier layers 56 over thesecond diode elements 54. - A layer of
material 64, preferably silicon nitride, is deposited conformally onto thesecond diode elements 54 and diffusion barrier layers 56 to act as an etch stop for a subsequent chemical-mechanical planarization step. An insulatinglayer 66, preferably comprising silicon oxide formed from TEOS, is deposited to a thickness that at least covers the top surface oflayer 64. Chemical-mechanical planarization is performed until the top portions oflayer 64 are exposed to make a flat top surface forsilicon oxide layer 66. The exposed portions oflayer 64 are patterned and etched to expose at least a portion of a top surface of thediffusion barrier layer 56. - A layer of insulating
material 12, preferably silicon nitride, is deposited over thesilicon oxide layer 66. Thelayer 12 is patterned and etched to form vias down throughlayer 64 and ontodiffusion barrier layer 56. A chalcogenide glass layer is deposited, overfilling the vias. The chalcogenide glass forms the programmableconductor memory cells 58 and preferably comprises a germanium selenide glass, such as Ge2Se8 or Ge25Se75, with a conductive material, such as metal ions, preferably silver ions, mixed or dissolved therein. In one embodiment, the glass is formed by co-sputtering Ge—Se glass, such as from a pressed powder target, and silver. In other embodiments the Ge—Se glass may be deposited first and then the silver ions diffused therein, such as by photodissolution, as is known in the art of programmable conductor memory cell fabrication. Preferably, the concentration of silver in the chalcogenide glass memory element is between about 20 atomic % and 36 atomic %, more preferably, between about 29 atomic % and 32 atomic %. - A layer of a conducting
material 27, preferably from Group IB or Group IIB, more preferably silver, is deposited over thechalcogenide glass layer 58. Preferably, the thickness of the conducting layer is between about 50 nm and 100 nm. Both theconducting layer 27 and thechalcogenide glass layer 58 are patterned and etched to form programmable conductor chalcogenideglass memory elements 58 with metal ions mixed or dissolved therein and electrodes and conductinglines 27 for thememory cells 58. - A layer of insulating
material 64, preferably comprising BPSG (borophosphosilicate glass), is deposited over the conductinglines 27 and planarized. A via is etched through insulatinglayers region 52 of thesubstrate 8. The via is filled with conducting material, preferably polysilicon or a metal such as tungsten, thus forming aconductive plug 60 that makes contact to the dopedsilicon substrate region 52. A conductive line, preferably comprising aluminum or copper, is formed over theBPSG 64 and makes contact with theconductive plug 60, and thus to the diodes in the integrated programmable conductor memory cell and diode devices. - This invention has been described herein in considerable detail to provide those skilled in the art with the information needed to apply the novel principles and to construct and use such specialized components as are required. However, it is to be understood that the invention can be carried out by specifically different equipment and devices, and that various modifications, both as to the structure and as to the method of fabricating the structure, can be accomplished without departing from the scope of the invention itself.
Claims (15)
1-84. (canceled)
85. A method of fabricating a memory device, the method comprising:
forming a first chalcogenide;
forming a resistance variable memory element over the first chalcogenide layer, forming the resistance variable element comprising:
forming a second chalcogenide layer and doping the second chalcogenide glass with a metal, wherein the first and second chalcogenide layers form a diode.
86. The method of claim 85 , further comprising forming a silicide layer below the first layer.
87. The method of claim 86 , further comprising forming a barrier layer over the resistance variable memory element.
88. The method of claim 85 , wherein doping the chalcogenide glass layer comprises doping the chalcogenide glass layer with silver.
89. The method of claim 85 , further comprising forming a via within an insulating layer, wherein at least the first layer and the resistance variable memory element are formed within the via.
90. The method of claim 85 , further comprising forming an electrode over the metal doped chalcogenide glass layer.
91. The method of claim 85 , further comprising forming an electrode below the first chalcogenide layer.
92. A method of forming a memory device, the method comprising:
forming a diode;
forming a barrier layer over the diode;
forming an insulating layer over the barrier layer;
forming a via within the insulating layer to expose a surface of the barrier layer;
forming a chalcogenide layer in contact with the barrier layer;
doping the chalcogenide layer with a metal.
93. The method of claim 92 , wherein the diode is a polysilicon diode.
94. The method of claim 93 , wherein the diode comprises a region of a fist conductivity type within a substrate and a polysilicon layer of a second conductivity type over the region of the first conductivity type.
95. The method of claim 94 , further comprising forming a conductive plug in contact with the region of the first conductivity type.
96. The method of claim 92 , further comprising forming an electrode over the chalcogenide layer.
97. The method of claim 92 , further comprising forming a silicide layer below the diode.
98. The method of claim 92 , wherein doping the chalcogenide layer with a metal comprises doping the chalcogenide layer with silver.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/476,763 US20060243973A1 (en) | 2002-04-10 | 2006-06-29 | Thin film diode integrated with chalcogenide memory cell |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/121,794 US6855975B2 (en) | 2002-04-10 | 2002-04-10 | Thin film diode integrated with chalcogenide memory cell |
US11/003,733 US7112484B2 (en) | 2002-04-10 | 2004-12-06 | Thin film diode integrated with chalcogenide memory cell |
US11/476,763 US20060243973A1 (en) | 2002-04-10 | 2006-06-29 | Thin film diode integrated with chalcogenide memory cell |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/003,733 Continuation US7112484B2 (en) | 2002-04-10 | 2004-12-06 | Thin film diode integrated with chalcogenide memory cell |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060243973A1 true US20060243973A1 (en) | 2006-11-02 |
Family
ID=28790405
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/121,794 Expired - Lifetime US6855975B2 (en) | 2002-04-10 | 2002-04-10 | Thin film diode integrated with chalcogenide memory cell |
US11/003,733 Expired - Lifetime US7112484B2 (en) | 2002-04-10 | 2004-12-06 | Thin film diode integrated with chalcogenide memory cell |
US11/476,763 Abandoned US20060243973A1 (en) | 2002-04-10 | 2006-06-29 | Thin film diode integrated with chalcogenide memory cell |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/121,794 Expired - Lifetime US6855975B2 (en) | 2002-04-10 | 2002-04-10 | Thin film diode integrated with chalcogenide memory cell |
US11/003,733 Expired - Lifetime US7112484B2 (en) | 2002-04-10 | 2004-12-06 | Thin film diode integrated with chalcogenide memory cell |
Country Status (3)
Country | Link |
---|---|
US (3) | US6855975B2 (en) |
AU (1) | AU2003231999A1 (en) |
WO (1) | WO2003088251A2 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100779099B1 (en) | 2006-08-29 | 2007-11-27 | 한국전자통신연구원 | Fabrication method for phase-change memory device having gst chalcogenide pattern |
KR100887058B1 (en) | 2007-09-06 | 2009-03-04 | 주식회사 하이닉스반도체 | Manufacturing method of phase change memory device and operating method thereof |
KR100909537B1 (en) | 2007-09-07 | 2009-07-27 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method thereof |
US20100200830A1 (en) * | 2009-02-06 | 2010-08-12 | Micron Technology, Inc. | Memory device having self-aligned cell structure |
US20100302842A1 (en) * | 2009-06-02 | 2010-12-02 | Elpida Memory, Inc. | Semiconductor memory device, manufacturing method thereof, data processing system, and data processing device |
US20130175494A1 (en) * | 2012-01-11 | 2013-07-11 | Micron Technology, Inc. | Memory cells including top electrodes comprising metal silicide, apparatuses including such cells, and related methods |
US9864138B2 (en) | 2015-01-05 | 2018-01-09 | The Research Foundation For The State University Of New York | Integrated photonics including germanium |
US10698156B2 (en) | 2017-04-27 | 2020-06-30 | The Research Foundation For The State University Of New York | Wafer scale bonded active photonics interposer |
US10816724B2 (en) | 2018-04-05 | 2020-10-27 | The Research Foundation For The State University Of New York | Fabricating photonics structure light signal transmission regions |
US10877300B2 (en) | 2018-04-04 | 2020-12-29 | The Research Foundation For The State University Of New York | Heterogeneous structure on an integrated photonics platform |
US10976491B2 (en) | 2016-11-23 | 2021-04-13 | The Research Foundation For The State University Of New York | Photonics interposer optoelectronics |
US11029466B2 (en) | 2018-11-21 | 2021-06-08 | The Research Foundation For The State University Of New York | Photonics structure with integrated laser |
US11550099B2 (en) | 2018-11-21 | 2023-01-10 | The Research Foundation For The State University Of New York | Photonics optoelectrical system |
Families Citing this family (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6801450B2 (en) * | 2002-05-22 | 2004-10-05 | Hewlett-Packard Development Company, L.P. | Memory cell isolation |
US7067862B2 (en) * | 2002-08-02 | 2006-06-27 | Unity Semiconductor Corporation | Conductive memory device with conductive oxide electrodes |
US6864521B2 (en) * | 2002-08-29 | 2005-03-08 | Micron Technology, Inc. | Method to control silver concentration in a resistance variable memory element |
US6815266B2 (en) * | 2002-12-30 | 2004-11-09 | Bae Systems Information And Electronic Systems Integration, Inc. | Method for manufacturing sidewall contacts for a chalcogenide memory device |
US7425735B2 (en) * | 2003-02-24 | 2008-09-16 | Samsung Electronics Co., Ltd. | Multi-layer phase-changeable memory devices |
KR100533958B1 (en) * | 2004-01-05 | 2005-12-06 | 삼성전자주식회사 | Phase-change memory device and method of manufacturing the same |
DE102004014487A1 (en) * | 2004-03-24 | 2005-11-17 | Infineon Technologies Ag | Memory device with embedded in insulating material, active material |
DE102004020575B3 (en) * | 2004-04-27 | 2005-08-25 | Infineon Technologies Ag | Semiconductor memory in crosspoint architecture, includes chalcogenide glass forming memory cell with pn junction to bit line and electrode forming memory cell with word line |
WO2005124788A2 (en) * | 2004-06-14 | 2005-12-29 | Axon Technologies Corporation | Nanoscale programmable structures and methods of forming and using same |
KR100642634B1 (en) * | 2004-06-29 | 2006-11-10 | 삼성전자주식회사 | PRAMs Having A Gate Phase-Change Layer Pattern And Methods Of Forming The Same |
KR100653701B1 (en) * | 2004-08-20 | 2006-12-04 | 삼성전자주식회사 | Method of forming a small via structure in a semiconductor device and method of fabricating phase change memory device using the same |
EP1675183A1 (en) * | 2004-12-21 | 2006-06-28 | STMicroelectronics S.r.l. | Phase change memory cell with diode junction selection and manufacturing method thereof |
FR2880177B1 (en) * | 2004-12-23 | 2007-05-18 | Commissariat Energie Atomique | MEMORY PMC HAVING IMPROVED RETENTION TIME AND WRITING SPEED |
DE102005001253A1 (en) * | 2005-01-11 | 2006-07-20 | Infineon Technologies Ag | Memory cell arrangement for solid electrolyte memory cells has lower electrode and upper electrode and activated solid electrolyte material area between them as memory material area and whole of material area is coherently designed |
KR100682939B1 (en) * | 2005-03-16 | 2007-02-15 | 삼성전자주식회사 | Semiconductor memory device with three dimensional solid electrolyte structure and manufacturing method thereof |
US7709289B2 (en) * | 2005-04-22 | 2010-05-04 | Micron Technology, Inc. | Memory elements having patterned electrodes and method of forming the same |
US7427770B2 (en) * | 2005-04-22 | 2008-09-23 | Micron Technology, Inc. | Memory array for increased bit density |
US7812404B2 (en) | 2005-05-09 | 2010-10-12 | Sandisk 3D Llc | Nonvolatile memory cell comprising a diode and a resistance-switching material |
KR100650753B1 (en) * | 2005-06-10 | 2006-11-27 | 주식회사 하이닉스반도체 | Phase change ram device and method of manufacturing the same |
US20070007579A1 (en) * | 2005-07-11 | 2007-01-11 | Matrix Semiconductor, Inc. | Memory cell comprising a thin film three-terminal switching device having a metal source and /or drain region |
US20070034905A1 (en) * | 2005-08-09 | 2007-02-15 | Micron Technology, Inc. | Phase-change memory device and its methods of formation |
US20070045606A1 (en) * | 2005-08-30 | 2007-03-01 | Michele Magistretti | Shaping a phase change layer in a phase change memory cell |
KR100675289B1 (en) * | 2005-11-14 | 2007-01-29 | 삼성전자주식회사 | Phase changeable memory cell array region and methods of forming the same |
KR100745761B1 (en) * | 2006-02-07 | 2007-08-02 | 삼성전자주식회사 | Phase change ram comprising resistive element having diode function and methods of manufacturing and operating the same |
US7875871B2 (en) | 2006-03-31 | 2011-01-25 | Sandisk 3D Llc | Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride |
KR100809597B1 (en) * | 2006-04-06 | 2008-03-04 | 삼성전자주식회사 | Method for forming minute pattern and method for forming semiconductor memory device using the same |
KR100729361B1 (en) * | 2006-04-24 | 2007-06-15 | 삼성전자주식회사 | Gap fill method and method for forming semiconductor memory device using the same |
KR100748557B1 (en) * | 2006-05-26 | 2007-08-10 | 삼성전자주식회사 | Phase-change memory device |
US7423282B2 (en) * | 2006-07-06 | 2008-09-09 | Infineon Technologies Ag | Memory structure and method of manufacture |
US7560723B2 (en) * | 2006-08-29 | 2009-07-14 | Micron Technology, Inc. | Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication |
KR100795350B1 (en) * | 2006-11-24 | 2008-01-17 | 삼성전자주식회사 | Non-volatile memory device, method for manufacturing the same and method for operating the same |
KR100846506B1 (en) * | 2006-12-19 | 2008-07-17 | 삼성전자주식회사 | Phase change random access memory comprising PN diode and methods of manufacturing and operating the same |
US20080164453A1 (en) * | 2007-01-07 | 2008-07-10 | Breitwisch Matthew J | Uniform critical dimension size pore for pcram application |
US7382647B1 (en) * | 2007-02-27 | 2008-06-03 | International Business Machines Corporation | Rectifying element for a crosspoint based memory array architecture |
KR20080095683A (en) * | 2007-04-25 | 2008-10-29 | 삼성전자주식회사 | Phase change memory devices and method for forming thereof |
US7929335B2 (en) * | 2007-06-11 | 2011-04-19 | International Business Machines Corporation | Use of a symmetric resistive memory material as a diode to drive symmetric or asymmetric resistive memory |
KR100881055B1 (en) * | 2007-06-20 | 2009-01-30 | 삼성전자주식회사 | Phase-change memory unit, method of forming the phase-change memory unit, phase-change memory device having the phase-change memory unit and method of manufacturing the phase-change memory device |
US20090104756A1 (en) * | 2007-06-29 | 2009-04-23 | Tanmay Kumar | Method to form a rewriteable memory cell comprising a diode and a resistivity-switching grown oxide |
US7824956B2 (en) | 2007-06-29 | 2010-11-02 | Sandisk 3D Llc | Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same |
US8233308B2 (en) | 2007-06-29 | 2012-07-31 | Sandisk 3D Llc | Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same |
US7902537B2 (en) * | 2007-06-29 | 2011-03-08 | Sandisk 3D Llc | Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same |
FR2922368A1 (en) * | 2007-10-16 | 2009-04-17 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A CBRAM MEMORY HAVING IMPROVED RELIABILITY |
US8212281B2 (en) | 2008-01-16 | 2012-07-03 | Micron Technology, Inc. | 3-D and 3-D schottky diode for cross-point, variable-resistance material memories, processes of forming same, and methods of using same |
US7883931B2 (en) | 2008-02-06 | 2011-02-08 | Micron Technology, Inc. | Methods of forming memory cells, and methods of forming programmed memory cells |
US8035099B2 (en) * | 2008-02-27 | 2011-10-11 | Spansion Llc | Diode and resistive memory device structures |
US7961507B2 (en) * | 2008-03-11 | 2011-06-14 | Micron Technology, Inc. | Non-volatile memory with resistive access component |
US20090298222A1 (en) * | 2008-05-28 | 2009-12-03 | Ovonyx, Inc. | Method for manufacturing Chalcogenide devices |
US20100006961A1 (en) * | 2008-07-09 | 2010-01-14 | Analog Devices, Inc. | Recessed Germanium (Ge) Diode |
US7825479B2 (en) | 2008-08-06 | 2010-11-02 | International Business Machines Corporation | Electrical antifuse having a multi-thickness dielectric layer |
US8878153B2 (en) * | 2009-12-08 | 2014-11-04 | Nec Corporation | Variable resistance element having gradient of diffusion coefficient of ion conducting layer |
US8198124B2 (en) | 2010-01-05 | 2012-06-12 | Micron Technology, Inc. | Methods of self-aligned growth of chalcogenide memory access device |
US8284597B2 (en) | 2010-05-06 | 2012-10-09 | Macronix International Co., Ltd. | Diode memory |
US8597974B2 (en) * | 2010-07-26 | 2013-12-03 | Micron Technology, Inc. | Confined resistance variable memory cells and methods |
US10056907B1 (en) | 2011-07-29 | 2018-08-21 | Crossbar, Inc. | Field programmable gate array utilizing two-terminal non-volatile memory |
US9729155B2 (en) | 2011-07-29 | 2017-08-08 | Crossbar, Inc. | Field programmable gate array utilizing two-terminal non-volatile memory |
US8830725B2 (en) | 2011-08-15 | 2014-09-09 | International Business Machines Corporation | Low temperature BEOL compatible diode having high voltage margins for use in large arrays of electronic components |
US8853665B2 (en) | 2012-07-18 | 2014-10-07 | Micron Technology, Inc. | Semiconductor constructions, memory cells, memory arrays and methods of forming memory cells |
US8956939B2 (en) | 2013-04-29 | 2015-02-17 | Asm Ip Holding B.V. | Method of making a resistive random access memory device |
JP2014216647A (en) | 2013-04-29 | 2014-11-17 | エーエスエムアイピー ホールディング ビー.ブイ. | Method for manufacturing resistive random access memory having metal-doped resistive switching layer |
US9166159B2 (en) | 2013-05-23 | 2015-10-20 | Micron Technology, Inc. | Semiconductor constructions and methods of forming memory cells |
US9520562B2 (en) | 2013-07-19 | 2016-12-13 | Asm Ip Holding B.V. | Method of making a resistive random access memory |
US9472757B2 (en) | 2013-07-19 | 2016-10-18 | Asm Ip Holding B.V. | Method of making a resistive random access memory device |
US9425237B2 (en) | 2014-03-11 | 2016-08-23 | Crossbar, Inc. | Selector device for two-terminal memory |
US9768234B2 (en) | 2014-05-20 | 2017-09-19 | Crossbar, Inc. | Resistive memory architecture and devices |
US9633724B2 (en) | 2014-07-07 | 2017-04-25 | Crossbar, Inc. | Sensing a non-volatile memory device utilizing selector device holding characteristics |
US10211397B1 (en) * | 2014-07-07 | 2019-02-19 | Crossbar, Inc. | Threshold voltage tuning for a volatile selection device |
US10115819B2 (en) | 2015-05-29 | 2018-10-30 | Crossbar, Inc. | Recessed high voltage metal oxide semiconductor transistor for RRAM cell |
US9698201B2 (en) | 2014-07-09 | 2017-07-04 | Crossbar, Inc. | High density selector-based non volatile memory cell and fabrication |
US9685483B2 (en) | 2014-07-09 | 2017-06-20 | Crossbar, Inc. | Selector-based non-volatile cell fabrication utilizing IC-foundry compatible process |
US9460788B2 (en) | 2014-07-09 | 2016-10-04 | Crossbar, Inc. | Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor |
KR102453349B1 (en) * | 2016-02-25 | 2022-10-07 | 삼성전자주식회사 | Variable resistance memory devices and methods of manufacturing the same |
CN107481948B (en) * | 2016-06-08 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Layout structure of process window for simultaneously detecting multiple bottom contact plugs |
US10096362B1 (en) | 2017-03-24 | 2018-10-09 | Crossbar, Inc. | Switching block configuration bit comprising a non-volatile memory cell |
JP6719416B2 (en) * | 2017-03-30 | 2020-07-08 | 東京エレクトロン株式会社 | Recessed part filling method and processing device |
US10141503B1 (en) * | 2017-11-03 | 2018-11-27 | International Business Machines Corporation | Selective phase change material growth in high aspect ratio dielectric pores for semiconductor device fabrication |
US11791005B2 (en) | 2020-06-03 | 2023-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and method of operating same |
Citations (92)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3961314A (en) * | 1974-03-05 | 1976-06-01 | Energy Conversion Devices, Inc. | Structure and method for producing an image |
US3966317A (en) * | 1974-04-08 | 1976-06-29 | Energy Conversion Devices, Inc. | Dry process production of archival microform records from hard copy |
US4267261A (en) * | 1971-07-15 | 1981-05-12 | Energy Conversion Devices, Inc. | Method for full format imaging |
US4269935A (en) * | 1979-07-13 | 1981-05-26 | Ionomet Company, Inc. | Process of doping silver image in chalcogenide layer |
US4312938A (en) * | 1979-07-06 | 1982-01-26 | Drexler Technology Corporation | Method for making a broadband reflective laser recording and data storage medium with absorptive underlayer |
US4316946A (en) * | 1979-12-03 | 1982-02-23 | Ionomet Company, Inc. | Surface sensitized chalcogenide product and process for making and using the same |
US4320191A (en) * | 1978-11-07 | 1982-03-16 | Nippon Telegraph & Telephone Public Corporation | Pattern-forming process |
US4499557A (en) * | 1980-10-28 | 1985-02-12 | Energy Conversion Devices, Inc. | Programmable cell for use in programmable electronic arrays |
US4637895A (en) * | 1985-04-01 | 1987-01-20 | Energy Conversion Devices, Inc. | Gas mixtures for the vapor deposition of semiconductor material |
US4646266A (en) * | 1984-09-28 | 1987-02-24 | Energy Conversion Devices, Inc. | Programmable semiconductor structures and methods for using the same |
US4664939A (en) * | 1985-04-01 | 1987-05-12 | Energy Conversion Devices, Inc. | Vertical semiconductor processor |
US4668968A (en) * | 1984-05-14 | 1987-05-26 | Energy Conversion Devices, Inc. | Integrated circuit compatible thin film field effect transistor and method of making same |
US4670763A (en) * | 1984-05-14 | 1987-06-02 | Energy Conversion Devices, Inc. | Thin film field effect transistor |
US4671618A (en) * | 1986-05-22 | 1987-06-09 | Wu Bao Gang | Liquid crystalline-plastic material having submillisecond switch times and extended memory |
US4673957A (en) * | 1984-05-14 | 1987-06-16 | Energy Conversion Devices, Inc. | Integrated circuit compatible thin film field effect transistor and method of making same |
US4728406A (en) * | 1986-08-18 | 1988-03-01 | Energy Conversion Devices, Inc. | Method for plasma - coating a semiconductor body |
US4737379A (en) * | 1982-09-24 | 1988-04-12 | Energy Conversion Devices, Inc. | Plasma deposited coatings, and low temperature plasma method of making same |
US4795657A (en) * | 1984-04-13 | 1989-01-03 | Energy Conversion Devices, Inc. | Method of fabricating a programmable array |
US4800526A (en) * | 1987-05-08 | 1989-01-24 | Gaf Corporation | Memory element for information storage and retrieval system and associated process |
US4809044A (en) * | 1986-08-22 | 1989-02-28 | Energy Conversion Devices, Inc. | Thin film overvoltage protection devices |
US4818717A (en) * | 1986-06-27 | 1989-04-04 | Energy Conversion Devices, Inc. | Method for making electronic matrix arrays |
US4843443A (en) * | 1984-05-14 | 1989-06-27 | Energy Conversion Devices, Inc. | Thin film field effect transistor and method of making same |
US4891330A (en) * | 1987-07-27 | 1990-01-02 | Energy Conversion Devices, Inc. | Method of fabricating n-type and p-type microcrystalline semiconductor alloy material including band gap widening elements |
US5177567A (en) * | 1991-07-19 | 1993-01-05 | Energy Conversion Devices, Inc. | Thin-film structure for chalcogenide electrical switching devices and process therefor |
US5219788A (en) * | 1991-02-25 | 1993-06-15 | Ibm Corporation | Bilayer metallization cap for photolithography |
US5296716A (en) * | 1991-01-18 | 1994-03-22 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US5315131A (en) * | 1990-11-22 | 1994-05-24 | Matsushita Electric Industrial Co., Ltd. | Electrically reprogrammable nonvolatile memory device |
US5314772A (en) * | 1990-10-09 | 1994-05-24 | Arizona Board Of Regents | High resolution, multi-layer resist for microlithography and method therefor |
US5406509A (en) * | 1991-01-18 | 1995-04-11 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US5414271A (en) * | 1991-01-18 | 1995-05-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements having improved set resistance stability |
US5500532A (en) * | 1994-08-18 | 1996-03-19 | Arizona Board Of Regents | Personal electronic dosimeter |
US5512328A (en) * | 1992-08-07 | 1996-04-30 | Hitachi, Ltd. | Method for forming a pattern and forming a thin film used in pattern formation |
US5512773A (en) * | 1993-12-23 | 1996-04-30 | U.S. Philips Corporation | Switching element with memory provided with Schottky tunnelling barrier |
US5591501A (en) * | 1995-12-20 | 1997-01-07 | Energy Conversion Devices, Inc. | Optical recording medium having a plurality of discrete phase change data recording points |
US5596522A (en) * | 1991-01-18 | 1997-01-21 | Energy Conversion Devices, Inc. | Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements |
US5714768A (en) * | 1995-10-24 | 1998-02-03 | Energy Conversion Devices, Inc. | Second-layer phase change memory array on top of a logic device |
US5726083A (en) * | 1994-11-29 | 1998-03-10 | Nec Corporation | Process of fabricating dynamic random access memory device having storage capacitor low in contact resistance and small in leakage current through tantalum oxide film |
US5751012A (en) * | 1995-06-07 | 1998-05-12 | Micron Technology, Inc. | Polysilicon pillar diode for use in a non-volatile memory cell |
US5761115A (en) * | 1996-05-30 | 1998-06-02 | Axon Technologies Corporation | Programmable metallization cell structure and method of making same |
US5869843A (en) * | 1995-06-07 | 1999-02-09 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cells thereof |
US6011757A (en) * | 1998-01-27 | 2000-01-04 | Ovshinsky; Stanford R. | Optical recording media having increased erasability |
US6031287A (en) * | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US6177338B1 (en) * | 1999-02-08 | 2001-01-23 | Taiwan Semiconductor Manufacturing Company | Two step barrier process |
US6236059B1 (en) * | 1996-08-22 | 2001-05-22 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element and method of making same |
US20020000666A1 (en) * | 1998-08-31 | 2002-01-03 | Michael N. Kozicki | Self-repairing interconnections for electrical circuits |
US6339544B1 (en) * | 2000-09-29 | 2002-01-15 | Intel Corporation | Method to enhance performance of thermal resistor device |
US6348365B1 (en) * | 2001-03-02 | 2002-02-19 | Micron Technology, Inc. | PCRAM cell manufacturing |
US6350679B1 (en) * | 1999-08-03 | 2002-02-26 | Micron Technology, Inc. | Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry |
US6376284B1 (en) * | 1996-02-23 | 2002-04-23 | Micron Technology, Inc. | Method of fabricating a memory device |
US6391688B1 (en) * | 1995-06-07 | 2002-05-21 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US20030001229A1 (en) * | 2001-03-01 | 2003-01-02 | Moore John T. | Chalcogenide comprising device |
US6507061B1 (en) * | 2001-08-31 | 2003-01-14 | Intel Corporation | Multiple layer phase-change memory |
US6511862B2 (en) * | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Modified contact for programmable devices |
US6511867B2 (en) * | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Utilizing atomic layer deposition for programmable device |
US6512241B1 (en) * | 2001-12-31 | 2003-01-28 | Intel Corporation | Phase change material memory device |
US6514805B2 (en) * | 2001-06-30 | 2003-02-04 | Intel Corporation | Trench sidewall profile for device isolation |
US20030027416A1 (en) * | 2001-08-01 | 2003-02-06 | Moore John T. | Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry |
US20030032254A1 (en) * | 2000-12-08 | 2003-02-13 | Gilton Terry L. | Resistance variable device, analog memory device, and programmable memory cell |
US20030035314A1 (en) * | 1998-12-04 | 2003-02-20 | Kozicki Michael N. | Programmable microelectronic devices and methods of forming and programming same |
US20030035315A1 (en) * | 2001-04-06 | 2003-02-20 | Kozicki Michael N. | Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same |
US20030038301A1 (en) * | 2001-08-27 | 2003-02-27 | John Moore | Apparatus and method for dual cell common electrode PCRAM memory device |
US20030043631A1 (en) * | 2001-08-30 | 2003-03-06 | Gilton Terry L. | Method of retaining memory state in a programmable conductor RAM |
US20030045049A1 (en) * | 2001-08-29 | 2003-03-06 | Campbell Kristy A. | Method of forming chalcogenide comprising devices |
US20030045054A1 (en) * | 2001-08-29 | 2003-03-06 | Campbell Kristy A. | Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device |
US6531373B2 (en) * | 2000-12-27 | 2003-03-11 | Ovonyx, Inc. | Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements |
US20030048744A1 (en) * | 2001-09-01 | 2003-03-13 | Ovshinsky Stanford R. | Increased data storage in optical data storage and retrieval systems using blue lasers and/or plasmon lenses |
US20030049912A1 (en) * | 2001-08-29 | 2003-03-13 | Campbell Kristy A. | Method of forming chalcogenide comprsing devices and method of forming a programmable memory cell of memory circuitry |
US20030048519A1 (en) * | 2000-02-11 | 2003-03-13 | Kozicki Michael N. | Microelectronic photonic structure and device and method of forming the same |
US20030047772A1 (en) * | 2001-03-15 | 2003-03-13 | Jiutao Li | Agglomeration elimination for metal sputter deposition of chalcogenides |
US20030047765A1 (en) * | 2001-08-30 | 2003-03-13 | Campbell Kristy A. | Stoichiometry for chalcogenide glasses useful for memory devices and method of formation |
US6534781B2 (en) * | 2000-12-26 | 2003-03-18 | Ovonyx, Inc. | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
US6545907B1 (en) * | 2001-10-30 | 2003-04-08 | Ovonyx, Inc. | Technique and apparatus for performing write operations to a phase change material memory device |
US6545287B2 (en) * | 2001-09-07 | 2003-04-08 | Intel Corporation | Using selective deposition to form phase-change memory cells |
US20030068861A1 (en) * | 2001-08-30 | 2003-04-10 | Jiutao Li | Integrated circuit device and fabrication using metal-doped chalcogenide materials |
US6555860B2 (en) * | 2000-09-29 | 2003-04-29 | Intel Corporation | Compositionally modified resistive electrode |
US6563164B2 (en) * | 2000-09-29 | 2003-05-13 | Ovonyx, Inc. | Compositionally modified resistive electrode |
US6566700B2 (en) * | 2001-10-11 | 2003-05-20 | Ovonyx, Inc. | Carbon-containing interfacial layer for phase-change memory |
US6567293B1 (en) * | 2000-09-29 | 2003-05-20 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
US20030096497A1 (en) * | 2001-11-19 | 2003-05-22 | Micron Technology, Inc. | Electrode structure for use in an integrated circuit |
US20030095426A1 (en) * | 2001-11-20 | 2003-05-22 | Glen Hush | Complementary bit PCRAM sense amplifier and method of operation |
US6570784B2 (en) * | 2001-06-29 | 2003-05-27 | Ovonyx, Inc. | Programming a phase-change material memory |
US6569705B2 (en) * | 2000-12-21 | 2003-05-27 | Intel Corporation | Metal structure for a phase-change memory device |
US6673700B2 (en) * | 2001-06-30 | 2004-01-06 | Ovonyx, Inc. | Reduced area intersection between electrode and programming element |
US6673648B2 (en) * | 2001-11-08 | 2004-01-06 | Intel Corporation | Isolating phase change material memory cells |
US6687427B2 (en) * | 2000-12-29 | 2004-02-03 | Intel Corporation | Optic switch |
US6690026B2 (en) * | 2001-09-28 | 2004-02-10 | Intel Corporation | Method of fabricating a three-dimensional array of active media |
US6696355B2 (en) * | 2000-12-14 | 2004-02-24 | Ovonyx, Inc. | Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory |
US20040035401A1 (en) * | 2002-08-26 | 2004-02-26 | Subramanian Ramachandran | Hydrogen powered scooter |
US6707712B2 (en) * | 2001-08-02 | 2004-03-16 | Intel Corporation | Method for reading a structural phase-change memory |
US6714954B2 (en) * | 2002-05-10 | 2004-03-30 | Energy Conversion Devices, Inc. | Methods of factoring and modular arithmetic |
US6847536B1 (en) * | 2003-07-19 | 2005-01-25 | Samsung Electronics Co., Ltd | Semiconductor memory device having structure for preventing level of boosting voltage applied to a node from dropping and method of forming the same |
US6849868B2 (en) * | 2002-03-14 | 2005-02-01 | Micron Technology, Inc. | Methods and apparatus for resistance variable material cells |
Family Cites Families (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3271591A (en) | 1963-09-20 | 1966-09-06 | Energy Conversion Devices Inc | Symmetrical current controlling device |
US3622319A (en) | 1966-10-20 | 1971-11-23 | Western Electric Co | Nonreflecting photomasks and methods of making same |
US3868651A (en) | 1970-08-13 | 1975-02-25 | Energy Conversion Devices Inc | Method and apparatus for storing and reading data in a memory having catalytic material to initiate amorphous to crystalline change in memory structure |
US3743847A (en) | 1971-06-01 | 1973-07-03 | Motorola Inc | Amorphous silicon film as a uv filter |
US4177474A (en) | 1977-05-18 | 1979-12-04 | Energy Conversion Devices, Inc. | High temperature amorphous semiconductor member and method of making the same |
DE2901303C2 (en) | 1979-01-15 | 1984-04-19 | Max Planck Gesellschaft Zur Foerderung Der Wissenschaften E.V., 3400 Goettingen | Solid ionic conductor material, its use and process for its manufacture |
US4405710A (en) | 1981-06-22 | 1983-09-20 | Cornell Research Foundation, Inc. | Ion beam exposure of (g-Gex -Se1-x) inorganic resists |
US4545111A (en) | 1983-01-18 | 1985-10-08 | Energy Conversion Devices, Inc. | Method for making, parallel preprogramming or field programming of electronic matrix arrays |
US4608296A (en) | 1983-12-06 | 1986-08-26 | Energy Conversion Devices, Inc. | Superconducting films and devices exhibiting AC to DC conversion |
US4769338A (en) | 1984-05-14 | 1988-09-06 | Energy Conversion Devices, Inc. | Thin film field effect transistor and method of making same |
US4678679A (en) | 1984-06-25 | 1987-07-07 | Energy Conversion Devices, Inc. | Continuous deposition of activated process gases |
US4710899A (en) | 1985-06-10 | 1987-12-01 | Energy Conversion Devices, Inc. | Data storage medium incorporating a transition metal for increased switching speed |
US4766471A (en) | 1986-01-23 | 1988-08-23 | Energy Conversion Devices, Inc. | Thin film electro-optical devices |
US4845533A (en) | 1986-08-22 | 1989-07-04 | Energy Conversion Devices, Inc. | Thin film electrical devices with amorphous carbon electrodes and method of making same |
US4853785A (en) | 1986-10-15 | 1989-08-01 | Energy Conversion Devices, Inc. | Electronic camera including electronic signal storage cartridge |
US4788594A (en) | 1986-10-15 | 1988-11-29 | Energy Conversion Devices, Inc. | Solid state electronic camera including thin film matrix of photosensors |
US4847674A (en) | 1987-03-10 | 1989-07-11 | Advanced Micro Devices, Inc. | High speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism |
US4775425A (en) | 1987-07-27 | 1988-10-04 | Energy Conversion Devices, Inc. | P and n-type microcrystalline semiconductor alloy material including band gap widening elements, devices utilizing same |
US4804490A (en) * | 1987-10-13 | 1989-02-14 | Energy Conversion Devices, Inc. | Method of fabricating stabilized threshold switching material |
US5272359A (en) | 1988-04-07 | 1993-12-21 | California Institute Of Technology | Reversible non-volatile switch based on a TCNQ charge transfer complex |
GB8910854D0 (en) | 1989-05-11 | 1989-06-28 | British Petroleum Co Plc | Semiconductor device |
US4920078A (en) * | 1989-06-02 | 1990-04-24 | Bell Communications Research, Inc. | Arsenic sulfide surface passivation of III-V semiconductors |
US5159661A (en) | 1990-10-05 | 1992-10-27 | Energy Conversion Devices, Inc. | Vertically interconnected parallel distributed processor |
US5330630A (en) | 1991-01-02 | 1994-07-19 | Energy Conversion Devices, Inc. | Switch with improved threshold voltage |
US5534712A (en) | 1991-01-18 | 1996-07-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements characterized by reduced current and improved thermal stability |
US5534711A (en) | 1991-01-18 | 1996-07-09 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US5335219A (en) | 1991-01-18 | 1994-08-02 | Ovshinsky Stanford R | Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements |
US5536947A (en) | 1991-01-18 | 1996-07-16 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom |
US5341328A (en) | 1991-01-18 | 1994-08-23 | Energy Conversion Devices, Inc. | Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life |
US5166758A (en) | 1991-01-18 | 1992-11-24 | Energy Conversion Devices, Inc. | Electrically erasable phase change memory |
US5128099A (en) | 1991-02-15 | 1992-07-07 | Energy Conversion Devices, Inc. | Congruent state changeable optical memory material and device |
US5359205A (en) | 1991-11-07 | 1994-10-25 | Energy Conversion Devices, Inc. | Electrically erasable memory elements characterized by reduced current and improved thermal stability |
US5238862A (en) | 1992-03-18 | 1993-08-24 | Micron Technology, Inc. | Method of forming a stacked capacitor with striated electrode |
US5350484A (en) | 1992-09-08 | 1994-09-27 | Intel Corporation | Method for the anisotropic etching of metal films in the fabrication of interconnects |
US5379250A (en) | 1993-08-20 | 1995-01-03 | Micron Semiconductor, Inc. | Zener programmable read only memory |
US5818749A (en) | 1993-08-20 | 1998-10-06 | Micron Technology, Inc. | Integrated circuit memory device |
US5543737A (en) | 1995-02-10 | 1996-08-06 | Energy Conversion Devices, Inc. | Logical operation circuit employing two-terminal chalcogenide switches |
US6420725B1 (en) | 1995-06-07 | 2002-07-16 | Micron Technology, Inc. | Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
WO1996041381A1 (en) | 1995-06-07 | 1996-12-19 | Micron Technology, Inc. | A stack/trench diode for use with a multi-state material in a non-volatile memory cell |
US5789758A (en) | 1995-06-07 | 1998-08-04 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
US5837564A (en) | 1995-11-01 | 1998-11-17 | Micron Technology, Inc. | Method for optimal crystallization to obtain high electrical performance from chalcogenides |
US5694054A (en) | 1995-11-28 | 1997-12-02 | Energy Conversion Devices, Inc. | Integrated drivers for flat panel displays employing chalcogenide logic elements |
US5687112A (en) | 1996-04-19 | 1997-11-11 | Energy Conversion Devices, Inc. | Multibit single cell memory element having tapered contact |
US5851882A (en) | 1996-05-06 | 1998-12-22 | Micron Technology, Inc. | ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask |
US5789277A (en) | 1996-07-22 | 1998-08-04 | Micron Technology, Inc. | Method of making chalogenide memory device |
US5814527A (en) | 1996-07-22 | 1998-09-29 | Micron Technology, Inc. | Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories |
US6087674A (en) | 1996-10-28 | 2000-07-11 | Energy Conversion Devices, Inc. | Memory element with memory material comprising phase-change material and dielectric material |
US5825046A (en) | 1996-10-28 | 1998-10-20 | Energy Conversion Devices, Inc. | Composite memory material comprising a mixture of phase-change memory material and dielectric material |
US5846889A (en) | 1997-03-14 | 1998-12-08 | The United States Of America As Represented By The Secretary Of The Navy | Infrared transparent selenide glasses |
US5998066A (en) | 1997-05-16 | 1999-12-07 | Aerial Imaging Corporation | Gray scale mask and depth pattern transfer technique using inorganic chalcogenide glass |
US5933365A (en) | 1997-06-19 | 1999-08-03 | Energy Conversion Devices, Inc. | Memory element with energy control mechanism |
US5912839A (en) * | 1998-06-23 | 1999-06-15 | Energy Conversion Devices, Inc. | Universal memory element and method of programming same |
US6141241A (en) | 1998-06-23 | 2000-10-31 | Energy Conversion Devices, Inc. | Universal memory element with systems employing same and apparatus and method for reading, writing and programming same |
US6072716A (en) | 1999-04-14 | 2000-06-06 | Massachusetts Institute Of Technology | Memory structures and methods of making same |
US6143604A (en) | 1999-06-04 | 2000-11-07 | Taiwan Semiconductor Manufacturing Company | Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM) |
US6818481B2 (en) * | 2001-03-07 | 2004-11-16 | Micron Technology, Inc. | Method to manufacture a buried electrode PCRAM cell |
US6847535B2 (en) * | 2002-02-20 | 2005-01-25 | Micron Technology, Inc. | Removable programmable conductor memory card and associated read/write device and method of operation |
WO2003079463A2 (en) * | 2002-03-15 | 2003-09-25 | Axon Technologies Corporation | Programmable structure, an array including the structure, and methods of forming the same |
-
2002
- 2002-04-10 US US10/121,794 patent/US6855975B2/en not_active Expired - Lifetime
-
2003
- 2003-04-10 AU AU2003231999A patent/AU2003231999A1/en not_active Withdrawn
- 2003-04-10 WO PCT/US2003/010953 patent/WO2003088251A2/en not_active Application Discontinuation
-
2004
- 2004-12-06 US US11/003,733 patent/US7112484B2/en not_active Expired - Lifetime
-
2006
- 2006-06-29 US US11/476,763 patent/US20060243973A1/en not_active Abandoned
Patent Citations (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4267261A (en) * | 1971-07-15 | 1981-05-12 | Energy Conversion Devices, Inc. | Method for full format imaging |
US3961314A (en) * | 1974-03-05 | 1976-06-01 | Energy Conversion Devices, Inc. | Structure and method for producing an image |
US3966317A (en) * | 1974-04-08 | 1976-06-29 | Energy Conversion Devices, Inc. | Dry process production of archival microform records from hard copy |
US4320191A (en) * | 1978-11-07 | 1982-03-16 | Nippon Telegraph & Telephone Public Corporation | Pattern-forming process |
US4312938A (en) * | 1979-07-06 | 1982-01-26 | Drexler Technology Corporation | Method for making a broadband reflective laser recording and data storage medium with absorptive underlayer |
US4269935A (en) * | 1979-07-13 | 1981-05-26 | Ionomet Company, Inc. | Process of doping silver image in chalcogenide layer |
US4316946A (en) * | 1979-12-03 | 1982-02-23 | Ionomet Company, Inc. | Surface sensitized chalcogenide product and process for making and using the same |
US4499557A (en) * | 1980-10-28 | 1985-02-12 | Energy Conversion Devices, Inc. | Programmable cell for use in programmable electronic arrays |
US4737379A (en) * | 1982-09-24 | 1988-04-12 | Energy Conversion Devices, Inc. | Plasma deposited coatings, and low temperature plasma method of making same |
US4795657A (en) * | 1984-04-13 | 1989-01-03 | Energy Conversion Devices, Inc. | Method of fabricating a programmable array |
US4673957A (en) * | 1984-05-14 | 1987-06-16 | Energy Conversion Devices, Inc. | Integrated circuit compatible thin film field effect transistor and method of making same |
US4670763A (en) * | 1984-05-14 | 1987-06-02 | Energy Conversion Devices, Inc. | Thin film field effect transistor |
US4668968A (en) * | 1984-05-14 | 1987-05-26 | Energy Conversion Devices, Inc. | Integrated circuit compatible thin film field effect transistor and method of making same |
US4843443A (en) * | 1984-05-14 | 1989-06-27 | Energy Conversion Devices, Inc. | Thin film field effect transistor and method of making same |
US4646266A (en) * | 1984-09-28 | 1987-02-24 | Energy Conversion Devices, Inc. | Programmable semiconductor structures and methods for using the same |
US4637895A (en) * | 1985-04-01 | 1987-01-20 | Energy Conversion Devices, Inc. | Gas mixtures for the vapor deposition of semiconductor material |
US4664939A (en) * | 1985-04-01 | 1987-05-12 | Energy Conversion Devices, Inc. | Vertical semiconductor processor |
US4671618A (en) * | 1986-05-22 | 1987-06-09 | Wu Bao Gang | Liquid crystalline-plastic material having submillisecond switch times and extended memory |
US4818717A (en) * | 1986-06-27 | 1989-04-04 | Energy Conversion Devices, Inc. | Method for making electronic matrix arrays |
US4728406A (en) * | 1986-08-18 | 1988-03-01 | Energy Conversion Devices, Inc. | Method for plasma - coating a semiconductor body |
US4809044A (en) * | 1986-08-22 | 1989-02-28 | Energy Conversion Devices, Inc. | Thin film overvoltage protection devices |
US4800526A (en) * | 1987-05-08 | 1989-01-24 | Gaf Corporation | Memory element for information storage and retrieval system and associated process |
US4891330A (en) * | 1987-07-27 | 1990-01-02 | Energy Conversion Devices, Inc. | Method of fabricating n-type and p-type microcrystalline semiconductor alloy material including band gap widening elements |
US5314772A (en) * | 1990-10-09 | 1994-05-24 | Arizona Board Of Regents | High resolution, multi-layer resist for microlithography and method therefor |
US5315131A (en) * | 1990-11-22 | 1994-05-24 | Matsushita Electric Industrial Co., Ltd. | Electrically reprogrammable nonvolatile memory device |
US5414271A (en) * | 1991-01-18 | 1995-05-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements having improved set resistance stability |
US5596522A (en) * | 1991-01-18 | 1997-01-21 | Energy Conversion Devices, Inc. | Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements |
US5296716A (en) * | 1991-01-18 | 1994-03-22 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US5406509A (en) * | 1991-01-18 | 1995-04-11 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US5219788A (en) * | 1991-02-25 | 1993-06-15 | Ibm Corporation | Bilayer metallization cap for photolithography |
US5177567A (en) * | 1991-07-19 | 1993-01-05 | Energy Conversion Devices, Inc. | Thin-film structure for chalcogenide electrical switching devices and process therefor |
US5512328A (en) * | 1992-08-07 | 1996-04-30 | Hitachi, Ltd. | Method for forming a pattern and forming a thin film used in pattern formation |
US5512773A (en) * | 1993-12-23 | 1996-04-30 | U.S. Philips Corporation | Switching element with memory provided with Schottky tunnelling barrier |
US5500532A (en) * | 1994-08-18 | 1996-03-19 | Arizona Board Of Regents | Personal electronic dosimeter |
US5726083A (en) * | 1994-11-29 | 1998-03-10 | Nec Corporation | Process of fabricating dynamic random access memory device having storage capacitor low in contact resistance and small in leakage current through tantalum oxide film |
US6391688B1 (en) * | 1995-06-07 | 2002-05-21 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US5751012A (en) * | 1995-06-07 | 1998-05-12 | Micron Technology, Inc. | Polysilicon pillar diode for use in a non-volatile memory cell |
US5869843A (en) * | 1995-06-07 | 1999-02-09 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cells thereof |
US5714768A (en) * | 1995-10-24 | 1998-02-03 | Energy Conversion Devices, Inc. | Second-layer phase change memory array on top of a logic device |
US5591501A (en) * | 1995-12-20 | 1997-01-07 | Energy Conversion Devices, Inc. | Optical recording medium having a plurality of discrete phase change data recording points |
US6376284B1 (en) * | 1996-02-23 | 2002-04-23 | Micron Technology, Inc. | Method of fabricating a memory device |
US5896312A (en) * | 1996-05-30 | 1999-04-20 | Axon Technologies Corporation | Programmable metallization cell structure and method of making same |
US5761115A (en) * | 1996-05-30 | 1998-06-02 | Axon Technologies Corporation | Programmable metallization cell structure and method of making same |
US6236059B1 (en) * | 1996-08-22 | 2001-05-22 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element and method of making same |
US6031287A (en) * | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US6011757A (en) * | 1998-01-27 | 2000-01-04 | Ovshinsky; Stanford R. | Optical recording media having increased erasability |
US20020000666A1 (en) * | 1998-08-31 | 2002-01-03 | Michael N. Kozicki | Self-repairing interconnections for electrical circuits |
US6388324B2 (en) * | 1998-08-31 | 2002-05-14 | Arizona Board Of Regents | Self-repairing interconnections for electrical circuits |
US20030035314A1 (en) * | 1998-12-04 | 2003-02-20 | Kozicki Michael N. | Programmable microelectronic devices and methods of forming and programming same |
US6177338B1 (en) * | 1999-02-08 | 2001-01-23 | Taiwan Semiconductor Manufacturing Company | Two step barrier process |
US6350679B1 (en) * | 1999-08-03 | 2002-02-26 | Micron Technology, Inc. | Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry |
US20030048519A1 (en) * | 2000-02-11 | 2003-03-13 | Kozicki Michael N. | Microelectronic photonic structure and device and method of forming the same |
US6339544B1 (en) * | 2000-09-29 | 2002-01-15 | Intel Corporation | Method to enhance performance of thermal resistor device |
US6563164B2 (en) * | 2000-09-29 | 2003-05-13 | Ovonyx, Inc. | Compositionally modified resistive electrode |
US6555860B2 (en) * | 2000-09-29 | 2003-04-29 | Intel Corporation | Compositionally modified resistive electrode |
US6567293B1 (en) * | 2000-09-29 | 2003-05-20 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
US20030032254A1 (en) * | 2000-12-08 | 2003-02-13 | Gilton Terry L. | Resistance variable device, analog memory device, and programmable memory cell |
US6696355B2 (en) * | 2000-12-14 | 2004-02-24 | Ovonyx, Inc. | Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory |
US6569705B2 (en) * | 2000-12-21 | 2003-05-27 | Intel Corporation | Metal structure for a phase-change memory device |
US6534781B2 (en) * | 2000-12-26 | 2003-03-18 | Ovonyx, Inc. | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
US6531373B2 (en) * | 2000-12-27 | 2003-03-11 | Ovonyx, Inc. | Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements |
US6687427B2 (en) * | 2000-12-29 | 2004-02-03 | Intel Corporation | Optic switch |
US20030001229A1 (en) * | 2001-03-01 | 2003-01-02 | Moore John T. | Chalcogenide comprising device |
US6348365B1 (en) * | 2001-03-02 | 2002-02-19 | Micron Technology, Inc. | PCRAM cell manufacturing |
US20030047772A1 (en) * | 2001-03-15 | 2003-03-13 | Jiutao Li | Agglomeration elimination for metal sputter deposition of chalcogenides |
US20030047773A1 (en) * | 2001-03-15 | 2003-03-13 | Jiutao Li | Agglomeration elimination for metal sputter deposition of chalcogenides |
US20030035315A1 (en) * | 2001-04-06 | 2003-02-20 | Kozicki Michael N. | Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same |
US6570784B2 (en) * | 2001-06-29 | 2003-05-27 | Ovonyx, Inc. | Programming a phase-change material memory |
US6687153B2 (en) * | 2001-06-29 | 2004-02-03 | Ovonyx, Inc. | Programming a phase-change material memory |
US6514805B2 (en) * | 2001-06-30 | 2003-02-04 | Intel Corporation | Trench sidewall profile for device isolation |
US6673700B2 (en) * | 2001-06-30 | 2004-01-06 | Ovonyx, Inc. | Reduced area intersection between electrode and programming element |
US6511867B2 (en) * | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Utilizing atomic layer deposition for programmable device |
US6511862B2 (en) * | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Modified contact for programmable devices |
US20030027416A1 (en) * | 2001-08-01 | 2003-02-06 | Moore John T. | Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry |
US6707712B2 (en) * | 2001-08-02 | 2004-03-16 | Intel Corporation | Method for reading a structural phase-change memory |
US20030038301A1 (en) * | 2001-08-27 | 2003-02-27 | John Moore | Apparatus and method for dual cell common electrode PCRAM memory device |
US6737312B2 (en) * | 2001-08-27 | 2004-05-18 | Micron Technology, Inc. | Method of fabricating dual PCRAM cells sharing a common electrode |
US20030049912A1 (en) * | 2001-08-29 | 2003-03-13 | Campbell Kristy A. | Method of forming chalcogenide comprsing devices and method of forming a programmable memory cell of memory circuitry |
US20030045054A1 (en) * | 2001-08-29 | 2003-03-06 | Campbell Kristy A. | Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device |
US20030045049A1 (en) * | 2001-08-29 | 2003-03-06 | Campbell Kristy A. | Method of forming chalcogenide comprising devices |
US20030043631A1 (en) * | 2001-08-30 | 2003-03-06 | Gilton Terry L. | Method of retaining memory state in a programmable conductor RAM |
US20030047765A1 (en) * | 2001-08-30 | 2003-03-13 | Campbell Kristy A. | Stoichiometry for chalcogenide glasses useful for memory devices and method of formation |
US20030068862A1 (en) * | 2001-08-30 | 2003-04-10 | Jiutao Li | Integrated circuit device and fabrication using metal-doped chalcogenide materials |
US20030068861A1 (en) * | 2001-08-30 | 2003-04-10 | Jiutao Li | Integrated circuit device and fabrication using metal-doped chalcogenide materials |
US6507061B1 (en) * | 2001-08-31 | 2003-01-14 | Intel Corporation | Multiple layer phase-change memory |
US6674115B2 (en) * | 2001-08-31 | 2004-01-06 | Intel Corporation | Multiple layer phrase-change memory |
US20030048744A1 (en) * | 2001-09-01 | 2003-03-13 | Ovshinsky Stanford R. | Increased data storage in optical data storage and retrieval systems using blue lasers and/or plasmon lenses |
US6545287B2 (en) * | 2001-09-07 | 2003-04-08 | Intel Corporation | Using selective deposition to form phase-change memory cells |
US6690026B2 (en) * | 2001-09-28 | 2004-02-10 | Intel Corporation | Method of fabricating a three-dimensional array of active media |
US6566700B2 (en) * | 2001-10-11 | 2003-05-20 | Ovonyx, Inc. | Carbon-containing interfacial layer for phase-change memory |
US6545907B1 (en) * | 2001-10-30 | 2003-04-08 | Ovonyx, Inc. | Technique and apparatus for performing write operations to a phase change material memory device |
US6673648B2 (en) * | 2001-11-08 | 2004-01-06 | Intel Corporation | Isolating phase change material memory cells |
US20030096497A1 (en) * | 2001-11-19 | 2003-05-22 | Micron Technology, Inc. | Electrode structure for use in an integrated circuit |
US20030095426A1 (en) * | 2001-11-20 | 2003-05-22 | Glen Hush | Complementary bit PCRAM sense amplifier and method of operation |
US6512241B1 (en) * | 2001-12-31 | 2003-01-28 | Intel Corporation | Phase change material memory device |
US6849868B2 (en) * | 2002-03-14 | 2005-02-01 | Micron Technology, Inc. | Methods and apparatus for resistance variable material cells |
US6714954B2 (en) * | 2002-05-10 | 2004-03-30 | Energy Conversion Devices, Inc. | Methods of factoring and modular arithmetic |
US20040035401A1 (en) * | 2002-08-26 | 2004-02-26 | Subramanian Ramachandran | Hydrogen powered scooter |
US6847536B1 (en) * | 2003-07-19 | 2005-01-25 | Samsung Electronics Co., Ltd | Semiconductor memory device having structure for preventing level of boosting voltage applied to a node from dropping and method of forming the same |
Cited By (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100779099B1 (en) | 2006-08-29 | 2007-11-27 | 한국전자통신연구원 | Fabrication method for phase-change memory device having gst chalcogenide pattern |
US7939365B2 (en) | 2007-09-06 | 2011-05-10 | Hynix Semiconductor Inc. | Phase change memory device, manufacturing method thereof and operating method thereof |
KR100887058B1 (en) | 2007-09-06 | 2009-03-04 | 주식회사 하이닉스반도체 | Manufacturing method of phase change memory device and operating method thereof |
US20110193046A1 (en) * | 2007-09-06 | 2011-08-11 | Hynix Semiconductor Inc. | Phase change memory device, manufacturing method thereof and operating method thereof |
KR100909537B1 (en) | 2007-09-07 | 2009-07-27 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method thereof |
US20100200830A1 (en) * | 2009-02-06 | 2010-08-12 | Micron Technology, Inc. | Memory device having self-aligned cell structure |
US8502182B2 (en) * | 2009-02-06 | 2013-08-06 | Micron Technology, Inc. | Memory device having self-aligned cell structure |
US9773839B2 (en) | 2009-02-06 | 2017-09-26 | Micron Technology, Inc. | Memory device having self-aligned cell structure |
US10276635B2 (en) | 2009-02-06 | 2019-04-30 | Micron Technology, Inc. | Memory device having self-aligned cell structure |
US20100302842A1 (en) * | 2009-06-02 | 2010-12-02 | Elpida Memory, Inc. | Semiconductor memory device, manufacturing method thereof, data processing system, and data processing device |
US20130175494A1 (en) * | 2012-01-11 | 2013-07-11 | Micron Technology, Inc. | Memory cells including top electrodes comprising metal silicide, apparatuses including such cells, and related methods |
US9048415B2 (en) * | 2012-01-11 | 2015-06-02 | Micron Technology, Inc. | Memory cells including top electrodes comprising metal silicide, apparatuses including such cells, and related methods |
US9553264B2 (en) | 2012-01-11 | 2017-01-24 | Micron Technology, Inc. | Memory cells and semiconductor structures including electrodes comprising a metal, and related methods |
US10295745B2 (en) | 2015-01-05 | 2019-05-21 | The Research Foundation For The State University Of New York | Integrated photonics including germanium |
US10571631B2 (en) | 2015-01-05 | 2020-02-25 | The Research Foundation For The State University Of New York | Integrated photonics including waveguiding material |
US11703643B2 (en) | 2015-01-05 | 2023-07-18 | The Research Foundation For The State University Of New York | Integrated photonics including waveguiding material |
US9864138B2 (en) | 2015-01-05 | 2018-01-09 | The Research Foundation For The State University Of New York | Integrated photonics including germanium |
US10830952B2 (en) | 2015-01-05 | 2020-11-10 | The Research Foundation For The State University Of New York | Integrated photonics including germanium |
US10976491B2 (en) | 2016-11-23 | 2021-04-13 | The Research Foundation For The State University Of New York | Photonics interposer optoelectronics |
US11435523B2 (en) | 2017-04-27 | 2022-09-06 | The Research Foundation For The State University Of New York | Wafer scale bonded active photonics interposer |
US10698156B2 (en) | 2017-04-27 | 2020-06-30 | The Research Foundation For The State University Of New York | Wafer scale bonded active photonics interposer |
US11841531B2 (en) | 2017-04-27 | 2023-12-12 | The Research Foundation For The State University Of New York | Wafer scale bonded active photonics interposer |
US10877300B2 (en) | 2018-04-04 | 2020-12-29 | The Research Foundation For The State University Of New York | Heterogeneous structure on an integrated photonics platform |
US11550173B2 (en) | 2018-04-04 | 2023-01-10 | The Research Foundation For The State University Of New York | Heterogeneous structure on an integrated photonics platform |
US11378739B2 (en) | 2018-04-05 | 2022-07-05 | The Research Foundation For The State University Of New York | Fabricating photonics structure light signal transmission regions |
US10816724B2 (en) | 2018-04-05 | 2020-10-27 | The Research Foundation For The State University Of New York | Fabricating photonics structure light signal transmission regions |
US11635568B2 (en) | 2018-04-05 | 2023-04-25 | The Research Foundation For The State University Of New York | Photonics light signal transmission |
US11029466B2 (en) | 2018-11-21 | 2021-06-08 | The Research Foundation For The State University Of New York | Photonics structure with integrated laser |
US11550099B2 (en) | 2018-11-21 | 2023-01-10 | The Research Foundation For The State University Of New York | Photonics optoelectrical system |
Also Published As
Publication number | Publication date |
---|---|
US6855975B2 (en) | 2005-02-15 |
AU2003231999A1 (en) | 2003-10-27 |
US20050101084A1 (en) | 2005-05-12 |
WO2003088251A2 (en) | 2003-10-23 |
US7112484B2 (en) | 2006-09-26 |
US20030193053A1 (en) | 2003-10-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6855975B2 (en) | Thin film diode integrated with chalcogenide memory cell | |
US6229157B1 (en) | Method of forming a polysilicon diode and devices incorporating such diode | |
US6838307B2 (en) | Programmable conductor memory cell structure and method therefor | |
US6825058B2 (en) | Methods of fabricating trench isolated cross-point memory array | |
US5985698A (en) | Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell | |
US6118135A (en) | Three-dimensional container diode for use with multi-state material in a non-volatile memory cell | |
US7193267B2 (en) | Cross-point resistor memory array | |
US6905937B2 (en) | Methods of fabricating a cross-point resistor memory array | |
US9698202B2 (en) | Parallel bit line three-dimensional resistive random access memory | |
US8853682B2 (en) | Methods of self-aligned growth of chalcogenide memory access device | |
US8471233B2 (en) | Semiconductor memory and method of manufacturing the same | |
US20040171208A1 (en) | Method of manufacture of programmable conductor memory | |
KR20190047884A (en) | Resistive random access memory device for 3d stack and memory array using the same and fabrication method thereof | |
CN112447716A (en) | Vertical transistor array and method of forming a vertical transistor array | |
US8791010B1 (en) | Silver interconnects for stacked non-volatile memory device and method | |
CN111584495B (en) | Resistive random access memory and manufacturing method thereof | |
CN117412664A (en) | Semiconductor structure, forming method thereof and memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION |