US20060226487A1 - Resistor with reduced leakage - Google Patents
Resistor with reduced leakage Download PDFInfo
- Publication number
- US20060226487A1 US20060226487A1 US11/451,045 US45104506A US2006226487A1 US 20060226487 A1 US20060226487 A1 US 20060226487A1 US 45104506 A US45104506 A US 45104506A US 2006226487 A1 US2006226487 A1 US 2006226487A1
- Authority
- US
- United States
- Prior art keywords
- body region
- dielectric
- layer
- overlying
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
Definitions
- the present invention relates generally to semiconductor devices and more particularly to a resistor with reduced leakage.
- Resistors are commonly used in semiconductor integrated circuits. Resistors are used, for example, in analog and in mixed mode analog and digital circuits. Resistors are also used in input and output circuits as input and output resistors.
- a resistor may be formed in a portion of a single crystal silicon layer. Such a single crystal resistor has high stability and low noise, compared with conventional polycrystalline resistor structures. Resistors should also have low parasitic capacitance. Resistors formed on silicon-on-insulator substrates have extremely low parasitic capacitance due to full dielectric isolation and the insulating substrate.
- the resistor body is usually formed below a silicon oxide layer, which underlies a polycrystalline silicon layer.
- the polycrystalline silicon layer is usually connected to one of the two terminals of the resistor.
- CMOS complementary metal-oxide-semiconductor
- the thickness of the silicon oxide layer is progressively reduced. As the thickness of silicon oxide layer is reduced, leakage current between the polycrystalline silicon layer and the resistor body increases. The increased leakage current results in increased noise.
- resistors are sometimes used as part of an input protection circuit to provide protection of the circuit against electrostatic discharge (ESD) events.
- ESD electrostatic discharge
- the resistor is used to both attenuate the ESD voltage and also to absorb ESD energy. Large voltages in the order of thousands of volts may appear across the two terminals of the resistor used for ESD applications. Since the polycrystalline silicon layer and the resistor body are connected to the two terminals of the resistor, the silicon oxide layer between the polycrystalline silicon layer and the resistor body may potentially breakdown.
- a resistor with reduced leakage and noise is provided.
- a method of fabricating the resistor is also provided.
- a resistor is formed in a semiconductor layer, e.g., a silicon layer on an SOI substrate.
- a body region is formed in a portion of the semiconductor layer and is doped to a first conductivity type.
- a first contact region which is also doped to the first conductivity type, is formed in the semiconductor layer adjacent the body region.
- a second contact region is also formed in the semiconductor layer spaced from the first contact region by the body region. The second contact region is doped to the first conductivity type.
- a dielectric layer overlies the body region and is formed from a material with a relative permittivity greater than about 8.
- An electrode overlies the dielectric.
- a silicon-on-insulator resistor includes a silicon layer that overlies an insulator layer.
- a body region is formed in a portion of the silicon layer and a dielectric layer overlies the body region.
- the dielectric is a high permittivity dielectric layer.
- a top electrode overlies the dielectric layer and a pair of doped regions are formed in the silicon layer oppositely adjacent the body region. The pair of doped regions is doped to the same conductivity type as the body region.
- a silicon-on-insulator device in yet another embodiment, includes a substrate and an insulator layer overlying the substrate. An active area is formed in a silicon layer overlying the insulator layer. A body region of a first conductivity type is formed in a portion of the silicon layer. An interfacial layer, e.g., SiO 2 or SiON, overlies and abuts the body region. A high-k dielectric layer, e.g., a layer having a relative permittivity greater than about 8, overlies the interfacial layer. A top electrode overlies the high-k dielectric layer. A pair of doped regions of the first conductivity type are formed in the active area oppositely adjacent the body region.
- An interfacial layer e.g., SiO 2 or SiON
- a resistor of the preferred embodiment can be formed by providing a silicon-on-insulator substrate that includes a silicon layer overlying an insulator layer.
- a resistor body of a first conductivity type is formed in a portion of the silicon layer, e.g., by doping the portion of the layer.
- a dielectric layer e.g., with a relative permittivity greater than about 8, overlies the body region.
- a top electrode is formed on the dielectric layer and a pair of doped regions are formed oppositely adjacent the body region.
- FIG. 1 shows a first embodiment silicon-on-insulator resistor
- FIG. 2 shows a second embodiment silicon-on-insulator resistor
- FIG. 3 a shows a top view of a resistor of one embodiment of the invention
- FIGS. 3 b and 3 c show cross sectional views of the resistor of FIG. 3 a;
- FIG. 4 shows an SOI transistor and resistor formed on the same chip
- FIGS. 5 a - 5 f show cross-sectional views of a device during various stages of fabrication
- FIG. 6 shows an example of a circuit that can include a resistor of the present invention.
- FIG. 7 shows an example of a diode that can be implemented on the same chip as a resistor of the present invention.
- resistors with reduced leakage current are taught.
- Such resistors may be formed on a semiconductor-on-insulator (SOI) substrate.
- the semiconductor-on-insulator substrate is a silicon-on-insulator substrate having a silicon layer overlying a silicon oxide layer which in turn overlies a substrate.
- the silicon layer in the silicon-on-insulator substrate may be relaxed silicon or strained silicon.
- FIG. 1 a cross-section of a resistor 100 of the preferred embodiment is depicted.
- the device is formed on a silicon-on-insulator substrate, which includes a substrate 102 , a buried insulator layer 104 and a semiconductor layer 106 .
- the resistor has a body region 108 , or resistor body 108 , formed within a portion of the silicon layer 106 .
- a pair of doped regions 110 and 112 are formed oppositely adjacent to the resistor body 108 .
- the doped regions may be silicided to form low resistance regions.
- a stack comprising of a top electrode 114 (usually polycrystalline silicon) on a dielectric 116 is formed on the resistor body 108 , as shown in FIG. 1 .
- the dielectric 116 may be formed from the same dielectric layer used by transistors formed on other portions of the integrated circuit. Therefore, the thickness of the dielectric 116 tends to be scaled towards smaller thicknesses as technology progresses.
- the doped regions 110 and 112 electrically communicate with other portions of the integrated circuit.
- a first terminal 118 of the resistor 100 may be connected to ground potential (labeled GND), and a second terminal 120 may be connected to a circuit node with a potential V.
- the potential V may be at a potential higher than ground potential.
- a current flows through the resistor along a first current path 122 .
- the resistor body 108 predominantly contributes to the resistance seen between the two terminals 118 and 120 of the resistor.
- a second current path also exists between the two terminals 118 and 120 of the resistor. This path is labeled with reference number 124 in FIG. 1 .
- the second current path 124 shunts the first current path 122 , and may adversely affect the properties of the resistor 100 .
- the current flowing along the second current path 124 increases with reduced dielectric 116 thickness. This is because when the dielectric thickness is small, quantum mechanical tunneling of charge carriers may occur through the dielectric 116 .
- the dielectric thickness may be increased while maintaining the same capacitive properties. As a result of the increase of the dielectric thickness, the leakage current flowing along the second current path 124 may be significantly suppressed.
- the dielectric 116 that overlies the resistor body 108 comprises a high permittivity (high-k) dielectric.
- high-k dielectric the thickness of the dielectric 116 can be significantly larger than that if a silicon oxide dielectric is employed.
- the high-k dielectric preferably has a permittivity of larger than about 8, and more preferably has a permittivity of larger than about 10, and even more preferably has a permittivity of larger than about 20.
- the high permittivity dielectric 116 may be one of the following materials: aluminum oxide (Al 2 O 3 ), hafnium oxide (Hfo 2 ), hafnium oxynitride (HfON), hafnium silicate (HfSiO 4 ), zirconium oxide (ZrO 2 ), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO 4 ), yttrium oxide (Y 2 O 3 ), lanthanum oxide (La 2 O 3 ), cerium oxide (CeO 2 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), and combinations thereof.
- the high-k dielectric 116 is hafnium oxide.
- the dielectric 116 may additionally comprise silicon oxide (SiO 2 ), silicon oxynitride (SiON), or silicon nitride (Si 3 N 4 ).
- the silicon oxide equivalent thickness (EOT) of the dielectric is preferably larger than about 5 angstroms, more preferably larger than about 10 angstroms, and even more preferably larger than about 20 angstroms.
- the physical thickness of the dielectric may be larger than about 5 angstroms, more preferably larger than about 20 angstroms, and even more preferably larger than about 40 angstroms.
- the top electrode 114 comprises a conductive material such as polycrystalline or amorphous silicon, polycrystalline silicon-germanium, a metal, a metallic nitride, a metallic silicide, or a metallic oxide, and combinations thereof.
- the top electrode 114 comprises polycrystalline silicon possibly in combination with a silicide layer.
- Metals such as molybdenum, tungsten, titanium, tantalum, platinum, and hafnium may be used as the portion of the top electrode 114 .
- Metallic nitrides may include, but will not be restricted to, molybdenum nitride, tungsten nitride, titanium nitride, and tantalum nitride.
- Metallic silicides may include, but will not be restricted to, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum silicide, and erbium silicide.
- Metallic oxides may include, but will not be restricted to, ruthenium oxide and indium tin oxide.
- the resistor body 108 thickness is preferably in the range of about 20 angstroms to about 1000 angstroms, and more preferably in the range of about 20 angstroms to about 400 angstroms.
- the first current path 122 flows in close proximity to the interface between the resistor body 108 and the dielectric 116 .
- measures should be taken to ensure that the interface 108 / 116 has a low interface trap density of less than about 10 10 cm ⁇ 2 .
- Interface traps result in charge carriers flowing in the resistor to be instantaneously trapped or detrapped, causing an instantaneously decrease or increase in the current, respectively. This manifests as a current noise source in the resistor.
- the dielectric 116 overlying the resistor body 108 preferably comprises of at least two layers: a high-k dielectric 126 overlying an interfacial dielectric layer 128 , as shown in FIG. 2 .
- the interfacial dielectric layer 128 is preferably one that has excellent interfacial properties in contact with the resistor body 108 .
- the interfacial layer 128 comprises silicon oxide (e.g., SiO 2 ) or silicon oxynitride (e.g., SiO x N y ).
- the resistor body 108 may be doped n-type or p-type.
- the doped regions 110 and 112 adjacent to the resistor body 108 are doped the same type as the resistor body 108 .
- the doped regions 110 and 112 preferably have a high doping concentration, e.g., between about 10 18 cm ⁇ 3 and about 5 ⁇ 10 21 cm ⁇ 3 .
- the resistor body 108 has a doping concentration that is lower and is selected to provide the desired resistivity. Typical values are between about 10 16 cm ⁇ 3 and 10 19 cm ⁇ 3 .
- FIG. 3 a shows a top view or layout view of a resistor 100 of an embodiment of this invention.
- the resistor has a width W and a length L.
- the width W may have a dimension of larger than about 0.1 microns, and preferably larger than about 1 micron.
- the length L may have a dimension of larger than about 0.1 micron, and preferably larger than about 1 micron.
- the detailed structure of the resistor may be seen in cross-sectional views along the lines 3 b - 3 b′ and 3 c - 3 c′.
- the top electrode 114 extends laterally into the isolation regions 130 .
- the isolation region 116 may comprise isolation structures known and used in the art, such as shallow trench isolation.
- the shallow trench isolation structure may comprise a dielectric filling material such as chemical vapor deposited silicon oxide.
- the shallow trench isolation structure may also comprise trench liner oxide (not shown for simplicity) on the boundaries of the trench.
- the trench liner oxide may or may not contain nitrogen.
- FIG. 1 showed an active region 106 surrounded by mesa isolation. It is understood that the resistor may be used in a semiconductor-on-insulator technology employing trench isolation, or may be used in a semiconductor-on-insulator technology employing mesa isolation. In mesa isolation, trenches are not filled with a dielectric filling material prior to the formation of transistors or resistors.
- the top electrode in FIG. 3 b is shown to have a thickness t, preferably in the range of about 200 angstroms to about 2000 angstroms.
- the resistor structure may additionally have spacers 132 formed on the sides of the top electrode 114 .
- the top electrode 114 may be formed of the same material as the gate electrode of a transistor formed in another portion of the integrated circuit, as shown in FIG. 4 .
- FIG. 3 c The cross-sectional view along line 3 c - 3 c′ is shown in FIG. 3 c. This view shows the doped regions 110 and 112 .
- the resistor 100 may be formed in an active region 106 c in the vicinity of an active device 140 such as a transistor.
- transistor 140 is formed in active region 106 a and includes source region 142 , drain region 144 , gate dielectric 146 and gate electrode 148 .
- the resistor dielectric 116 may or may not be the same dielectric material as the transistor gate dielectric 146 .
- the gate electrode 114 of the resistor 100 may or may not be formed of the same material as the gate electrode 148 of the transistor 140 .
- the distance between doped regions 110 and 112 is typically between about 2 and 100 times greater the channel length of transistor 140 (i.e., the distance between source and drain regions 142 and 144 ).
- a semiconductor-on-insulator substrate including substrate 102 , insulator 104 and semiconductor layer 106 , is provided and an active region mask 150 is used to define trenches 152 in the semiconductor layer 106 .
- the semiconductor layer 106 preferably has a thickness of about 1000 angstroms or thinner.
- the insulator 104 thickness is preferably about 1200 angstroms or thinner.
- the mask 150 preferably comprises silicon nitride, and more preferably comprises silicon nitride on a silicon oxide layer.
- Trench filling dielectric material is deposited by chemical vapor deposition to fill the trenches 152 , followed by a chemical mechanical planarization process step. These steps create isolation region 130 .
- the mask 150 is then removed to give the cross-section shown in FIG. 5 b.
- An ion implantation process step may be performed to dope the active region, a portion of which will become the resistor body 108 .
- the dose of the implantation will determine the resistivity of the semiconductor layer and therefore the resistance of the resistor.
- an implant dose in the range of about 10 13 to about 10 16 cm ⁇ 2 may be used.
- a dielectric 116 comprising a high-k material is then formed over the active region 106 , as shown in FIG. 5 c.
- the physical thickness of the dielectric may be larger than about 5 angstroms, more preferably larger than about 20 angstroms, and even more preferably larger than about 40 angstroms. Further, the dielectric may be smaller than about 200 angstroms, preferably smaller than about 100 angstroms and most preferably smaller than about 50 angstroms.
- the dielectric 116 may be formed together with the formation of a transistor gate dielectric 146 in a different portion of the semiconductor chip (see FIG. 4 ). By forming the dielectric 116 together with the gate dielectric 146 of a transistor in a different portion of the chip, no additional process steps are introduced.
- High-k dielectric materials as previously described may be used. The high-k dielectric may be formed by chemical vapor deposition, sputter deposition, or other known techniques of forming high-k dielectric materials.
- An interfacial layer (see FIG. 2 ) may be formed on the body region 108 prior to the formation of the high-k dielectric material.
- the interfacial layer may be a silicon oxide layer or a silicon oxynitride layer, and may be formed by thermal oxidation and/or nitridation.
- the active region 106 may additionally be treated in a hydrogen-containing or nitrogen-containing ambient prior to the formation of the interfacial layer.
- the top electrode material 114 can then be deposited over the dielectric layer 116 .
- the top electrode 114 material can be amorphous or polycrystalline silicon, polycrystalline silicon germanium, metals, metallic silicides, or metallic nitrides, as previously described.
- the electrode 114 material can be deposited by conventional techniques such as chemical vapor deposition.
- the electrode 114 may also be formed by the deposition of silicon and metal, followed by an anneal to form a metal silicide electrode that includes silicon portion 160 and silicide portion 162 .
- the electrode material is then patterned using photolithography techniques, and etched using plasma etch processes to form the electrodes 114 .
- the deposition of the top electrode material may be the same process step as the deposition of gate electrode material of a transistor to be formed in a different portion of the semiconductor chip, and the etching of the top electrode may similarly be accomplished together with the etching of the gate electrode of the said transistor.
- the completed top electrode is shown in FIG. 5 d.
- the dielectric 118 is retained at least in the portion of the resistor covered by the electrode 114 . Doping may be introduced in regions 110 and 112 (see FIGS. 1, 2 or 3 c ) adjacent to the body region 108 to make electrical contacts with the resistor body 108 .
- spacers 132 may be additionally formed on the sides of the electrode 114 . This may be followed by another implant to the doped regions ( 110 and 112 ) of the active region 106 not covered by the spacers 132 or electrode 114 .
- a contact etch-stop layer 154 may be formed on the electrode 114 and spacers 132 .
- An inter-layer dielectric (ILD) 156 may be formed over the resistor and contact holes etched through the ILD 156 to reach the electrode 114 and the doped regions ( 110 and 112 ) of the resistor. Conductive materials (e.g., tungsten) are then used to fill the contact holes to form contact plugs 158 , as shown in FIG. 5f .
- ILD inter-layer dielectric
- the resistor of the present invention can be used in a number of circuits.
- FIG. 6 provides but one example, namely an electrostatic discharge (ESD) protection circuit. This circuit will now be described.
- ESD electrostatic discharge
- FIG. 6 shows an example of how concepts of the present invention can be deployed for protection of integrated circuits.
- resistors 100 and 100 ′ are coupled between an I/O pad 166 and two circuit portions 168 and 170 .
- the resistors 100 and 100 ′ can be any of the various embodiment resistors described in this specification.
- the circuit portion 168 is labeled as an output circuit and the circuit portion 170 is labeled as an input circuit. It is understood, however, that these circuit portions can be any circuit that should be shielded from high voltages.
- the I/O pad 166 is provided to indicate any node that might be subject to a high voltage. The most typical of these nodes are the inputs and outputs between the chip and the outside world (e.g., external circuitry when connected to a system or handling devices when the system is being assembled).
- the pad 166 is indicated as being an I/O pad, which stands for input/output. It is noted, however, that in this patent the term I/O is meant to include pads for input only, output only or both input and output (or any other node that might be subject to a high voltage).
- the circuit of FIG. 6 also shows a first diode string 172 coupled between a supply voltage source V DD (e.g., a voltage source of 5V, 3.3V, 2.5V or 1.8V) and the I/O pad 166 and a second diode string 174 coupled between a supply voltage source V SS and the I/O pad 166 .
- V DD supply voltage source
- V SS supply voltage source
- Each diode string 172 and 174 includes one or more diodes 176 .
- the diode 176 comprises a diode of the type described in co-pending application Ser. No. 10/641,813 (attorney docket TSM03-0554), which is incorporated herein by reference.
- diode string 172 can include a diode 176 with a p-doped region coupled to I/O pad 166 and another 176 (or the same diode in a one diode string) with an n-doped region coupled to V DD .
- the diode string 174 is coupled between the I/O pad 166 and the reference voltage V SS (e.g., ground). In this case, a p-doped region is coupled to ground and an n-doped region is coupled to the pad 166 .
- FIG. 7 shows a cross-sectional view of a gated diode 176 . Except for reference numbers, FIG. 7 is the same as FIG. 4 in the co-pending '813 application.
- the diode 176 is formed in a bulk semiconductor substrate 102 . In another example, the diode can be formed in the semiconductor layer 106 (e.g., of FIG. 1 or 2 ).
- the gated diode 176 includes an n+ doped region 178 and a p+ doped region 180 that are separated by a body region 182 .
- a gate 184 overlies the body region 182 and is separated therefrom by a dielectric 186 .
- the gate includes an n-doped portion 188 adjacent a p-doped portion 190 .
- other conductors can be used to form the gate 184 .
- FIG. 7 also shows spacers 192 and conductive regions 194 (e.g., silicide) as described previously.
- dielectric layer 186 comprises a high-k dielectric.
- the dielectric layer 186 can be formed from the same layer that is used to formed dielectric layer 116 for the resistors as described above. Combining process steps in the formation of resistors 100 , diodes 176 and transistors 140 (e.g., components of circuits 168 and 170 ) simplifies the formation of circuits, such as the ESD protection circuit of FIG. 6 .
- diode 176 is described herein with respect to a specific example, it is understood that any of the variations and embodiments described in the co-pending and incorporated '183 application can be utilized in the present invention.
Abstract
A resistor 100 is formed in a semiconductor layer 106, e.g., a silicon layer on an SOI substrate. A body region 108 is formed in a portion of the semiconductor layer 106 and is doped to a first conductivity type (e.g., n-type or p-type). A first contact region 110, which is also doped to the first conductivity type, is formed in the semiconductor layer 106 adjacent the body region 108. A second contact region 112 is also formed in the semiconductor layer 106 and is spaced from the first contact region 110 by the body region 108. A dielectric layer 116 overlies the body region and is formed from a material with a relative permittivity greater than about 8. An electrode 114 overlies the dielectric 116.
Description
- This application is a divisional of U.S. patent application Ser. No. 10/667,871, entitled “Resistor with Reduced Leakage,” filed on Sep. 22, 2003, which claims the benefit of U.S. Provisional Application Ser. No. 60/496,310, filed on Aug. 18, 2003, both of which applications are hereby incorporated herein by reference.
- This application relates to the following publication and/or patent. Each of these documents is incorporated herein by reference.
Publication No./Patent No. Filing Date Issue Date 2005/0035410 A1 Aug. 15, 2003 Feb. 17, 2005 6,936,881 Jul. 25, 2003 Aug. 30, 2005 - 1. Technical Field
- The present invention relates generally to semiconductor devices and more particularly to a resistor with reduced leakage.
- 2. Background
- Resistors are commonly used in semiconductor integrated circuits. Resistors are used, for example, in analog and in mixed mode analog and digital circuits. Resistors are also used in input and output circuits as input and output resistors.
- In integrated circuits formed on silicon-on-insulator substrates, a resistor may be formed in a portion of a single crystal silicon layer. Such a single crystal resistor has high stability and low noise, compared with conventional polycrystalline resistor structures. Resistors should also have low parasitic capacitance. Resistors formed on silicon-on-insulator substrates have extremely low parasitic capacitance due to full dielectric isolation and the insulating substrate.
- In resistors formed on silicon-on-insulator substrates, the resistor body is usually formed below a silicon oxide layer, which underlies a polycrystalline silicon layer. The polycrystalline silicon layer is usually connected to one of the two terminals of the resistor. With complementary metal-oxide-semiconductor (CMOS) technology scaling, the thickness of the silicon oxide layer is progressively reduced. As the thickness of silicon oxide layer is reduced, leakage current between the polycrystalline silicon layer and the resistor body increases. The increased leakage current results in increased noise.
- In addition, resistors are sometimes used as part of an input protection circuit to provide protection of the circuit against electrostatic discharge (ESD) events. In this case, the resistor is used to both attenuate the ESD voltage and also to absorb ESD energy. Large voltages in the order of thousands of volts may appear across the two terminals of the resistor used for ESD applications. Since the polycrystalline silicon layer and the resistor body are connected to the two terminals of the resistor, the silicon oxide layer between the polycrystalline silicon layer and the resistor body may potentially breakdown.
- In the preferred embodiment, a resistor with reduced leakage and noise is provided. A method of fabricating the resistor is also provided.
- In accordance with a preferred embodiment of the present invention, a resistor is formed in a semiconductor layer, e.g., a silicon layer on an SOI substrate. A body region is formed in a portion of the semiconductor layer and is doped to a first conductivity type. A first contact region, which is also doped to the first conductivity type, is formed in the semiconductor layer adjacent the body region. A second contact region is also formed in the semiconductor layer spaced from the first contact region by the body region. The second contact region is doped to the first conductivity type. A dielectric layer overlies the body region and is formed from a material with a relative permittivity greater than about 8. An electrode overlies the dielectric.
- According to another aspect of the invention, a silicon-on-insulator resistor includes a silicon layer that overlies an insulator layer. A body region is formed in a portion of the silicon layer and a dielectric layer overlies the body region. Preferably, the dielectric is a high permittivity dielectric layer. A top electrode overlies the dielectric layer and a pair of doped regions are formed in the silicon layer oppositely adjacent the body region. The pair of doped regions is doped to the same conductivity type as the body region.
- In yet another embodiment, a silicon-on-insulator device includes a substrate and an insulator layer overlying the substrate. An active area is formed in a silicon layer overlying the insulator layer. A body region of a first conductivity type is formed in a portion of the silicon layer. An interfacial layer, e.g., SiO2 or SiON, overlies and abuts the body region. A high-k dielectric layer, e.g., a layer having a relative permittivity greater than about 8, overlies the interfacial layer. A top electrode overlies the high-k dielectric layer. A pair of doped regions of the first conductivity type are formed in the active area oppositely adjacent the body region.
- A resistor of the preferred embodiment can be formed by providing a silicon-on-insulator substrate that includes a silicon layer overlying an insulator layer. A resistor body of a first conductivity type is formed in a portion of the silicon layer, e.g., by doping the portion of the layer. A dielectric layer, e.g., with a relative permittivity greater than about 8, overlies the body region. A top electrode is formed on the dielectric layer and a pair of doped regions are formed oppositely adjacent the body region.
- For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
-
FIG. 1 shows a first embodiment silicon-on-insulator resistor; -
FIG. 2 shows a second embodiment silicon-on-insulator resistor; -
FIG. 3 a shows a top view of a resistor of one embodiment of the invention; -
FIGS. 3 b and 3 c show cross sectional views of the resistor ofFIG. 3 a; -
FIG. 4 shows an SOI transistor and resistor formed on the same chip; -
FIGS. 5 a-5 f show cross-sectional views of a device during various stages of fabrication; -
FIG. 6 shows an example of a circuit that can include a resistor of the present invention; and -
FIG. 7 shows an example of a diode that can be implemented on the same chip as a resistor of the present invention. - In aspects of this invention, resistors with reduced leakage current are taught. Such resistors may be formed on a semiconductor-on-insulator (SOI) substrate. In the preferred embodiment, the semiconductor-on-insulator substrate is a silicon-on-insulator substrate having a silicon layer overlying a silicon oxide layer which in turn overlies a substrate. The silicon layer in the silicon-on-insulator substrate may be relaxed silicon or strained silicon.
- Referring now to
FIG. 1 , a cross-section of aresistor 100 of the preferred embodiment is depicted. In this example, the device is formed on a silicon-on-insulator substrate, which includes asubstrate 102, a buriedinsulator layer 104 and asemiconductor layer 106. The resistor has abody region 108, orresistor body 108, formed within a portion of thesilicon layer 106. A pair ofdoped regions resistor body 108. - Although not shown in this figure, the doped regions may be silicided to form low resistance regions. In addition, to prevent the silicidation of the body region of the resistor, a stack comprising of a top electrode 114 (usually polycrystalline silicon) on a dielectric 116 is formed on the
resistor body 108, as shown inFIG. 1 . The dielectric 116 may be formed from the same dielectric layer used by transistors formed on other portions of the integrated circuit. Therefore, the thickness of the dielectric 116 tends to be scaled towards smaller thicknesses as technology progresses. - As shown substantially in
FIG. 1 , the dopedregions first terminal 118 of theresistor 100 may be connected to ground potential (labeled GND), and asecond terminal 120 may be connected to a circuit node with a potential V. The potential V may be at a potential higher than ground potential. As a result, a current flows through the resistor along a firstcurrent path 122. Theresistor body 108 predominantly contributes to the resistance seen between the twoterminals - A second current path also exists between the two
terminals reference number 124 inFIG. 1 . The secondcurrent path 124 shunts the firstcurrent path 122, and may adversely affect the properties of theresistor 100. The current flowing along the secondcurrent path 124 increases with reduced dielectric 116 thickness. This is because when the dielectric thickness is small, quantum mechanical tunneling of charge carriers may occur through the dielectric 116. According to the preferred embodiment of this invention, by incorporating at least a high permittivity (high-k) material in the dielectric 116, the dielectric thickness may be increased while maintaining the same capacitive properties. As a result of the increase of the dielectric thickness, the leakage current flowing along the secondcurrent path 124 may be significantly suppressed. - Therefore, in the preferred embodiment of the present invention, the dielectric 116 that overlies the
resistor body 108 comprises a high permittivity (high-k) dielectric. By using a high-k dielectric, the thickness of the dielectric 116 can be significantly larger than that if a silicon oxide dielectric is employed. The high-k dielectric preferably has a permittivity of larger than about 8, and more preferably has a permittivity of larger than about 10, and even more preferably has a permittivity of larger than about 20. Thehigh permittivity dielectric 116 may be one of the following materials: aluminum oxide (Al2O3), hafnium oxide (Hfo2), hafnium oxynitride (HfON), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO4), yttrium oxide (Y2O3), lanthanum oxide (La2O3), cerium oxide (CeO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), and combinations thereof. In the preferred embodiment, the high-k dielectric 116 is hafnium oxide. The dielectric 116 may additionally comprise silicon oxide (SiO2), silicon oxynitride (SiON), or silicon nitride (Si3N4). - The silicon oxide equivalent thickness (EOT) of the dielectric is preferably larger than about 5 angstroms, more preferably larger than about 10 angstroms, and even more preferably larger than about 20 angstroms. The physical thickness of the dielectric may be larger than about 5 angstroms, more preferably larger than about 20 angstroms, and even more preferably larger than about 40 angstroms.
- The
top electrode 114 comprises a conductive material such as polycrystalline or amorphous silicon, polycrystalline silicon-germanium, a metal, a metallic nitride, a metallic silicide, or a metallic oxide, and combinations thereof. In the preferred embodiment, thetop electrode 114 comprises polycrystalline silicon possibly in combination with a silicide layer. - Metals such as molybdenum, tungsten, titanium, tantalum, platinum, and hafnium may be used as the portion of the
top electrode 114. Metallic nitrides may include, but will not be restricted to, molybdenum nitride, tungsten nitride, titanium nitride, and tantalum nitride. Metallic silicides may include, but will not be restricted to, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum silicide, and erbium silicide. Metallic oxides may include, but will not be restricted to, ruthenium oxide and indium tin oxide. - It should be noted that the
resistor body 108 thickness is preferably in the range of about 20 angstroms to about 1000 angstroms, and more preferably in the range of about 20 angstroms to about 400 angstroms. As such, the firstcurrent path 122 flows in close proximity to the interface between theresistor body 108 and the dielectric 116. As a result, measures should be taken to ensure that theinterface 108/116 has a low interface trap density of less than about 1010 cm−2. Interface traps result in charge carriers flowing in the resistor to be instantaneously trapped or detrapped, causing an instantaneously decrease or increase in the current, respectively. This manifests as a current noise source in the resistor. - To reduce the amount of current noise, the dielectric 116 overlying the
resistor body 108 preferably comprises of at least two layers: a high-k dielectric 126 overlying aninterfacial dielectric layer 128, as shown inFIG. 2 . Theinterfacial dielectric layer 128 is preferably one that has excellent interfacial properties in contact with theresistor body 108. In the preferred embodiment, theinterfacial layer 128 comprises silicon oxide (e.g., SiO2) or silicon oxynitride (e.g., SiOxNy). - The
resistor body 108 may be doped n-type or p-type. The dopedregions resistor body 108 are doped the same type as theresistor body 108. The dopedregions resistor body 108 has a doping concentration that is lower and is selected to provide the desired resistivity. Typical values are between about 1016 cm−3 and 1019 cm−3. -
FIG. 3 a shows a top view or layout view of aresistor 100 of an embodiment of this invention. The resistor has a width W and a length L. In the preferred embodiment, the width W may have a dimension of larger than about 0.1 microns, and preferably larger than about 1 micron. In the preferred embodiment, the length L may have a dimension of larger than about 0.1 micron, and preferably larger than about 1 micron. The detailed structure of the resistor may be seen in cross-sectional views along thelines 3 b-3 b′ and 3 c-3 c′. - The detailed cross-sectional view along
line 3 b-3 b′ ofFIG. 3a is shown inFIG. 3 b. Thetop electrode 114 extends laterally into theisolation regions 130. Theisolation region 116 may comprise isolation structures known and used in the art, such as shallow trench isolation. The shallow trench isolation structure may comprise a dielectric filling material such as chemical vapor deposited silicon oxide. The shallow trench isolation structure may also comprise trench liner oxide (not shown for simplicity) on the boundaries of the trench. The trench liner oxide may or may not contain nitrogen. - Other isolation types could alternately be used. For example,
FIG. 1 showed anactive region 106 surrounded by mesa isolation. It is understood that the resistor may be used in a semiconductor-on-insulator technology employing trench isolation, or may be used in a semiconductor-on-insulator technology employing mesa isolation. In mesa isolation, trenches are not filled with a dielectric filling material prior to the formation of transistors or resistors. - The top electrode in
FIG. 3 b is shown to have a thickness t, preferably in the range of about 200 angstroms to about 2000 angstroms. The resistor structure may additionally havespacers 132 formed on the sides of thetop electrode 114. Thetop electrode 114 may be formed of the same material as the gate electrode of a transistor formed in another portion of the integrated circuit, as shown inFIG. 4 . - The cross-sectional view along
line 3 c-3 c′ is shown inFIG. 3 c. This view shows the dopedregions - Referring now to
FIG. 4 , theresistor 100 may be formed in anactive region 106 c in the vicinity of anactive device 140 such as a transistor. InFIG. 4 ,transistor 140 is formed inactive region 106 a and includessource region 142,drain region 144,gate dielectric 146 andgate electrode 148. Theresistor dielectric 116 may or may not be the same dielectric material as thetransistor gate dielectric 146. Thegate electrode 114 of theresistor 100 may or may not be formed of the same material as thegate electrode 148 of thetransistor 140. In a typical embodiment, the distance betweendoped regions regions 142 and 144). - Next, a method of manufacturing the resistor is to be described with respect to
FIGS. 5 a-5 f, which are taken along the same cross-sectional line asFIG. 3 b. Referring first toFIG. 5 a, a semiconductor-on-insulator substrate, includingsubstrate 102,insulator 104 andsemiconductor layer 106, is provided and anactive region mask 150 is used to definetrenches 152 in thesemiconductor layer 106. Thesemiconductor layer 106 preferably has a thickness of about 1000 angstroms or thinner. Theinsulator 104 thickness is preferably about 1200 angstroms or thinner. Themask 150 preferably comprises silicon nitride, and more preferably comprises silicon nitride on a silicon oxide layer. - Trench filling dielectric material is deposited by chemical vapor deposition to fill the
trenches 152, followed by a chemical mechanical planarization process step. These steps createisolation region 130. Themask 150 is then removed to give the cross-section shown inFIG. 5 b. - An ion implantation process step may be performed to dope the active region, a portion of which will become the
resistor body 108. The dose of the implantation will determine the resistivity of the semiconductor layer and therefore the resistance of the resistor. For example, an implant dose in the range of about 1013 to about 1016 cm−2 may be used. - A dielectric 116 comprising a high-k material is then formed over the
active region 106, as shown inFIG. 5 c. The physical thickness of the dielectric may be larger than about 5 angstroms, more preferably larger than about 20 angstroms, and even more preferably larger than about 40 angstroms. Further, the dielectric may be smaller than about 200 angstroms, preferably smaller than about 100 angstroms and most preferably smaller than about 50 angstroms. - The dielectric 116 may be formed together with the formation of a
transistor gate dielectric 146 in a different portion of the semiconductor chip (seeFIG. 4 ). By forming the dielectric 116 together with thegate dielectric 146 of a transistor in a different portion of the chip, no additional process steps are introduced. High-k dielectric materials as previously described may be used. The high-k dielectric may be formed by chemical vapor deposition, sputter deposition, or other known techniques of forming high-k dielectric materials. - An interfacial layer (see
FIG. 2 ) may be formed on thebody region 108 prior to the formation of the high-k dielectric material. The interfacial layer may be a silicon oxide layer or a silicon oxynitride layer, and may be formed by thermal oxidation and/or nitridation. Theactive region 106 may additionally be treated in a hydrogen-containing or nitrogen-containing ambient prior to the formation of the interfacial layer. - Referring now to
FIG. 5 d, thetop electrode material 114 can then be deposited over thedielectric layer 116. Thetop electrode 114 material can be amorphous or polycrystalline silicon, polycrystalline silicon germanium, metals, metallic silicides, or metallic nitrides, as previously described. Theelectrode 114 material can be deposited by conventional techniques such as chemical vapor deposition. For example, theelectrode 114 may also be formed by the deposition of silicon and metal, followed by an anneal to form a metal silicide electrode that includessilicon portion 160 andsilicide portion 162. The electrode material is then patterned using photolithography techniques, and etched using plasma etch processes to form theelectrodes 114. - The deposition of the top electrode material may be the same process step as the deposition of gate electrode material of a transistor to be formed in a different portion of the semiconductor chip, and the etching of the top electrode may similarly be accomplished together with the etching of the gate electrode of the said transistor. The completed top electrode is shown in
FIG. 5 d. The dielectric 118 is retained at least in the portion of the resistor covered by theelectrode 114. Doping may be introduced inregions 110 and 112 (seeFIGS. 1, 2 or 3 c) adjacent to thebody region 108 to make electrical contacts with theresistor body 108. - As shown in
FIG. 5 e,spacers 132 may be additionally formed on the sides of theelectrode 114. This may be followed by another implant to the doped regions (110 and 112) of theactive region 106 not covered by thespacers 132 orelectrode 114. A contact etch-stop layer 154 may be formed on theelectrode 114 andspacers 132. An inter-layer dielectric (ILD) 156 may be formed over the resistor and contact holes etched through theILD 156 to reach theelectrode 114 and the doped regions (110 and 112) of the resistor. Conductive materials (e.g., tungsten) are then used to fill the contact holes to form contact plugs 158, as shown inFIG. 5f . - The resistor of the present invention can be used in a number of circuits.
FIG. 6 provides but one example, namely an electrostatic discharge (ESD) protection circuit. This circuit will now be described. -
FIG. 6 shows an example of how concepts of the present invention can be deployed for protection of integrated circuits. In this example,resistors O pad 166 and twocircuit portions resistors circuit portion 168 is labeled as an output circuit and thecircuit portion 170 is labeled as an input circuit. It is understood, however, that these circuit portions can be any circuit that should be shielded from high voltages. - The I/
O pad 166 is provided to indicate any node that might be subject to a high voltage. The most typical of these nodes are the inputs and outputs between the chip and the outside world (e.g., external circuitry when connected to a system or handling devices when the system is being assembled). Thepad 166 is indicated as being an I/O pad, which stands for input/output. It is noted, however, that in this patent the term I/O is meant to include pads for input only, output only or both input and output (or any other node that might be subject to a high voltage). - The circuit of
FIG. 6 , also shows afirst diode string 172 coupled between a supply voltage source VDD (e.g., a voltage source of 5V, 3.3V, 2.5V or 1.8V) and the I/O pad 166 and asecond diode string 174 coupled between a supply voltage source VSS and the I/O pad 166. Eachdiode string more diodes 176. In the preferred embodiment, thediode 176 comprises a diode of the type described in co-pending application Ser. No. 10/641,813 (attorney docket TSM03-0554), which is incorporated herein by reference. For example,diode string 172 can include adiode 176 with a p-doped region coupled to I/O pad 166 and another 176 (or the same diode in a one diode string) with an n-doped region coupled to VDD. Thediode string 174 is coupled between the I/O pad 166 and the reference voltage VSS (e.g., ground). In this case, a p-doped region is coupled to ground and an n-doped region is coupled to thepad 166. -
FIG. 7 shows a cross-sectional view of agated diode 176. Except for reference numbers,FIG. 7 is the same asFIG. 4 in the co-pending '813 application. In the illustrated example, thediode 176 is formed in abulk semiconductor substrate 102. In another example, the diode can be formed in the semiconductor layer 106 (e.g., ofFIG. 1 or 2). - The
gated diode 176 includes an n+ dopedregion 178 and a p+ dopedregion 180 that are separated by abody region 182. Agate 184 overlies thebody region 182 and is separated therefrom by a dielectric 186. In the illustrated embodiment, the gate includes an n-dopedportion 188 adjacent a p-dopedportion 190. In other embodiments, other conductors can be used to form thegate 184.FIG. 7 also showsspacers 192 and conductive regions 194 (e.g., silicide) as described previously. - In the preferred embodiment,
dielectric layer 186 comprises a high-k dielectric. In fact, thedielectric layer 186 can be formed from the same layer that is used to formeddielectric layer 116 for the resistors as described above. Combining process steps in the formation ofresistors 100,diodes 176 and transistors 140 (e.g., components ofcircuits 168 and 170) simplifies the formation of circuits, such as the ESD protection circuit ofFIG. 6 . - While
diode 176 is described herein with respect to a specific example, it is understood that any of the variations and embodiments described in the co-pending and incorporated '183 application can be utilized in the present invention. - In the foregoing specification, the invention has been described with reference to specific embodiments. However, various modifications and changes can be made by one skilled in the art without departing from the scope of the preferred embodiment. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the preferred embodiment.
Claims (25)
1. A resistor comprising:
a semiconductor layer;
a body region formed in a portion of the semiconductor layer, the body region being doped to a first conductivity type and having a first resistivity;
a first contact region formed in the semiconductor layer adjacent the body region, the first contact region being doped to the first conductivity type;
a second contact region formed in the semiconductor layer spaced from the first contact region by the body region, the second contact region being doped to the first conductivity type;
a dielectric layer overlying the body region, said dielectric comprising a material with a relative permittivity greater than about 8; and
a conductive electrode overlying said dielectric.
2. The resistor of claim 1 further comprising an insulator layer underlying the semiconductor layer.
3. The resistor of claim 1 wherein the electrode has a width larger than about 1 micron.
4. The resistor of claim 1 wherein the electrode has a length larger than about 1 micron.
5. The resistor of claim 1 further comprising spacers formed on sides of the electrode.
6. A silicon-on-insulator resistor comprising:
a silicon layer overlying an insulator layer;
a body region formed in a portion of the silicon layer;
a dielectric layer overlying the body region, said dielectric comprising a high permittivity dielectric layer;
a conductive top electrode overlying said dielectric layer; and
a pair of doped regions formed in the silicon layer oppositely adjacent the body region, the pair of doped regions being doped to the same conductivity type as the body region.
7. The resistor of claim 6 wherein the high permittivity dielectric is selected from a group comprising of aluminum oxide, hafnium oxynitride, hafnium silicate, zirconium oxide, zirconium oxynitride, zirconium silicate, yttrium oxide, lanthanum oxide, cerium oxide, titanium oxide, and tantalum oxide, and combinations thereof.
8. The resistor of claim 6 wherein the permittivity dielectric layer comprises hafnium oxide.
9. The resistor of claim 6 wherein the silicon layer is a strained silicon layer.
10. A silicon-on-insulator device comprising:
an active area comprising a silicon layer overlying an insulator layer;
a body region of a first conductivity type formed in a portion of the silicon layer;
a dielectric layer overlying the body region, said dielectric comprising a material selected from the group consisting of aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium silicate, zirconium oxide, zirconium oxynitride, zirconium silicate, yttrium oxide, lanthanum oxide, cerium oxide, titanium oxide, tantalum oxide, and combinations thereof;
a conductive top electrode overlying the dielectric layer; and
a pair of doped regions of the first conductivity type formed in the silicon layer oppositely adjacent the body region.
11. The device of claim 10 wherein the silicon layer has a thickness in the range of about 20 angstroms to about 400 angstroms.
12. The device of claim 10 and further comprising a second active area overlying the insulator layer, the second active area including a transistor formed therein.
13. The device of claim 12 wherein the transistor includes a gate dielectric formed of the same material as the dielectric layer overlying the body region.
14. The device of claim 12 wherein the transistor includes a gate dielectric formed of a different material as the dielectric layer overlying the body region.
15. The device of claim 12 wherein the transistor includes a gate electrode formed of the same material as the top electrode.
16. A silicon-on-insulator device comprising:
a substrate;
an insulator layer overlying the substrate;
an active area formed in a silicon layer overlying the insulator layer;
a body region of a first conductivity type formed in a portion of the silicon layer;
an interfacial layer overlying and abutting the body region;
a high-k dielectric layer overlying the interfacial layer, the high-k dielectric layer comprising a material having a relative permittivity greater than about 8;
a conductive top electrode overlying the high-k dielectric layer; and
a pair of doped regions of the first conductivity type formed in the active area oppositely adjacent the body region.
17. The device of claim 16 and further comprising a second active area overlying the insulator layer, the second active area including a transistor formed therein.
18. An electrostatic discharge protection circuit comprising:
an I/O pad;
a circuit that is to be protected;
a diode coupled between the I/O pad and a reference voltage node;
a resistor coupled between the I/O pad and the circuit, the resistor including a body region, a first contact region adjacent the body region to electrically couple the body region to the I/O pad, a second contact region adjacent the body region to electrically couple the body region to the circuit, a dielectric layer having a relative permittivity greater than about 8 overlying the body region, and an electrode overlying the dielectric layer.
19. The circuit of claim 18 wherein the diode comprises:
a diode body region;
a diode dielectric having a relative permittivity greater than about 8 overlying the diode body region;
a diode electrode overlying the diode dielectric; and
a p-doped region and an n-doped region oppositely adjacent to the diode body region.
20. The circuit of claim 19 wherein the p-doped region of the diode is electrically coupled to the I/O pad and the n-doped region of the diode is electrically coupled to the reference voltage node.
21. The circuit of claim 19 wherein the n-doped region of the diode is electrically coupled to the I/O pad and the p-doped region of the diode is electrically coupled to the reference voltage node.
22. The circuit of claim 18 and further comprising a second diode coupled between the I/O pad and a second reference voltage node.
23. The circuit of claim 22 wherein the second diode comprises:
a diode body region;
a diode dielectric having a relative permittivity greater than about 8 overlying the diode body region;
a diode electrode overlying the diode dielectric; and
a p-doped region and an n-doped region oppositely adjacent to the diode body region.
24. The circuit of claim 22 and further comprising:
a second circuit; and
a second resistor coupled between the second circuit and the I/O pad, the second resistor comprising a body region, a first contact region adjacent the body region to electrically couple the body region to the I/O pad, a second contact region adjacent the body region to electrically couple the body region to the second circuit, a dielectric layer having a relative permittivity greater than about 8 overlying the body region, and an electrode overlying the dielectric layer.
25. The circuit of claim 24 wherein the circuit comprises an output circuit and wherein the second circuit comprises an input circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/451,045 US20060226487A1 (en) | 2003-08-18 | 2006-06-12 | Resistor with reduced leakage |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US49631003P | 2003-08-18 | 2003-08-18 | |
US10/667,871 US7071052B2 (en) | 2003-08-18 | 2003-09-22 | Resistor with reduced leakage |
US11/451,045 US20060226487A1 (en) | 2003-08-18 | 2006-06-12 | Resistor with reduced leakage |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/667,871 Division US7071052B2 (en) | 2003-08-18 | 2003-09-22 | Resistor with reduced leakage |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060226487A1 true US20060226487A1 (en) | 2006-10-12 |
Family
ID=36102706
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/667,871 Expired - Lifetime US7071052B2 (en) | 2003-08-18 | 2003-09-22 | Resistor with reduced leakage |
US11/451,045 Abandoned US20060226487A1 (en) | 2003-08-18 | 2006-06-12 | Resistor with reduced leakage |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/667,871 Expired - Lifetime US7071052B2 (en) | 2003-08-18 | 2003-09-22 | Resistor with reduced leakage |
Country Status (4)
Country | Link |
---|---|
US (2) | US7071052B2 (en) |
CN (2) | CN1624927A (en) |
SG (1) | SG118214A1 (en) |
TW (1) | TWI231988B (en) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7176129B2 (en) * | 2001-11-20 | 2007-02-13 | The Regents Of The University Of California | Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications |
US20050062131A1 (en) * | 2003-09-24 | 2005-03-24 | Murduck James Matthew | A1/A1Ox/A1 resistor process for integrated circuits |
US7172930B2 (en) * | 2004-07-02 | 2007-02-06 | International Business Machines Corporation | Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer |
US7544545B2 (en) * | 2005-12-28 | 2009-06-09 | Vishay-Siliconix | Trench polysilicon diode |
US8558278B2 (en) | 2007-01-16 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with optimized drive current and method of forming |
US7943961B2 (en) | 2008-03-13 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
US7902000B2 (en) * | 2008-06-04 | 2011-03-08 | International Business Machines Corporation | MugFET with stub source and drain regions |
US7808051B2 (en) | 2008-09-29 | 2010-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell without OD space effect in Y-direction |
US7977743B2 (en) | 2009-02-25 | 2011-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alternating-doping profile for source/drain of a FET |
US8053809B2 (en) * | 2009-05-26 | 2011-11-08 | International Business Machines Corporation | Device including high-K metal gate finfet and resistive structure and method of forming thereof |
US8343819B2 (en) | 2010-01-14 | 2013-01-01 | International Business Machines Corporation | Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same |
US8648438B2 (en) | 2011-10-03 | 2014-02-11 | International Business Machines Corporation | Structure and method to form passive devices in ETSOI process flow |
US20130270647A1 (en) * | 2012-04-17 | 2013-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for nfet with high k metal gate |
US9496325B2 (en) * | 2012-06-26 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate resistor and method of making same |
KR102191221B1 (en) | 2014-09-23 | 2020-12-16 | 삼성전자주식회사 | Resistor and semiconductor device including the same |
US10937872B1 (en) * | 2019-08-07 | 2021-03-02 | Vanguard International Semiconductor Corporation | Semiconductor structures |
CN111916728B (en) * | 2020-07-15 | 2022-09-23 | 中国科学院宁波材料技术与工程研究所 | Electrochemical doping method of lithium-rich manganese-based positive electrode material and lithium-rich manganese-based positive electrode material doped with lithium-rich manganese-based positive electrode material |
Citations (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4892614A (en) * | 1986-07-07 | 1990-01-09 | Texas Instruments Incorporated | Integrated circuit isolation process |
US4952993A (en) * | 1987-07-16 | 1990-08-28 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US5130773A (en) * | 1989-06-30 | 1992-07-14 | Hitachi, Ltd. | Semiconductor device with photosensitivity |
US5273915A (en) * | 1992-10-05 | 1993-12-28 | Motorola, Inc. | Method for fabricating bipolar junction and MOS transistors on SOI |
US5338960A (en) * | 1992-08-05 | 1994-08-16 | Harris Corporation | Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures |
US5525828A (en) * | 1991-10-31 | 1996-06-11 | International Business Machines Corporation | High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields |
US5596529A (en) * | 1993-11-30 | 1997-01-21 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US5656524A (en) * | 1994-05-06 | 1997-08-12 | Texas Instruments Incorporated | Method of forming a polysilicon resistor using an oxide, nitride stack |
US5965917A (en) * | 1999-01-04 | 1999-10-12 | Advanced Micro Devices, Inc. | Structure and method of formation of body contacts in SOI MOSFETS to elimate floating body effects |
US5972722A (en) * | 1998-04-14 | 1999-10-26 | Texas Instruments Incorporated | Adhesion promoting sacrificial etch stop layer in advanced capacitor structures |
US6015990A (en) * | 1997-02-27 | 2000-01-18 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of manufacturing the same |
US6027988A (en) * | 1997-05-28 | 2000-02-22 | The Regents Of The University Of California | Method of separating films from bulk substrates by plasma immersion ion implantation |
US6096591A (en) * | 1997-06-30 | 2000-08-01 | Advanced Micro Devices, Inc. | Method of making an IGFET and a protected resistor with reduced processing steps |
US6100204A (en) * | 1998-07-28 | 2000-08-08 | Advanced Micro Devices, Inc. | Method of making ultra thin gate oxide using aluminum oxide |
US6100153A (en) * | 1998-01-20 | 2000-08-08 | International Business Machines Corporation | Reliable diffusion resistor and diffusion capacitor |
US6103599A (en) * | 1997-07-25 | 2000-08-15 | Silicon Genesis Corporation | Planarizing technique for multilayered substrates |
US6107125A (en) * | 1997-06-18 | 2000-08-22 | International Business Machines Corporation | SOI/bulk hybrid substrate and method of forming the same |
US6190996B1 (en) * | 1997-11-12 | 2001-02-20 | Micron Technology, Inc. | Method of making an insulator for electrical structures |
US6281059B1 (en) * | 2000-05-11 | 2001-08-28 | Worldwide Semiconductor Manufacturing Corp. | Method of doing ESD protective device ion implant without additional photo mask |
US20010028089A1 (en) * | 2000-04-04 | 2001-10-11 | Adan Alberto O. | Semiconductor device of SOI structure |
US6303479B1 (en) * | 1999-12-16 | 2001-10-16 | Spinnaker Semiconductor, Inc. | Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts |
US20020008289A1 (en) * | 2000-07-24 | 2002-01-24 | Junichi Murota | Mosfet with strained channel layer |
US20020045318A1 (en) * | 1999-04-09 | 2002-04-18 | Coming Chen | Method for manufacturing mos transistor |
US6420218B1 (en) * | 2000-04-24 | 2002-07-16 | Advanced Micro Devices, Inc. | Ultra-thin-body SOI MOS transistors having recessed source and drain regions |
US6433382B1 (en) * | 1995-04-06 | 2002-08-13 | Motorola, Inc. | Split-gate vertically oriented EEPROM device and process |
US6448613B1 (en) * | 2000-01-07 | 2002-09-10 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with minimized parasitic Miller capacitance |
US20020163036A1 (en) * | 2001-05-01 | 2002-11-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor Device |
US6489684B1 (en) * | 2001-05-14 | 2002-12-03 | Taiwan Semiconductor Manufacturing Company | Reduction of electromigration in dual damascene connector |
US6498359B2 (en) * | 2000-05-22 | 2002-12-24 | Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V. | Field-effect transistor based on embedded cluster structures and process for its production |
US6531741B1 (en) * | 1999-03-03 | 2003-03-11 | International Business Machines Corporation | Dual buried oxide film SOI structure and method of manufacturing the same |
US6541343B1 (en) * | 1999-12-30 | 2003-04-01 | Intel Corporation | Methods of making field effect transistor structure with partially isolated source/drain junctions |
US20030080388A1 (en) * | 2001-10-29 | 2003-05-01 | Power Integrations, Inc. | Lateral power mosfet for high switching speeds |
US20030098479A1 (en) * | 1999-12-30 | 2003-05-29 | Anand Murthy | Novel MOS transistor structure and method of fabrication |
US6586311B2 (en) * | 2001-04-25 | 2003-07-01 | Advanced Micro Devices, Inc. | Salicide block for silicon-on-insulator (SOI) applications |
US20030183880A1 (en) * | 2002-03-27 | 2003-10-02 | Yoshiro Goto | Semiconductor device covering transistor and resistance with capacitor material |
US6657259B2 (en) * | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
US6674100B2 (en) * | 1996-09-17 | 2004-01-06 | Matsushita Electric Industrial Co., Ltd. | SiGeC-based CMOSFET with separate heterojunctions |
US20040016972A1 (en) * | 2002-07-29 | 2004-01-29 | Dinkar Singh | Enhanced t-gate structure for modulation doped field effect transistors |
US6686247B1 (en) * | 2002-08-22 | 2004-02-03 | Intel Corporation | Self-aligned contacts to gates |
US6690082B2 (en) * | 2001-09-28 | 2004-02-10 | Agere Systems Inc. | High dopant concentration diffused resistor and method of manufacture therefor |
US20040070035A1 (en) * | 2001-11-01 | 2004-04-15 | Anand Murthy | Semiconductor transistor having a stressed channel |
US20040087098A1 (en) * | 2002-11-01 | 2004-05-06 | Chartered Semiconductor Manufacturing Ltd. | Mim and metal resistor formation at cu beol using only one extra mask |
US6737710B2 (en) * | 1999-06-30 | 2004-05-18 | Intel Corporation | Transistor structure having silicide source/drain extensions |
US6784101B1 (en) * | 2002-05-16 | 2004-08-31 | Advanced Micro Devices Inc | Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation |
US20040179391A1 (en) * | 2003-03-11 | 2004-09-16 | Arup Bhattacharyya | Electronic systems, constructions for detecting properties of objects, and assemblies for identifying persons |
US6798021B2 (en) * | 2002-05-23 | 2004-09-28 | Renesas Technology Corp. | Transistor having a graded active layer and an SOI based capacitor |
US6812103B2 (en) * | 2002-06-20 | 2004-11-02 | Micron Technology, Inc. | Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects |
US20040217448A1 (en) * | 2002-08-26 | 2004-11-04 | Yukihiro Kumagai | Semiconductor device |
US6821840B2 (en) * | 2002-09-02 | 2004-11-23 | Advanced Micro Devices, Inc. | Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area |
US20040266116A1 (en) * | 2003-06-26 | 2004-12-30 | Rj Mears, Llc | Methods of fabricating semiconductor structures having improved conductivity effective mass |
US20040262683A1 (en) * | 2003-06-27 | 2004-12-30 | Bohr Mark T. | PMOS transistor strain optimization with raised junction regions |
US20050029601A1 (en) * | 2003-08-04 | 2005-02-10 | International Business Machines Corporation | Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions |
US6867101B1 (en) * | 2001-04-04 | 2005-03-15 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having a nitride/high-k/nitride gate dielectric stack by atomic layer deposition (ALD) and a device thereby formed |
US6872610B1 (en) * | 2003-11-18 | 2005-03-29 | Texas Instruments Incorporated | Method for preventing polysilicon mushrooming during selective epitaxial processing |
US20050121727A1 (en) * | 2001-11-26 | 2005-06-09 | Norio Ishitsuka | Semiconductor device and manufacturing method |
US6924181B2 (en) * | 2003-02-13 | 2005-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Strained silicon layer semiconductor product employing strained insulator layer |
US20050224986A1 (en) * | 2004-04-06 | 2005-10-13 | Horng-Huei Tseng | Stable metal structure with tungsten plug |
US20050236694A1 (en) * | 2004-04-27 | 2005-10-27 | Zhen-Cheng Wu | Silicon oxycarbide and silicon carbonitride based materials for MOS devices |
US6969618B2 (en) * | 2002-08-23 | 2005-11-29 | Micron Technology, Inc. | SOI device having increased reliability and reduced free floating body effects |
US20060001073A1 (en) * | 2003-05-21 | 2006-01-05 | Jian Chen | Use of voids between elements in semiconductor structures for isolation |
Family Cites Families (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US153549A (en) * | 1874-07-28 | Improvement in automatic gas lighters and extinguishers | ||
US30091A (en) * | 1860-09-18 | Shutter-bolt | ||
US4069094A (en) | 1976-12-30 | 1978-01-17 | Rca Corporation | Method of manufacturing apertured aluminum oxide substrates |
JPS551103A (en) | 1978-06-06 | 1980-01-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor resistor |
US4497683A (en) | 1982-05-03 | 1985-02-05 | At&T Bell Laboratories | Process for producing dielectrically isolated silicon devices |
US4631803A (en) | 1985-02-14 | 1986-12-30 | Texas Instruments Incorporated | Method of fabricating defect free trench isolation devices |
US4946799A (en) | 1988-07-08 | 1990-08-07 | Texas Instruments, Incorporated | Process for making high performance silicon-on-insulator transistor with body node to source node connection |
US5155571A (en) | 1990-08-06 | 1992-10-13 | The Regents Of The University Of California | Complementary field effect transistors having strained superlattice structure |
JP3019430B2 (en) | 1991-01-21 | 2000-03-13 | ソニー株式会社 | Semiconductor integrated circuit device |
US5461250A (en) | 1992-08-10 | 1995-10-24 | International Business Machines Corporation | SiGe thin film or SOI MOSFET and method for making the same |
US5534713A (en) | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
US5479033A (en) | 1994-05-27 | 1995-12-26 | Sandia Corporation | Complementary junction heterostructure field-effect transistor |
US5447884A (en) | 1994-06-29 | 1995-09-05 | International Business Machines Corporation | Shallow trench isolation with thin nitride liner |
US5629544A (en) | 1995-04-25 | 1997-05-13 | International Business Machines Corporation | Semiconductor diode with silicide films and trench isolation |
US5955766A (en) | 1995-06-12 | 1999-09-21 | Kabushiki Kaisha Toshiba | Diode with controlled breakdown |
US5708288A (en) | 1995-11-02 | 1998-01-13 | Motorola, Inc. | Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method |
TW335558B (en) | 1996-09-03 | 1998-07-01 | Ibm | High temperature superconductivity in strained SiSiGe |
US5789807A (en) | 1996-10-15 | 1998-08-04 | International Business Machines Corporation | On-chip power distribution for improved decoupling |
US5811857A (en) | 1996-10-22 | 1998-09-22 | International Business Machines Corporation | Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications |
US5763315A (en) | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
US5714777A (en) | 1997-02-19 | 1998-02-03 | International Business Machines Corporation | Si/SiGe vertical junction field effect transistor |
US5906951A (en) | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
DE19720008A1 (en) | 1997-05-13 | 1998-11-19 | Siemens Ag | Integrated CMOS circuit arrangement and method for its production |
WO1998059365A1 (en) | 1997-06-24 | 1998-12-30 | Massachusetts Institute Of Technology | CONTROLLING THREADING DISLOCATION DENSITIES IN Ge ON Si USING GRADED GeSi LAYERS AND PLANARIZATION |
US6221709B1 (en) | 1997-06-30 | 2001-04-24 | Stmicroelectronics, Inc. | Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor |
EP0923116A1 (en) | 1997-12-12 | 1999-06-16 | STMicroelectronics S.r.l. | Process for manufacturing integrated multi-crystal silicon resistors in MOS technology and integrated MOS device comprising multi-crystal silicon resistors |
JP3265569B2 (en) | 1998-04-15 | 2002-03-11 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US6558998B2 (en) | 1998-06-15 | 2003-05-06 | Marc Belleville | SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit |
JP3403076B2 (en) | 1998-06-30 | 2003-05-06 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US6387739B1 (en) | 1998-08-07 | 2002-05-14 | International Business Machines Corporation | Method and improved SOI body contact structure for transistors |
US6008095A (en) | 1998-08-07 | 1999-12-28 | Advanced Micro Devices, Inc. | Process for formation of isolation trenches with high-K gate dielectrics |
US6015993A (en) | 1998-08-31 | 2000-01-18 | International Business Machines Corporation | Semiconductor diode with depleted polysilicon gate structure and method |
JP2000132990A (en) | 1998-10-27 | 2000-05-12 | Fujitsu Ltd | Redundant judging circuit, semiconductor memory apparatus and redundant judge method |
US6258664B1 (en) | 1999-02-16 | 2001-07-10 | Micron Technology, Inc. | Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions |
US6358791B1 (en) | 1999-06-04 | 2002-03-19 | International Business Machines Corporation | Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby |
US6362082B1 (en) | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
US6339232B1 (en) | 1999-09-20 | 2002-01-15 | Kabushika Kaisha Toshiba | Semiconductor device |
TW503439B (en) | 2000-01-21 | 2002-09-21 | United Microelectronics Corp | Combination structure of passive element and logic circuit on silicon on insulator wafer |
US6475838B1 (en) | 2000-03-14 | 2002-11-05 | International Business Machines Corporation | Methods for forming decoupling capacitors |
US6359791B1 (en) * | 2000-03-23 | 2002-03-19 | Special Product Company | High density telecommunications enclosure and mounting assembly |
JP2001338988A (en) | 2000-05-25 | 2001-12-07 | Hitachi Ltd | Semiconductor device and its manufacturing method |
US6555839B2 (en) | 2000-05-26 | 2003-04-29 | Amberwave Systems Corporation | Buried channel strained silicon FET using a supply layer created through ion implantation |
JP3843708B2 (en) | 2000-07-14 | 2006-11-08 | 日本電気株式会社 | Semiconductor device, manufacturing method thereof, and thin film capacitor |
US6429061B1 (en) | 2000-07-26 | 2002-08-06 | International Business Machines Corporation | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation |
FR2812764B1 (en) | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | METHOD FOR MANUFACTURING SUBSTRATE OF SUBSTRATE-SELF-INSULATION OR SUBSTRATE-ON-VACUUM AND DEVICE OBTAINED |
JP2002076287A (en) | 2000-08-28 | 2002-03-15 | Nec Kansai Ltd | Semiconductor device and its manufacturing method |
JP4044276B2 (en) | 2000-09-28 | 2008-02-06 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US6413802B1 (en) | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
AU2002228779A1 (en) | 2000-12-04 | 2002-06-18 | Amberwave Systems Corporation | Cmos inverter circuits utilizing strained silicon surface channel mosfets |
US6414355B1 (en) | 2001-01-26 | 2002-07-02 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness |
US6894324B2 (en) | 2001-02-15 | 2005-05-17 | United Microelectronics Corp. | Silicon-on-insulator diodes and ESD protection circuits |
US6518610B2 (en) | 2001-02-20 | 2003-02-11 | Micron Technology, Inc. | Rhodium-rich oxygen barriers |
US6475869B1 (en) | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
US6593181B2 (en) | 2001-04-20 | 2003-07-15 | International Business Machines Corporation | Tailored insulator properties for devices |
US6952040B2 (en) | 2001-06-29 | 2005-10-04 | Intel Corporation | Transistor structure and method of fabrication |
US6576526B2 (en) | 2001-07-09 | 2003-06-10 | Chartered Semiconductor Manufacturing Ltd. | Darc layer for MIM process integration |
AU2002331077A1 (en) | 2001-08-13 | 2003-03-03 | Amberwave Systems Corporation | Dram trench capacitor and method of making the same |
US6521952B1 (en) | 2001-10-22 | 2003-02-18 | United Microelectronics Corp. | Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection |
US6657276B1 (en) | 2001-12-10 | 2003-12-02 | Advanced Micro Devices, Inc. | Shallow trench isolation (STI) region with high-K liner and method of formation |
US6600170B1 (en) | 2001-12-17 | 2003-07-29 | Advanced Micro Devices, Inc. | CMOS with strained silicon channel NMOS and silicon germanium channel PMOS |
US7138310B2 (en) | 2002-06-07 | 2006-11-21 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
US6617643B1 (en) | 2002-06-28 | 2003-09-09 | Mcnc | Low power tunneling metal-oxide-semiconductor (MOS) device |
US6573172B1 (en) | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
US6720619B1 (en) | 2002-12-13 | 2004-04-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices |
US6919233B2 (en) | 2002-12-31 | 2005-07-19 | Texas Instruments Incorporated | MIM capacitors and methods for fabricating same |
US6921913B2 (en) | 2003-03-04 | 2005-07-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel transistor structure with lattice-mismatched zone |
US6794764B1 (en) | 2003-03-05 | 2004-09-21 | Advanced Micro Devices, Inc. | Charge-trapping memory arrays resistant to damage from contact hole information |
US6762448B1 (en) | 2003-04-03 | 2004-07-13 | Advanced Micro Devices, Inc. | FinFET device with multiple fin structures |
-
2003
- 2003-09-22 US US10/667,871 patent/US7071052B2/en not_active Expired - Lifetime
- 2003-11-27 SG SG200306932A patent/SG118214A1/en unknown
-
2004
- 2004-04-12 TW TW093110079A patent/TWI231988B/en active
- 2004-08-17 CN CNA2004100582297A patent/CN1624927A/en active Pending
- 2004-08-17 CN CNU2004200772827U patent/CN2731713Y/en not_active Expired - Lifetime
-
2006
- 2006-06-12 US US11/451,045 patent/US20060226487A1/en not_active Abandoned
Patent Citations (67)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4892614A (en) * | 1986-07-07 | 1990-01-09 | Texas Instruments Incorporated | Integrated circuit isolation process |
US4952993A (en) * | 1987-07-16 | 1990-08-28 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US5130773A (en) * | 1989-06-30 | 1992-07-14 | Hitachi, Ltd. | Semiconductor device with photosensitivity |
US5525828A (en) * | 1991-10-31 | 1996-06-11 | International Business Machines Corporation | High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields |
US5338960A (en) * | 1992-08-05 | 1994-08-16 | Harris Corporation | Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures |
US5273915A (en) * | 1992-10-05 | 1993-12-28 | Motorola, Inc. | Method for fabricating bipolar junction and MOS transistors on SOI |
US5596529A (en) * | 1993-11-30 | 1997-01-21 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US5656524A (en) * | 1994-05-06 | 1997-08-12 | Texas Instruments Incorporated | Method of forming a polysilicon resistor using an oxide, nitride stack |
US6433382B1 (en) * | 1995-04-06 | 2002-08-13 | Motorola, Inc. | Split-gate vertically oriented EEPROM device and process |
US6674100B2 (en) * | 1996-09-17 | 2004-01-06 | Matsushita Electric Industrial Co., Ltd. | SiGeC-based CMOSFET with separate heterojunctions |
US6015990A (en) * | 1997-02-27 | 2000-01-18 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of manufacturing the same |
US6027988A (en) * | 1997-05-28 | 2000-02-22 | The Regents Of The University Of California | Method of separating films from bulk substrates by plasma immersion ion implantation |
US6107125A (en) * | 1997-06-18 | 2000-08-22 | International Business Machines Corporation | SOI/bulk hybrid substrate and method of forming the same |
US6096591A (en) * | 1997-06-30 | 2000-08-01 | Advanced Micro Devices, Inc. | Method of making an IGFET and a protected resistor with reduced processing steps |
US6103599A (en) * | 1997-07-25 | 2000-08-15 | Silicon Genesis Corporation | Planarizing technique for multilayered substrates |
US6190996B1 (en) * | 1997-11-12 | 2001-02-20 | Micron Technology, Inc. | Method of making an insulator for electrical structures |
US6489215B2 (en) * | 1997-11-12 | 2002-12-03 | Micron Technology, Inc. | Method of making insulator for electrical structures |
US6495900B1 (en) * | 1997-11-12 | 2002-12-17 | Micron Technology, Inc. | Insulator for electrical structure |
US6100153A (en) * | 1998-01-20 | 2000-08-08 | International Business Machines Corporation | Reliable diffusion resistor and diffusion capacitor |
US5972722A (en) * | 1998-04-14 | 1999-10-26 | Texas Instruments Incorporated | Adhesion promoting sacrificial etch stop layer in advanced capacitor structures |
US6100204A (en) * | 1998-07-28 | 2000-08-08 | Advanced Micro Devices, Inc. | Method of making ultra thin gate oxide using aluminum oxide |
US5965917A (en) * | 1999-01-04 | 1999-10-12 | Advanced Micro Devices, Inc. | Structure and method of formation of body contacts in SOI MOSFETS to elimate floating body effects |
US6531741B1 (en) * | 1999-03-03 | 2003-03-11 | International Business Machines Corporation | Dual buried oxide film SOI structure and method of manufacturing the same |
US20020045318A1 (en) * | 1999-04-09 | 2002-04-18 | Coming Chen | Method for manufacturing mos transistor |
US6737710B2 (en) * | 1999-06-30 | 2004-05-18 | Intel Corporation | Transistor structure having silicide source/drain extensions |
US6303479B1 (en) * | 1999-12-16 | 2001-10-16 | Spinnaker Semiconductor, Inc. | Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts |
US6541343B1 (en) * | 1999-12-30 | 2003-04-01 | Intel Corporation | Methods of making field effect transistor structure with partially isolated source/drain junctions |
US20030098479A1 (en) * | 1999-12-30 | 2003-05-29 | Anand Murthy | Novel MOS transistor structure and method of fabrication |
US6797556B2 (en) * | 1999-12-30 | 2004-09-28 | Intel Corporation | MOS transistor structure and method of fabrication |
US20030136985A1 (en) * | 1999-12-30 | 2003-07-24 | Murthy Anand S. | Field effect transistor structure with partially isolated source/drain junctions and methods of making same |
US6448613B1 (en) * | 2000-01-07 | 2002-09-10 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with minimized parasitic Miller capacitance |
US20010028089A1 (en) * | 2000-04-04 | 2001-10-11 | Adan Alberto O. | Semiconductor device of SOI structure |
US6420218B1 (en) * | 2000-04-24 | 2002-07-16 | Advanced Micro Devices, Inc. | Ultra-thin-body SOI MOS transistors having recessed source and drain regions |
US6281059B1 (en) * | 2000-05-11 | 2001-08-28 | Worldwide Semiconductor Manufacturing Corp. | Method of doing ESD protective device ion implant without additional photo mask |
US6498359B2 (en) * | 2000-05-22 | 2002-12-24 | Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V. | Field-effect transistor based on embedded cluster structures and process for its production |
US20020008289A1 (en) * | 2000-07-24 | 2002-01-24 | Junichi Murota | Mosfet with strained channel layer |
US6867101B1 (en) * | 2001-04-04 | 2005-03-15 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having a nitride/high-k/nitride gate dielectric stack by atomic layer deposition (ALD) and a device thereby formed |
US6586311B2 (en) * | 2001-04-25 | 2003-07-01 | Advanced Micro Devices, Inc. | Salicide block for silicon-on-insulator (SOI) applications |
US20020163036A1 (en) * | 2001-05-01 | 2002-11-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor Device |
US6489684B1 (en) * | 2001-05-14 | 2002-12-03 | Taiwan Semiconductor Manufacturing Company | Reduction of electromigration in dual damascene connector |
US6690082B2 (en) * | 2001-09-28 | 2004-02-10 | Agere Systems Inc. | High dopant concentration diffused resistor and method of manufacture therefor |
US20030080388A1 (en) * | 2001-10-29 | 2003-05-01 | Power Integrations, Inc. | Lateral power mosfet for high switching speeds |
US6885084B2 (en) * | 2001-11-01 | 2005-04-26 | Intel Corporation | Semiconductor transistor having a stressed channel |
US20040070035A1 (en) * | 2001-11-01 | 2004-04-15 | Anand Murthy | Semiconductor transistor having a stressed channel |
US20050121727A1 (en) * | 2001-11-26 | 2005-06-09 | Norio Ishitsuka | Semiconductor device and manufacturing method |
US6657259B2 (en) * | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
US20030183880A1 (en) * | 2002-03-27 | 2003-10-02 | Yoshiro Goto | Semiconductor device covering transistor and resistance with capacitor material |
US6784101B1 (en) * | 2002-05-16 | 2004-08-31 | Advanced Micro Devices Inc | Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation |
US6798021B2 (en) * | 2002-05-23 | 2004-09-28 | Renesas Technology Corp. | Transistor having a graded active layer and an SOI based capacitor |
US6812103B2 (en) * | 2002-06-20 | 2004-11-02 | Micron Technology, Inc. | Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects |
US20040140506A1 (en) * | 2002-07-29 | 2004-07-22 | International Business Machines Corporation | Enhanced T-gate structure for modulation doped field effect transistors |
US6740535B2 (en) * | 2002-07-29 | 2004-05-25 | International Business Machines Corporation | Enhanced T-gate structure for modulation doped field effect transistors |
US20040016972A1 (en) * | 2002-07-29 | 2004-01-29 | Dinkar Singh | Enhanced t-gate structure for modulation doped field effect transistors |
US6686247B1 (en) * | 2002-08-22 | 2004-02-03 | Intel Corporation | Self-aligned contacts to gates |
US6969618B2 (en) * | 2002-08-23 | 2005-11-29 | Micron Technology, Inc. | SOI device having increased reliability and reduced free floating body effects |
US20040217448A1 (en) * | 2002-08-26 | 2004-11-04 | Yukihiro Kumagai | Semiconductor device |
US6821840B2 (en) * | 2002-09-02 | 2004-11-23 | Advanced Micro Devices, Inc. | Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area |
US20040087098A1 (en) * | 2002-11-01 | 2004-05-06 | Chartered Semiconductor Manufacturing Ltd. | Mim and metal resistor formation at cu beol using only one extra mask |
US6924181B2 (en) * | 2003-02-13 | 2005-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Strained silicon layer semiconductor product employing strained insulator layer |
US20040179391A1 (en) * | 2003-03-11 | 2004-09-16 | Arup Bhattacharyya | Electronic systems, constructions for detecting properties of objects, and assemblies for identifying persons |
US20060001073A1 (en) * | 2003-05-21 | 2006-01-05 | Jian Chen | Use of voids between elements in semiconductor structures for isolation |
US20040266116A1 (en) * | 2003-06-26 | 2004-12-30 | Rj Mears, Llc | Methods of fabricating semiconductor structures having improved conductivity effective mass |
US20040262683A1 (en) * | 2003-06-27 | 2004-12-30 | Bohr Mark T. | PMOS transistor strain optimization with raised junction regions |
US20050029601A1 (en) * | 2003-08-04 | 2005-02-10 | International Business Machines Corporation | Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions |
US6872610B1 (en) * | 2003-11-18 | 2005-03-29 | Texas Instruments Incorporated | Method for preventing polysilicon mushrooming during selective epitaxial processing |
US20050224986A1 (en) * | 2004-04-06 | 2005-10-13 | Horng-Huei Tseng | Stable metal structure with tungsten plug |
US20050236694A1 (en) * | 2004-04-27 | 2005-10-27 | Zhen-Cheng Wu | Silicon oxycarbide and silicon carbonitride based materials for MOS devices |
Also Published As
Publication number | Publication date |
---|---|
US7071052B2 (en) | 2006-07-04 |
TWI231988B (en) | 2005-05-01 |
US20050040493A1 (en) | 2005-02-24 |
TW200509359A (en) | 2005-03-01 |
CN2731713Y (en) | 2005-10-05 |
CN1624927A (en) | 2005-06-08 |
SG118214A1 (en) | 2006-01-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20060226487A1 (en) | Resistor with reduced leakage | |
US7037772B2 (en) | Method of manufacturing an integrated circuit including capacitor with high permittivity capacitor dielectric | |
US7354843B2 (en) | Method of forming a capacitor that includes forming a bottom electrode in a strained silicon layer | |
US20050035410A1 (en) | Semiconductor diode with reduced leakage | |
US9240404B2 (en) | Embedded polysilicon resistor in integrated circuits formed by a replacement gate process | |
US6429066B1 (en) | Method for producing a polysilicon circuit element | |
KR100436475B1 (en) | Semiconductor diode with depleted polysilicon gate structure and method | |
US8803253B2 (en) | Replacement metal gate process for CMOS integrated circuits | |
US20070040222A1 (en) | Method and apparatus for improved ESD performance | |
US9831235B2 (en) | Method of making structure having a gate stack | |
US7755140B2 (en) | Process charging and electrostatic damage protection in silicon-on-insulator technology | |
JP5389022B2 (en) | Electrostatic discharge protection device and method for manufacturing semiconductor device including the same | |
US6664140B2 (en) | Methods for fabricating integrated circuit devices using antiparallel diodes to reduce damage during plasma processing | |
US20080036002A1 (en) | Semiconductor device and method of fabricating semiconductor device | |
US9331136B2 (en) | Integrated circuit and method of fabricating the same | |
US20050242399A1 (en) | MOSFET with electrostatic discharge protection structure and method of fabrication | |
US20210193692A1 (en) | Semiconductor device and method of forming the same | |
US7176529B2 (en) | Semiconductor device and method of manufacturing the same | |
US9058995B2 (en) | Self-protected drain-extended metal-oxide-semiconductor transistor | |
CN109103202B (en) | Semiconductor device and method for manufacturing the same | |
US6573576B2 (en) | Semiconductor device and method for fabricating the same | |
US20220293582A1 (en) | Gate dielectric layer protection | |
JP2658238B2 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |