US20060145196A1 - High-sensitivity image sensor and fabrication method thereof - Google Patents
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- US20060145196A1 US20060145196A1 US11/024,783 US2478304A US2006145196A1 US 20060145196 A1 US20060145196 A1 US 20060145196A1 US 2478304 A US2478304 A US 2478304A US 2006145196 A1 US2006145196 A1 US 2006145196A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
Definitions
- the present invention relates to an image sensor and, more particularly, to a high-sensitivity image sensor embodied on a silicon-on-insulator (hereinafter referred to as “SOI”), achieving a high sensitivity and a high degree of integration.
- SOI silicon-on-insulator
- an image sensor generally has stacked structure comprising a P-type silicon substrate 1 and an N-type silicon substrate 2 formed by epitaxial growth.
- the stacked structure also includes a photodiode 3 and a bipolar transistor 4 that functions as a circuit for processing a signal produced from the photodiode 3 .
- the N-type silicon substrate is divided into plural regions by P-type buried diffusion layers 5 .
- the photodiode 3 and the bipolar transistor 4 are provided in or on the plural regions of the N-type silicon substrate.
- the photodiode 3 is constructed by using a PN junction that is an interface between the P-type silicon substrate 1 and the N-type silicon substrate 2 .
- the bipolar transistor 4 has a P-type diffusion layer in the upper part of the N-type silicon substrate 2 .
- An N + -type diffusion layer 7 is placed from the surface of the N-type silicon substrate 2 to the upper part of the P-type silicon substrate 1 .
- An oxide layer 6 is provided on the entire surface of the N-type silicon substrate 2 .
- metal interconnects are connected to the N + -type diffusion layer 7 , and the P-type diffusion layer.
- the photosensitivity of this type of the photodiode depends on the photosensitivity of the PN junction as well as the absorption amount influenced by the size and the thickness of the photodiode.
- FIG. 1 b is a cross-sectional view illustrating an image sensor on an SOI wafer.
- the SOI wafer comprises a P-type silicon substrate 11 and an N-type silicon substrate 12 under which an N-type diffusion layer 19 is placed.
- An oxide layer 13 is positioned between the P-type silicon substrate 11 and the N-type diffusion layer 19 .
- the N-type silicon substrate 12 is divided into plural regions by trench-type isolation layers 14 .
- a photodiode 15 and a bipolar transistor 16 are provided in or on the plural regions of the N-type silicon substrate 12 .
- the trench-type isolation layers 14 extend from an oxide layer 17 positioned on the N ⁇ type silicon substrate 12 to the upper part of the oxide layer 13 .
- a P-type diffusion layer which acts as an active layer, is positioned near the surface of the N-type silicon substrate 12 .
- An N + -type diffusion layer 18 extends from the surface of N-type silicon substrate 12 to the N-type diffusion layer 19 .
- a conventional CMOS image sensor using a bulk-silicon substrate has a technical limitation in terms of the improvement of sensitivity and a noise characteristic, and the possibility that light-excited carriers can be created in undesirable region by light irradiation always remains. Furthermore, a presence of parasitic stray capacitance causes an increment of a noise and the degradation of operation speed, so that a characteristic of the sensor is deteriorated.
- a dark current component which is a type of leakage current generated when a depletion region of an intrinsic semiconductor is formed toward the substrate, works as a noise component of a photo-current. Such a characteristic decreases sensitivity of the sensor and a response speed of the photo current, so that a response speed to an incoming image gets to fall.
- an epitaxial silicon layer placed on a buried oxide layer is so thin that an operation of a high voltage transistor is difficult.
- the present invention is directed to a high sensitivity image sensor and fabrication method thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a method of fabricating a high-sensitivity image sensor embodied on a SOI, achieving a high sensitivity and a high degree of integration.
- Another object of the present invention is to provide a high-sensitivity image sensor embodied on a SOI, achieving a high sensitivity and a high degree of integration.
- a method of fabricating a high-sensitivity image sensor comprises: etching a predetermined region of active silicon and a buried oxide layer by using a mask over an SOI substrate to expose an N-type silicon substrate; implanting P-type ions into the exposed N-type silicon substrate to form a P-type region; forming crossed active silicon by patterning the rest of the active silicon not etched while the active silicon is etched to expose the N-type silicon substrate; implanting P-type ions into first two predetermined regions facing each other of the crossed active silicon to form P-type regions; implanting N-type ions into second two predetermined regions facing each other except for the P-type regions of the crossed active silicon to form N-type regions; forming a gate oxide layer and a gate electrode on the cross active silicon; and forming a connection part to connect the P-type region of the cross active silicon to the P-type region of the silicon substrate.
- a high-sensitivity image sensor comprises: a photodiode region having a PN junction between an N-type substrate and a P-type region thereon; a crossed monocrystalline active silicon at a distance to the photodiode region; source and drain regions in the first two end parts of the crossed monocrystalline active silicon; impurity regions in the second end parts except for the source and drain regions; a channel region between the source and drain regions; a gate oxide layer on the channel region; a gate electrode on the gate oxide layer; and a connection part connecting the impurity regions to the P-type region of the photodiode region.
- FIGS. 1 a and 1 b are image sensors fabricated in accordance with the prior art
- FIGS. 2 through 8 are cross-sectional views illustrating example processes of fabricating a high-sensitivity image sensor in accordance with the present invention
- FIG. 9 illustrates structure of a high-sensitivity image sensor in accordance with the present invention.
- FIG. 10 is a cross-sectional view illustrating operation principles of a high-sensitivity image sensor in accordance with the present invention.
- predetermined regions of active silicon 20 and a buried oxide layer 21 are etched by using a mask over an SOI substrate to expose an N-type silicon substrate 22 .
- the SOI substrate can be manufactured according to various kind of fabrication methods. Particularly, the SOI substrate manufactured by an SIMOX (separation by implanted oxygen) method has a characteristic that the active silicon on a buried oxide layer is monocrystalline.
- P-type ions are implanted into the exposed N-type silicon substrate 22 to form P-type regions 23 , so that a PN junction is completed.
- a photodiode is defined by the PN junction.
- the ion implantation is conducted to the sufficient depth for ensuring that irradiated light is converted to photoelectrons as much as possible.
- the shape of the photodiode is preferably buried-type so that a dark current can be minimized.
- crossed active silicon 24 is formed by patterning the rest of the active silicon 25 not etched while the active silicon is etched to expose the N-type silicon substrate 22 .
- the crossed active silicon 24 is a cross shape with four branches, each of which has a predetermined length as seen from the top.
- FIG. 5 a is a cross-sectional view illustrating the process that implants P-type ions into two end parts 26 facing each other of the crossed active silicon 24 to form P-type regions.
- FIG. 5 b is a top view illustrating a crossed active silicon region 27 . The P-type regions face each other and are connected to the P-type region 23 of the photodiode.
- FIG. 6 a is a cross-sectional view illustrating the process that implants N-type ions into two end parts of the crossed active silicon 24 except the P-type regions 26 to form N-type regions 28 as source and drain regions.
- FIG. 6 b is a top view illustrating the crossed active silicon region 27 .
- a gate electrode 29 is completed by patterning and etching the gate insulation layer and the silicon layer.
- the gate electrode has a narrower width than that of the region excluding the P-type regions and the N-type regions from the crossed active silicon region 27 .
- connection part 30 which connects the P-type region 26 of the crossed active silicon to the P-type region 23 of the photodiode, is completed.
- a photodiode region is shown, having the PN junction between the P-type silicon substrate 23 and the N-type silicon substrate 22 .
- the monocrystalline active silicon is originated from the construction of the SOI substrate.
- the P-type regions 26 which are formed by implanting P-type ions into two end parts facing each other out of four end parts of the crossed active silicon 24 , are also shown.
- the P-type regions of the photodiode and the crossed monocrystalline active silicon are tied by the connection part 30 .
- the N-type regions 28 are presented in two end parts of the crossed active silicon region not occupied by the P-type regions 26 and defined as source and drain regions.
- the gate oxide layer (not shown) and the gate electrode 29 are positioned on the crossed monocrystalline active silicon.
- the gate electrode 29 has a narrower width than that of the region excluding the P-type regions and the N-type regions from the crossed active silicon region 27 .
- FIG. 10 is a cross-sectional view illustrating the operation principle of a high-sensitivity image sensor in accordance with the present invention.
- Light is irradiated 31 on the photodiode region.
- a light shield screen 32 is provided to prevent light from being irradiated on the region except for the photodiode region.
- the light shield screen 32 is positioned over the crossed active silicon and the gate electrode, and preferably made of Al. Electron-hole pairs are created in the photodiode by the light irradiation.
- the holes move along the P-type regions 23 of the photodiode, the connection part 30 and the P-type regions 26 located in the end parts of the crossed monocrystalline active silicon, and are accumulated in the middle part 33 of the monocrystalline active silicon.
- the electrons move along the N-type substrate and are accumulated under a buried oxide layer 34 that is positioned below the middle part of the monocrystalline active silicon.
- a PNP lateral bipolar transistor (hereinafter referred to as “LBT”) is constructed by the source, the middle part of the monocrystalline active silicon and the drain, which are vertically positioned.
- LBT PNP lateral bipolar transistor
- a electrode is intentionally fabricated to adjust electric potential with light-excited pumping carriers in the neutral region under a channel of a photosensing transistor (or photo transistor) that produces a signal charge.
- the electrode is intended to send a signal to the photodiode positioned in the lower substrate so as to obtain a sufficient dynamic range and maximize the realization of an input color signal.
- the electrons which are light-excited minority carriers and accumulated under the buried oxide layer, function as a substrate bias, so that potential in the middle part of the monocrystalline active silicon is increased.
- the disclosed method using the SOI substrate reduces a dark current that occurs in an image sensor, a unit cell size and parasitic stray capacitance of the image sensor, so that the image sensor embodied by the illustrated method operates at a high speed and has a high sensitivity.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to an image sensor and, more particularly, to a high-sensitivity image sensor embodied on a silicon-on-insulator (hereinafter referred to as “SOI”), achieving a high sensitivity and a high degree of integration.
- 2. Background of the Related Art
- Referring to
FIG. 1 a, an image sensor generally has stacked structure comprising a P-type silicon substrate 1 and an N-type silicon substrate 2 formed by epitaxial growth. The stacked structure also includes aphotodiode 3 and abipolar transistor 4 that functions as a circuit for processing a signal produced from thephotodiode 3. The N-type silicon substrate is divided into plural regions by P-type burieddiffusion layers 5. Thephotodiode 3 and thebipolar transistor 4 are provided in or on the plural regions of the N-type silicon substrate. - The
photodiode 3 is constructed by using a PN junction that is an interface between the P-type silicon substrate 1 and the N-type silicon substrate 2. Thebipolar transistor 4 has a P-type diffusion layer in the upper part of the N-type silicon substrate 2. An N+-type diffusion layer 7 is placed from the surface of the N-type silicon substrate 2 to the upper part of the P-type silicon substrate 1. - An oxide layer 6 is provided on the entire surface of the N-
type silicon substrate 2. For the bipolar transistor, metal interconnects are connected to the N+-type diffusion layer 7, and the P-type diffusion layer. The photosensitivity of this type of the photodiode depends on the photosensitivity of the PN junction as well as the absorption amount influenced by the size and the thickness of the photodiode. -
FIG. 1 b is a cross-sectional view illustrating an image sensor on an SOI wafer. The SOI wafer comprises a P-type silicon substrate 11 and an N-type silicon substrate 12 under which an N-type diffusion layer 19 is placed. Anoxide layer 13 is positioned between the P-type silicon substrate 11 and the N-type diffusion layer 19. - The N-
type silicon substrate 12 is divided into plural regions by trench-type isolation layers 14. Aphotodiode 15 and abipolar transistor 16 are provided in or on the plural regions of the N-type silicon substrate 12. The trench-type isolation layers 14 extend from anoxide layer 17 positioned on the N−type silicon substrate 12 to the upper part of theoxide layer 13. - For the
photodiode 15, a P-type diffusion layer which acts as an active layer, is positioned near the surface of the N-type silicon substrate 12. An N+-type diffusion layer 18 extends from the surface of N-type silicon substrate 12 to the N-type diffusion layer 19. - A conventional CMOS image sensor using a bulk-silicon substrate has a technical limitation in terms of the improvement of sensitivity and a noise characteristic, and the possibility that light-excited carriers can be created in undesirable region by light irradiation always remains. Furthermore, a presence of parasitic stray capacitance causes an increment of a noise and the degradation of operation speed, so that a characteristic of the sensor is deteriorated. In detail, for the CMOS image sensor using a bulk-silicon substrate, a dark current component, which is a type of leakage current generated when a depletion region of an intrinsic semiconductor is formed toward the substrate, works as a noise component of a photo-current. Such a characteristic decreases sensitivity of the sensor and a response speed of the photo current, so that a response speed to an incoming image gets to fall.
- Moreover, for a CMOS image sensor using a conventional SOI substrate, an epitaxial silicon layer placed on a buried oxide layer is so thin that an operation of a high voltage transistor is difficult.
- Accordingly, the present invention is directed to a high sensitivity image sensor and fabrication method thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a method of fabricating a high-sensitivity image sensor embodied on a SOI, achieving a high sensitivity and a high degree of integration.
- Another object of the present invention is to provide a high-sensitivity image sensor embodied on a SOI, achieving a high sensitivity and a high degree of integration.
- To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method of fabricating a high-sensitivity image sensor comprises: etching a predetermined region of active silicon and a buried oxide layer by using a mask over an SOI substrate to expose an N-type silicon substrate; implanting P-type ions into the exposed N-type silicon substrate to form a P-type region; forming crossed active silicon by patterning the rest of the active silicon not etched while the active silicon is etched to expose the N-type silicon substrate; implanting P-type ions into first two predetermined regions facing each other of the crossed active silicon to form P-type regions; implanting N-type ions into second two predetermined regions facing each other except for the P-type regions of the crossed active silicon to form N-type regions; forming a gate oxide layer and a gate electrode on the cross active silicon; and forming a connection part to connect the P-type region of the cross active silicon to the P-type region of the silicon substrate. A high-sensitivity image sensor comprises: a photodiode region having a PN junction between an N-type substrate and a P-type region thereon; a crossed monocrystalline active silicon at a distance to the photodiode region; source and drain regions in the first two end parts of the crossed monocrystalline active silicon; impurity regions in the second end parts except for the source and drain regions; a channel region between the source and drain regions; a gate oxide layer on the channel region; a gate electrode on the gate oxide layer; and a connection part connecting the impurity regions to the P-type region of the photodiode region.
- It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:
-
FIGS. 1 a and 1 b are image sensors fabricated in accordance with the prior art; -
FIGS. 2 through 8 are cross-sectional views illustrating example processes of fabricating a high-sensitivity image sensor in accordance with the present invention; -
FIG. 9 illustrates structure of a high-sensitivity image sensor in accordance with the present invention; -
FIG. 10 is a cross-sectional view illustrating operation principles of a high-sensitivity image sensor in accordance with the present invention. - Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
- First, referring to
FIG. 2 , predetermined regions of active silicon 20 and a buried oxide layer 21 are etched by using a mask over an SOI substrate to expose an N-type silicon substrate 22. The SOI substrate can be manufactured according to various kind of fabrication methods. Particularly, the SOI substrate manufactured by an SIMOX (separation by implanted oxygen) method has a characteristic that the active silicon on a buried oxide layer is monocrystalline. - Referring to
FIG. 3 , P-type ions are implanted into the exposed N-type silicon substrate 22 to form P-type regions 23, so that a PN junction is completed. A photodiode is defined by the PN junction. The ion implantation is conducted to the sufficient depth for ensuring that irradiated light is converted to photoelectrons as much as possible. In addition, the shape of the photodiode is preferably buried-type so that a dark current can be minimized. - Referring to
FIGS. 4 a and 4 b, crossed active silicon 24 is formed by patterning the rest of theactive silicon 25 not etched while the active silicon is etched to expose the N-type silicon substrate 22. The crossed active silicon 24 is a cross shape with four branches, each of which has a predetermined length as seen from the top. -
FIG. 5 a is a cross-sectional view illustrating the process that implants P-type ions into twoend parts 26 facing each other of the crossed active silicon 24 to form P-type regions.FIG. 5 b is a top view illustrating a crossedactive silicon region 27. The P-type regions face each other and are connected to the P-type region 23 of the photodiode. -
FIG. 6 a is a cross-sectional view illustrating the process that implants N-type ions into two end parts of the crossed active silicon 24 except the P-type regions 26 to form N-type regions 28 as source and drain regions.FIG. 6 b is a top view illustrating the crossedactive silicon region 27. - Referring to
FIG. 7 , after a gate insulation layer and a silicon layer are sequentially provided on the crossed active silicon 24, agate electrode 29 is completed by patterning and etching the gate insulation layer and the silicon layer. The gate electrode has a narrower width than that of the region excluding the P-type regions and the N-type regions from the crossedactive silicon region 27. - Referring to
FIG. 8 , aconnection part 30, which connects the P-type region 26 of the crossed active silicon to the P-type region 23 of the photodiode, is completed. - Referring to
FIG. 9 , a photodiode region is shown, having the PN junction between the P-type silicon substrate 23 and the N-type silicon substrate 22. A crossed monocrystallineactive silicon region 25 formed by etching the monocrystalline active silicon, which lies at a distance to the photodiode region on the SOI substrate, is presented. The monocrystalline active silicon is originated from the construction of the SOI substrate. The P-type regions 26, which are formed by implanting P-type ions into two end parts facing each other out of four end parts of the crossed active silicon 24, are also shown. The P-type regions of the photodiode and the crossed monocrystalline active silicon are tied by theconnection part 30. The N-type regions 28 are presented in two end parts of the crossed active silicon region not occupied by the P-type regions 26 and defined as source and drain regions. The gate oxide layer (not shown) and thegate electrode 29 are positioned on the crossed monocrystalline active silicon. Thegate electrode 29 has a narrower width than that of the region excluding the P-type regions and the N-type regions from the crossedactive silicon region 27. -
FIG. 10 is a cross-sectional view illustrating the operation principle of a high-sensitivity image sensor in accordance with the present invention. Light is irradiated 31 on the photodiode region. Alight shield screen 32 is provided to prevent light from being irradiated on the region except for the photodiode region. Thelight shield screen 32 is positioned over the crossed active silicon and the gate electrode, and preferably made of Al. Electron-hole pairs are created in the photodiode by the light irradiation. The holes move along the P-type regions 23 of the photodiode, theconnection part 30 and the P-type regions 26 located in the end parts of the crossed monocrystalline active silicon, and are accumulated in themiddle part 33 of the monocrystalline active silicon. The electrons move along the N-type substrate and are accumulated under a buriedoxide layer 34 that is positioned below the middle part of the monocrystalline active silicon. - If a certain amount of the holes are accumulated in the
middle part 33 of the monocrystalline active silicon, a PNP lateral bipolar transistor (hereinafter referred to as “LBT”) is constructed by the source, the middle part of the monocrystalline active silicon and the drain, which are vertically positioned. Thus, the PNP LBT may effectively operate. In detail, a electrode is intentionally fabricated to adjust electric potential with light-excited pumping carriers in the neutral region under a channel of a photosensing transistor (or photo transistor) that produces a signal charge. The electrode is intended to send a signal to the photodiode positioned in the lower substrate so as to obtain a sufficient dynamic range and maximize the realization of an input color signal. The electrons, which are light-excited minority carriers and accumulated under the buried oxide layer, function as a substrate bias, so that potential in the middle part of the monocrystalline active silicon is increased. - Accordingly, the disclosed method using the SOI substrate reduces a dark current that occurs in an image sensor, a unit cell size and parasitic stray capacitance of the image sensor, so that the image sensor embodied by the illustrated method operates at a high speed and has a high sensitivity.
- It is noted that this patent claims priority from Korean Patent Application Serial Number 10-2003-0087286, which was filed on Dec. 31, 2003, and is hereby incorporated by reference in its entirety.
- The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teachings can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.
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