US20060124981A1 - DRAM technology compatible processor/memory chips - Google Patents
DRAM technology compatible processor/memory chips Download PDFInfo
- Publication number
- US20060124981A1 US20060124981A1 US11/347,989 US34798906A US2006124981A1 US 20060124981 A1 US20060124981 A1 US 20060124981A1 US 34798906 A US34798906 A US 34798906A US 2006124981 A1 US2006124981 A1 US 2006124981A1
- Authority
- US
- United States
- Prior art keywords
- logic
- electronic system
- logic plane
- volatile memory
- memory cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000005516 engineering process Methods 0.000 title description 16
- 239000003990 capacitor Substances 0.000 claims abstract description 112
- 230000006870 function Effects 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims description 27
- 229910044991 metal oxide Inorganic materials 0.000 claims description 17
- 150000004706 metal oxides Chemical class 0.000 claims description 17
- 230000005669 field effect Effects 0.000 claims description 16
- 230000008878 coupling Effects 0.000 claims description 14
- 238000010168 coupling process Methods 0.000 claims description 14
- 238000005859 coupling reaction Methods 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000007667 floating Methods 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 claims description 6
- 230000005641 tunneling Effects 0.000 claims description 6
- 238000003491 array Methods 0.000 abstract description 8
- 238000012545 processing Methods 0.000 description 10
- 238000013459 approach Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000013386 optimize process Methods 0.000 description 5
- 229920000747 poly(lactic acid) Polymers 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 230000006386 memory function Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000135 prohibitive effect Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Definitions
- the present invention relates generally to semiconductor integrated circuits and, more particularly, to DRAM technology compatible processor/memory chips.
- DRAM Dynamic Random Access Memory
- EEPROM Electrically Erasable and Programmable Read Only Memory
- Flash memory Flash memory
- DRAM Dynamic Random Access Memory
- EEPROM Electrically Erasable and Programmable Read Only Memory
- PDA's Programmable Logic Arrays
- PLAs on a DRAM die would be well suited for memory address correction/repair by changing the addresses to remove faulty rows/columns, and replace them with functional ones.
- An example of a redundancy repair scheme is shown in U.S. Pat. # 5,324,681 issued Lowrey on Jun. 28, 1994. Another is provided in U.S. Pat. # 4,051,354 issued Choate on Sep. 27, 1997. Another is provide in U.S. Pat. # 5,327,380 issued Kersh III on Jul. 5, 1994. None of these, however, incorporate an optimized DRAM technology process flow. PLAs on a DRAM die would also be desirable for use as dedicated processors embedded on the DRAM chip.
- the present invention includes a compact non-volatile memory cell structure formed using a DRAM process technology.
- the present invention includes a programmable logic array having a first logic plane that receives a number of input signals.
- the first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs.
- a second logic plane is provided which has a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.
- Each non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET).
- Each non-volatile memory cell includes a stacked capacitor formed according to a dynamic random access memory (DRAM) process.
- DRAM dynamic random access memory
- each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET.
- Gate 112 includes a polysilicon gate 112 , a polycide gate 112 , salicided gate structure, or other conductive gate material as known to one of ordinary skill in the art of DRAM transistor fabrication.
- the channel region 114 couples a first diffused region 115 to a second diffused region 116 .
- the DRAM transistor is formed according to a conventional, DRAM optimized process flow, as is known to those of ordinary skill in the art of DRAM chip fabrication.
- capacitor 120 includes a stacked capacitor which is cup shaped 120 .
- the bottom plate 121 has interior walls 121 A and exterior walls 12 1 B.
- the capacitor dielectric 122 is conformal to the interior walls 121 A and the exterior walls 121 B of the bottom plate 121 .
- the top plate 123 is conformal to the capacitor dielectric 122 .
- a portion of the top plate 123 is located within and opposes the interior walls 121 A of the bottom plate 121 , separated therefrom by the capacitor dielectric 122 .
- a portion of the top plate 123 is locate outside of and opposes the exterior walls 121 B of the bottom plate 121 , separated therefrom by the capacitor dielectric 122 .
- FIG. 2 is a simplified block diagram of a field programmable logic array (PLA) 200 according to the teachings of the present invention.
- PLA 200 includes two major constituents: a first logic plane 220 and a second logic plane 230 .
- the first and second logic planes 220 and 230 are formed using an array of non-volatile memory cells 100 as presented and described in detail in connection to FIG. 1 .
- the first and second logic planes 220 and 230 each comprise NOR logic circuits such that PLA 200 implements NOR-NOR logic.
- FIG. 3 is provided by way of example and not by way of limitation. Specifically, the teachings of the present application are not limited to programmable logic arrays in the NOR-NOR approach. Further, the teachings of the present application are not limited to the specific logical function shown in FIG. 3 . Other logical functions can be implemented in a programmable logic array with non-volatile memory cells 100 using any one of the various two level logic approaches.
- second logic plane 320 comprises a second array of non-volatile memory cells 100 that are selectively programmed to provide the second level of the two level logic needed to implement a specific logical function.
- the array of non-volatile memory cells 100 is also configured such that the output lines 318 comprise a logical NOR function of the signals from the interconnection lines 314 that are coupled to particular output lines through the non-volatile memory cells 100 of the second logic plane 320 .
- FIG. 4 is a schematic diagram that illustrates one embodiment of a decoder, indicated generally at 400 , that is constructed according to the teachings of the present invention.
- Decoder 400 can be used, for example, as a memory address decoder such as a column decoder or a row decoder.
- the ability to process data stored on the DRAM die allows a number of cost effective applications that do not currently exist or that, heretofore were to costly to be commercially viable. It is particularly suited to processing data which requires a large number of parallel operations.
- the use of programmable embedded processors avoids the necessity of transferring intermediate data on and off chip through input/output drivers and circuits and greatly speeds data processing. This aids in applications such as a dedicated signal processor in which data may be loaded in to a range of DRAM addresses and then having an algorithm such as the Fast Fourier Transform (FFT), performed on the data with the results stored in another range of DRAM memory all on the same chip.
- FFT Fast Fourier Transform
Abstract
The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.
Description
- This application is a Continuation of U.S. application Ser. No. 10/191,167, filed on Jul. 9, 2002, which is a Divisional of U.S. application Ser. No. 09/261,598, filed Feb. 26, 1999, now U.S. Pat. No. 6,452,856, which are incorporated herein by reference.
- This application is related to commonly assigned applications, U.S. application Ser. No. 09/259,493, filed Feb. 26, 1999, now U.S. Pat. No. 6,380,581, U.S. application Ser. No. 09/261,597, filed Feb. 26, 1999, now U.S. Pat. No. 6,297,989, and U.S. application Ser. No. 09/261,479, filed Feb. 26, 1999, now U.S. Pat. No. 6,256,225 which are hereby incorporated by reference.
- The present invention relates generally to semiconductor integrated circuits and, more particularly, to DRAM technology compatible processor/memory chips.
- Many products need various amounts of memory. Two of the most useful types of memory are high speed, low cost memory typically implemented as Dynamic Random Access Memory (DRAM) and non-volatile memory typically implemented as Electrically Erasable and Programmable Read Only Memory (EEPROM) or Flash memory. The ability to combine DRAM and EEPROM styles of memory, as well as logic and data processing functions implemented by Programmable Logic Arrays (PLA's) especially if little or no additional manufacturing complexity is required, would allow a number of cost effective applications that do not currently exist or that, heretofore were too costly to be commercially viable.
- With the increasing array density of successive generations of DRAM chips, the attractiveness of merging other functions onto the chip also increases. However, any successful merged technology product must be cost competitive with the existing alternative of combining separate chips at the card or package level, each being produced with independently optimized technologies. Any significant addition of process steps to an existing DRAM technology in order to provide added functions such as high speed logic, SRAM or EEPROM becomes rapidly cost prohibitive due to the added process complexity cost and decreased yield. Thus, there is a need for a means of providing additional functions on a DRAM chip with little or no modification of the DRAM optimized process flow.
- Among the desired additional functions, EEPROM is one for which the differences between the separately optimized technologies is the greatest. The typical EEPROM cell consists of a MOSFET with two stacked gates, a floating gate directly over the device channel and a control gate atop and capacitively coupled to it.
- It would be very desirable to reduce all the major elements of a PC on to a single chip, including CPU, memory and input/output. While at the present time it may not be possible to make a whole PC on a single die, many processor like functions might most conveniently be embedded on the DRAM die. PLAs on a DRAM die would be well suited for memory address correction/repair by changing the addresses to remove faulty rows/columns, and replace them with functional ones. An example of a redundancy repair scheme is shown in U.S. Pat. # 5,324,681 issued Lowrey on Jun. 28, 1994. Another is provided in U.S. Pat. # 4,051,354 issued Choate on Sep. 27, 1997. Another is provide in U.S. Pat. # 5,327,380 issued Kersh III on Jul. 5, 1994. None of these, however, incorporate an optimized DRAM technology process flow. PLAs on a DRAM die would also be desirable for use as dedicated processors embedded on the DRAM chip.
- Recent publications outline the problems in trying to embed DRAMs in high performance ULSI logic. The conclusions are that because of the height differences between conventional stacked capacitor DRAM cells and high performance logic circuits that this can only be reasonably accomplished with trench capacitor DRAMS.
- Modern DRAM technologies are driven by market forces and technology limitations to converge upon a high degree of commonality in basic cell structure. For the DRAM technology generations from 4 Mbit through 1 Gbit, the cell technology has converged into two basic structural alternatives; trench capacitor and stacked capacitor. A method for utilizing a trench DRAM capacitor technology to provide a compatible EEPROM cell has been described in U.S. Pat. # 5,598,367. A different approach is needed for stacked capacitors however.
- Thus, there is a need for merging processor and memory functions on a single DRAM chip. Similarly, there is a need for using PLAs on a DRAM chip as decoder devices. It is desirable that such processor/PLA capability be fabricated onto the DRAM chip with little or no modification of the DRAM optimized process flow.
- The above mentioned problems for merging processor/PLAs and memory functions on a single DRAM chip as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. The present invention includes a compact non-volatile memory cell structure formed using a DRAM process technology.
- The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A second logic plane is provided which has a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET). Each non-volatile memory cell includes a stacked capacitor formed according to a dynamic random access memory (DRAM) process. And, each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET.
- Another embodiment of the present invention includes an address decoder for a memory device. The address decoder includes a number of address lines and a number of output lines. The address lines, and the output lines form an array. A number of non-volatile memory cells are disposed at intersections of output lines and address lines. Each non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines.
- These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
-
FIG. 1 is a perspective view illustrating in detail the make up of each non-volatile memory cell according to the teachings of the present invention. -
FIG. 2 is a simplified block diagram of a field programmable logic array (PLA) according to the teachings of the present invention. -
FIG. 3 is a schematic diagram illustrating generally an architecture of one embodiment of a programmable logic array (PLA) constructed according to the teachings of the present invention. -
FIG. 4 is a schematic diagram illustrating generally an architecture of one embodiment of a programmable decoder according to the teachings of the present invention. -
FIG. 5 illustrates application of programmed logic arrays (PLA's), formed according to the teaching of the present invention, embedded processor on a DRAM die. - In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
-
FIG. 1 is a perspective view illustrating in detail the make up of the non-volatile memory cell, e.g. 100, according to the teachings of the present invention. Thenon-volatile memory cell 100 includes all the embodiments of the non-volatile memory cell structure presented and described in detail in the co-filed application attorney docket number 303.556us1, entitled “DRAM Technology Compatible Non-volatile Memory Cells,” by Wendell P. Noble and Eugene H. Cloud, which is hereby incorporated by reference in its entirety. - As shown in
FIG. 1 , the non-volatilememory cell structure 100 includes aMOSFET 110 and acapacitor 120 fabricated using conventional DRAM process steps. In one embodiment, theMOSFET 110 includes an n-channel metal oxide semiconductor (NMOS)transistor 110 formed in asemiconducting substrate 111. TheMOSFET 110 includes agate 112 separated by agate oxide 113 from achannel region 114 of theMOSFET 110. In one embodiment, thegate oxide 113 has a thickness of less than 100 Angstroms (Å) and acts as a tunneling oxide.Gate 112 includes apolysilicon gate 112, apolycide gate 112, salicided gate structure, or other conductive gate material as known to one of ordinary skill in the art of DRAM transistor fabrication. Thechannel region 114 couples a first diffusedregion 115 to a second diffusedregion 116. The DRAM transistor is formed according to a conventional, DRAM optimized process flow, as is known to those of ordinary skill in the art of DRAM chip fabrication. - As shown in
FIG. 1 ; thecapacitor 120 is formed in a subsequent layer above theMOSFET 110. Thecapacitor 120 is separated from theMOSFET 110 by aninsulator layer 132.Capacitor 120 includes abottom plate 121 and atop plate 123, or acontrol gate 123 which is separated from thebottom plate 121 by a dielectric layer orcapacitor dielectric 122. Thebottom plate 121 serves as astorage node 121 and the top plate serves as aplate capacitor 123 for thecapacitor 120. Thebottom plate 121 comprises a floatinggate 121 for thenon-volatile memory cell 100 which is connected throughinsulator layer 132 togate 112 by anelectrical contact 130. In one embodiment, theentire stack top plate 123 comprises acontrol gate 123 for thenon-volatile memory cell 100. - In one embodiment, shown in
FIG. 1 ,capacitor 120 includes a stacked capacitor which is cup shaped 120. Thebottom plate 121 hasinterior walls 121A and exterior walls 12 1B. Thecapacitor dielectric 122 is conformal to theinterior walls 121A and theexterior walls 121B of thebottom plate 121. Thetop plate 123 is conformal to thecapacitor dielectric 122. A portion of thetop plate 123 is located within and opposes theinterior walls 121A of thebottom plate 121, separated therefrom by thecapacitor dielectric 122. A portion of thetop plate 123 is locate outside of and opposes theexterior walls 121B of thebottom plate 121, separated therefrom by thecapacitor dielectric 122. In one embodiment, the capacitor dielectric has a thickness of less than the equivalent of 100 Angstroms (Å) of SiO2. As one of ordinary skill in the art will understand upon reading this disclosure, other of stackedcapacitor 120 configurations, such as domes or flat plates, are applicable. To create an array of such cells, such as shown in the co-filed application attorney docket number 303.556us1, entitled “DRAM Technology Compatible Non-volatile Memory Cells,” by Wendell P. Noble and Eugene H. Cloud, bit lines are connected to the first and second diffused regions, 115 and 116. For minimum cell size, the bit lines may consist of diffusion lines which traverse the array. By then patterning thetop plate 123 of the stackedcapacitor 120 into strips orthogonal to the diffused bit lines,control gate 123 word lines couple to thebottom plate 121 and theMOSFET 110 of thenon-volatile memory cell 100 structure. - The resulting
non-volatile memory cell 100 has the same physical and electrical features as conventional non-volatile memory cells and thus conventional methods of programing (e.g. channel hot electron “CHE” injection) and erasure (e.g. Fowler Nordheim “F-N” tunneling) may be used. However, whereas conventional non-volatile memory cells have capacitive coupling ratios of 0.6 to 1.0, as defined in the co-filed application attorney docket number 303.556us1, entitled “DRAM Technology Compatible Non-volatile Memory Cells,” by Wendell P. Noble and Eugene H. Cloud, the inherently high stackedcapacitor 120 surface area of the present invention can provide coupling ratios many times this. Therefore the gate voltage swings needed for programming and erasure are greatly reduced. -
FIG. 2 is a simplified block diagram of a field programmable logic array (PLA) 200 according to the teachings of the present invention.PLA 200 includes two major constituents: afirst logic plane 220 and asecond logic plane 230. The first and second logic planes 220 and 230 are formed using an array ofnon-volatile memory cells 100 as presented and described in detail in connection toFIG. 1 . In one embodiment, the first and second logic planes 220 and 230 each comprise NOR logic circuits such thatPLA 200 implements NOR-NOR logic. In other embodiments, first and second logic planes 220 and 230 are constructed from arrays ofnon-volatile memory cells 100 that are configured to implement AND-OR, OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND logic. -
Input lines 225 are coupled to receive a number of input signals. Inverters/drivers 250 are coupled to theinput lines 225 such thatfirst logic plane 220 is capable of receiving each of the input signals and their complements.First logic plane 220 produces a number of output signals that are logical combinations of the signals from inverters/drivers 250. The output signals fromfirst logic plane 220 are provided tosecond logic plane 230 via interconnection lines 222.Second logic plane 230 produces a number of output signals that are logical combinations of the signals frominterconnection lines 222. - In addition, various control circuits and signals not detailed herein initiate and synchronize the
PLA 200 operation as known to those skilled in the art. ThePLA 200 implementation described with respect toFIG. 2 is illustrative only and is not intended to be exclusive or limiting. -
FIG. 3 is a schematic diagram illustrating generally an architecture of one embodiment of a programmable logic array (PLA), indicated generally at 300, and constructed according to the teachings of the present invention.PLA 300 implements an illustrative logical function using a two level logic approach. Specifically,PLA 300 includes first and second logic planes 310 and 320. In this example, the logic function is implemented using NOR-NOR logic. First and second logic planes 310 and 320 each include an array ofnon-volatile memory cells 100, as presented and described in detail in connection toFIG. 1 , that are configured to implement the logical function ofPLA 300. - It is noted that the configuration of
FIG. 3 is provided by way of example and not by way of limitation. Specifically, the teachings of the present application are not limited to programmable logic arrays in the NOR-NOR approach. Further, the teachings of the present application are not limited to the specific logical function shown inFIG. 3 . Other logical functions can be implemented in a programmable logic array withnon-volatile memory cells 100 using any one of the various two level logic approaches. -
First logic plane 310 receives a number of input signals at input lines 312. In this example, no inverters are provided for generating complements of the input signals. However,first logic plane 310 can include inverters to produce the complementary signals when needed in a specific application. -
First logic plane 310 includes a number ofnon-volatile memory cells 100 that form an array. Thenon-volatile memory cells 100 are located at the intersection ofinput lines 312, andinterconnect lines 314. Not all of thenon-volatile memory cells 100 are operatively conductive in the first logic plane. Rather, thenon-volatile memory cells 100 are selectively programmed to respond to theinput lines 312 and change the potential of theinterconnect lines 314 so as to implement a desired logic function. Thus, somenon-volatile memory cells 100 are left unprogrammed. This selective interconnection is referred to as programming since the logical function implemented by the programmable logic array is enterred into the array by thenon-volatile memory cells 100 that are used at the intersections ofinput lines 312, andinterconnect lines 314 in the array. - In this embodiment, each of the
interconnect lines 314 acts as a NOR gate for theinput lines 312 that are connected to theinterconnect lines 314 through thenon-volatile memory cells 100 of the array. For example,interconnection line 314 a acts as a NOR gate for the signals oninput lines interconnect line 314 a is maintained at a high potential unless one or more of thenon-volatile memory cells 100 that are coupled to interconnectline 314a are turned on by a high logic level signal on one of theinput line 312. When a control gate address is activated, throughinput lines 312, eachnon-volatile memory cell 100 either conducts or does not conduct depending on the charge stored upon its floating gate, this performs the NOR positive logic circuit function, an inversion of the OR circuit function results from inversion of data onto theinterconnect lines 314 through thenon-volatile memory cells 100 of the array. Thesense amplifiers 316 at the ends of theinterconnect lines 314 are used as amplifiers and drivers for the passing data into thesecond array 320. In this manner a NOR-NOR is most easily implemented utilizing the normal DRAM array structure, only the function of devices is changed. - In a similar manner,
second logic plane 320 comprises a second array ofnon-volatile memory cells 100 that are selectively programmed to provide the second level of the two level logic needed to implement a specific logical function. In this embodiment, the array ofnon-volatile memory cells 100 is also configured such that theoutput lines 318 comprise a logical NOR function of the signals from theinterconnection lines 314 that are coupled to particular output lines through thenon-volatile memory cells 100 of thesecond logic plane 320. -
FIG. 4 is a schematic diagram that illustrates one embodiment of a decoder, indicated generally at 400, that is constructed according to the teachings of the present invention.Decoder 400 can be used, for example, as a memory address decoder such as a column decoder or a row decoder. -
Decoder 400 ofFIG. 4 includes a number of non-volatile memory cells, e.g. 435, as described in detail in connection withFIG. 1 . The number of non-volatile memory cells are formed at the intersection of output lines O1. through O4 with either an address line A1 through A3 or inverse address line A1 through A3. The inverse address lines are coupled to associated address lines through an inverter as shown. For example, non-volatile memory cell is located at the intersection of address line A1 and output line O1. Decoder 400 is programmed and reprogrammed according to the techniques generally know for programming conventional non-volatile memory cells. Any selected number of the non-volatile memory cells be operatively coupled to the address lines, A1 through A3, inverse address lines, A1 through A3, or the output lines, O1 through O4. In this manner, the number of non-volatile memory cells are selectively programmed into the array in order to implement a desired logical function. - In this embodiment of
FIG. 4 , each of the output lines, O1 through O4, implements a NOR logic function for the address lines, A1 through A3, and inverse address lines, A1 through A3, that are connected to it through the vertical transistors. For example, output line O1 is coupled to the drains ofnon-volatile memory cells Non-volatile memory cells FIG. 1 , that are coupled to receive signals from address lines A1, A2, and A3, respectively. Output line O1 produces the logical NOR of the logic values provided on address lines A1, A2, and A3. Output line O1 produces a low logic level when any one of the address lines A1, A2, and A3 is brought to a high logic level and the floating gate on an associated non-volatile memory cell, as shown in detail inFIG. 1 , is absent of charge (e.g. in an unprogrammed state). Further, output line O1 produces a high logic level only when the address lines A1, A2, and A3 are all at a low logic level. - The remaining output lines are selectively coupled to other non-volatile memory cells as shown to implement additional NOR functions. These NOR functions are chosen such that the input address lines, A1, A2, and A3, (and inverse address lines, A1, A2, A3) can be used to selectively address the output lines, O1 through O4. It is noted that the logical functions implemented in
array 400 are shown by way of illustration and not by way of limitation. Other logical functions can be implemented without departing from the spirit and scope of the present invention. - Generally speaking,
decoder 400 can be fabricated with N address input lines to uniquely select 2N output lines. Thus, in an alternative embodiment, two address lines, A1 and A2, are used to selectively access four output lines, O1 through O4. In this embodiment, the purpose of address line A3 is to hold the output lines at a low level when an address signal has not yet been received. -
FIG. 5 illustrates application of PLA's, structure according to the teachings of the present invention, as an embedded processor on aDRAM die 500. In the embodiment shown inFIG. 5 , data from theDRAM memory arrays 510 is input to theprocessor 520 at the top of theFIG. 5 via interconnect lines 512. At the end of the processing, as defined by the program selected for data processing from theprogram circuit 540, processed data is sent back for storage in theDRAM arrays 510 from adata output circuit 530 via interconnect lines 514. In one embodiment ofFIG. 5 , the individual cell type for implementation of aparticular processor 520 function includes a program stored in theprogram circuit 540 using EEPROM cells. Memory is held in thememory arrays 510 andregisters 590 using conventional DRAM cells. In this embodiment, the individual cell type for implementation of theparticular processor 520 function includes a function andsequence circuit 550,FLAGS 560, one or moreserial adders 570, and adata selector 580 using PLAs constructed according to teachings of the present invention. As is shown inFIG. 5 , most functions in the processor can be implemented using PLA's according to the teachings of the present invention. - Thus, the ability to provide processor/PLA capability on a DRAM chip according to a DRAM optimized process flow has been shown by the present invention. This disclosure provides not only a technique for combining logic (implemented with PLA's) with stacked capacitor DRAM cells but also describes the alternative approach to improving system performance, namely “embedded logic in DRAMs”, not DRAMs embedded in logic.
- The ability to process data stored on the DRAM die allows a number of cost effective applications that do not currently exist or that, heretofore were to costly to be commercially viable. It is particularly suited to processing data which requires a large number of parallel operations. The use of programmable embedded processors avoids the necessity of transferring intermediate data on and off chip through input/output drivers and circuits and greatly speeds data processing. This aids in applications such as a dedicated signal processor in which data may be loaded in to a range of DRAM addresses and then having an algorithm such as the Fast Fourier Transform (FFT), performed on the data with the results stored in another range of DRAM memory all on the same chip. The user application can retrieve the resultant processed data from the memory. The ability of an on chip non-volatile memory means that the processor program instructions, implementing various algorithms, can not only be stored on the die but also can be easily changed to suit a variety of applications. The PLA's of the present invention allow powerful techniques for data processing which are especially useful for parallel data processing applications such as image processing or general Digital Signal Processing (DSP). The PLA's of the present invention are also suitable for making general purpose processors embedded in a DRAM by which one could emulate a general purpose processor such as an 80C251, an 8 bit general purpose microprocessor. Here, 5-10 Mbits of the DRAM of the DRAM chip can be configured for PLA's, non-volatile storage, and where DRAM serves as registers.
- Thus, the ability to provide processor/PLA capability on a DRAM chip according to a DRAM optimized process flow has been shown by the present invention. This disclosure provides not only a technique for combining logic (implemented with PLA's) with stacked capacitor DRAM cells but also describes the alternative approach to improving system performance, namely “embedded logic in DRAMs”, not DRAMs embedded in logic.
- The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A second logic plane is provided which has a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET). Each non-volatile memory cell includes a stacked capacitor formed according to a dynamic random access memory (DRAM) process. And, each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET.
- Another embodiment of the present invention includes an address decoder for a memory device. The address decoder includes a number of address lines and a number of output lines. The address lines, and the output lines form an array. A number of non-volatile memory cells are disposed at intersections of output lines and address lines. Each non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines.
- Methods, integrated circuits, and electronic systems are similarly provided and included within the scope of the present invention.
- It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims (76)
1. An electronic system, comprising:
an electronic device; and
a processor operatively coupled to electronic device; and
wherein the processor includes at least one programmable logic array including:
a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs, and
wherein the non-volatile memory cells each include:
a metal oxide semiconductor field effect transistor (MOSFET);
a stacked capacitor formed according to a dynamic random access memory (DRAM) process, wherein the stacked capacitor has a coupling ratio greater than 1.0; and
an electrical contact that couples the stacked capacitor to a gate of the MOSFET.
2. The electronic system of claim 1 , wherein the electronic device includes a memory formed on a die common with the processor.
3. The electronic system of claim 1 , wherein the processor further comprises:
a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane and interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; and
wherein the non-volatile memory cells of the second logic plane each include:
a metal oxide semiconductor field effect transistor (MOSFET);
a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the stacked capacitor being adapted to provide a coupling ratio of greater than 1.0; and
an electrical contact that couples the stacked capacitor to a gate of the MOSFET.
4. The electronic system of claim 3 , wherein the first logic plane and the second logic plane each comprise NOR planes.
5. The electronic system of claim 3 , wherein the electronic device and the processor are formed on a same bulk semiconductor substrate, and wherein the electrical contact includes a polysilicon plug.
6. The electronic system of claim 5 , wherein the substrate includes a working surface and includes an insulating layer formed on top of an underlying semiconductor.
7. The electronic system of claim 1 , wherein the programmable logic array is operatively coupled to a computer system.
8. The electronic system of claim 1 , wherein the stacked capacitor includes a fin type capacitor.
9. The electronic system of claim 1 , wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the MOSFET.
10. The electronic system of claim 3 , wherein:
the processor includes at least one register formed from dynamic random access memory cells, and wherein the processor includes at least one function and sequence circuit.
11. The electronic system of claim 3 , wherein the processor includes a program circuit that stores a program.
12. The electronic system of claim 11 , wherein the program circuit stores the program in an EEPROM.
13. The electronic system of claim 3 , wherein the first logic plane includes N address lines and 2N output lines.
14. An electronic system with a programmable logic array, comprising:
a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of outputs; and
a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being operably coupled to receive the outputs of the first logic plane and interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,
wherein at least one of the non-volatile memory cells includes:
a transistor;
a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and
an electrical contact that couples the stacked capacitor to a gate of the transistor.
15. The electronic system of claim 14 , wherein the implemented logical function includes at least one of NOR-NOR, AND-OR, OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.
16. The electronic system of claim 14 , wherein the first logic plane includes inverters adapted to generate a complement of the input signal.
17. The electronic system of claim 14 , wherein the electrical contact includes a polysilicon plug, and wherein the stacked capacitor includes a fin type capacitor.
18. The electronic system of claim 14 , wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact operatively couples the storage node of the stacked capacitor to the gate of the transistor.
19. The electronic system of claim 18 , wherein the transistor is a metal oxide semiconductor field effect transistor.
20. An electronic system, comprising:
an electronic device; and
a processor operatively coupled to the electronic device; and
wherein the processor includes at least one programmable logic array including:
a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and
wherein the non-volatile memory cells of the first logic plane each include:
a metal oxide semiconductor field effect transistor;
a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and
an electrical contact that couples the stacked capacitor to a gate of the transistor.
21. The electronic system of claim 20 , wherein the electronic device includes a memory formed on a substrate common with the processor.
22. The electronic system of claim 20 , wherein the processor comprises:
a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being adapted to produce a number of logic outputs,
wherein the non-volatile memory cells of the second logic plane each include:
a metal oxide semiconductor field effect transistor;
a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and
an electrical contact that couples the stacked capacitor to a gate of the transistor.
23. The electronic system of claim 22 , wherein the logic outputs of the second logic plane consist of outputs of at least one of NOR-NOR, AND-OR, OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.
24. The electronic system of claim 22 , wherein the first logic plane includes inverters that are adapted to generate a complement of the input signal.
25. The electronic system of claim 22 , wherein the logic outputs of the second logic plane include NAND outputs.
26. The electronic system of claim 22 , wherein the cup-shaped stacked capacitor of at least one of the first logic plane and the second logic plane includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.
27. The electronic system of claim 22 , wherein the first logic plane includes N address lines and 2N output lines.
28. The electronic system of claim 20 , wherein the stacked capacitor includes a fin type capacitor.
29. An electronic system with a programmable logic array, comprising:
a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs; and
a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,
wherein the non-volatile memory cells each include:
a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide;
a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and
an electrical contact that couples the stacked capacitor to the gate of the transistor.
30. The electronic system of claim 29 , wherein the gate oxide has a thickness of less than 100 angstroms.
31. The electronic system of claim 29 , wherein the gate oxide is adapted to act as a tunneling oxide.
32. The electronic system of claim 29 , wherein the logic outputs of the first logic plane include at least one of AND and NAND, and wherein the logic outputs of the second logic plane include at least one of AND and NAND.
33. The electronic system of claim 29 , wherein the first logic plane includes inverters that are adapted to generate a complement of the input signal.
34. The electronic system of claim 29 , wherein the stacked capacitor includes a fin type capacitor.
35. The electronic system of claim 29 , wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.
36. An electronic system with a programmable logic array, comprising:
a first logic plane adapted to receive a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs; and
a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,
wherein the non-volatile memory cells each include:
a metal oxide semiconductor field effect transistor;
a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric; and
an electrical contact that couples the bottom plate of the stacked capacitor to a gate of the transistor.
37. The electronic system of claim 36 , wherein the bottom plate serves as a storage node.
38. The electronic system of claim 36 , wherein the bottom plate comprises a floating gate for the at least one non-volatile memory cell.
39. The electronic system of claim 36 , wherein the logic outputs of the first logic plane include at least one of AND and NAND, and wherein the logic outputs of the second logic plane include at least one of AND and NAND.
40. The electronic system of claim 39 , wherein the first logic plane includes inverters that generate a complement of the input signal.
41. The electronic system of claim 40 , wherein the electrical contact includes a polysilicon plug.
42. The electronic system of claim 41 , wherein the stacked capacitor includes a fin type capacitor.
43. An electronic system with a programmable logic array, comprising:
a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs; and
a second logic plane having a number of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,
wherein the non-volatile memory cells each include:
a metal oxide semiconductor field effect transistor;
a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0, the capacitor including a bottom plate and a top plate separated by a capacitor dielectric; and
an electrical contact that couples the bottom plate of the stacked capacitor to a gate of the transistor.
44. The electronic system of claim 43 , wherein the bottom plate serves as a storage node.
45. The electronic system of claim 43 , wherein the bottom plate comprises a floating gate for the at least one non-volatile memory cell.
46. The electronic system of claim 43 , wherein the logic outputs of the first logic plane include at least one of AND and NAND, and wherein the logic outputs of the second logic plane include at least one of AND and NAND.
47. The electronic system of claim 46 , wherein the first logic plane includes inverters that are adapted to generate a complement of the input signal.
48. The electronic system of claim 47 , wherein the electrical contact includes a polysilicon plug.
49. An electronic system with a programmable logic array, comprising:
a first logic plane adapted to receive a number of input signals, the first logic plane having a plurality of non-volatile memory cells that are interconnected to provide a number of logic outputs; and
a second logic plane having a number of non-volatile memory cells, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,
wherein the non-volatile memory cells each include:
a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide;
a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and
an electrical contact that couples the stacked capacitor to a gate of the transistor.
50. The electronic system of claim 49 , wherein the gate oxide acts as a tunneling oxide.
51. The electronic system of claim 49 , wherein the logic outputs of the first logic plane include at least one of AND and NAND, and wherein the logic outputs of the second logic plane include at least one of AND and NAND.
52. The electronic system of claim 49 , wherein the first logic plane includes inverters that are adapted to generate complements of the input signal, wherein the electrical contact includes a polysilicon plug, and wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.
53. An electronic system with a programmable logic array, comprising:
a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic output; and
a second logic plane having a number of non-volatile memory cells, the non-volatile memory cells of the second logic plane being adapted to receive the outputs of the first logic plane, the non-volatile memory cells of the second logic plane being interconnected to produce a number of logic outputs,
wherein the non-volatile memory cells each include:
a metal oxide semiconductor field effect transistor comprising a gate and a channel region separated by a gate oxide, the gate oxide being adapted to act as a tunneling oxide;
a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and
an electrical contact that couples the stacked capacitor to a gate of the transistor.
54. The electronic system of claim 53 , wherein the outputs of the first logic plane include a NOR output and the outputs of the second plane include a NAND output.
55. The electronic system of claim 53 , wherein the first logic plane includes N address lines and 2N output lines.
56. An electronic system, comprising:
a memory; and
a processor coupled to the memory and formed on a die common with the memory; and
wherein the die includes at least one programmable logic array including:
a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile first memory cells arranged in rows and columns that are interconnected to provide a number of first logic outputs; and
a second logic plane having a number of non-volatile second memory cells arranged in rows and columns, the non-volatile second memory cells being adapted to receive the outputs of the first logic plane and that are interconnected to produce a number of second logic outputs,
wherein the first non-volatile memory cells each include:
a metal oxide semiconductor field effect transistor;
a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and
an electrical contact that couples the stacked capacitor to a gate of the transistor.
57. The electronic system of claim 56 , wherein the implemented logical function includes at least one of NOR-NOR, AND-OR, OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.
58. The electronic system of claim 56 , wherein the first logic plane includes inverters adapted to generate complements of the input signals.
59. The electronic system of claim 56 , wherein the electrical contact includes a polysilicon plug.
60. The electronic system of claim 56 , wherein the stacked capacitor includes a fin type capacitor.
61. The electronic system of claim 60 , wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.
62. The electronic system of claim 60 , wherein the first logic plane includes N address lines and 2N logic outputs.
63. An electronic system, comprising:
a memory; and
a processor coupled to the memory and formed on a die common with the memory; and
wherein the processor includes at least one programmable logic array including:
a first logic plane adapted to receive an input signal, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logic outputs, and
wherein the non-volatile memory cells each include:
a metal oxide semiconductor field effect transistor (MOSFET) having a gate oxide, wherein the gate oxide has a thickness of less than 100 angstroms;
a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the stacked capacitor being adapted to provide a coupling ratio of greater than 1.0; and
an electrical contact that couples the stacked capacitor to a gate of the MOSFET.
64. The electronic system of claim 63 , wherein the programmable logic array includes a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.
65. The electronic system of claim 64 , wherein the first logic plane and the second logic plane each comprise NOR planes.
66. The electronic system of claim 63 , wherein the logic outputs of the first logic plane include at least one of NOR, OR, AND, NAND; and the logic outputs of the second logic plane include at least one of NOR, OR, AND, NAND.
67. The electronic system of claim 63 , wherein the logic outputs of the first logic plane include at least one of AND and NAND, and wherein the logic outputs of the second logic plane include at least one of AND and NAND.
68. The electronic system of claim 63 , wherein the processor includes at least one register formed from dynamic random access memory cells; and wherein the processor includes at least one function and sequence circuit.
69. The electronic system of claim 63 , wherein the processor includes a program circuit that stores a program.
70. The electronic system of claim 69 , wherein the program circuit stores the program in an EEPROM.
71. The electronic system of claim 63 , wherein the gate oxide acts as a tunneling oxide.
72. The electronic system of claim 63 , wherein the first logic plane includes inverters that are adapted to generate complements of the input signal.
73. The electronic system of claim 63 , wherein the electrical contact includes a polysilicon plug.
74. The electronic system of claim 63 , wherein the stacked capacitor includes a fin type capacitor.
75. The electronic system of claim 63 , wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.
76. The electronic system of claim 63 , wherein the stacked capacitor includes a cup-shaped capacitor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/347,989 US20060124981A1 (en) | 1999-02-26 | 2006-02-06 | DRAM technology compatible processor/memory chips |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/261,598 US6452856B1 (en) | 1999-02-26 | 1999-02-26 | DRAM technology compatible processor/memory chips |
US10/191,167 US7023040B2 (en) | 1999-02-26 | 2002-07-09 | DRAM technology compatible processor/memory chips |
US11/347,989 US20060124981A1 (en) | 1999-02-26 | 2006-02-06 | DRAM technology compatible processor/memory chips |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/191,167 Continuation US7023040B2 (en) | 1999-02-26 | 2002-07-09 | DRAM technology compatible processor/memory chips |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060124981A1 true US20060124981A1 (en) | 2006-06-15 |
Family
ID=22994018
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/261,598 Expired - Lifetime US6452856B1 (en) | 1999-02-26 | 1999-02-26 | DRAM technology compatible processor/memory chips |
US10/191,330 Expired - Fee Related US6924194B2 (en) | 1999-02-26 | 2002-07-09 | DRAM technology compatible processor/memory chips |
US10/191,329 Expired - Lifetime US6741519B2 (en) | 1999-02-26 | 2002-07-09 | DRAM technology compatible processor/memory chips |
US10/191,167 Expired - Fee Related US7023040B2 (en) | 1999-02-26 | 2002-07-09 | DRAM technology compatible processor/memory chips |
US10/191,332 Expired - Fee Related US6809985B2 (en) | 1999-02-26 | 2002-07-09 | DRAM technology compatible processor/memory chips |
US11/347,989 Abandoned US20060124981A1 (en) | 1999-02-26 | 2006-02-06 | DRAM technology compatible processor/memory chips |
Family Applications Before (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/261,598 Expired - Lifetime US6452856B1 (en) | 1999-02-26 | 1999-02-26 | DRAM technology compatible processor/memory chips |
US10/191,330 Expired - Fee Related US6924194B2 (en) | 1999-02-26 | 2002-07-09 | DRAM technology compatible processor/memory chips |
US10/191,329 Expired - Lifetime US6741519B2 (en) | 1999-02-26 | 2002-07-09 | DRAM technology compatible processor/memory chips |
US10/191,167 Expired - Fee Related US7023040B2 (en) | 1999-02-26 | 2002-07-09 | DRAM technology compatible processor/memory chips |
US10/191,332 Expired - Fee Related US6809985B2 (en) | 1999-02-26 | 2002-07-09 | DRAM technology compatible processor/memory chips |
Country Status (1)
Country | Link |
---|---|
US (6) | US6452856B1 (en) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6452856B1 (en) | 1999-02-26 | 2002-09-17 | Micron Technology, Inc. | DRAM technology compatible processor/memory chips |
US6963103B2 (en) | 2001-08-30 | 2005-11-08 | Micron Technology, Inc. | SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US7075829B2 (en) * | 2001-08-30 | 2006-07-11 | Micron Technology, Inc. | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators |
US6754108B2 (en) * | 2001-08-30 | 2004-06-22 | Micron Technology, Inc. | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US7158410B2 (en) * | 2004-08-27 | 2007-01-02 | Micron Technology, Inc. | Integrated DRAM-NVRAM multi-level memory |
US8330202B2 (en) * | 2005-02-23 | 2012-12-11 | Micron Technology, Inc. | Germanium-silicon-carbide floating gates in memories |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US7212447B2 (en) * | 2005-08-04 | 2007-05-01 | Micron Technology, Inc. | NAND flash memory cell programming |
US8110469B2 (en) | 2005-08-30 | 2012-02-07 | Micron Technology, Inc. | Graded dielectric layers |
JP2007335750A (en) | 2006-06-16 | 2007-12-27 | Toshiba Corp | Semiconductor memory device |
KR100810614B1 (en) * | 2006-08-23 | 2008-03-06 | 삼성전자주식회사 | Semiconductor memory device having DRAM cell mode and non-volatile memory cell mode and operation method thereof |
US7440311B2 (en) * | 2006-09-28 | 2008-10-21 | Novelics, Llc | Single-poly non-volatile memory cell |
US8033959B2 (en) * | 2009-05-18 | 2011-10-11 | Adidas Ag | Portable fitness monitoring systems, and applications thereof |
IN2012DN06399A (en) | 2010-02-07 | 2015-10-02 | Zeno Semiconductor Inc | |
US9720843B2 (en) * | 2012-12-28 | 2017-08-01 | Intel Corporation | Access type protection of memory reserved for use by processor logic |
WO2014109771A1 (en) | 2013-01-14 | 2014-07-17 | Hewlett-Packard Development Company, L.P. | Nonvolatile memory array logic |
US9236126B2 (en) * | 2013-06-17 | 2016-01-12 | Seoul National University R&Db Foundation | Simplified nonvolatile memory cell string and NAND flash memory array using the same |
US9628550B1 (en) | 2013-10-24 | 2017-04-18 | Ca, Inc. | Lightweight software management shell |
JP2015230611A (en) * | 2014-06-05 | 2015-12-21 | 富士通株式会社 | Electronic device and control method of electronic device |
US10884656B2 (en) | 2017-06-16 | 2021-01-05 | Microsoft Technology Licensing, Llc | Performing background functions using logic integrated with a memory |
Citations (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3590337A (en) * | 1968-10-14 | 1971-06-29 | Sperry Rand Corp | Plural dielectric layered electrically alterable non-destructive readout memory element |
US4051354A (en) * | 1975-07-03 | 1977-09-27 | Texas Instruments Incorporated | Fault-tolerant cell addressable array |
US4646271A (en) * | 1983-12-23 | 1987-02-24 | Hitachi, Ltd. | Content addressable memory having dual access modes |
US4652777A (en) * | 1984-12-18 | 1987-03-24 | Cline Ronald L | CMOS programmable logic array |
US4703456A (en) * | 1985-04-24 | 1987-10-27 | Fujitsu Limited | Non-volatile random access memory cell |
US4713677A (en) * | 1985-02-28 | 1987-12-15 | Texas Instruments Incorporated | Electrically erasable programmable read only memory cell including trench capacitor |
US4720323A (en) * | 1984-12-07 | 1988-01-19 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device |
US4757360A (en) * | 1983-07-06 | 1988-07-12 | Rca Corporation | Floating gate memory device with facing asperities on floating and control gates |
US4761768A (en) * | 1985-03-04 | 1988-08-02 | Lattice Semiconductor Corporation | Programmable logic device |
US4766569A (en) * | 1985-03-04 | 1988-08-23 | Lattice Semiconductor Corporation | Programmable logic array |
US4799194A (en) * | 1986-02-27 | 1989-01-17 | Fujitsu Limited | Semiconductor random access nonvolatile memory device with restore and control circuits |
US4813018A (en) * | 1986-11-28 | 1989-03-14 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device |
US5051958A (en) * | 1984-11-13 | 1991-09-24 | Fujitsu Limited | Nonvolatile static memory device utilizing separate power supplies |
US5057448A (en) * | 1988-02-26 | 1991-10-15 | Hitachi, Ltd. | Method of making a semiconductor device having DRAM cells and floating gate memory cells |
US5065201A (en) * | 1989-03-14 | 1991-11-12 | Sharp Kabushiki Kaisha | Semiconductor memory device |
US5075888A (en) * | 1988-01-09 | 1991-12-24 | Sharp Kabushiki Kaisha | Semiconductor memory device having a volatile memory device and a non-volatile memory device |
US5089641A (en) * | 1991-03-11 | 1992-02-18 | Wisconsin Alumni Research Foundation | Synthesis of 1α-hydroxy-secosterol compounds |
US5175120A (en) * | 1991-10-11 | 1992-12-29 | Micron Technology, Inc. | Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors |
US5189641A (en) * | 1987-06-08 | 1993-02-23 | Fujitsu Limited | Non-volatile random access memory device |
US5196722A (en) * | 1992-03-12 | 1993-03-23 | International Business Machines Corporation | Shadow ram cell having a shallow trench eeprom |
US5247346A (en) * | 1988-02-05 | 1993-09-21 | Emanuel Hazani | E2 PROM cell array including single charge emitting means per row |
US5250827A (en) * | 1990-06-21 | 1993-10-05 | Seiko Instruments Inc. | Semiconductor integrated circuit having a DRAM cell unit and a nonvolatile cell unit |
US5250857A (en) * | 1991-01-25 | 1993-10-05 | Nec Corporation | Dynamic logic circuit with reduced operating current |
US5281548A (en) * | 1992-07-28 | 1994-01-25 | Micron Technology, Inc. | Plug-based floating gate memory |
US5292681A (en) * | 1993-09-16 | 1994-03-08 | Micron Semiconductor, Inc. | Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors |
US5324681A (en) * | 1991-10-04 | 1994-06-28 | Micron Technology, Inc. | Method of making a 3-dimensional programmable antifuse for integrated circuits |
US5327380A (en) * | 1988-10-31 | 1994-07-05 | Texas Instruments Incorporated | Method and apparatus for inhibiting a predecoder when selecting a redundant row line |
US5331188A (en) * | 1992-02-25 | 1994-07-19 | International Business Machines Corporation | Non-volatile DRAM cell |
US5347490A (en) * | 1990-06-15 | 1994-09-13 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device |
US5397727A (en) * | 1994-07-20 | 1995-03-14 | Micron Technology, Inc. | Method of forming a floating gate programmable read only memory cell transistor |
US5399516A (en) * | 1992-03-12 | 1995-03-21 | International Business Machines Corporation | Method of making shadow RAM cell having a shallow trench EEPROM |
US5416735A (en) * | 1991-07-02 | 1995-05-16 | Sharp Kabushiki Kaisha | Non-volatile random access memory with ferroelectric capacitor |
US5442210A (en) * | 1992-11-12 | 1995-08-15 | Nippon Precision Circuits Inc. | Semiconductor device |
US5488579A (en) * | 1994-04-29 | 1996-01-30 | Motorola Inc. | Three-dimensionally integrated nonvolatile SRAM cell and process |
US5591658A (en) * | 1994-08-30 | 1997-01-07 | National Semiconductor Corporation | Method of fabricating integrated circuit chip containing EEPROM and capacitor |
US5595929A (en) * | 1996-01-16 | 1997-01-21 | Vanguard International Semiconductor Corporation | Method for fabricating a dram cell with a cup shaped storage node |
US5598367A (en) * | 1995-06-07 | 1997-01-28 | International Business Machines Corporation | Trench EPROM |
US5612238A (en) * | 1993-12-28 | 1997-03-18 | Nippon Steel Corporation | Method of manufacturing first and second memory cell arrays with a capacitor and a nonvolatile memory cell |
US5621233A (en) * | 1994-09-16 | 1997-04-15 | Motorola Inc. | Electrically programmable read-only memory cell |
US5702988A (en) * | 1996-05-02 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Blending integrated circuit technology |
US5723375A (en) * | 1996-04-26 | 1998-03-03 | Micron Technology, Inc. | Method of making EEPROM transistor for a DRAM |
US5748530A (en) * | 1993-05-11 | 1998-05-05 | Nkk Corporation | Non-voltile memory device, non-volatile memory cell and method of adjusting the threshold value of the non-volatile memory cell and each of plural transistors |
US5763913A (en) * | 1996-08-21 | 1998-06-09 | Lg Semicon Co., Ltd. | Flash memory device with improved efficiency and reliability and method of making the same |
US5764096A (en) * | 1994-07-05 | 1998-06-09 | Gatefield Corporation | General purpose, non-volatile reprogrammable switch |
US5825609A (en) * | 1996-04-23 | 1998-10-20 | International Business Machines Corporation | Compound electrode stack capacitor |
US5880991A (en) * | 1997-04-14 | 1999-03-09 | International Business Machines Corporation | Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure |
US5886379A (en) * | 1996-05-16 | 1999-03-23 | Lg Semicon Co., Ltd. | Semiconductor memory device with increased coupling ratio |
US5908311A (en) * | 1996-07-25 | 1999-06-01 | National Semiconductor Corporation | Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells |
US5912840A (en) * | 1997-08-21 | 1999-06-15 | Micron Technology | Memory cell architecture utilizing a transistor having a dual access gate |
US5914904A (en) * | 1996-10-01 | 1999-06-22 | Altera Corporation | Compact electrically erasable memory cells and arrays |
US5981335A (en) * | 1997-11-20 | 1999-11-09 | Vanguard International Semiconductor Corporation | Method of making stacked gate memory cell structure |
US6015986A (en) * | 1995-12-22 | 2000-01-18 | Micron Technology, Inc. | Rugged metal electrodes for metal-insulator-metal capacitors |
US6021066A (en) * | 1999-01-04 | 2000-02-01 | International Business Machines Corporation | NVRAM array architecture utilizing common bitline and wordline |
US6101131A (en) * | 1998-04-15 | 2000-08-08 | Chang; Ming-Bing | Flash EEPROM device employing polysilicon sidewall spacer as an erase gate |
US6118695A (en) * | 1997-09-18 | 2000-09-12 | Sanyo Electric Co., Ltd. | Nonvolatile semiconductor memory device |
US6141248A (en) * | 1999-07-29 | 2000-10-31 | Micron Technology, Inc. | DRAM and SRAM memory cells with repressed memory |
US6245613B1 (en) * | 1998-04-28 | 2001-06-12 | International Business Machines Corporation | Field effect transistor having a floating gate |
US6256225B1 (en) * | 1999-02-26 | 2001-07-03 | Micron Technology, Inc. | Construction and application for non-volatile reprogrammable switches |
US6259126B1 (en) * | 1999-11-23 | 2001-07-10 | International Business Machines Corporation | Low cost mixed memory integration with FERAM |
US6285055B1 (en) * | 1998-01-26 | 2001-09-04 | Sony Corporation | Memory device and method of manufacturing the same, and integrated circuit and method of manufacturing semiconductor device |
US6297989B1 (en) * | 1999-02-26 | 2001-10-02 | Micron Technology, Inc. | Applications for non-volatile memory cells |
US6424011B1 (en) * | 1997-04-14 | 2002-07-23 | International Business Machines Corporation | Mixed memory integration with NVRAM, dram and sram cell structures on same substrate |
US6452856B1 (en) * | 1999-02-26 | 2002-09-17 | Micron Technology, Inc. | DRAM technology compatible processor/memory chips |
US6545904B2 (en) * | 2001-03-16 | 2003-04-08 | Micron Technology, Inc. | 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array |
US6620659B2 (en) * | 1997-12-08 | 2003-09-16 | International Business Machines Corporation | Merged logic and memory combining thin film and bulk Si transistors |
-
1999
- 1999-02-26 US US09/261,598 patent/US6452856B1/en not_active Expired - Lifetime
-
2002
- 2002-07-09 US US10/191,330 patent/US6924194B2/en not_active Expired - Fee Related
- 2002-07-09 US US10/191,329 patent/US6741519B2/en not_active Expired - Lifetime
- 2002-07-09 US US10/191,167 patent/US7023040B2/en not_active Expired - Fee Related
- 2002-07-09 US US10/191,332 patent/US6809985B2/en not_active Expired - Fee Related
-
2006
- 2006-02-06 US US11/347,989 patent/US20060124981A1/en not_active Abandoned
Patent Citations (75)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3590337A (en) * | 1968-10-14 | 1971-06-29 | Sperry Rand Corp | Plural dielectric layered electrically alterable non-destructive readout memory element |
US4051354A (en) * | 1975-07-03 | 1977-09-27 | Texas Instruments Incorporated | Fault-tolerant cell addressable array |
US4757360A (en) * | 1983-07-06 | 1988-07-12 | Rca Corporation | Floating gate memory device with facing asperities on floating and control gates |
US4646271A (en) * | 1983-12-23 | 1987-02-24 | Hitachi, Ltd. | Content addressable memory having dual access modes |
US4646271B1 (en) * | 1983-12-23 | 1993-08-03 | Hitachi Ltd | |
US5051958A (en) * | 1984-11-13 | 1991-09-24 | Fujitsu Limited | Nonvolatile static memory device utilizing separate power supplies |
US4720323A (en) * | 1984-12-07 | 1988-01-19 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device |
US4652777A (en) * | 1984-12-18 | 1987-03-24 | Cline Ronald L | CMOS programmable logic array |
US4713677A (en) * | 1985-02-28 | 1987-12-15 | Texas Instruments Incorporated | Electrically erasable programmable read only memory cell including trench capacitor |
US4761768A (en) * | 1985-03-04 | 1988-08-02 | Lattice Semiconductor Corporation | Programmable logic device |
US4766569A (en) * | 1985-03-04 | 1988-08-23 | Lattice Semiconductor Corporation | Programmable logic array |
US4703456A (en) * | 1985-04-24 | 1987-10-27 | Fujitsu Limited | Non-volatile random access memory cell |
US4799194A (en) * | 1986-02-27 | 1989-01-17 | Fujitsu Limited | Semiconductor random access nonvolatile memory device with restore and control circuits |
US4813018A (en) * | 1986-11-28 | 1989-03-14 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device |
US5189641A (en) * | 1987-06-08 | 1993-02-23 | Fujitsu Limited | Non-volatile random access memory device |
US5075888A (en) * | 1988-01-09 | 1991-12-24 | Sharp Kabushiki Kaisha | Semiconductor memory device having a volatile memory device and a non-volatile memory device |
US5247346A (en) * | 1988-02-05 | 1993-09-21 | Emanuel Hazani | E2 PROM cell array including single charge emitting means per row |
US5057448A (en) * | 1988-02-26 | 1991-10-15 | Hitachi, Ltd. | Method of making a semiconductor device having DRAM cells and floating gate memory cells |
US5327380B1 (en) * | 1988-10-31 | 1999-09-07 | Texas Instruments Inc | Method and apparatus for inhibiting a predecoder when selecting a redundant row line |
US5327380A (en) * | 1988-10-31 | 1994-07-05 | Texas Instruments Incorporated | Method and apparatus for inhibiting a predecoder when selecting a redundant row line |
US5065201A (en) * | 1989-03-14 | 1991-11-12 | Sharp Kabushiki Kaisha | Semiconductor memory device |
US5347490A (en) * | 1990-06-15 | 1994-09-13 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device |
US5250827A (en) * | 1990-06-21 | 1993-10-05 | Seiko Instruments Inc. | Semiconductor integrated circuit having a DRAM cell unit and a nonvolatile cell unit |
US5250857A (en) * | 1991-01-25 | 1993-10-05 | Nec Corporation | Dynamic logic circuit with reduced operating current |
US5089641A (en) * | 1991-03-11 | 1992-02-18 | Wisconsin Alumni Research Foundation | Synthesis of 1α-hydroxy-secosterol compounds |
US5416735A (en) * | 1991-07-02 | 1995-05-16 | Sharp Kabushiki Kaisha | Non-volatile random access memory with ferroelectric capacitor |
US5324681A (en) * | 1991-10-04 | 1994-06-28 | Micron Technology, Inc. | Method of making a 3-dimensional programmable antifuse for integrated circuits |
US5175120A (en) * | 1991-10-11 | 1992-12-29 | Micron Technology, Inc. | Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors |
US5389567A (en) * | 1992-02-25 | 1995-02-14 | International Business Machines Corporation | Method of forming a non-volatile DRAM cell |
US5331188A (en) * | 1992-02-25 | 1994-07-19 | International Business Machines Corporation | Non-volatile DRAM cell |
US5399516A (en) * | 1992-03-12 | 1995-03-21 | International Business Machines Corporation | Method of making shadow RAM cell having a shallow trench EEPROM |
US5196722A (en) * | 1992-03-12 | 1993-03-23 | International Business Machines Corporation | Shadow ram cell having a shallow trench eeprom |
US5281548A (en) * | 1992-07-28 | 1994-01-25 | Micron Technology, Inc. | Plug-based floating gate memory |
US5442210A (en) * | 1992-11-12 | 1995-08-15 | Nippon Precision Circuits Inc. | Semiconductor device |
US5748530A (en) * | 1993-05-11 | 1998-05-05 | Nkk Corporation | Non-voltile memory device, non-volatile memory cell and method of adjusting the threshold value of the non-volatile memory cell and each of plural transistors |
US5292681A (en) * | 1993-09-16 | 1994-03-08 | Micron Semiconductor, Inc. | Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors |
US5612238A (en) * | 1993-12-28 | 1997-03-18 | Nippon Steel Corporation | Method of manufacturing first and second memory cell arrays with a capacitor and a nonvolatile memory cell |
US5496756A (en) * | 1994-04-29 | 1996-03-05 | Motorola Inc. | Method for forming a nonvolatile memory device |
US5488579A (en) * | 1994-04-29 | 1996-01-30 | Motorola Inc. | Three-dimensionally integrated nonvolatile SRAM cell and process |
US5764096A (en) * | 1994-07-05 | 1998-06-09 | Gatefield Corporation | General purpose, non-volatile reprogrammable switch |
US5397727A (en) * | 1994-07-20 | 1995-03-14 | Micron Technology, Inc. | Method of forming a floating gate programmable read only memory cell transistor |
US5591658A (en) * | 1994-08-30 | 1997-01-07 | National Semiconductor Corporation | Method of fabricating integrated circuit chip containing EEPROM and capacitor |
US5621233A (en) * | 1994-09-16 | 1997-04-15 | Motorola Inc. | Electrically programmable read-only memory cell |
US5598367A (en) * | 1995-06-07 | 1997-01-28 | International Business Machines Corporation | Trench EPROM |
US6015986A (en) * | 1995-12-22 | 2000-01-18 | Micron Technology, Inc. | Rugged metal electrodes for metal-insulator-metal capacitors |
US5595929A (en) * | 1996-01-16 | 1997-01-21 | Vanguard International Semiconductor Corporation | Method for fabricating a dram cell with a cup shaped storage node |
US5825609A (en) * | 1996-04-23 | 1998-10-20 | International Business Machines Corporation | Compound electrode stack capacitor |
US5998250A (en) * | 1996-04-23 | 1999-12-07 | International Business Machines Corporation | Compound electrode stack capacitor |
US5723375A (en) * | 1996-04-26 | 1998-03-03 | Micron Technology, Inc. | Method of making EEPROM transistor for a DRAM |
US5702988A (en) * | 1996-05-02 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Blending integrated circuit technology |
US5886379A (en) * | 1996-05-16 | 1999-03-23 | Lg Semicon Co., Ltd. | Semiconductor memory device with increased coupling ratio |
US5908311A (en) * | 1996-07-25 | 1999-06-01 | National Semiconductor Corporation | Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells |
US5763913A (en) * | 1996-08-21 | 1998-06-09 | Lg Semicon Co., Ltd. | Flash memory device with improved efficiency and reliability and method of making the same |
US5914904A (en) * | 1996-10-01 | 1999-06-22 | Altera Corporation | Compact electrically erasable memory cells and arrays |
US5880991A (en) * | 1997-04-14 | 1999-03-09 | International Business Machines Corporation | Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure |
US6141242A (en) * | 1997-04-14 | 2000-10-31 | International Business Machines Corporation | Low cost mixed memory integration with substantially coplanar gate surfaces |
US6424011B1 (en) * | 1997-04-14 | 2002-07-23 | International Business Machines Corporation | Mixed memory integration with NVRAM, dram and sram cell structures on same substrate |
US6232173B1 (en) * | 1997-04-14 | 2001-05-15 | International Business Machines Corporation | Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure |
US5912840A (en) * | 1997-08-21 | 1999-06-15 | Micron Technology | Memory cell architecture utilizing a transistor having a dual access gate |
US6118695A (en) * | 1997-09-18 | 2000-09-12 | Sanyo Electric Co., Ltd. | Nonvolatile semiconductor memory device |
US5981335A (en) * | 1997-11-20 | 1999-11-09 | Vanguard International Semiconductor Corporation | Method of making stacked gate memory cell structure |
US6620659B2 (en) * | 1997-12-08 | 2003-09-16 | International Business Machines Corporation | Merged logic and memory combining thin film and bulk Si transistors |
US6285055B1 (en) * | 1998-01-26 | 2001-09-04 | Sony Corporation | Memory device and method of manufacturing the same, and integrated circuit and method of manufacturing semiconductor device |
US6101131A (en) * | 1998-04-15 | 2000-08-08 | Chang; Ming-Bing | Flash EEPROM device employing polysilicon sidewall spacer as an erase gate |
US6245613B1 (en) * | 1998-04-28 | 2001-06-12 | International Business Machines Corporation | Field effect transistor having a floating gate |
US6021066A (en) * | 1999-01-04 | 2000-02-01 | International Business Machines Corporation | NVRAM array architecture utilizing common bitline and wordline |
US6297989B1 (en) * | 1999-02-26 | 2001-10-02 | Micron Technology, Inc. | Applications for non-volatile memory cells |
US6319773B1 (en) * | 1999-02-26 | 2001-11-20 | Micron Technology, Inc. | Construction and application for non-volatile, reprogrammable switches |
US6452856B1 (en) * | 1999-02-26 | 2002-09-17 | Micron Technology, Inc. | DRAM technology compatible processor/memory chips |
US6256225B1 (en) * | 1999-02-26 | 2001-07-03 | Micron Technology, Inc. | Construction and application for non-volatile reprogrammable switches |
US6809985B2 (en) * | 1999-02-26 | 2004-10-26 | Micron Technology, Inc. | DRAM technology compatible processor/memory chips |
US6924194B2 (en) * | 1999-02-26 | 2005-08-02 | Micron Technology, Inc. | DRAM technology compatible processor/memory chips |
US6141248A (en) * | 1999-07-29 | 2000-10-31 | Micron Technology, Inc. | DRAM and SRAM memory cells with repressed memory |
US6259126B1 (en) * | 1999-11-23 | 2001-07-10 | International Business Machines Corporation | Low cost mixed memory integration with FERAM |
US6545904B2 (en) * | 2001-03-16 | 2003-04-08 | Micron Technology, Inc. | 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array |
Also Published As
Publication number | Publication date |
---|---|
US20020176313A1 (en) | 2002-11-28 |
US20020172089A1 (en) | 2002-11-21 |
US6809985B2 (en) | 2004-10-26 |
US7023040B2 (en) | 2006-04-04 |
US20020176314A1 (en) | 2002-11-28 |
US6452856B1 (en) | 2002-09-17 |
US6741519B2 (en) | 2004-05-25 |
US6924194B2 (en) | 2005-08-02 |
US20020176293A1 (en) | 2002-11-28 |
US20020027825A1 (en) | 2002-03-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20060124981A1 (en) | DRAM technology compatible processor/memory chips | |
US6597037B1 (en) | Programmable memory address decode array with vertical transistors | |
US6380581B1 (en) | DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors | |
US6297989B1 (en) | Applications for non-volatile memory cells | |
US7276762B2 (en) | NROM flash memory devices on ultrathin silicon | |
US7115939B2 (en) | Floating gate transistor with horizontal gate layers stacked next to vertical body | |
US5866928A (en) | Single digit line with cell contact interconnect | |
US5605853A (en) | Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells | |
JPH10289980A (en) | New structure for low-cost hybrid memory integrated circuit and new nvram structure as well as method for formation of structure of hybrid memory and nvram | |
US6067249A (en) | Layout of flash memory and formation method of the same | |
US5047814A (en) | E2 PROM cell including isolated control diffusion | |
US6031771A (en) | Memory redundancy circuit using single polysilicon floating gate transistors as redundancy elements | |
US5889303A (en) | Split-Control gate electrically erasable programmable read only memory (EEPROM) cell | |
US6319773B1 (en) | Construction and application for non-volatile, reprogrammable switches | |
US5621697A (en) | High density integrated circuit with bank select structure | |
US5247346A (en) | E2 PROM cell array including single charge emitting means per row | |
EP0946988B1 (en) | Memory redundancy circuit using single polysilicon floating gate transistors as redundancy elements | |
JPH0217875B2 (en) | ||
JPH0644778A (en) | Semiconductor memory device | |
JPH0568862B2 (en) | ||
US7020016B2 (en) | Random access memory cell and method for fabricating same | |
JPS6239571B2 (en) | ||
JPS594155A (en) | Semiconductor memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |