US20060114103A1

US20060114103A1 - Semiconductor device

Info

Publication number: US20060114103A1
Application number: US10/540,268
Authority: US
Inventors: Mitsuo Usami
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 2002-12-25
Filing date: 2003-12-24
Publication date: 2006-06-01
Also published as: EP1580903A4; KR20050089162A; EP1724710A3; EP1580903A1; EP1724710B1; JP2004206371A; KR20060107583A; TW200418169A; TWI336518B; KR100983427B1; AU2003292765A1; KR100764383B1; WO2004059867A1; DE60327115D1; EP1580903B1; EP1724710A2; DE60321387D1

Abstract

An IC chip (12) having a memory (16) for memorizing a first random number (11) and information other than the first random number (11) (identification number 17 and the like) and for transmitting information in the memory (16) non-contact condition with a time difference according to a numeric value of the first random number (11). By setting the first random number (11) in a memory address counter (13) of the IC chip (12) for time difference control, the memory address counter (13) can be used for memory data transmission control at the same time, thereby building up a logic simply. As a consequence, it is possible to construct a semiconductor device capable of anti-collision control in the size of 0.5 mm square or less.

Description

TECHNICAL FIELD

The present invention relates to a semiconductor device and more particularly to a technology which is effective for application to the configuration of an IC chip with anti-collision control function, used for IC tag.

BACKGROUND ART

As a means for controlling anti-collision with signals from plural IC tags to identify an IC tag by exchanging signals between a reception unit and plural IC tags, which the inventor of the present invention has considered, following technology can be considered.
First, the IC tag transmits an identification number contained in that IC tag by a bit corresponding to a transmission request from the reception unit. The reception unit sends back one bit of received identification number to the IC tag. Then, the IC tag compares the sent-back one bit with the transmitted one bit and if they are equal, it transmits a next one bit and if they are not equal, the transmission is stopped because it means that other IC tag exists. Then, if the IC tag transmits all bits and is notified that the reception unit has received the identification number properly, the IC tag terminates subsequent response completely. By repeating this sequence, even if plural IC tags exist, it is possible to recognize them individually (see, for example, Japanese Patent Laid-Open No. 10-021691).

DISCLOSURE OF THE INVENTION

As a result of considering the technology for controlling anti-collision in the aforementioned IC tag or the like, following matters have been made evident.
For example, the above-mentioned method requires a complicated logical circuit for identifying plural IC tags. As for the reason, because the IC tag does not transmits plural bits of the identification number continuously but repeats transmission/reception with a reception unit in the unit of a bit, a complicated command is necessary, the number of operating stages is large, a complicated flip-flop is necessary, switching of transmission/reception needs to be controlled in a complicated way, a memory address counter needs a complicated control and a data comparison circuit is required.
Due to complicatedness of this logical circuit, the size of the semiconductor is increased, thereby inducing an increase of cost of the semiconductor device, which is a cause which blocks prevailing of the IC tag.
Accordingly, an object of the present invention is to provide a semiconductor device having a small size anti-collision control function, the anti-collision control function being built up with a simple logic, such as an IC chip loaded on an IC tag.
The above-mentioned and other objects and novel features of the present invention will become apparent from a description of this specification and the accompanying drawings.
An outline of the present invention disclosed in this specification is as follows.
A first means for solving the above-described problem exists in a semiconductor device for sending information in non-contact condition, comprising a memory which memorizes a first random number and information other than the first random number and for sending information in the memory with a time difference according to a numeric value of the first random number, this semiconductor device being characterized in that the first random number is set in a memory address counter of the semiconductor device for time difference control.
A second means for solving the above-described problem exists in a semiconductor device containing a memory which memorizes the first random number and information other than the first random number, the semiconductor device sending information in non-contact condition and being characterized in that the plural semiconductor devices operates synchronously with a clock from outside and when a reception unit located outside the semiconductor device detects that the plural semiconductor devices are operating, each semiconductor device sends out information in the memory of the semiconductor device with a time difference according to a numeric value of the first random number.
A third means for solving the above-described problem exists in a semiconductor device containing a memory which memorizes the first random number and the second random number and other information than the first random number and the second random number, the semiconductor device sending information in non-contact condition and being characterized in that the plural semiconductor devices operates synchronously with a clock from outside and when a reception unit located outside the semiconductor device detects that the plural semiconductor devices are operating, each semiconductor device sends out information in the memory of the semiconductor device with a time difference according to a numeric value of the first random number and further when the reception unit detects that the plural semiconductor devices possess the same first random numbers, each of the semiconductor devices sends out information in the memory of the semiconductor device with a time difference according to a numeric value of the second random number of the semiconductor device.
A fourth means for solving the above-described problem exists in a semiconductor device having a memory which memorizes the first random number and other information than the first random number, the semiconductor device sending information in the memory in non-contact condition with a time difference according to a numeric value of the first random number and being characterized in that the memory memorizes an error detection code and when the plural semiconductor devices operates synchronously with a clock from outside, the error detection code is sent out from the plural semiconductor devices and the reception unit receives the error detection code as a logical sum, recognizing that it is an error detection code which never appears when a single semiconductor device sends out so as to detect that the plural semiconductor devices are operating.
A fifth means for solving the above-described problem exists in a semiconductor device having a memory which memorizes the first random number and information other than the first random number, the semiconductor device sending information in the memory in non-contact condition with a time difference according to a numeric value of the first random number and being characterized in comprising a counter having a bit count equal to the first random number and that the first random number in the memory is set in the counter and the content of the counter is changed according to a clock from outside and when the content of the counter reaches a specified code, information in the memory is sent.
A sixth means for solving the above-described problem exists in a semiconductor device having a memory which memorizes the first random number and information other than the first random number, the semiconductor device sending information in the memory in non-contact condition with a time difference according to a numeric value of the first random number and being characterized in that carrier signal from outside the semiconductor device is changed from L level to H level and remains in that state over a specified time and after that, drops to the L level and after a predetermined time elapses, returns to H level, recognizing that a first clock comes.
A seventh means for solving the above-described problem exists in a semiconductor device having a memory which memorizes the first random number and information other than the first random number, the semiconductor device sending information in the memory in non-contact condition with a time difference according to a numeric value of the first random number and being characterized in further comprising a counter indicating an address of the memory and that counter performs count operation with the first random number set.
An eighth means for solving the above-described problem exists in a semiconductor device having a memory which memorizes the first random number and the second random number and information other than the first and second random numbers, in which when plural semiconductor devices operate synchronously with a clock from outside and a reception unit detects that such plural semiconductor devices are operating, each of the semiconductor chips sends out information in the memory of the semiconductor device according to the first random number and further when the reception unit detects that the plural semiconductor devices possess the same first random number, each semiconductor device sends out information in the memory of the semiconductor device non-contact condition with a time difference according to a numeric value of the second random number, the semiconductor device being characterized in that the semiconductor device has a counter indicating an address of the memory and that counter performs count operation with the second random number set.
A ninth means for solving the above-described problem exists in a semiconductor device having a memory which memorizes the first random number and the second random number and information other than the first and second random numbers, in which when plural semiconductor devices operate synchronously with a clock from outside when a reception unit detects that such plural semiconductor devices are operating, each of the semiconductor chips sends out information in the memory of the semiconductor device with a time difference according to the first random number and further when the reception unit detects that the plural semiconductor devices possess the same first random number, each semiconductor device sends out information in the memory of the semiconductor device non-contact condition with a time difference according to a numeric value of the second random number, the semiconductor device being characterized in that the semiconductor device has a counter indicating an address of the memory and that counter performs count operation with the second random number set and a specific modulation period exists after a last clock signal from outside is changed from H level to L level and after that specific period, carrier obtains a timing of returning to the amplitude of an initial carrier so as to realize a set for setting the second random number.
A tenth means for solving the above-described problem exists in a semiconductor device having a memory which memorizes the first random number and the second random number and information other than the first and second random numbers, in which when plural semiconductor devices operate synchronously with a clock from outside and a reception unit detects that such plural semiconductor devices are operating, each of the semiconductor chips sends out information in the memory of the semiconductor device according to the first random number and further when the reception unit detects that the plural semiconductor devices possess the same first random number, each semiconductor device sends out information in the memory of the semiconductor device non-contact condition with a time difference according to a numeric value of the second random number, the semiconductor device being characterized in that the semiconductor device has a counter indicating an address of the memory and that counter performs count operation with the second random number set and the semiconductor device contains a flip-flop which indicates that the counter is used as the counter for indicating an address.
The effects which can be obtained by the inventions disclosed in this specification are as follows.

- (1) An anti-collision control IC tag can be achieved with a simple logic circuit.
- (2) Because no command is required, any complicated decoding circuit is not required and a logic can be built up simply.
- (3) Because there are a number of repetitions on the operation stage, the quantity of the flip-flops to be controlled can be reduced, thereby making it possible to build up a simple logic.
- (4) The memory address counter can be used for memory data transmission control also, thereby making it possible to build logic simply.
- (5) As a result of (1) to (4), a semiconductor device capable of anti-collision control can be constructed in the size of 0.5 mm square or less.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the configuration of a semiconductor device of a first embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of a semiconductor device of a second embodiment of the present invention.
FIG. 3 is a signal waveform diagram showing a reception signal of the semiconductor device according to a third embodiment of the present invention.
FIG. 4 is an explanatory diagram showing a method for controlling anti-collision in case where plural IC tags exist according to a fourth embodiment of the present invention.
FIGS. 5A to 5C are configuration diagrams showing an IC tag equipped with the semiconductor device of the first-third embodiment of the present invention as a fifth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In all drawings for explaining the embodiments, like reference numerals are attached to the same components and duplicated description thereof is omitted.
(First Embodiment)
FIG. 1 is a block diagram showing a configuration of the semiconductor device of the first embodiment of the present invention. A semiconductor device of this embodiment is, for example, an IC chip 12, which comprises a memory address counter 13, an antenna 14, a rectifying circuit 15, a memory 16, a first flip-flop 18 and the like.
Information such as first random number 11 and identification number 17 is written in the memory 16.
The memory address counter 13 is a counter indicating bit address of the memory 16 and has the same bit number as the first random number 11.
Next, the operation of the first semiconductor device of the first embodiment will be described with reference to FIG. 1. First, electromagnetic wave is received from outside by the antenna 14 so that DC voltage is generated in the rectifying circuit 15.
“H” is set in the first flip-flop 18 as the initial condition and at this time, the first random number 11 in the memory 16 is set in the memory address counter 13.
Next, receiving a clock from an external reception unit, the memory address counter 13 counts up or counts down.
When the content of the memory address counter 13 reaches a specified code (for example “0”), the first flip-flop 18 is set to “L” and information in the memory 16 such as the identification number 17 is sent to an external reception unit through the rectifying circuit 15 and the antenna 14.
That is, according to numerals of the first random number 11, information in the memory 16 such as the identification number 17 is sent from the IC chip 12 with a time difference.
If plural IC chips 12 for sending information in non-contact condition exist, the plural IC chips 12 operate at the same time synchronously with a clock from outside. In this case, because the first random number 11 is written in the memory 16 of each IC chip 12 at random preliminarily, each IC chip 12 sends information in the memory 16 of the same IC chip 12 with a time difference.
Because the memory address counter 13 indicates a bit address of the memory 16 and performs counting operation with the first random number 11 set, it can control anti-collision with such a simple circuit configuration.
Next, the function of the first flip-flop 18 will be briefly described. To realize the above-mentioned operation, a stage for setting the first random number 11 within the memory 16 in the memory address counter 13 is necessary. This is set when the output of the first flip-flop 18 is “H”. When the first random number 11 set in the memory address counter 13 is counted up or counted down to “0” by a clock from the reception unit, the output of the first flip-flop 18 is set to “L” so that information in the memory 16 such as the identification number 17 is sent out according to a memory address.
(Second Embodiment)
FIG. 2 is block diagram showing the configuration of the semiconductor device according to the second embodiment of the present invention.
As shown in FIG. 2, the semiconductor device of the second embodiment is, for example, an IC chip 12, which is equipped with a second flip-flop 21 in addition to the semiconductor device of the first embodiment and includes a second random number 22 additionally as information in the memory 16.
Next, as shown in FIG. 2, operation of the semiconductor device of the second embodiment will be described. Like the first embodiment described previously, when electromagnetic wave is received from outside, DC voltage is generated in the rectifying circuit 15 and the first random number 11 in the memory 16 is set in the memory address counter 13 and then, the memory address counter 13 counts up or counts down.
When the content of the memory address counter 13 reaches a specified code (for example, “0”), the first flip-flop 18 is set to “L” and information in the memory 16 such as the identification number 17 is sent through the rectifying circuit 15 and the antenna 14.
Then, plural IC chips 12 operates at the same time synchronously with an external clock and when a reception unit outside the IC chip 12 detects that plural IC chips exist and operate, the respective IC chips 12 send information contained in the memory 16 of each IC chip 12 with a time difference according to a value of the first random number 11 and further when the reception unit detects that the plural IC chips 12 have the same first random number 11, the second flip-flop 21 is set to “H”.
Then, the second random number 22 is set in the memory address counter 13 and counted up or counted down.
When the content of the memory address counter 13 reaches a specific code (for example, “0”), information in the memory 16 such as the identification number 17 is sent through the rectifying circuit 15 and the antenna 14.
Thus, after information in the memory 16 such as the identification number 17 is sent out according to a numeric value of the first random number 11 with a time difference and when the reception unit detects that the plural IC chips 12 possess the same random number 11, each IC chip 12 sends out information in the memory 16 such as the identification number 17 according to the second random number 22 with a time difference.
The memory address counter 13 indicates a bit address of the memory 16 and performs counting operation with the second random number 22 set.
Next, the function of the second flip-flop 21 will be briefly described. To realize the above-mentioned operation, a stage for setting the second random number 22 within the memory 16 in the memory address counter 13 is temporarily necessary. This is set when the output of the second flip-flop 21 is “H”. When the second random number 22 set in the memory address counter 13 is counted up or counted down to “0” by a clock from the reception unit, the output of the second flip-flop 21 is set to “L” so that information in the memory 16 such as the identification number 17 is sent out according to a memory address.
The reason why the first random number 11 and the second random number 22 are possessed is due to discrete probability of anti-collision control. Because the first random number 11 and the second random number 22 determine a memory data sending timing and further, they are written at random by user upon manufacturing of the IC chip 12 in advance, finite bit length is used.
Thus, it is not possible to avoid a collision of the same random numbers at a certain probability in viewpoints of principle. Whether or not such a collision occurs can be detected with a reception unit because error detection code deflects.
Thus, by sending a mode switching modulation signal from the reception unit to the IC chip 12, memory data is sent out again according to the second random number 22 possessed by each IC chip 12. Although a probability that the first random number 11 and the second random number 22 may collide with each other is not generally 0, the probability is extremely small.
(Third Embodiment)
The third embodiment of the present invention is, for example, an IC tag loaded with an IC chip, which includes additionally an error detection code as information in the memory 16 of the semiconductor device (IC chip 12) of the first or second embodiment.
FIG. 3 is a signal waveform diagram showing a reception signal of the semiconductor device according to the third embodiment of the present invention.
The operation of the semiconductor device of the third embodiment will be described with reference to FIG. 3. If a signal is received from outside by the IC chip 12, a carrier modulation signal 31 is changed from “L” level having no carrier to “H” level having a carrier. Then, this signal continues on the “H” level over a specific time and after that, drops to “L” level temporarily and after a specified time elapses, it turns to “H” level, so that it is recognized as a first clock signal 32.
After that, continuously, the clock signal is supplied to the IC tag containing the IC chip 12 from an antenna of the reception unit. All IC tags send out the content of a specified memory 16 according to this clock signal.
If the reception unit receives a specified bit and an error is found when the error detection code is recognized, the condition is that plural IC tags exist or that a true error occurs, the reception unit continues to send out the clock signal.
Each IC tag sets the first random number 11 in its own memory 16 in its own memory address counter 13 and progresses count-up or count-down with the clock signal according to the first random number 11. When the memory address counter 13 reaches “0”, the content of the memory 16 is sent with the clock signal.
Further, the reception unit receives a predetermined bit so as to confirm an error detection code. Because if an error exists, it means that plural tags exist or a true error occurs, after the reception unit sends a specified clock to the IC tag, it sends out a mode switching modulation signal 33.
Consequently, each IC tag sets the second random number 22 in the memory 16 of the IC tag within its own memory address counter 13 and progresses count-up or count-down with the clock signal. When the memory address counter 13 reaches “0”, it sends out information in its own memory 16 with the clock signal.
As description above, the IC chip 12 for sending out information in non-contact condition includes the memory 16 for memorizing the first random number 11 and other information than the first random number 11. The IC chips 12, which sends out information in the memory 16 according to a numeric value of the first random number 11 with a time difference, has an error detection code as well as the first random number 11. When plural IC chips 12 operate at the same time with an external clock, the error detection code is sent out from the plural IC chips at the same time. That error detection code is received by the reception unit as a logical sum and recognized to be an error detection code which never appears if a single IC chip sends and thus, the reception unit detects that plural IC chips 12 are operating.
The plural IC chips 12 for sending information in non-contact condition have a memory 16 which memorizes, in advance, the first random number 11 and the second random number 22 and other information than the first random number 11 and the second random number 22. When the plural IC chips 12 operate at the same time synchronously with an external clock and the reception unit detects that the plural IC chips 12 exist, each IC chip 12 sends out information in the memory 16 of the IC chip 12 according to a numeric value of the first random number 11. with a time difference. Further, when the reception unit detects that the plural IC chips 12 possess the same first random number 11, each IC chip 12 sends out information in the memory 16 of the IC chip 12 with a time difference according to a numeric value of the second random number 22. The IC chip 12 contains a memory address counter 13 indicating a bit address in the memory 16. The memory address counter 13 performs count operation with a numeric value of the second random number 22 set. After a specific modulation period (carrier modulation signal 31) after a last clock signal from outside is changed from “H” level to “L” level, the carrier attains a timing of returning to an initial carrier amplitude and then, a signal for setting the second random number 22 sends out information in the memory 16 of the IC chip 12.
As a consequence, anti-collision control can be performed with a simpler logic.
(Fourth Embodiment)
FIG. 4 is an explanatory diagram of anti-collision control method in case where plural IC tags exist according to the fourth embodiment of the present invention.
A method of anti-collision control in case where plural IC tags exist will be described with reference to FIG. 4. In FIG. 4, first IC tags 41, second IC tags 42, third IC tags 43, fourth IC tags 44 and fifth IC tags 45 exist.
Electromagnetic wave 46 is irradiated from a reception unit antenna 47 to these IC tags. The reception unit 48 is capable of controlling this electromagnetic wave 46.
The first IC tag 41, the second IC tag 42, the third IC tag 43, the fourth IC tag 44 and the fifth IC tag 45 contain the IC chip 12 according to the first embodiment—third embodiment. Each IC chip contains the random number described in the first to third embodiments.
Data from each IC tag can be read by the reception unit 48 individually. For data read by the reception unit 48, the random number of each group and a random number error detection code are checked to verify whether or not reading is performed properly against noise. The error check method may be of cipher system having an evident algorithm or a cyclic redundancy check code.
Although five IC tags exist in this example, the quantity does not need to be five but 1,000 to 10,000 IC tags may exist.
(Fifth Embodiment)
FIGS. 5A to 5C are configuration diagrams showing the IC tag loaded with the semiconductor device (IC chip 12) of the first-third embodiments.
The implementation configuration of the semiconductor device (IC chip 12) of the first embodiment to third embodiment will be described with reference to FIG. 5. As shown in FIGS. 5A to SC, the IC tag of the fifth embodiment is comprised of the IC chip 12 of the first-third embodiment, a tag sheet 51, an index 54, and antennas 52, 53, 55, 56, 57.
Referring to FIG. 5A, the first straight antenna 52 and the second straight antenna 53 are connected to the IC chip 12 on the tag sheet 51. Further, the index 54 is attached to the tag sheet 51.
Further, referring to FIG. 5B, the first modified antenna 55 and the second modified antenna 56 are connected to the IC chip 12 on the tag sheet 51. The index 54 is attached to the tag sheet 51.
Referring to FIG. 5C, the third modified antenna 57 and the second modified antenna 56 are connected to the IC chip 12 on the tag sheet 51. The index 54 is attached to the tag sheet 51.
Although the positions of the tag sheet 51, the index 54 and the IC chip 12 are common, three kinds of the IC tags each having a different antenna configuration are achieved.
Meanwhile, the memory 16 of each IC chip 12 has a different identification number based on the technology described in the first-fourth embodiments.
Although these IC tags are attached to various products and used for identifying each product, there exist a condition in which plural IC tags exist nearby.
If the antennas exist nearby, parasitic capacity is generated between the antennas so that the resonant frequency decreases. The reason is that because the resonant frequency is proportional to an inverse number of square roots of a product of antenna capacity and antenna inductance, the resonant frequency decreases if the antenna capacity is increased by addition of the parasitic capacity.
In a tag system for controlling anti-collision, a necessity of hopping the frequency of the reception unit is generated. If antennas of the same shape overlap, two antennas come to exist in the same electric wave area so that energy of each tag decreases, thereby inducing a drop in communication distance.
In the fifth embodiment, when antennas of FIGS. 5A, 5B, and 5C are overlapped, antenna patterns do not coincide completely. Thus, generation of parasitic capacity is suppressed and an area for obtaining electric wave is secured, so that it is possible to suppress drop in the resonant frequency and reduction in the obtained energy.
That is, such a device as hopping can be saved and an effect that no drop in the communication distance is induced can be expected.
The three kinds of the antenna patterns shown here are examples. If a number of patterns are created by changing the shape of the antenna, even if antennas of arbitrary kinds are overlapped, the probability that they coincide completely drops, thereby making it possible to carry out anti-collision control effectively.
In the meantime, the index 54 indicates the direction of the tag sheet 51 and is used for aligning the direction of the tag sheet when the tag sheet is bonded.
By adopting the above-described configuration for the semiconductor device of the first-third embodiments, the effect of anti-collision control is further exerted.
Although the invention achieved by this inventor has been described specifically about its embodiments, the present invention is not restricted to the above-described embodiments and needless to say, may be modified in various ways within a scope not departing from the gist thereof.
For example, although in the above-described embodiments, the IC chip for sending information in non-contact condition has been described, the present invention is not restricted to this, but the present invention can be applied to other semiconductor devices and particularly, the effect of the present invention is more valid as the size of the semiconductor device decreases.
Further, although in the above-described embodiments, an example of application to the IC tag has been described, the present invention is not restricted to this but the present invention can be applied to other product such as the IC card.

INDUSTRIAL APPLICABILITY

The present invention is effective for application to the configuration of the IC chip with anti-collision control function used in the semiconductor device, particularly the IC tag.

Claims

1-5. (canceled)

6. A semiconductor device comprising:

a memory which memorizes a first random number and other information; and

a memory address counter indicating an address of the memory,

wherein the first random number in the memory is set in the memory address counter and information in the memory is sent out non contact condition with a time difference according to a numeric value of the first random number.

7. An IC tag for transmitting first information to a reception unit, comprising:

a first memory which memorizes the first information;

a second memory which memorizes second information; and

a counter in which its count value indicates a bit address of the first memory,

wherein the IC tag carries out count-up or count-down of a count value of the counter according to a clock signal received from the reception unit and the IC tag sets information of the second memory as an initial value of the counter and after the count value of the counter reaches a specified code, the first information stored in the bit address of the first memory indicated by the count value is sent out to the reception unit successively.

8. The IC tag according to claim 7,

wherein the second memories are provided in plural number and the IC tag sets the second information of any one of the second memories as an initial value of the counter.

9. The IC tag according to claim 8, further comprising a mode switching portion,

wherein the IC tag selects the second information of any one of the second memories by means of the mode switching portion and sets it as an initial value of the counter.

10. The IC tag according to claim 9,

wherein the mode switching portion is a flip-flop and the IC tag selects the second information of any one of the second memories according to a value of the flip-flop and sets it as an initial value of the counter.

11. The IC tag according to claim 10,

wherein the specified code is zero.

12. The IC tag according to claim 10,

wherein the counter and the second memory have the same bit number.

13. The IC tag according to claim 10,

wherein the first information is comprised of at least identification number and an error detection code for detecting an error in the identification number.

14. A reading method for reading the first information from an IC tag having a first memory which memorizes first information, a second memory which memorizes second information and a counter in which a count value thereof indicates a bit address of the first memory to the reception unit, comprising:

transmitting a clock signal from the reception unit to the IC tag;

setting information of the second memory in the IC tag as an initial value of the counter;

performing count-up or count-down of a count value of the counter according to the clock signal; and

after the count value of the counter reaches a specified code, transmitting the first information stored in the bit address of the first memory indicated with the count value successively to the reception unit.

15. The reading method according to claim 14,

wherein the second memories of the IC tag are provided in plural number and the second information of any one of the second memories is selected according to the mode switching signal and set up in the IC tag as an initial value of the counter.

16. The IC tag according to claim 8,

wherein the specified code is zero.

17. The IC tag according to claim 9,

wherein the specified code is zero.

18. The IC tag according to claim 10,

wherein the specified code is zero.

19. The IC tag according to claim 8,

wherein the counter and the second memory have the same bit number.

20. The IC tag according to claim 9,

wherein the counter and the second memory have the same bit number.

21. The IC tag according to claim 10,

wherein the counter and the second memory have the same bit number.

22. The IC tag according to claim 8,

23. The IC tag according to claim 9,

24. The IC tag according to claim 10,