US20060096779A1 - Multilayer type printed-wiring board and method of measuring impedance of multilayer type printed-wiring board - Google Patents
Multilayer type printed-wiring board and method of measuring impedance of multilayer type printed-wiring board Download PDFInfo
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- US20060096779A1 US20060096779A1 US10/303,850 US30385002A US2006096779A1 US 20060096779 A1 US20060096779 A1 US 20060096779A1 US 30385002 A US30385002 A US 30385002A US 2006096779 A1 US2006096779 A1 US 2006096779A1
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- pattern
- impedance
- wire pattern
- data transmission
- impedance measuring
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
Abstract
The impedance of a newly manufactured data transmission wire pattern can be measured easily and accurately. A multilayer type printed-wiring board 1 comprises a pair of data transmission wire patterns 4, 5 arranged between a CPU module 2 and a memory module 3 on respective inner layer substrates 6, 7, impedance measuring wire patterns 21 and 22 arranged respectively in the layers same as those of the data transmission wire patterns 4, 5, a prepreg layer 11 arranged on the impedance measuring wire patterns 21, 22, land sections 23, 23 for signals arranged on the prepreg layer 11 and electrically connected to the impedance measuring wire patterns 21, 22 so as to be brought into contact with the signal terminal 41 of a probe 40 and a GND land section 24 also arranged on the prepreg layer 11 and electrically connected to the impedance measuring wire patterns 21, 22 so as to be brought into contact with the GND terminal 42 of the probe 40, the impedance measuring wire patterns 21, 22 having a pattern length not smaller than 30 mm that is the minimal length required for use with a TDR unit and a pattern width same as that of the data transmission wire patterns 4, 5.
Description
- 1. Field of the Invention
- This invention relates to a multilayer type printed-wiring board provided with a checking coupon for measuring the characteristic impedance of the data transmission wire pattern arranged between a CPU module and a memory module.
- 2. Related Background Art
- Electronic devices such as game machines for home use and mobile telephone sets typically comprises a printed-wiring board arranged in the cabinet thereof and a CPU (central processing unit) module and a main memory module are mounted there along with other modules. The CPU module and the memory module are connected to each other by a data transmission wire pattern arranged on the printed-wiring board.
- Meanwhile, the data transmission wire pattern of a printed-wiring board have to be designed in such a way that the impedance of the wire pattern shows a value that corresponds to the impedance specified for the CPU module and the memory module mounted on the printed-wiring board so that the CPU and the memory may operate reliably on a stable basis.
- However, some of the data transmission wire patterns of the printed-wiring boards shipped from manufacturing plants after the completion of the manufacturing process can show discrepancies between the design values and the actual values due to various reasons including the conditions for etching copper foils in the data transmission wire patterns to consequently give rise to an impedance greater or smaller than the design value. When the impedance does not agree with the design value, it is no longer possible to transmit exchange signals between the CPU module and the memory module.
- In view of the above circumstances, it is therefore an object of the present invention to provide a novel multilayer type printed-wiring board adapted to measuring the impedance of the data transmission wire pattern on the manufacturing floor in an easy and simple fashion.
- Another object of the present invention is to provide a multilayer type printed-wiring board comprising a pair of data transmission wire patterns arranged at the opposite sides of the inner layer substrate and adapted to measuring the impedances of the two data transmission wire patterns in a single measuring operation to improve the efficiency of the measurement process.
- According to the invention, the above objects are achieved by providing a multilayer type printed-wiring board comprising;
- a first insulating layer;
- a data transmission wire pattern arranged on said first insulating layer and adapted to data transmission between a CPU module and a main memory module to be used for the CPU;
- an impedance measuring wire pattern arranged on said first insulating layer in the layer same as that of said data transmission wire pattern with a predetermined clearance to any adjacent wiring pattern;
- a second insulating layer arranged on said data transmission wire pattern and said impedance measuring wire pattern; and
- land sections for signals arranged on said second insulating layer and electrically connected to said impedance measuring wire pattern arranged on said first insulating layer by way of a through hole so as to be held in contact with the signal terminal of the probe for measuring the impedance of said impedance measuring wire pattern and a GND (grounding) land section held in contact with the GND terminal of said probe;
- said impedance measuring wire pattern having a pattern length not smaller than about 30 mm and a pattern width same as that of said data transmission wire pattern when using a TDR (time domain reflectometer) unit.
- As pointed out above, the impedance measuring wire pattern for measuring the impedance of the multilayer type printed-wiring board is arranged in the layer same as that of the data transmission wire pattern adapted to data transmission between the CPU module and the main memory module to be used for the CPU, for which a certain level of impedance have to be secured.
- Preferably, the transmission frequency of said data transmission wire pattern of said multilayer type printed-wiring board is not less than 130 MHz so as to allow high speed data transmissions.
- Preferably, the clearance between said impedance measuring wire pattern of said multilayer type printed-wiring board and any adjacent wiring pattern is not less that twice of the pattern width of said impedance measuring wire pattern so as not to have any interference of the adjacent wiring pattern.
- Preferably, the wiring pattern arranged around the impedance measuring wire pattern of the multilayer type printed-wiring board is a GND pattern connected to said GND land section by way of a plurality of through holes so as to eliminate any inductance component.
- Still preferably, when a plurality of data transmission wire patterns are arranged in different layers in said multilayer type printed-wiring board, a plurality of impedance measuring wire patterns are arranged in different layers in correspondence to the respective data transmission wire patterns and electrically connected to each other by way of through holes.
- Thus, with a multilayer type printed-wiring board according to the invention, since an impedance measuring wire pattern is arranged in the layer of the data transmission wire pattern and the pattern width that affects the impedance of the device is made equal to that of the data transmission wire pattern so that the impedance of the data transmission wire pattern can be measured accurately by means of a method of measuring the impedance of a multilayer type printed-wiring board according to the invention. The impedance of a multilayer type printed-wiring board can be measured accurately by means of a TDR (time domain reflectometer) unit when the impedance measuring wire pattern has a pattern length not smaller than about 30 mm.
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FIG. 1 is a schematic plan view of an embodiment of multilayer type printed-wiring board according to the invention; -
FIG. 2 is a schematic cross sectional view of a principal part of the multilayer type printed-wiring board ofFIG. 1 ; -
FIG. 3 is an exploded schematic perspective view of a checking pattern arranged on the multilayer type printed-wiring board ofFIG. 1 ; -
FIG. 4A is a schematic plan view of the checking pattern ofFIG. 3 andFIG. 4B is a schematic cross sectional view of the checking pattern ofFIG. 3 . -
FIG. 5 is a schematic perspective view of a principal part of the multilayer type printed-wiring board ofFIG. 1 being measured for impedance by means of a TDR unit; -
FIG. 6 is a graph illustrating the waveform of the impedance of the multilayer type printed-wiring board ofFIG. 1 ; and -
FIG. 7 is a schematic cross sectional view of another embodiment of multilayer type printed-wiring board according to the invention. - Now, a multilayer type printed-wiring board and a method of measuring the impedance of a multilayer type printed-wiring board according to the invention will be described in greater detail by referring to the accompanying drawing.
FIG. 1 is a schematic plan view of an embodiment of multilayer type printed-wiring board according to the invention. The multilayer type printed-wiring board 1 has a total of six electro-conductive layers and is adapted to be used in a game machine for home use. - Referring to
FIG. 1 , the multilayer type printed-wiring board 1 comprises a CPU (central processing unit)module 2 and a pair ofmemory modules CPU module 2 that are arranged on one of the opposite sides of the multilayer type printed-wiring board 1. TheCPU module 2 has an operating frequency higher than that of any ordinary CPU and is adapted to operate at a frequency above about 290 MHz or more and typically between 300 MHz and 400 MHz so that it may be able to operate for a high speed image processing operation at a rate of 66 million polygons per second. Thememory modules CPU module 2, each having a memory capacity of 128 Mbytes. Thememory modules CPU module 2 and themselves and typically comprises so many RDRAMs (Direct Rambus Dynamic Random-access Memories: trademark, available from Rambus Technology). - The printed-
wiring board 1 carrying theCPU module 2 and thememory modules transmission wire patterns CPU module 2 and thememory modules FIG. 2 . The datatransmission wire patterns CPU module 2 so that they may effectively operate for high speed data transmissions between theCPU module 2 and thememory modules transmission wire patterns CPU module 2. - The data
transmission wire patterns CPU module 2 and thememory modules CPU module 2 and thememory modules transmission wire patterns CPU module 2 and thememory modules - The layered structure of the above described embodiment of multilayer type printed-
wiring board 1 will be discussed below. Referring now toFIG. 2 , the multilayer type printed-wiring board 1 comprises first and secondinner layer substrates inner layer substrate 6 carries on one of the surfaces thereof the datatransmission wire pattern 4 of the second layer and on the other surface thereof awiring pattern 8 that operates as a GND layer and forms the third layer. On the other hand, theinner layer substrate 7 carries on one of the surfaces thereof the datatransmission wire pattern 5 of the fourth layer and on the other surface thereof awiring pattern 9 that operates as a power supply layer and forms the fifth layer. Then, theinner layer substrates wiring pattern 8 of the third layer and the datatransmission wire pattern 5 of the fourth layer that are arranged vis-a-vis are pressed and bonded together with aprepreg layer 10 interposed therebetween, said prepreglayer 10 being made of glass fibers impregnated with epoxy resin. - Another
wiring pattern 12 that operates as a GND layer and forms the first layer is arranged on theinner layer substrate 6 with anotherprepreg layer 11 interposed therebetween. Still anotherwiring pattern 14 that operates as a signal layer and forms the sixth layer is arranged on theinner layer substrate 7 with still anotherprepreg layer 13 interposed therebetween. Thus, the multilayer printed-wiring board 1 having the above listed layers shows a strip line structure, in which the datatransmission wire pattern 4 is sandwiched by theinner layer substrate 6 that operates as an insulating layer and theprepreg layer 11 and the insulating layer is provided on the opposite surfaces thereof with therespective wiring patterns transmission wire pattern 5 is sandwiched by theinner layer substrate 7 that operates as an insulating layer and theprepreg layer 10 and the insulating layer is provided on the opposite surfaces thereof with therespective wiring patterns - Meanwhile, the above described data
transmission wire pattern CPU modules 2 and thememory modules wiring board 1 is provided with checkingcoupons transmission wire patterns checking coupons transmission wire patterns checking coupons transmission wire pattern checking coupons checking coupon 16 will be described below. - Referring to
FIG. 3 , thechecking coupon 16 comprises a first impedance measuringwire pattern 21 for measuring the impedance on one of the opposite surfaces of theinner layer substrate 6 that operates as an insulating layer, a second impedance measuringwire pattern 22 for measuring the impedance on one of the opposite surfaces of theinner layer substrate 7 that operates as an insulating layer and land sections includingland sections GND land section 24 arranged on theprepreg 11 operating as an insulating layer. - The first impedance
measuring wire pattern 21 arranged on one of the opposite surfaces of theinner layer substrate 6 is found in the second layer same as the datatransmission wire pattern 4 and made to show a pattern width and a pattern height same as those of the datatransmission wire pattern 4 so that its impedance characteristics may be identical with those of the datatransmission wire pattern 4. The first impedancemeasuring wire pattern 21 is provided at an end thereof with a first connectingsection 21 a for establishing electric connection with one of theland sections section 21 b for establishing electric connection with the second impedance measuringwire pattern 22. The first impedancemeasuring wire pattern 21 is also provided with aperipheral clearance 26 for preventing any electric interference of thewiring pattern 25 arranged adjacently relative to it. Theclearance 26 has a width more than twice, preferably more than three times, of the width W1 of the first impedancemeasuring wire pattern 21 in order to reliably eliminate any interference of thewiring pattern 25. In this embodiment, thewiring pattern 25 operates as GND (ground). The first impedancemeasuring wire pattern 21 is formed in the step of patterning the copper foil bonded onto theinner layer substrate 6 of the second layer. - On the other hand, the second impedance measuring
wire pattern 22 arranged on one of the opposite surfaces of theinner layer substrate 7 is found in the fourth layer same as the datatransmission wire pattern 5 and made to show a pattern width and a pattern height same as those of the datatransmission wire pattern 5 so that its impedance characteristics may be identical with those of the datatransmission wire pattern 5. The second impedance measuringwire pattern 22 is provided at an end thereof with a first connectingsection 22 a for establishing electric connection with the second connectingsection 21 b of the first impedancemeasuring wire pattern 21 arranged in the second layer and at the other end thereof with a second connectingsection 22 b for establishing electric connection with theother land section 23 for signals arranged in the first layer. The second impedance measuringwire pattern 22 is also provided with aperipheral clearance 28 for preventing any electric interference of thewiring pattern 27 arranged adjacently relative to it. Theclearance 28 has a width more than twice, preferably more than three times, of the width W2 of the second impedance measuringwire pattern 22 in order to reliably eliminate any interference of thewiring pattern 27. In this embodiment, thewiring pattern 27 operates as GND (ground). The first impedancemeasuring wire pattern 22 is formed in the step of patterning the copper foil bonded onto theinner layer substrate 7 of the fourth layer. - The
prepreg layer 11 is formed on the first impedancemeasuring wire pattern 21 arranged on one of the surfaces of theinner layer substrate 6 and theland section 23 for signals to be brought into contact with the probe of the TDR unit for measuring impedances and theGND land section 24 are arranged in part of thewiring pattern 12 of the GND layer that is by turn arranged on theprepreg layer 11. Theland sections GND land 24 is arranged around the outer peripheries of theland sections clearances 29 separating them from each other in order to electrically isolate it from theland sections wiring pattern 12 arranged around theprepreg layer 11 and operating as GND. - Now, the electric connections between the
land sections measuring wire pattern 21 of the second layer and the second impedance measuringwire pattern 22 of the fourth layer will be described below. The first impedancemeasuring wire pattern 21 and the second impedance measuringwire pattern 22 are electrically connected to each other by way of the second connectingsection 21 b of the second impedance measuring wire pattern and the first connectingsection 22 a of the second impedance measuringwire pattern 22 illustrated inFIGS. 2 and 3 . As shown inFIGS. 2 and 3 , the second connectingsection 21 b of the second impedance measuringwire pattern 21 and the first connectingsection 22 a of the second impedance measuringwire pattern 22 are electrically connected to each other by bonding theinner layer substrates prepreg layer 6 interposed therebetween, subsequently boring a throughhole 31 running through the second connectingsection 21 b and first connectingsection 22 a by means of a drill and forming a plating layer (not shown) on the inner wall of the through hole by means of a non-electrolytic or electrolytic plating method. - One of the
land sections section 22 a of the first impedancemeasuring wire pattern 21 of the second layer. On the other band, theother land section 23 for signals and the first connectingsection 22 a are electrically connected to each other by boring a throughhole 32 through the center of theland section 23 for signals of the substrate integrally that is formed by laying theprepreg layer 11 where the copper foil of the first layer is bonded to theinner layer substrates prepreg layer 13 where the copper foil of the sixth layer is bonded and bonding the two prepreg layers together in a press process and subsequently forming a plating layer on the inner wall of the throughhole 32. - The
other land section 23 of the first layer is electrically connected to the second connectingsection 22 b of the second impedance measuringwire pattern 22 of the fourth layer. To be more accurate, theother land section 23 for signals and the second connectingsection 22 b become electrically connected to each other by forming a plating layer (not shown on the inner wall of a throughhole 33 that is formed simultaneously with the above described throughhole 32. - Meanwhile, the first and second impedance measuring
wire patterns - In the case of this embodiment, the applicable transmission frequency of the first and second impedance measuring
wire pattern transmission wire patterns
is obtained. - Therefore, the effective wavelength λ in a conductor is expressed by [Formula 1] below.
- When measuring impedances by means of a TDR unit, the minimal length, or min L, of the data
transmission wire patterns
min L=λ/4=0.125/4=0.03125 (m)≈30 (mm) [Formula 1] - Note that min L is made equal to a quarter of the effective wavelength, or λ/4, because it is the minimum length necessary for reproducing the original waveform, taking the influence of reflections and other factors due to mismatched impedances into consideration.
- In other words, the data
transmission wire patterns
min L≧(applicable transmission frequency×3)/4 - In this embodiment, a length of 65 mm is selected because it represents the most table value as shown in Table 1 below.
TABLE 1 pattern length L (mm) less than 30 30 50 55 60 65 70 90 100 or more measured unmeasurable 52.1 51.5 51.3 51.1 51.1 51.1 51.1 51.1 value (Ω) - Meanwhile, as shown in
FIGS. 4A and 4B , thewiring pattern 12 that operates as part of the checkingpattern 16, thewiring pattern 25 of the second layer and thewiring pattern 27 of the fourth layer are electrically connected to each other by way of the plating layer (not shown) on the inner surfaces of the plurality of throughholes 34 so as to eliminate any inductance component of thewiring patterns
gap P (mm)≦(propagation velocity)÷(4×thrice of applicable frequency)
≦(wavelength at 1.2 GHz in copper)/4
≦125 (mm)/4
≦31.25 (mm) - The above described checking
patterns transmission wire patterns wiring board 1. A TDR (time domain reflectometer) unit is typically used to observe the impedances. As shown inFIG. 5 , a TDR unit comprises aprobe 40 that is provided withsignal terminals respective land sections GND terminal 42 to be held in contact with theGND land section 24. From the viewpoint of the checkingpatterns signal terminals 41 are brought into contact with therespective land sections GND terminal 42 is brought into contact with theGND land section 24 when measuring the impedances. The TDR unit is used to measure the impedances of the first and secondimpedance measuring patterns FIG. 6 . - Referring to
FIG. 3 , since the firstimpedance measuring pattern 21 and the secondimpedance measuring pattern 22 of the multilayer type printed-wiring board 1 are electrically connected to each other, it is possible to measure both the impedance of the firstimpedance measuring pattern 21 arranged in the second layer and that of the secondimpedance measuring pattern 22 arranged in the fourth layer in a single measuring session. In other words, the TDR unit can measure both the impedance of the firstimpedance measuring pattern 21 and that of the secondimpedance measuring pattern 22 by counting the elapsed time since the start of the measuring session. - Referring to
FIG. 6 showing the waveform displayed on the monitoring screen of the TDR unit, the observed impedance fluctuates at point A that corresponds to theland sections section 21 a and the first connectingsection 22 a connecting the firstimpedance measuring pattern 21 and the secondimpedance measuring pattern 22. Thereafter, the observed impedance fluctuates once again at point C that corresponds to the second connectingsection 22 b of the secondimpedance measuring pattern 22. The observed impedance is held to a constant level both in the interim between point A and point B and in the interim between point B and point C. Therefore, when the impedance is visually observed, it is possible to check the impedance of the firstimpedance measuring pattern 21 and that of the secondimpedance measuring pattern 22 by locating point A, point B and point C where the impedance fluctuates in the waveform of impedance. - With the above described multilayer type printed-
wiring board 1, the impedances of the datatransmission wire patterns impedance measuring pattern 21 and the secondimpedance measuring pattern 22 having a width and a height same as those of the datatransmission wire patterns transmission wire patterns FIG. 3 , the impedances of the wiring patterns arranged in different layers can be measured in a single measuring session to remarkably reduce the time required for the checking process because the firstimpedance measuring pattern 21 and the secondimpedance measuring pattern 22 are electrically connected to each other by way of the second connectingsection 21 b and the first connectingsection 22 a. - While the present invention is described above in terms of a six-layered printed-
wiring board 1, the present invention is by no means limited thereto and may also be applied to a printed-wiring board as shown inFIG. 7 . - Referring to
FIG. 7 , the printed-wiring board 50 comprises two electro-conductive layers and afirst wiring pattern 52 operating as a GND layer is arranged on one of the surfaces ofsubstrate 51 while asecond wiring pattern 53 operating as a signal layer is arranged on the other surface of thesubstrate 51. With a printed-wiring board 50 having such a configuration, it may be so arranged that land sections for signals and a GND land section are provided at the side of thefirst wiring pattern 53 and a measuring probe is provided at the side of thesecond wiring pattern 52.
Claims (11)
1. A multilayer type printed-wiring board comprising;
a first insulating layer;
a data transmission wire pattern arranged on said first insulating layer and adapted to data transmission between a CPU module and a main memory module to be used for the CPU;
an impedance measuring wire pattern arranged on said first insulating layer in the layer same as that of said data transmission wire pattern with a predetermined clearance to any adjacent wiring pattern;
a second insulating layer arranged on said data transmission wire pattern and said impedance measuring wire pattern; and
land sections for signals arranged on said second insulating layer and electrically connected to said impedance measuring wire pattern arranged on said first insulating layer by way of a through hole so as to be held in contact with the signal terminal of the probe for measuring the impedance of said impedance measuring wire pattern and a GND (grounding) land section held in contact with the GND terminal of said probe;
said impedance measuring wire pattern having a pattern length not smaller than about 30 mm and a pattern width same as that of said data transmission wire pattern.
2. The multilayer type printed-wiring board according to claim 1 , wherein the transmission frequency of said data transmission wire pattern is not less than 130 MHz.
3. The multilayer type printed-wiring board according to claim 1 , wherein the clearance between said impedance measuring wire pattern and any adjacent wiring pattern is not less than twice of the pattern width of said impedance measuring wire pattern.
4. The multilayer type printed-wiring board according to claim 1 , wherein the wiring pattern arranged around the impedance measuring wire pattern is a GND pattern connected to said GND land section by way of a plurality of through holes.
5. The multilayer type printed-wiring board according to claim 1 , wherein a plurality of impedance measuring wire patterns are arranged in different layers and electrically connected to each other by way of through holes.
6. A method of measuring the impedance of a multilayer type printed-wiring board comprising:
a first insulating layer;
a data transmission wire pattern arranged on said first insulating layer and adapted to data transmission between a CPU module and a main memory module to be used for the CPU;
an impedance measuring wire pattern arranged on said first insulating layer in the layer same as that of said data transmission wire pattern with a predetermined clearance to any adjacent wiring pattern;
a second insulating layer arranged on said data transmission wire pattern and said impedance measuring wire pattern;
land sections for signals arranged on said second insulating layer and electrically connected to said impedance measuring wire pattern arranged on said first insulating layer by way of a through hole so as to be held in contact with the signal terminal of the probe for measuring the impedance of said impedance measuring wire pattern and a GND (grounding) land section held in contact with the GND terminal of said probe; and
said impedance measuring wire pattern having a pattern length not smaller than about 30 mm and a pattern width same as that of said data transmission wire pattern;
said method comprising a step of:
measuring the impedance of said impedance measuring wire pattern by bringing the signal terminal and the GND terminal of said probe into contact respectively with said land sections for signal and said GND land section.
7. The method of measuring the impedance of a multilayer type printed-wiring board according to claim 6 , wherein the transmission frequency of said data transmission wire pattern is not less than 130 MHz.
8. The method of measuring the impedance of a multilayer type printed-wiring board according to claim 6 , wherein the clearance between said impedance measuring wire pattern and any adjacent wiring pattern is not less than twice of the pattern width of said impedance measuring wire pattern.
9. The method of measuring the impedance of a multilayer type printed-wiring board according to claim 6 , wherein the wiring pattern arranged around the impedance measuring wire pattern is a GND pattern connected to said GND land section by way of a plurality of through holes.
10. The method of measuring the impedance of a multilayer type printed-wiring board according to claim 6 , wherein a plurality of impedance measuring wire patterns are arranged in different layers and electrically connected to each other by way of through holes.
11. The method of measuring the impedance of a multilayer type printed-wiring board according to claim 10 , wherein the impedances of said wiring patterns arranged in different layers are measured by measuring said plurality of impedance measuring patterns arranged in different layers in a single measuring operation.
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US10/303,850 US20060096779A1 (en) | 2000-03-02 | 2002-11-26 | Multilayer type printed-wiring board and method of measuring impedance of multilayer type printed-wiring board |
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JP2000061874A JP2001251061A (en) | 2000-03-02 | 2000-03-02 | Multilayer printed wiring board |
US09/793,977 US6512181B2 (en) | 2000-03-02 | 2001-02-28 | Multilayer type printed-wiring board and method of measuring impedance of multilayer type printed-wiring board |
JPP2000-061874 | 2001-03-02 | ||
US10/303,850 US20060096779A1 (en) | 2000-03-02 | 2002-11-26 | Multilayer type printed-wiring board and method of measuring impedance of multilayer type printed-wiring board |
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US09/793,977 Division US6512181B2 (en) | 2000-03-02 | 2001-02-28 | Multilayer type printed-wiring board and method of measuring impedance of multilayer type printed-wiring board |
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US20060096779A1 true US20060096779A1 (en) | 2006-05-11 |
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US09/793,977 Expired - Fee Related US6512181B2 (en) | 2000-03-02 | 2001-02-28 | Multilayer type printed-wiring board and method of measuring impedance of multilayer type printed-wiring board |
US10/303,850 Abandoned US20060096779A1 (en) | 2000-03-02 | 2002-11-26 | Multilayer type printed-wiring board and method of measuring impedance of multilayer type printed-wiring board |
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DE10305520A1 (en) * | 2003-02-11 | 2004-08-19 | Robert Bosch Gmbh | Attenuation of cavity resonance generated in a multilayer hybrid electronic printed circuit board |
US20040194999A1 (en) * | 2003-04-03 | 2004-10-07 | Matsushita Electric Industrial Co., Ltd. | Wiring board, method for manufacturing a wiring board and electronic equipment |
US7034544B2 (en) * | 2003-06-30 | 2006-04-25 | Intel Corporation | Methods for minimizing the impedance discontinuity between a conductive trace and a component and structures formed thereby |
JP4259311B2 (en) * | 2003-12-19 | 2009-04-30 | 株式会社日立製作所 | Multilayer wiring board |
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- 2001-02-28 US US09/793,977 patent/US6512181B2/en not_active Expired - Fee Related
- 2001-02-28 CN CN01116888.9A patent/CN1313722A/en active Pending
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CN105228378A (en) * | 2015-08-31 | 2016-01-06 | 北大方正集团有限公司 | A kind of circuit board and impedance method for measurement thereof |
CN105338728A (en) * | 2015-10-23 | 2016-02-17 | 北大方正集团有限公司 | Circuit board impedance measuring method and circuit board |
Also Published As
Publication number | Publication date |
---|---|
US20020040809A1 (en) | 2002-04-11 |
US6512181B2 (en) | 2003-01-28 |
JP2001251061A (en) | 2001-09-14 |
CN1313722A (en) | 2001-09-19 |
TW516342B (en) | 2003-01-01 |
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