US 20060039317 A1
An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal processor. The channel pooling signal processor includes a plurality of computation units typically realized in a heterogeneous multiprocessing architecture, a test interface for testing the function of the plurality of the computation units, a general-purpose microprocessor for managing the dataflow into and out of the channel pooling signal processor as well as effecting the control and configuration of the computation units, and an interconnect mechanism for connecting the plurality of computation units to the input, output, test interface, and the general-purpose microprocessor.
9. Method for reconfiguring a signal processor having a plurality of computational units in a base-station transceiver system to support at least one of a plurality of service classes of interest that include at least one of multiple cellular telephone telecommunication system standards, applications and protocols, comprising the steps of:
profiling the function to be performed by the signal processor by:
first surveying all signal processing and control functions required to accommodate the service classes of interest,
analyzing the commonality of signal functions across the service classes of interest;
defining the data processing computational units necessary to serve the services of interest;
analyzing the data flow from the profiling; and
interconnecting the plurality of computational units based on the results of the data flow analysis.
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18. The method as claimed in
categorizing the functions according to a type of operation such as one of arithmetic/logical, control and memory access; and
determining the characteristic computational power required to perform each such function.
19. The method as claimed in
measuring the number of static operations of a given type required to realize a receiver for a particular system standard.
20. A CDMA base station transceiver system for operating across a plurality of cellular telephone telecommunication system standards comprising:
a computational unit having a fixed hardware portion and flexible hardware portion; and
means for reconfiguring the flexible hardware portion to accommodate each of the different cellular telephone telecommunication system standards.
21. A CDMA base station transceiver as claimed in
a channel pooling signal processor, including:
a reconfigurable multiprocessor having a plurality of computational units and an interconnect mechanism, each said computational unit having a data sequencer for controlling program execution, a configurable logic unit and a dedicated memory.
22. A CDMA base station transceiver system as claimed in
a general purpose microprocessor for managing data flow into and out of said channel pooling signal processor;
wherein the interconnect mechanism connects said plurality of computational units and said general purpose microprocessor; and
a digital signal processor connected to said channel pooling signal processor;
wherein said channel pooling signal processor performs more computationally intensive signal processing operations and said digital signal processor performs less computationally intensive signal processing operations.
23. A CDMA base station transceiver system as claimed in
matched filter functions to perform preamble processing,
parameter estimator, and
channel element processing.
24. The CDMA base station transceiver system as claimed in
diversity method selection,
code modulation, and
a channel summer.
25. The CDMA base station transceiver system as claimed in
26. A CDMA base station transceiver system as claimed in
said computational unit flexible portion performs at least one of the functions of descrambling and dechannelization of a received signal.
This application claims priority to the provisional patent applications with the following Ser. Nos.: 60/173,630 and 60/178,815, filed on Dec. 30, 1999 and Jan. 28, 2000, respectively.
This application is related to the following applications which are incorporated herein by reference: a U.S. patent application entitled “A CONFIGURABLE ALL-DIGITAL COHERENT DEMODULATOR SYSTEM FOR SPREAD SPECTRUM APPLICATIONS”, bearing application Ser. No. ______; a U.S. patent application entitled “A CONFIGURABLE MULTI-MODE DESPREADER FOR SPREAD SPECTRUM APPLICATIONS” bearing application Ser. No. ______; a U.S. patent application entitled “APPARATUS AND METHOD FOR CALCULATING AND IMPLEMENTING A FIBONACCI MASK FOR A CODE GENERATOR” bearing application Ser. No. ______; a U.S. patent application entitled “A FAST INITIAL ACQUISITION & SEARCH DEVICE FOR A SPREAD SPECTRUM COMMUNICATION SYSTEM” bearing application Serial No. ______; and a U.S. patent application entitled “A CONFIGURABLE CODE GENERATOR” bearing application Ser. No. ______. All of the above applications are filed simultaneously herewith on ______.
In addition, this application is related to a U.S. patent application entitled “IMPROVED APPARATUS AND METHOD FOR MULTI-THREADED SIGNAL PROCESSING” bearing application Ser. No. 09/492,634, filed on Jan. 27, 2000, which is likewise incorporated herein by reference.
This invention relates generally to reconfigurable signal processors. Such processors are useful in wireless communication systems and, more particularly, in a method and apparatus for transmitting voice and data between multi-standard, multi-service base-stations. The invention will be described in such context.
In order to transmit and receive circuit and packet-switched voice and data traffic in a multi-user wireless communications environment, with services such as voice, video, image, data, fax, IP-based traffic transmissions, etc., it is necessary to employ a base-station transceiver system (hereafter referred to as “BTS”). A BTS provides a link for sending and receiving wireless communications within a localized region. Recently, there has been an increase in demand for different types of wireless communication services.
This has led to the need for data services (the term “data services” includes both voice and data services) requiring greater bandwidths and an increased number of channels. In addition, there is a growing need for BTSs to support multiple standards and protocols (i.e., service classes). Traditional signal processing architectures, such as that shown in
The prior art signal processing architecture shown in
Each circuit 110 is typically realized as a single-bus shared memory co-processing architecture which includes at least one application specific fixed function integrated circuit 114, one digital signal processor 116, and one memory 118 for processing data in that channel. A problem associated with the traditional signal processing architecture, such as that shown in
The problems of inadequate efficiency, demand for greater bandwidths, and more channels per data service have necessitated the development of an efficient, cost effective mechanism for the processing of wireless data.
In one embodiment of the invention, signal processing is performed in a signal processor that includes a plurality of computation units, a test interface, a general purpose microprocessor, and an interconnect mechanism. The signal processor is referred to as a “channel pooling signal processor.” Additionally, in an exemplary embodiment, a separate digital signal processor is also used with the channel pooling signal processor.
The computation units are flexibly configured and connected in that they may be used to achieve any one of several different transceiver functions. For example, the computation units can be configured to perform downconversion, dechannelization, demodulation, decoding, equalization, despreading, encoding, modulation, spreading, diversity processing. These computation units are typically able to support a specific type of signal processing associated with a specific class of waveforms (time-division, code-division, of frequency-division), represented by a mathematical function or sequence of mathematical functions operating across a variety of data rates, as well as multiple modes of operation.
The test interface is used for testing all internal states of the channel pooling signal processor, including testing the functions of the computation units. The general purpose microprocessor manages control of how the data flowing into and out of the channel pooling signal processor. Typically, the general purpose microprocessor is a programmable microprocessor capable of setting up the interconnect to route data from the input of the channel pooling signal processor, to and from any computation unit, and to the output of the channel pooling signal processor. The interconnect mechanism is used for connecting the components of the channel pooling signal processor to one another. In other words, the interconnect mechanism joins the computation units, the test interface, and the input-output interface, such that all of these components are under the control of the general-purpose microprocessor.
In another embodiment of the invention, the signal processing is performed using more than one channel pooling signal processor. The additional channel pooling signal processor(s) allow the method and structure to process multiple data streams corresponding to multiple channels of voice or data information.
An advantage of the method and structure of an embodiment of the invention is the ability to provide a linear increase in channel density solely via a linear increase in the system operating frequency or clock speed.
Another advantage of the method and structure of an embodiment of the invention includes the ability to use more than one channel pooling signal processor. Using multiple channel pooling signal processors allows multiple data streams corresponding to multiple channels to be processed.
Another advantage of the disclosed technology is that the general purpose microprocessor can enable configuration across different operating modes, for example, including: service type, channel type, data protection type, modulation type, and reception type.
An additional advantage of the invention is that a set of computation units may be optimized for the execution of functions with high computational complexity.
Still another advantage of the invention is that a greater number of channels can be processed on the same BTS, thus circumventing limitations of the prior art.
In an exemplary embodiment, the heterogeneous reconfigurable multiprocessor 66 includes a pool of parallel hardware signal processors referred to as computation units or kernels. The computation units perform the more computationally intensive signal processing operations required by a set of telecommunications standards, applications and services of interest, and are selected and configured in a modular, non-redundant manner. The individual computation units and their interconnections can be quickly reconfigured, so that the BTS 200 can quickly switch from one standard, application, and/or service of interest to another. The DSP 72 performs the less computationally intensive signal processing functions, while the microprocessor 74 performs control and other functions.
Each hardware device is controlled by a corresponding software module. A detailed description of the relationship between the software module and the hardware devices (i.e., multiprocessor 66, DSP 72, and general purpose microprocessor 74) is explained in U.S. patent application entitled “Reprogrammable Digital Wireless Communication Device and Method of Operating Same” bearing Ser. No. 09/565,687. This application is hereby incorporated by reference for all purposes.
The interconnect mechanism 32 provides a means for connecting the computation units 36, other components of the channel pooling signal processor 76, and other components in the BTS 200 to each other. For example, the interconnect mechanism 32 is capable of changing configurations for specific channels, while maintaining the status and operation modes of all other channels in an unchanged condition. In one embodiment, the interconnect mechanism 32 can be any interconnect mechanism known in the art such as a switch and switch controller, or a set of buses and a bus-controller. Preferably, the switch controller or bus-controller includes software to change the configurations for specific channels while maintaining the status and operating modes of all other channels in an unchanged state.
The test interface 34 allows the user to test the channel pooling signal processor 76 in all operating modes, including testing the computation units 36 in various modes of operation. The flexibility of the interconnect mechanism 32 and the general purpose microprocessor 74 allows individual computation units 36 to be tested for functionality and reliability while maintaining the status and operating modes of all other channels in an unchanged state. In an exemplary embodiment, the test interface 34 is implemented using JTAG or a proprietary testing interface.
The computation units 36A-36F perform the more computationally intensive operations required of BTS200. In an exemplary embodiment, computation units 36 are flexibly configurable and may be used to achieve any one of several different functions. These functions include, but are not limited to, channel decoding, equalization, chip-rate processing, synchronization, digital down-conversion and channelization, and parameter estimation of signal energy, interference energy, number of interferers, timing signals, coding signals, frequency signals, and error signals. Computation units 36 may be implemented to support a mathematical function operating across a variety of data rates, and/or modes of operation. In the usual case, these modes of operation correspond to specific predefined variations of existing dataflow or control flow algorithms, including, but not limited to, demodulation, despreading, detection, MLSE equalization, parameter estimation, energy estimation, synchronization estimation, channel estimation, interference estimation, channel decoding, convolutional decoding, and turbo decoding for narrowband and wideband TDMA, CDMA, and OFDM systems.
The type and number of computation units 36 required by the BTS 200 is determined according to system architecture requirements. The system designer bases system architecture requirements on factors including the number of channels requited to support the BTS 200 and the I/O bandwidth required per BTS 200. The resulting BTS 200 architecture may have either a homogeneous or heterogeneous set of computation units 36. A detailed description of an exemplary method used to determine the type and number of computation units 36 is explained in U.S. patent application entitled “Method of Profiling Disparate Communications and Signal Processing Standards and Services” bearing Ser. No. 09/565,654. This application is hereby incorporated by reference for all purposes.
If there are multiple non-identical computation units, the heterogeneous reconfigurable multiprocessor 66 operates during execution as a heterogeneous multiprocessing machine. Based on the selection of computation units 36, an augmented instruction set is defined for the heterogeneous reconfigurable multiprocessor 66. This augmented instruction set can be created, for example, by using a wide-word instruction by appending bits to an existing instruction word, with the new bit fields exclusively devoted to the decoding of instructions for the control and data flow for the heterogeneous reconfigurable multiprocessor. The instruction word, when decoded, feeds control units 156 and 158 of
For further illustration,
The heterogeneous reconfigurable multiprocessor 66 is designed according to a method referred to as profiling. Profiling includes the first step of surveying all signal processing and control functions required to accommodate the standards, applications, and/or services of interest. The most computationally intensive of these functions are then targeted to the heterogeneous reconfigurable multiprocessor 66, while the remaining functions are targeted to the DSP microprocessor 72. Typically, computational intensity is enumerated in units of millions of operations per second (MOPS). For example,
Additionally, computationally intensive functions are further categorized according to type of operation, e.g., arithmetic/logical, control, and memory access. For each category, characteristic power per MOPS is determined for hardware or software implementation from vendor data, analysis, or other means. Power, e.g., milliwatts, required per function is thereby characterized for implementation in both reconfigurable hardware or in software (i.e., running on a processor whose power-per-MOPS has been characterized). In addition, the corresponding code size (and therefore memory requirement) for software implementation is determined. From the above, and from budgeted power and memory resources, allocation of processing operations to hardware and software processors can be determined.
The entries in spreadsheet 200 correspond to a measurement of the number of static operations of a given type required to realize a receiver for a particular standard, i.e., to a specific time within a dynamic operational scenario. The analysis of
The second step of profiling involves analysis of commonality of signal processing functions across the standards, applications, and/or services of interest. An exemplary analysis is represented in
The third profiling step, defining the data processing computation units 36 necessary to serve the standards, applications, and/or services of interest, is shown conceptually in
The interconnection of computation units 36 must also be determined from profiling as shown in the exemplary abridged matrix 260 of
To summarize, reconfiguration of the heterogeneous reconfigurable multiprocessor 66 is affected by i) selection of hardware processing computation unit types, ii) control of the variable computation unit functionality, and iii) control of the reconfigurable data router 32.
Once the computation unit types and interconnections have been determined, the multiplicity of each computation unit type needs to be determined, as illustrated in
Thus, a manufacturer can enjoy mass customization based on a common product “platform.” Initial or subsequent configuration can be performed in the factory, at point-of-sale, by the network operator at time of delivery, or by the network operator or service provider while in the field. Post-delivery customization can be based upon any of a number of techniques, including but not limited to smart card, wired interface, and over-the-air/over-the-network download and billing.
Typically, in a CDMA base station transceiver system, at least one computation unit 36 should perform the function of chip-rate processing, including descrambling and dechannelization functions. The computation unit 36 utilized to perform such functions generally has a fixed hardware portion and a flexible hardware portion. The flexible hardware portion can be reconfigured to comply with different standards.
Using the profiling steps described above, functions to be performed by a CDMA, TDMA or OFDM system can be categorized and a library of reconfigurable computation units 36 for each such multiple access system can be created.
In an exemplary embodiment, the stated functions of the CDMA BTS engine 470 are performed by processors 66, 72, and 74 (see
In an exemplary embodiment, the finger computation units 502 despread and demodulate received signals, and provide symbols to the combiner computation unit 512. In an exemplary embodiment, each finger computation unit corresponds to a specific received multipath or echo for a specific user.
The code generator computation units 504 generate local replica of the scrambling and channelization codes. The output of the code generator computation units 504 is fed to the finger computation units 502, searcher computation units 506, and the preamble processor computation unit 508. In one embodiment, each finger computation unit 502, searcher computation unit 506, and the preamble processor computation unit 508 has its own corresponding code generator computation unit 504.
The searcher computation units 506 are hypothesis testing devices used to search for a new mobile that entered the antenna-sector of interest or search for a new multipath for an existing mobile.
The preamble processor computation unit 508 detects the presence of access bursts from new mobiles. An access burst is a random access attempt by a mobile.
The combiner computation units 510 ensure multipath and antenna diversity. The combiner computation units 510 take a set of finger computation units 502 corresponding to a single mobile and produce output statistics (e.g., sum, or weighted sum, etc.) that combines signals into one output.
The parameter estimator computation units 512 provide estimates for three types of random variables, namely, synchronization estimates (i.e., timing and frequency control estimates), channel estimates (i.e., amplitude, phase and delay estimates), and energy and interference estimates (i.e., signal interference ratio estimates).
The transmitter computation unit 514 generates downlink transmit signals of all common and dedicated control traffic channels.
The antenna buffer 516 performs antenna data decimation, antenna data buffering, and antenna source select functions.
The tracking scheduler 518 performs master timing control, uplink protocol timing updates, codes generation (except searcher), uplink context memory control and scheduling (except searcher), microprocessor interface 526 control, and time-slice pipeline control functions.
The combined data processor 520 performs combined-data scaling, receive-transmit data interface, and miscellaneous interfaces and functions.
The multiple search multi-selects 522 perform searcher symbol-rate processing and threshold and multi-dwell search algorithms.
The search control 524 performs searcher scheduling and context memory control, pipeline control, and microprocessor interface 526 control functions.
The microprocessor interface 526 provides general interface functions to a microprocessor. The transmitter controller 528 performs transmission control functions.
Advantageously, the architecture of the invention optimally combines fixed-function and reconfigurable logic resources. The system has reconfigurable control and data paths. The invention extends the performance efficiency of microprocessors and digital signal processors via the augmentation of data paths and control paths through a reconfigurable co-processing machine. The reconfigurability of the data path optimizes the performance of the data flow in the algorithms implemented on the processor.
The architecture efficiently redirects functions previously running on a fixed function data arithmetic logic unit to a more flexible heterogeneous reconfigurable multiprocessing unit. The invention does not depend upon the fine-grained reconfigurability of existing programmable logic devices, and hence solves an inherent problem to such devices, whereby the area and power of the chip are dominated by the routing resources. Furthermore, the invention does not substantially rely on instruction-set programmable processors. Instead, a quasi-fixed set of hardware computational resources that span the signal processing requirements of the standards, applications, and/or services of interest are configured together in a reprogrammable manner. This architecture can be applied to implement signal processing and/or control of processing applications.
In an exemplary embodiment, a base-station architecture may include only homogeneous computation units, where each homogeneous computation unit is identical in functionality, modes, and performance. In another exemplary embodiment, a base-station architecture may include heterogeneous computation units, where the computation units typically cover two or three different functions per channel.
For a given architecture, there are typically up to four modes of operation. These four modes of operation include, but are not limited to:
Preferably, each of these modes of operation is set directly, via in-situ or over-the-network programming.
The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the invention. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.