US20060029833A1 - Methods for forming a barrier layer with periodic concentrations of elements and structures resulting therefrom - Google Patents

Methods for forming a barrier layer with periodic concentrations of elements and structures resulting therefrom Download PDF

Info

Publication number
US20060029833A1
US20060029833A1 US11/199,620 US19962005A US2006029833A1 US 20060029833 A1 US20060029833 A1 US 20060029833A1 US 19962005 A US19962005 A US 19962005A US 2006029833 A1 US2006029833 A1 US 2006029833A1
Authority
US
United States
Prior art keywords
film
sub
microelectronic topography
deposition
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/199,620
Inventor
Igor Ivanov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/199,620 priority Critical patent/US20060029833A1/en
Assigned to BLUE29, LLC reassignment BLUE29, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IVANOV, IGOR C.
Publication of US20060029833A1 publication Critical patent/US20060029833A1/en
Assigned to KLA-TENCOR CORPORATION reassignment KLA-TENCOR CORPORATION SECURITY AGREEMENT Assignors: BLUE 29, LLC
Assigned to LAM RESEARCH CORPORATION reassignment LAM RESEARCH CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BLUE29, L.L.C.
Priority to US13/533,692 priority patent/US20120263869A1/en
Priority to US14/080,257 priority patent/US9953866B1/en
Priority to US15/925,446 priority patent/US20180218942A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1619Apparatus for electroless plating
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00Nanotechnology for materials or surface science, e.g. nanocomposites
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1633Process of electroless plating
    • C23C18/1646Characteristics of the product obtained
    • C23C18/165Multilayered product
    • C23C18/1651Two or more layers only obtained by electroless plating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1633Process of electroless plating
    • C23C18/1675Process conditions
    • C23C18/1682Control of atmosphere
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1633Process of electroless plating
    • C23C18/1675Process conditions
    • C23C18/1683Control of electrolyte composition, e.g. measurement, adjustment
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/6715Apparatus for applying a liquid, a resin, an ink or the like
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76858After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864Thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76867Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00Processes for servicing or operating cells for electrolytic coating
    • C25D21/10Agitating of electrolytes; Moving of racks
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/08Electroplating with moving electrolyte e.g. jet electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12458All metal or with adjacent metals having composition, density, or hardness gradient
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24612Composite web or sheet

Definitions

  • This invention generally relates to methods for processing a microelectronic topography and more particularly to electroless plating processes performed upon microelectronic topographies and structures resulting therefrom.
  • Electroless plating is a process for depositing materials on a catalytic surface from an electrolyte solution without an external source of current.
  • An advantage of an electroless plating process is that it can be selective, i.e., the material can be deposited only onto areas that demonstrate appropriate chemical properties.
  • local deposition can be performed onto metals that exhibit an affinity to the material being deposited or onto areas pretreated or pre-activated, e.g., with a catalyst.
  • the ratio of the deposition rate on the activated regions to the deposition rate at the non-activated regions is known as the “deposition process selectivity.”
  • high deposition selectivity may be advantageous for the formation of metal features within integrated circuits, such as but not limited to contacts, vias, and interconnect lines.
  • an electroless plating process is producing a deposition profile which is commensurate with the fabrication specifications of the device. For instance, in some cases, it may be advantageous to have a film deposited with substantially uniform thickness. In cases in which a film is electrolessly deposited across a microelectronic topography, however, obtaining thickness uniformity may be difficult. In particular, some electroless plating techniques are susceptible to the “edge effect” in which portions of a film deposited near the edge of the wafer are thinner than the portions of the film deposited near the center of the wafer. Such an effect also hinders fabrication specifications for depositing films having greater thicknesses near the edge of the wafer as compared to near the center of the wafer.
  • electroless plating may be used for the formation of metal features within integrated circuits.
  • electroless plating techniques may be particularly favorable for depositing materials into deep and/or narrow holes that cannot be uniformly covered by other deposition techniques, such as sputtering and evaporation, for example.
  • electroless plating techniques may be advantageous for forming copper features, complementing the trend in the integrated circuit industry of employing copper metallization structures instead of aluminum, tungsten, silicides, or the like.
  • a barrier layer may be arranged beneath and/or upon a metal feature to prevent elements within the metal feature from respectively diffusing to underlying and overlying layers of the topography.
  • barrier layers may, in some embodiments, be formed by electroless plating processes. Although conventional barrier layers are generally sufficient to inhibit most elemental diffusion from a metal feature, some diffusion may still occur. For example, copper atoms are particularly notorious for being able to migrate through barrier layers. The migrated copper atoms can potentially be exposed to oxidation or moisture at the surface of the barrier layer or may tunnel through silicon materials disposed adjacent to the barrier layer, affecting the reliability of the device and, in some cases, causing the device to malfunction.
  • barrier layers which inhibit a greater degree of elemental diffusion from overlying and/or underlying metal features than provided by conventional barrier layers.
  • An embodiment of one of the methods includes positioning the microelectronic topography within an electroless plating chamber, dispensing a first deposition solution upon the microelectronic topography to form a first sub-film, and subsequently removing the first deposition solution from the electroless plating chamber.
  • the method further includes dispensing a second deposition solution upon the microelectronic topography subsequent to the removal of the first deposition solution to form a second sub-film upon and in contact with the first sub-film.
  • the second sub-film includes multiple elements included within the first sub-film.
  • An embodiment of another of the methods includes forming a bulk metallic film upon the microelectronic topography using an electroless plating process.
  • the bulk metallic film includes a bottom portion, a top portion, and an intermediate portion interposed between the bottom and top portions.
  • One of the top and bottom portions includes a higher concentration of a first element than the intermediate portion and the other of the top and bottom portions.
  • the method further includes annealing the microelectronic topography to induce diffusion of the first element within the bulk metallic film such that the intermediate portion comprises a higher concentration of the first element than the bottom and top portions.
  • An embodiment of yet another of the methods includes exposing a microelectronic topography to a deposition solution and forming a first sub-film portion by interfacial electroless reduction of a first element within the deposition solution until a second different element reaches a certain concentration within the deposition solution.
  • the first sub-film includes a higher concentration of the first element than the second element.
  • the method further includes forming a second sub-film portion upon and in contact with the first sub-film portion by chemical adsorption until the first element increases to a particular concentration within the deposition solution.
  • the second sub-film includes a higher concentration of the second element than the first element.
  • the method includes reiterating the steps of forming the first and second sub-film portions to form a composite film comprising concentration variations of the first and second elements.
  • An embodiment of a microelectronic topography resulting from one or more of the methods includes a structure having a bulk concentration of a first element disposed throughout the structure and a film consisting essentially of one or more elements different than the first element formed in contact with the structure.
  • the film has periodic successions of regions each comprising at least one region with a concentration of a second element greater than a set amount and at least one region with a concentration of the second element less than the set amount.
  • Another embodiment of a microelectronic topography resulting from one or more of the methods includes a conductive structure having a bulk concentration of copper disposed throughout the structure and a film formed in contact with the conductive structure comprising alternating regions of comparatively greater and lesser concentrations of cobalt.
  • FIG. 1 depicts a partial cross-sectional view of a microelectronic topography having a liner layer and cap layer formed about a metallization structure;
  • FIG. 2 a depicts an exemplary view of at least one of the liner layer and cap layer illustrated in FIG. 1 , which may serve as a partial cross-sectional view or a partial plan view;
  • FIG. 2 b depicts another exemplary view of at least one of the liner layer and cap layer illustrated in FIG. 1 , which may serve as a partial cross-sectional view or a partial plan view;
  • FIG. 2 c depicts yet another exemplary view of at least one of the liner layer and cap layer illustrated in FIG. 1 , which may serve as a partial cross-sectional view or a partial plan view;
  • FIG. 3 depicts a flowchart of a method for forming a composite metallic layer having a variation of elemental concentrations
  • FIG. 4 depicts a flowchart of an alternative method for forming a composite metallic layer having a variation of elemental concentrations
  • FIG. 5 depicts a flowchart of another alternative method for forming a composite metallic layer having a variation of elemental concentrations
  • FIG. 6 depicts a flowchart of yet another alternative method for forming a composite metallic layer having a variation of elemental concentrations
  • FIG. 7 depicts a plan view of an electroless plating chamber configured for the method outlined in the flowchart of FIG. 6 ;
  • FIG. 8 depicts a schematic of a computer system which may be coupled to or incorporated within the electroless plating chamber illustrated in FIG. 8 ;
  • FIG. 9 depicts a plot of solution temperature versus process time for a plurality of different areas of a microelectronic topography
  • FIG. 10 a depicts a partial cross-sectional view of a microelectronic topography having a film first deposited by a reaction limited mechanism of film growth and further deposited by a mass diffusion limited mechanism of film growth;
  • FIG. 10 b depicts a partial cross-sectional view of a microelectronic topography having a film deposited exclusively by a reaction limited mechanism of film growth;
  • FIG. 10 c depicts a partial cross-sectional view of a microelectronic topography having a film first deposited by a reaction limited mechanism of film growth, followed by a mass diffusion limited mechanism of film growth, and finally by a second reaction limited mechanism of film growth;
  • FIG. 11 depicts a plot of solution dispensing time versus a plurality of different areas of a microelectronic topography
  • FIG. 12 depicts a flowchart of a method for depositing a film using an electroless deposition chamber
  • FIG. 13 depicts a cross-sectional view of an electroless plating chamber configured for the method outlined in the flowchart of FIG. 12 ;
  • FIG. 14 depicts a plan view of an exemplary test wafer having distinct regions each including comparatively different thicknesses and comparatively different elemental concentrations;
  • FIG. 15 a depicts a partial cross-sectional view of the test wafer illustrated in FIG. 14 ;
  • FIG. 15 b depicts an alternative partial cross-sectional view of the test wafer illustrated in FIG. 14 .
  • FIG. 1 illustrates a partial cross-sectional view of microelectronic topography 20 having liner layer 28 , cap layer 30 , as well as other metallic structures which may be formed from the methods and systems described below in reference to FIGS. 3-13 .
  • any of the metallic structures of microelectronic topography 20 may be formed by the methods and systems described below in reference to FIGS. 3-13 .
  • the elemental composition of liner layer 28 and cap layer 30 may be configured to reduce the diffusion of elements from metallization structure 22 to lower layer 26 , dielectric layer 24 and any layers formed upon cap layer 30 , reducing electromigration within an ensuing device.
  • cap layer 30 may be configured to prevent oxidation of metallization structure 22 .
  • liner layer 28 and cap layer 30 may generally be referred to as barrier layers. Such a reference, however, does not necessarily infer the exclusivity of the aforementioned functions.
  • liner layer 28 and/or cap layer may additionally or alternatively serve as adhesion layers and/or thermal expansion buffers.
  • microelectronic topography 20 is not necessarily limited to having both liner layer 28 and cap layer 30 be formed by the methods and systems described herein. In particular, the methods and systems may be applied to either or both of such layers.
  • microelectronic topography 20 is shown including both liner layer 28 and cap layer 30 , the topography is not necessarily so limited. In particular, microelectronic topography 20 may alternatively include only one of liner layer 28 and cap layer 30 .
  • microelectronic topography may refer to a substrate resulting from or used for the fabrication of a microelectronic device or circuit, such as an integrated circuit, for example.
  • metallization structure 22 may be any metal feature known for the fabrication of a microelectronic device.
  • metallization structure 22 may, in some embodiments, serve as a contact structure to portions of a semiconductor layer.
  • lower layer 26 may include a semiconductor material, such as silicon and may, in some embodiments, be doped either n-type or p-type. More specifically, lower layer 26 may be a monocrystalline silicon substrate or an epitaxial silicon layer grown on a monocrystalline silicon substrate.
  • lower layer 26 may include a silicon on insulator (SOI) layer, which may be formed upon a silicon wafer.
  • SOI silicon on insulator
  • lower layer 26 may include metallization and/or an interlevel dielectric layer.
  • metallization structure 22 may serve as a via, an interconnect or any other metallization feature to underlying portions of microelectronic topography 20 .
  • metallization structure 22 may include one or more layers of conductive materials, including but not limited to copper, aluminum, tungsten, titanium, silver, or any alloy of such metals.
  • the methods and systems described herein may be particularly applicable to microelectronic topographies including a metallization structure having a bulk concentration of copper and, in some cases, consisting essentially of copper.
  • copper has a relatively low resistivity and, therefore, is often favorable to use for metallization structures in microelectronic devices.
  • copper atoms are particularly notorious for their propensity to diffuse through materials.
  • the methods and systems described herein offer manners in which to fabricate barrier layers around copper metallization structures to substantially minimize or eliminate the diffusion of copper to other layers.
  • metallization structure 22 may, in some embodiments, be fabricated by electroless plating techniques, including those described herein as well as others known in the microelectronic fabrication industry. In other embodiments, metallization structure 22 may be formed by other deposition techniques known in the microelectronic fabrication industry, such as but not limited to sputtering or evaporation. In either case, metallization structure 22 may be formed within a trench formed within dielectric layer 24 . Such a fabrication sequence may be particularly advantageous for the incorporation of liner layer 22 within microelectronic topography 20 . In other embodiments, dielectric layer 24 may be formed subsequent to and about metallization structure 22 .
  • Dielectric layer 24 may include one or more of various dielectric materials used in microelectronic fabrication.
  • dielectric layer 24 may include silicon dioxide (SiO 2 ), silicon nitride (Si x N y ), silicon dioxide/silicon nitride/silicon dioxide (ONO), silicon carbide, carbon-doped SiO 2 , or carbonated polymers.
  • dielectric layer 24 may be undoped.
  • dielectric layer 24 may be doped to form, for example, low doped borophosphorus silicate glass (BPSG), low doped phosphorus silicate glass (PSG), or fluorinated silicate glass (FSG).
  • BPSG low doped borophosphorus silicate glass
  • PSG low doped phosphorus silicate glass
  • FSG fluorinated silicate glass
  • dielectric layer 24 may be formed from a low-permittivity (“low-k”) dielectric, generally known in the art as a dielectric having a dielectric constant of less than about 3.5.
  • low-k dielectric in current use, which is believed to make a conformal film, is fluorine-doped silicon dioxide.
  • dielectric layer 24 may have a thickness between approximately 2,000 angstroms and approximately 10,000 angstroms. Larger or smaller thicknesses of dielectric layer 24 , however, may be appropriate depending on the microelectronic device being formed.
  • the elemental composition of liner layer 28 and cap layer 30 may be configured to reduce the diffusion of elements from metallization structure 22 .
  • the selection and arrangement of the elements included within liner layer 28 and cap layer 30 may, in some embodiments, depend on the elements included in metallization structure 22 .
  • the inclusion of cobalt within liner layer 28 and cap layer 30 may be particularly beneficial since copper has relatively low solubility with cobalt.
  • Other materials which may be additionally or alternatively included within liner layer 28 and cap layer 30 may include phosphorus, boron, tungsten, chromium, molybdenum, nickel, palladium, rhodium, ruthenium, oxygen, and hydrogen.
  • Exemplary alloys which may be employed for liner layer 28 and cap layer 30 include but are not limited to cobalt-tungsten-phosphorus (CoWP), cobalt-tungsten-boron (CoWB), cobalt-tungsten-phosphorus-boron (CoWPB), cobalt-molybdenum-boron (CoMoB), cobalt-molybdenum-phosphorus (CoMoP), cobalt-molybdenum-chromium (CoMoCr), and cobalt-molybdenum-chromium-boron (CoMoCrB).
  • liner layer 29 and/or cap layer 30 may include single element layers of palladium, rhodium and ruthenium.
  • liner layer 29 and cap layer 30 may include the same collection of elements and, in some cases, a similar arrangement of elements. In other cases, however, liner layer 29 and cap layer 30 may include different arrangements of elements and, in some embodiments, a different collection of elements.
  • liner layer 28 and/or cap layer 30 may include a variation of elemental concentrations throughout the layers to reduce the diffusion of elements from metallization structure 22 therethrough.
  • liner layer 28 and/or cap layer 30 may include different concentrations of elements in different regions of the layer.
  • Exemplary elemental compositions of liner layer 28 and/or cap layer 30 are shown in FIGS. 2 a - 2 c .
  • the variation of elements within liner layer 28 and cap layer 30 may be arranged in sub-layers vertically disposed within the films.
  • FIGS. 2 a - 2 c may, in some embodiments, illustrate partial cross-sectional views of liner layer 28 and/or cap layer 30 .
  • the variation of elements may be additionally or alternatively arranged in regions extending horizontally between lateral edges of the films.
  • FIGS. 2 a - 2 c may alternatively illustrate partial plan views of the upper surface of cap layer 30 .
  • liner layer 28 may, in some cases, include a similar horizontal variation of elements and, therefore, FIGS. 2 a - 2 c may apply to liner layer 28 for horizontal variations of elements as well.
  • the variation of element concentrations may vary both horizontally and vertically within the films and, therefore, FIGS. 2 a - 2 c may be representative of either a cross-sectional view or a plan view of the layers.
  • liner layer 28 and/or cap layer 30 may, in some embodiments, include alternating regions of comparatively greater and lesser concentrations of an element. More specifically, FIG. 2 a illustrates an arrangement of atoms of an element (each atom shown as an “x” in FIG. 2 a ) which, in an effect, partitions the layer into regions 32 comprising comparatively fewer atoms of the element and regions 34 comprising comparatively greater quantities of atoms of the element. Regions 32 and 34 are disposed along opposing sides of each other and, therefore, alternative through the film. Regions 32 and regions 34 may be differentiated from each other by including concentrations of an element which respectively fit into different ranges of concentrations.
  • regions 32 may include between approximately 30% and approximately 50% of an element, while regions 34 may include between approximately 5% and approximately 20% of an element.
  • regions 32 and regions 34 are differentiated by different ranges of elemental concentrations, neither regions 32 nor regions 34 need to necessarily include the same concentrations of an element as shown in FIG. 2 a .
  • the elemental concentrations of regions 32 and 34 are not necessarily restricted to having different elemental concentrations either. Therefore, in some cases, two or more of the respective regions may include the same elemental concentration.
  • FIG. 2 a illustrates variation of only a single element within liner layer 28 and cap layer 30
  • other elements within the film may vary.
  • the other elements may vary in a similar manner as element x and, therefore, may be disposed within regions 34 and 32 having comparatively greater and lesser concentrations, respectively.
  • regions 32 and 34 may include an opposite arrangement of greater and lesser concentrations of the one or more elements.
  • regions 32 may include a low concentration of element x and a high concentration of another element and vice versa for regions 34 .
  • the concentration variation of the other element may not alternate through the film, but may follow its own succession of regions having varying concentrations of the element.
  • regions 32 and 34 are not restricted to having the same concentration levels of different elemental atoms.
  • regions 32 and 34 may include different ranges of concentrations for each element.
  • the concentration of other elements may not substantially vary through the film.
  • FIG. 2 b An alternative arrangement of elements for liner layer 28 and cap layer 30 is illustrated in FIG. 2 b .
  • FIG. 2 b illustrates liner layer 28 and cap layer 30 having concentration variations of two different elements (atoms of the elements shown as “x” and “o”).
  • the relative concentrations of the elements do not alternate through the films, but rather are disposed as periodic successions of regions 36 .
  • periodic successions of regions 36 are shown having three regions with relatively different concentrations of element atoms “x” and “o.”
  • periodic successions of regions 36 are shown to include three regions, liner layer 28 and cap layer 30 are not necessarily so restricted.
  • periodic successions of regions 36 may include any plurality of regions.
  • Each of periodic successions of regions 36 includes at least one region with a concentration of an element greater than a set amount and at least one region with a concentration of the element less than the set amount.
  • the set amounts may generally depend on the individual element and the design specifications of the film and, therefore, may vary between approximately 1% and approximately 99%. Set amounts for the multiple elements within a film are generally independent of each other.
  • periodic successions of regions 36 may include region 36 a having a greater concentration of elemental atoms “x” and “o” than region 36 b , which includes a greater concentration than region 36 c .
  • region 36 a may include a concentration of elemental atoms “x” and “o” greater than a set amount and region 36 c may include a concentration of elemental atoms “x” and “o” less than the set amount.
  • Region 36 b may fit into either of such categories, depending on the design specifications of the film.
  • periodic successions of regions 36 may include a series of regions having incrementally increasing relative concentrations.
  • regions 36 a , 36 b , and 36 may be arranged in an alternative sequence, such as having regions 36 a or 36 c interposed between the other regions such that progression of elemental concentrations through periodic successions of regions 36 is not incremental.
  • periodic successions of regions 36 may include regions which are differentiated from each other by respectively different ranges of elemental concentrations.
  • each of regions 36 a (as well as each of regions 36 b and 36 c ) do not necessarily need to include the same concentrations of elemental atoms “x” or “o.”
  • periodic successions of regions 36 are not restricted to having the same concentration levels of element atoms “x” and “o.”
  • regions 36 a , 36 b and 36 c may include different ranges of concentrations for each element.
  • region 36 a may alternatively include the relatively highest amount of elemental atoms “x” and include the relatively lowest amount of elemental atoms “o” among each succession of regions 36 .
  • region 36 b or 36 c may alternatively include the relatively highest amount of elemental atoms “x” and the relatively lowest amount of elemental atoms “o” among each succession of regions 36 .
  • FIG. 2 c illustrates liner layer 28 and/or cap layer 30 including region 38 with a relatively high concentration of element “+” interposed between regions 39 having comparatively lower concentrations of the element.
  • regions 39 do not necessarily need to include the same concentration of element “+.” Rather, regions 39 may include concentrations of an element which fits into a different range of concentrations than the concentration of region 38 .
  • region 38 is not restricted to being centered within liner layer 28 and cap layer 30 .
  • liner layer 28 and cap layer 30 are not necessarily restricted to the configurations illustrated in FIGS. 2 a - 2 c .
  • liner layer 28 and cap layer 30 may include any variation of elemental concentrations among distinct regions of the films.
  • liner layer 28 and/or cap layer 30 may include different concentrations of one or more elements at regular intervals of the layer as shown in FIGS. 2 a and 2 b , for example.
  • the variation of elemental concentration shown in FIG. 2 c may be appropriate to inhibit diffusion from metallization structure 22 .
  • the elements which are configured to vary within liner layer 28 and/or cap layer 30 may be any of the elements which may be included within the films.
  • the elements having varying concentrations in liner layer 28 and cap layer 30 may be cobalt, phosphorus, boron, tungsten, chromium, molybdenum, nickel, palladium, rhodium, ruthenium and/or hydrogen.
  • copper has relatively low solubility with cobalt and, therefore, it may be advantageous to vary the concentration of cobalt within liner layer 28 and/or cap layer 30 in some embodiments.
  • a variation of cobalt concentration throughout liner layer 28 and cap layer 30 may substantially reduce the migration of copper through the films compared to embodiments in which the concentration of cobalt is substantially even. In turn, the likelihood of copper atoms reaching surrounding layers may be reduced.
  • the level of cobalt concentration may alternate through liner layer 28 and cap layer 30 . Consequently, in some cases, liner layer 28 and cap layer 30 may include a composite film of alternating cobalt-rich and cobalt-poor regions.
  • liner layer 28 and/or cap layer 30 may include periodic regions of different concentrations of other elements as well or alternatively. It is noted that the variation of symbols denoting different elemental atoms in FIGS. 2 a - 2 c (i.e., “x,” “o,” and “+”) do not necessarily imply that the different configurations are particular to specific elements or combinations of elements. The differentiation is merely shown to emphasize that different elements may be formed in a periodic manner within barrier layers.
  • an exemplary cobalt concentration variation may be between, for example, approximately 10% and approximately 30%, or more specifically, a variation of approximately 20%.
  • an exemplary variation of phosphorus concentration may be between approximately 3% and approximately 12% and a variation of boron concentration may be between approximately 1% and approximately 2%.
  • liner layer 28 and cap layer 30 may include a concentration variation of molybdenum between approximately 1% and approximately 50%. Larger or smaller variations of concentrations may be employed for any of such elements as well as the other elements listed for liner layer 28 and cap layer 30 and, therefore, the aforementioned limitations do not necessarily limit the range of elemental concentrations within the layers.
  • one method for forming a barrier layer with a vertical variation of elemental concentrations may include depositing a plurality of sub-layers having different concentrations of elements.
  • a flowchart of a method of depositing a plurality of sub-layers having different concentrations of elements is shown in FIG. 3 .
  • the method may include positioning a microelectronic topography within an electroless plating chamber and dispensing a first deposition solution upon the microelectronic topography to form a first sub-layer upon the microelectronic topography.
  • the process may further include rotating a substrate holder upon which the microelectronic topography is positioned to facilitate the distribution of the first deposition solution across the topography.
  • the first sub-layer may include one or more elements formed within individual concentration ranges.
  • the distribution of the first deposition solution may be a single continuous flow across the surface of microelectronic topography.
  • the distribution of the first deposition solution may be a series of fragmented depositions of the solution at different locations extending different distances from a center of the microelectronic topography.
  • Such a technique may induce a horizontal variation of element concentrations within the first sub-layer and, in some cases, subsequent sub-films. Consequently, the ensuing composite layer may include both vertical and horizontal variations of elemental concentrations.
  • the method may additionally or alternatively be performed in a chamber configured to induce a variation of evaporation rates across a topography such that a horizontal variation of elemental concentrations within the first and/or subsequent sub-films may be obtained by such a manner.
  • a chamber configured to induce a variation of evaporation rates across a topography such that a horizontal variation of elemental concentrations within the first and/or subsequent sub-films may be obtained by such a manner.
  • the method may, in some embodiments, include blocks 43 a and 43 b in which dispensing the deposition solution and/or rotation of the substrate holder (when so applied) is terminated and subsequently resumed during the deposition of the first sub-film.
  • the processes associated with blocks 43 a and 43 b may be conducted as a single sequence of steps as indicated by the single direction arrow between the blocks.
  • the processes associated with blocks 43 a and 43 b may be reiterated multiple times during the deposition process as indicted by the bi-directional arrow between the blocks. In such embodiments, the sequence of steps may end with either of the processes when the method continues onto block 44 even though FIG. 1 illustrates the method continuing on to block 44 from block 43 b .
  • the sequence of steps may advantageously facilitate a substantial uniform deposition of elemental components across the topography within the first sub-film while still preventing the accumulation of bubbles upon the topography during deposition, as described in more detail below.
  • the sequence of steps may additionally or alternatively be used during the deposition of subsequent sub-films as well.
  • the overall method described in reference to FIG. 3 is used to fabricate a composite barrier layer with a variation of elemental concentrations (i.e., among the different sub-films)
  • the sub-film layers themselves may be formed to have a substantially uniform distribution and concentration of elements.
  • the adsorption potential of charged molecules within a deposition solution is influenced by the ratio of different surface materials (e.g., amount of conductive surfaces versus dielectric surfaces) within a given area of a topography.
  • an area with a greater density of conductive structures i.e., an area with relatively less dielectric surface material
  • the area with the greater density of conductive structures may have a different concentration and distribution of elements than the area with the lesser density of conductive structures.
  • the termination of dispensing the deposition solution and/or the termination of rotating the substrate holder during the deposition of a film may reduce or negate variations of charged molecule adsorption potentials relative to areas of a topography having different densities of surface materials.
  • the termination of one or more of the processes associated with block 43 a allows films having substantially similar distribution and concentration of elements to be deposited across a topography.
  • the termination processes of block 43 a may cause the formation of bubbles upon the microelectronic topography.
  • the formation of bubbles during electroless deposition processes often cause undesirable random non-uniformity in deposition thickness and, in some cases, cause defects to be formed within the film.
  • the recommencement of dispensing the deposition solution and/or rotating the substrate holder as noted in block 43 b may advantageously remove bubbles formed from the termination processes.
  • a film having a substantially uniform elemental composition, uniform thickness, a minimal number or no defects may be deposited with the technique described herein.
  • the duration of termination and resumption of the processes described in reference to FIG. 43 a and 43 b may be between approximately 0.5 seconds and approximately 1 minute. Shorter or longer durations, however, may be employed for each of such processes. In some embodiments, it may be advantageous for the termination of the processes to be short, such as between approximately 0.5 seconds and approximately 5 seconds, or more specifically about 2 seconds, to reduce the formation of bubbles during the deposition process. In some cases, it may be beneficial for the termination of the processes to be shorter than the duration for which the processes are resumed. For example, in some embodiments, it may be advantageous to resume the processes for a duration between approximately 15 seconds and approximately 45 seconds, or more specifically about 30 seconds.
  • the duration of the processes may be the same or the termination of the processes may be longer than the duration for resuming the processes.
  • blocks 43 a and 43 b and the associated termination and resuming processes may be omitted from the method described in reference to FIG. 3 . Blocks 43 a and 43 b and the arrows extending to and from it are outlined with dotted lines indicating the steps are optional.
  • the method may continue by removing the first deposition solution from the electroless plating chamber and subsequently dispensing a second deposition solution upon the microelectronic topography to form second sub-layer upon and in contact with the first sub-layer as respectively noted by blocks 44 and 48 in FIG. 3 .
  • the disbursement of the second deposition solution may be a single continuous flow or may be a series of fragmented depositions.
  • the method may, in some embodiments, continue to blocks 43 a and 43 b such that the deposition of the second sub-film includes the termination of dispensing the deposition solution and/or the termination of rotating the substrate holder as similarly described above for the formation of the first sub-film.
  • the second sub-layer may include multiple elements which are also included within the first sub-layer.
  • the second sub-layer may consist essentially of the same elements as included in the first sub-layer. In other embodiments, however, the first and second sub-layer may include some different elements.
  • the second sub-layer may include one or more elements having concentrations within different ranges than employed within the first sub-layer. In other words, a concentration of at least one of the elements within the second sub-layer may differ from a concentration of the same element within the first sub-layer. In this manner, the method induces a vertical variation of elemental concentrations.
  • the method may, in some embodiments, include block 46 in which chamber process parameters different than those used for the formation of the previous sub-film are established.
  • the incorporation of block 46 prior to the formation of the second sub-layer, as shown in FIG. 3 may in turn include establishing chamber process parameters different than those used during the formation of the first sub-layer.
  • Such different process parameters may be wholly or partially responsible for the variations of elemental concentrations between the first and second sub-layers.
  • the change in parameters by which the electroless deposition process is conducted may be sufficient to affect the concentration of elements within the second sub-layer as compared to the first sub-layer.
  • Such influential process parameters may include but are not limited to temperature, pressure, and the type of ambient gas included within the electroless plating chamber.
  • the first and second depositions solutions may include the same compositions and, therefore, the changes of chamber process parameters may be wholly responsible for the variations of elemental concentrations between the first and second sub-layers.
  • the first and second depositions solutions may include different compositions and, therefore, the changes of chamber process parameters may be partially responsible for the variations of elemental concentrations between the first and second sub-layers.
  • block 46 may not be employed prior to the formation of the second sub-layer. In such cases, the variation of compositions among the first and second deposition solutions may be wholly responsible for the variation of elemental concentrations between the first and second sub-layers.
  • Block 46 and the arrows extending to and from it are outlined with dotted lines indicating the step is optional and, therefore, block 46 and the associated establishment of different chamber process parameters may be omitted in some cases.
  • the second deposition solution may be removed from the electroless plating chamber subsequent to the formation of the second sub-layer as shown by block 50 in FIG. 3 . Thereafter, the method may follow several different routes. In particular, the method may, in some embodiments, end at block 58 after the removal of the second deposition solution from the electroless plating chamber. Alternatively, the method may include repeating the steps of dispensing and removing the first deposition solution (described in reference to block 42 and 44 ) to form a third sub-layer upon and in contact with the second sub-layer as shown by block 52 in FIG. 3 .
  • the third sub-layer may include a multiple of the same elements included within the first sub-layer.
  • the method may, in some embodiments, continue to blocks 43 a and 43 b such that the deposition of the third sub-film includes the termination of dispensing the deposition solution and/or the termination of rotating the substrate holder as similarly described above for the formation of the first sub-film.
  • the third sub-layer may consist essentially of the same elements as included in the first sub-layer. In other embodiments, however, the first and third sub-layers may include some different elements. In either case, the third sub-layer may, in some embodiments, include a concentration of at least one element which is closer to a concentration of the same element with the first sub-layer than a concentration of the same element within the second sub-layer. In particular, the third sub-layer may include one or more elements having concentrations within the same ranges as employed within the first sub-layer. In this manner, the method may induce a periodic variation of an element concentration similar to but not limited to the configurations described in reference to FIGS. 2 a and 2 c . In other embodiments, the third sub-layer may include a substantially different concentration of an element included within the first and second sub-layers and, therefore, may be similar to the configuration described in reference to FIG. 2 b.
  • the method may include reiterating the steps of dispensing and removing the first deposition solution (described in reference to block 42 and 44 ) and the steps of dispensing and removing the second deposition solution (described in reference to block 48 and 50 ) to form additional sub-layers above the second sub-layer as shown in block 54 of FIG. 3 .
  • the method may include consecutively dispensing and removing one or more additional deposition solutions different than the first and second deposition solutions to form one or more additional sub-layers above the second sub-layer as noted in block 56 .
  • the additional films may be configured to induce a periodic variation of an elemental concentration with the first and second sub-films similar to but not limited to the configurations described in reference to FIGS. 2 a - 2 c.
  • each sub-film formed by the method described in FIG. 3 may be between approximately 0.5 nm and approximately 100 nm, or more specifically between approximately 0.5 nm and approximately 50 nm. Sub-films with larger or smaller thicknesses, however, may be used to form the composite barrier layer described herein.
  • the method may, in some embodiments, continue to blocks 43 a and 43 b for any number of the sub-films formed by blocks 54 and 56 and, therefore, the deposition of such sub-films may, in some embodiments, include the termination of dispensing the deposition solution and/or the termination of rotating the substrate holder as similarly described above for the formation of the first sub-film.
  • the method may sometimes include establishing chamber process parameters different than those used for the formation of the previous sub-layer after the removal of the second deposition solution.
  • FIG. 3 shows that the method may, in some embodiments, include block 46 subsequent to block 50 and prior to any of blocks 52 , 54 , 56 or 58 .
  • the incorporation of block 46 subsequent to the formation of the second sub-layer thus may include establishing chamber process parameters different than those used during the formation of the second sub-layer.
  • the chamber process parameters may further be different from the chamber process parameters used during the formation of the first sub-layer.
  • the sub-layer formed upon the second sub-layer may include different elemental concentrations than the first and second sub-layers.
  • the chamber process parameters may be substantially similar to the parameters used during the formation of the first sub-layer such that a composite barrier layer having alternating regions of comparatively greater and lesser concentrations of one or more elements may be formed.
  • the change of process parameters prior to the formation of additional sub-layers above the second sub-layer may be wholly or partially responsible for the variations of elemental concentrations between the additional sub-layers and the second sub-layer.
  • deposition solutions dispensed upon the microelectronic topography subsequent to the removal of the second deposition solution may include the same or different elemental compositions as the first and second deposition solutions.
  • block 46 may be incorporated into the method directly prior to one or more of the individual additional sub-films referenced with respect to blocks 54 and 56 . Reference arrows indicating such possibilities have been omitted from FIG. 3 to simplify the drawing.
  • the process parameters for the deposition of the sub-films with respect to the method depicted in FIG. 3 may depend on the design specifications of the sub-films, such as but not limited to their elemental compositions and thicknesses, for example.
  • Some exemplary process parameters may include deposition solution flows between approximately 0.5 L/min and approximately 10 L/min and, in some embodiments, approximately 2 L/min.
  • wafer rotating speeds during deposition may be between approximately 1 rpm and approximately 100 rpm and, in some embodiments, approximately 30 rpm.
  • wafer rotation speeds during the removal of the deposition solutions may be faster, such as between approximately 150 rpm and approximately 2000 rpm and, in some cases, approximately 300 rpm. In this manner, the processing time between deposition cycles may be minimized.
  • the processing time between deposition cycles may be approximately 5 seconds.
  • the process time to deposit the sub-films may be between approximately 10 seconds and a few minutes, and more specifically, between approximately 10 seconds and approximately 30 seconds.
  • the temperature at which the electroless deposition process occurs may be between approximately 20° C. and approximately 120° C., or more specifically, between approximately 55° C. and approximately 90° C. In general, larger or smaller temperatures and slower and/or faster deposition flows, wafer rotation speeds, and process cycles times may be used to form the composite barrier layer and, therefore, the methods described herein are not necessarily limited to the aforementioned values.
  • Tables 1 and 2 below outline exemplary compositions of deposition solutions and chamber process parameters associated with the methods described herein, particularly in reference to FIG. 3 but not necessarily so limited.
  • Tables 1 and 2 outline exemplary compositions of deposition solutions and chamber process parameters for depositing sub-films of a composite barrier layer with a vertical variation, and in some embodiments a horizontal variation, of elemental concentrations.
  • Table 1 displays exemplary compositions of deposition solutions and chamber process parameters used to form sub-films of cobalt-tungsten-phosphorus (CoWP), cobalt-tungsten-phosphorus-boron (CoWPB), cobalt-molybdenum-phosphorus (CoMoP), cobalt-molybdenum-phosphorus (CoMoP), and cobalt-molybdenum-chromium-boron (CoMoCrB).
  • Table 2 displays exemplary compositions of deposition solutions and chamber process parameters used to form sub-films of some of such cobalt alloys with relatively high concentrations of W and Mo, such as greater than approximately 25%, for example.
  • Table 2 also displays exemplary compositions of deposition solutions and process parameters used to form ruthenium (Ru) sub-films.
  • TABLE 1 Exemplary Compositions of Deposition Solutions and Chamber Process Parameters used to form Films of CoWP, CoWPB, CoWB, CoMoB and CoMoCrB Compound CoWP CoWPB CoWB CoMoB CoMoCrB Cobalt sulfate heptahydrate 18 g/L 18 g/L 9-28 g/L 3-26 g/L 3-26 g/L Dimethylamine borane 0.6 g/L 0.8-6.0 g/L 0.6-6.0 g/L 0.6-6.0 g/L Hypophosphorous acid 8 g/L 14 g/L Citric acid monohydrate 57 g/L 57 g/L 42-84 g/L 28-84 g/L 28-84 g/L Pyrophosphoric acid 0-35.6 g/L 0-35.6 g/L Tung
  • noble catalytic metals such as palladium (Pd) and rhodium (Rh) as well as different combinations of the elements stated above for liner layer 28 and cap layer 30 may additionally or alternatively be formed as sub-film layers for a composite barrier layer formed from the method described in reference to FIG. 3 .
  • cobalt-molybdenum-chromium (CoMoCr) may be formed as a sub-film layer of a composite barrier layer.
  • the solution composition for the formation of a CoMoCr layer may include similar concentrations of components as described for CoMoCrB without the inclusion of dimethlylamine borane. As such, the formation of a composite barrier layer described in reference to FIG.
  • any of the compounds listed in Tables 1 and/or 2 may be formed upon one another to form a composite barrier layer having a variation of elemental concentration.
  • HEDTA hydroxyethyl ethylenediamine triacetic acid
  • pyrophosphoric acid has been found to be advantageous for forming films including cobalt and molybdenum.
  • EDTA ethylenediamine triacetic acid
  • the combination of ammonium hydroxide (NH 4 OH), hydroxlamine sulfate, and hydrazine sulfate has shown to be effective for depositing films including ruthenium. It is noted that the values for such components as well as all other component values listed in Tables 1 and 2 may be altered and still be used to produce sub-films for a composite barrier layer having variations of elemental concentrations. The values listed are merely exemplary.
  • An alternative or additional method used to form a barrier layer having a concentration variation of one or more elements involves an anneal process which diffuses one or more elements to a particular region of the film to create additional interfaces with which to block a diffusion channel.
  • the anneal process may be conducted after the deposition of any layer deposited by electroless plating techniques.
  • the anneal process may be performed subsequent to the method described above in reference to FIG. 3 to provide additional variation of elemental compositions within a barrier layer.
  • the anneal process may be performed subsequent to the methods described below in reference to FIGS. 5, 6 and 12 .
  • the anneal process may be performed subsequent to a conventional electroless deposition process.
  • the anneal method may be particularly advantageous for forming a barrier layer having phosphorus diffused near the middle of the film such that two additional interfaces are formed with which to block a diffusion channel such as shown in FIGS. 2 c , for example.
  • the anneal process may be configured to diffuse other elements in addition or alternative to phosphorus.
  • the anneal process may be configured to diffuse elements in regions of the substrate other than the middle.
  • FIG. 4 illustrates a flowchart including block 60 in which a bulk metallic film is formed upon a microelectronic topography using an electroless plating process.
  • the term “bulk metallic film” may generally refer to a film having a majority concentration of metallic elements and, therefore, may refer to a barrier layer formed with a combination of any of the elements mentioned above in reference to liner layer 28 and cap layer 30 of FIG. 1 .
  • the bulk metallic film may be formed having a bottom portion, a top portion, and an intermediate portion interposed between the bottom and top portions.
  • one of the top and bottom portions may include a higher concentration of at least one element than the intermediate portion and the other of the top and bottom portions.
  • Other variations of element concentrations may be formed for the bulk metallic layer and, therefore, the method is not necessarily restricted to the arrangement of elements among the particular regions of the film recited in block 60 of FIG. 4 .
  • the bulk metallic film may be formed upon and in contact with a metallic structure having a bulk elemental concentration different than the film, such as described for cap layer 30 in FIG. 1 being arranged upon and in contact with metallization structure 22 .
  • the bottom portion of the bulk metallic film may include a higher concentration of at least one element than the intermediate portion and the top portion.
  • the bulk metallic film may be formed upon and in contact with a dielectric structure, such as described for liner layer 28 in FIG. 1 being arranged in contact with dielectric layer 24 .
  • the top portion of the bulk metallic film may include a higher concentration of at least one element than the intermediate portion and the bottom portion.
  • Block 62 includes annealing the microelectronic topography to induce diffusion of at least one element within the bulk metallic film such that the intermediate portion comprises a higher concentration of the at least one element than the bottom and top portions.
  • the anneal process may include exposing a bulk metallic film to a temperature between approximately 400° C. and approximately 1000° C. for any predetermined length of time. A duration of at least approximately 10 minutes may be advantageous for ensuring diffusion of a large percentage of the element to the intermediate portion of the bulk metallic film and, in some embodiments, the anneal process may be conducted for a time period up to approximately 2 hours.
  • the heated environment to which the bulk metallic film is exposed may include one or more elements having a propensity for diffusion into exposed portions of the bulk metallic film, such as phosphorus or boron, for example.
  • the element included in the heated environment may be the same as one of the elements diffused into the intermediate portion of the bulk metallic film by the anneal process. In other embodiments, the element included in the heated environment may not be one of the elements diffused into the intermediate portion of the bulk metallic film by the anneal process.
  • An alternative method for forming a barrier layer with a concentration variation of one or more elements is outlined in the flowchart shown in FIG. 5 and involves a balance of different deposition mechanisms activated during a single deposition process.
  • the different deposition mechanisms may be induced by an additive to the deposition solution which slows the adsorption of one or more elements versus other elements in the solution.
  • the slower adsorption rate invokes a deposition process having different mechanisms of film growth which are dependent upon the concentrations of different elements within the deposition solution.
  • two elements may be deposited as a mixture within a layer, the concentration of the elements throughout the layer will differ.
  • An exemplary agent which may be used to slow the adsorption of one or more elements within a electroless plating solution may be but it not necessarily limited to pyrophosphoric acid as shown above in Table 1 for the formation of CoMoB and CoMoCrB.
  • the flowchart depicted in FIG. 5 includes block 66 noting the method includes exposing a microelectronic topography to a deposition solution. Such an exposure may include immersing the microelectronic topography within a bath of the deposition solution, dispensing the deposition solution upon the microelectronic topography, or a combination thereof.
  • the method includes block 68 in which a first sub-film portion having a higher concentration of a first element than a second different element is formed by interfacial electroless reduction of the first element within the deposition solution until the second element reaches a certain concentration within the deposition solution.
  • FIG. 5 includes block 70 in which a second sub-film portion having a higher concentration of the second element than the first element is formed upon and in contact within the first sub-film portion by chemical adsorption.
  • a deposition mechanism continues until the first element increases to a particular concentration within the deposition solution.
  • the deposition process reverts back to the mass-diffusion control mechanism to deposit the first element as a majority within a third sub-film portion.
  • the deposition mechanisms may be reiterated to form a composite barrier layer having alternating regions of relatively higher concentrations of the first and second elements, respectively.
  • the reiteration of the deposition mechanisms may be automatic by the inclusion of the aforementioned additive agent within the deposition solution and the fluctuation of elemental concentrations within the deposition solution. In this manner, the process is cyclic and is self-monitoring. It is noted that subsequent sub-film portions may have slightly different concentrations of the elements as compared to the first and second sub-film portions, but may generally follow an alternating sequence of having relatively greater concentrations of the different elements.
  • the deposition mechanisms may be reiterated any number of times and, therefore, any number of sub-films may be formed by the technique outlined in FIG. 5 .
  • process may be terminated upon the formation of the first and second sub-film portions and, therefore, block 72 may, in some embodiments, be omitted from the method.
  • the formation of the first and second sub-films as described in blocks 68 and 70 , and any subsequent sub-films may, in some embodiments, include the termination of dispensing the deposition solution upon the microelectronic topography (if applicable) and/or the termination of rotating the substrate holder as similarly described above in regard to blocks 43 a and 43 b of FIG. 3 .
  • Such a sequence of steps may advantageously allow sub-films to be formed having substantially uniform elemental composition, uniform thickness, and substantially free of defects.
  • Barrier layer formation involving a balance of deposition mechanisms may be particularly applicable for forming barrier layers with a variation of molybdenum.
  • molybdenum may be particularly amenable to slow adsorption rates relative to other elements in the presence of an additive agent, such as pyrophosphoric acid, for example.
  • a barrier film including alternating regions of relatively higher concentrations of cobalt and molybdenum, respectively may be deposited using the balanced deposition mechanism technique by having majority cobalt portions formed by interfacial electroless reduction and majority molybdenum portions formed by a chemical adsorption.
  • molybdenum oxide may be particularly suitable for formation from a process of balanced deposition mechanisms.
  • other methods for forming barrier layers having a variation of elemental concentrations may include controlling the process solution temperature on the substrate surface. More specifically, other methods may introduce a variation of solution temperature across a substrate to form a barrier film with a variation of elemental concentrations. Typically, the concentration of elements within an electrolessly deposited film is dependent on the temperature at which the deposition takes place. As such, introducing a variation of solution temperature across a substrate may induce a variation of elemental concentrations.
  • FIGS. 6-10 One manner in which to control process solution temperature across a substrate is shown and described in reference to FIGS. 6-10 . In particular, FIGS.
  • FIGS. 6-10 illustrate a flowchart outlining a method to control the flow pattern and, thus, the temperature variation of the solution across the substrate surface, systems configured to implement the method, and graphs outlining exemplary process parameters used administer the method. It is noted that the use of the methods and systems described in reference to FIGS. 6-10 are not necessarily mutually exclusive to other methods for forming barrier layers with a variation of elemental concentrations. Rather, the methods and systems may, in some embodiments, be used in combination with any of the methods described in reference to FIGS. 3-5 to form a barrier layer.
  • the method may include block 76 in which a microelectronic topography is positioned within an electroless plating chamber.
  • the method further includes block 78 in which a deposition solution is dispensed at a plurality of locations extending different distances from a center of the microelectronic topography each at a different moment in time during an electroless plating process.
  • the dispensing arm of the electroless deposition chamber moves to another position (not necessarily adjacent to the first zone) and the solution is dispensed thereon.
  • the amount, rate and duration the solution is dispensed on the microelectronic topography may be controlled.
  • Such a plurality of parameters may generally relate to the flow pattern of the solution across the wafer. Consequently, the method may include regulating a flow pattern of a solution to vary the temperature of the solution across the microelectronic topography and induce a variation of elemental concentrations within a deposited film.
  • An exemplary system for controlling flow patterns of solutions across a substrate is described in more detail below in reference to FIGS. 7 and 8 .
  • the method may include altering the temperature of the dispensed solution such that different regions of the substrate are exposed to different solution temperatures.
  • the exemplary system described in reference to FIGS. 7 and 8 may be configured to dispense the solution at different temperatures across a substrate.
  • heating and/or cooling mechanisms within a substrate holder of the electroless plating chamber may be used to change the temperature of the deposition solution during plating.
  • solution temperatures for electroless plating operations may generally be regulated between approximately 20° C. and approximately 120° C., or more specifically, between approximately 55° C. and approximately 90° C. Warmer or cooler solution temperatures may be used, however, depending of the fabrication specifications of the process.
  • the methods of controlling the process solution temperature and/or flow pattern across a substrate may induce a horizontal variation of elemental concentrations.
  • the methods may be used to induce a vertical variation of elemental concentrations.
  • the method may include altering the flow pattern and/or temperature of the solution as the film is deposited, such that elemental concentrations within the film vary across regions of the microelectronic topography and/or vary with the thickness of the film.
  • electroless plating chamber 80 includes substrate holder 84 supported by platen 86 and surrounded by chamber walls 88 .
  • the electroless plating chamber further includes dispensing arm 90 for supplying a deposition solution onto microelectronic topography 82 , which resides upon substrate holder 84 .
  • the cover of electroless plating chamber 80 is not shown in order to illustrate the alternate positions of dispensing arm 90 relative to microelectronic topography 82 . As shown by the dotted line outlines of dispensing arm 90 in FIG.
  • electroless plating chamber 80 may be configured to position dispensing arm 90 above a plurality of locations of microelectronic topography 82 . More specifically, dispensing arm 90 may be connected to rotary drive mechanism 94 for positioning the suspended end of dispensing arm 90 among positions 92 a - 92 d with respect to fixed axis 96 .
  • electroless plating chamber 80 may be configured to position dispensing arm 90 over a plurality of locations extending different distances from a center of microelectronic topography 82 each at a different moment in time during an electroless plating process. More specifically, positions of dispensing arm 90 may be controlled for delivering a deposition solution to a specific area of microelectronic topography 82 . In embodiments in which substrate holder 84 is configured to rotate microelectronic topography 82 during processing, such an array of different radial positions may advantageously offer full coverage of the microelectronic topography.
  • solution dispensed from dispense arm 90 may be distributed to cover different radial rings of microelectronic topography 82 , which collectively cover the entirety of the topography.
  • Exemplary wafer rotation speed may be between approximately 1 rpm and approximately 100 rpm and, in some embodiments, approximately 30 rpm, but faster or slower rotations speeds may be used. It is noted that the different areas of the microelectronic topography upon which the solution is dispensed by dispense arm 90 may overlap to ensure coverage of the entirety of the topography during processing, but generally the areas cover different regions of the topography and, therefore, are distinct.
  • FIG. 7 illustrates dispensing arm 90 positioned in four different locations
  • electroless plating chamber 80 may be configured to position dispensing arm 90 at any number of different locations greater or less than four. In some cases, positioning dispensing arm 90 in nine different positions has shown to provide sufficient coverage of a deposition solution over an entirety of a microelectronic topography, but the methods and systems described herein are not necessarily so limited.
  • positions 92 a - 92 d are illustrated with respect the same radial line of microelectronic topography 82
  • dispense arm 90 may be positioned along different radial lines of microelectronic topography 82 .
  • positions 92 a - 92 d are not restricted to being evenly spaced with respect to each other.
  • positions 92 a - 92 d may be spaced apart by different distances.
  • dispensing arm 90 may be located at a position not overlying microelectronic topography 82 in some embodiments, as shown by position 92 d in FIG. 7 . Although not necessary, such a position of dispense arm 90 may be advantageous for loading microelectronic topography 82 in and out of electroless plating chamber 80 .
  • the program instructions used to regulate the distribution of solution from dispense arm 90 described in more detail below may be configured to inhibit solution flow from the dispense arm in such a position.
  • the positioning of dispense arm 90 may be programmed through a computer system coupled to or incorporated within electroless plating chamber 80 .
  • a schematic diagram of an exemplary computer system is illustrated in FIG. 8 .
  • computer system 100 includes processor 106 and storage medium 102 , which in turn includes program instructions 104 .
  • the storage medium may include any device for storing program instructions, such as a read-only memory, a random access memory, a magnetic or optical disk, or a magnetic tape.
  • input 28 may be transmitted to processor 106 , which may be configured to execute program instructions 104 within storage medium 102 to provide output 109 to electroless plating chamber 80 .
  • program instructions 104 may be configured to exclusively regulate the position of dispense arm 90 .
  • program instructions 104 may also include program instructions for regulating other facets of electroless plating chamber 80 , such as but not limited to loading operations, drying operations, and pre-deposition or post-deposition cleaning operations.
  • dispense arm 90 may, in some embodiments, include a plurality of different sized nozzles 99 .
  • program instructions 104 may be configured to selectively dispense a deposition solution through distinct sets of the plurality of different sized nozzles with respect to plurality of positions 92 a - 92 c . More specifically, program instructions 104 may be configured to selectively dispense a deposition solution through one or more of nozzles 99 at each of positions 92 a - 92 c .
  • the selected nozzles may differ among all of the positions. In other embodiments, the selection of nozzles may differ for less than all of the positions.
  • block 78 of the method described in reference to FIG. 6 may, in some embodiments, include dispensing the deposition solution through a first nozzle above one of the plurality of locations of the microelectronic topography and may further include dispensing the deposition solution through a second different sized nozzle above another of the plurality of locations.
  • nozzles 100 are different sizes, different amounts of solution may be deposited at different locations upon microelectronic topography 82 .
  • different size areas of microelectronic topography 82 may be exposed to the deposition solution at a given time.
  • the diameters of nozzles 100 may be significantly smaller than a wafer diameter (e.g., between approximately 1 ⁇ 8 inch and approximately 1 inch, although other sizes may be used) such that only a portion of wafer is exposed to deposition solution thus creating an area with high density of nucleation sites.
  • dispense arm 90 may not include a plurality of different sized nozzles and, therefore, such an adaptation may be omitted from the methods and systems described in reference to FIGS. 6-8 .
  • program instructions 104 may be configured to vary the rate and/or duration at which a deposition solution is dispensed.
  • the method, system and program instructions described herein may be configured to vary the amount of solution dispensed upon microelectronic topography 82 in alternative manners than described for varying the distribution of a solution through different sized nozzles. For example, the method described above in reference to FIG.
  • deposition solution flow rate may vary between approximately 0.5 L/min and approximately 10.0 L/min and, more specifically between approximately 2.0 L/min and approximately 3.0 L/min.
  • Exemplary durations of flow may generally be between 10 seconds and a few minutes and more specifically between, approximately 30 seconds and approximately 60 seconds, but longer or short durations may be employed. In addition, larger or smaller flow rates may be used.
  • the selected rates of flow may induce laminar flow of the deposition solution in some embodiments.
  • Laminar flow may be advantageous in some cases, since it is less likely to cause bubbles on the surface of microelectronic topography 82 .
  • the occurrence of bubbles upon a microelectronic topography during an electroless deposition process often causes undesirable random non-uniformity in deposition thickness.
  • the selected rates of flow may induce turbulent flow of the deposition solution.
  • program instructions 104 may be configured to pulse a deposition solution through dispense arm 90 and, in some cases, pulse a deposition solution at different frequencies with respect to different regions of microelectronic topography 82 .
  • program instructions 104 may, in some embodiments, be configured to vary the angle of the line of trajectory from dispense arm 90 such that the solution is not limited to being dispensed perpendicular to the surface of microelectronic topography 82 . Varying the angle of the solution trajectory may, in some cases, be particularly advantageous for filling narrow holes within a topography.
  • dispense arm 90 may, in some embodiments, include thermocouple 98 .
  • the method, system and program instructions described in reference to FIGS. 6-8 may be configured to dispense deposition solutions at different temperatures with respect to the plurality of locations of dispense arm 90 during processing.
  • the method described in reference to FIG. 6 may, in some embodiments, include dispensing the deposition solution upon one of the plurality of locations of the microelectronic topography at a first temperature and may further include dispensing the deposition solution upon another of the plurality of locations of the microelectronic topography at a second distinct temperature. In this manner, the method, system and program instructions described in reference to FIGS.
  • a thin layer of the process liquid on a substrate surface generally has low thermal capacity, which allows the temperature of a solution to reduce quickly. Varying the timing at which the solution is distributed as well as varying the temperature at which the solution is dispensed relative to such time-varying distribution may allow the solution temperature across the microelectronic topography to be controlled either for a variation of temperature or temperature uniformity.
  • the configuration of the method, system and program instructions to dispense a solution at varying temperatures with respect to different regions of a microelectronic topography may aid in introducing solution temperature uniformity across the microelectronic topography.
  • regions of the solution may evaporate at different times affecting the temperature of the solution at such regions.
  • the use of dispense arm 90 and program instructions 104 may be optimized to account for such fluctuations among regions of the solution to produce solution temperature uniformity across a microelectronic topography in some embodiments. For example, FIG.
  • FIG. 9 illustrates the temperature of a deposition solution with respect to three zones of a microelectronic topography, each respectively corresponding to positions 92 a - 92 c of dispense arm 90 .
  • the temperature of the solution varies at each of the zones due to dispensing the solution at different times with respect to the zones.
  • solution temperature uniformity may be contrary to the aforementioned objective of forming a film with a variation of elemental concentration
  • the method, system and program instructions described in reference to FIGS. 6-8 are not necessarily limited to forming a film with a variation of elemental concentration.
  • the method, system and program instructions may be used to form portions or an entirety of a barrier layer without variations of elemental concentration.
  • one of the methods described in reference to FIGS. 3-5 may be used in combination with the method, system and program instructions described in reference to FIGS. 6-8 to induce a variation of elemental concentration with a barrier layer while incurring solution temperature uniformity across a microelectronic topography.
  • program instructions 104 for positioning dispense arm 90 may be configured to provide uniform or non-uniform heat density of the deposition solution across microelectronic topography 82 by regulating dispensing times across different positions.
  • films deposited using the method, system and program instructions described in reference to FIGS. 6-8 may formed with a uniform thickness profile or with a varying thickness profile.
  • solution temperature during an electroless deposition process has a direct effect on the thickness uniformity of the resulting film. Since the method, system and program instructions discussed in reference to FIGS. 6-8 may be configured to induce variation or uniformity of solution temperature across a microelectronic topography, the method, system and program instructions may be configured to induce variation or uniformity with regard to a thickness of a film deposited by electroless deposition techniques.
  • the temperature fluctuations among the zones may change mechanism of film growth from mass diffusion limited to reduction reaction rate limited, advantageously producing an amorphous (nanocrystalline) layer with low density of pinholes or growth defects as well as lower minimum film thickness and better surface roughness.
  • Exemplary amorphous layers resulting from changes of film growth mechanisms during an electroless plating process are shown in FIGS. 10 b and 10 c and are compared to a layer shown in FIG. 10 a formed from a conventional electroless plating process.
  • FIG. 10 b and 10 c Exemplary amorphous layers resulting from changes of film growth mechanisms during an electroless plating process are shown in FIGS. 10 b and 10 c and are compared to a layer shown in FIG. 10 a formed from a conventional electroless plating process.
  • FIG. 10 b and 10 c Exemplary amorphous layers resulting from changes of film growth mechanisms during an electroless plating process are shown in FIGS. 10 b and 10 c and are compared to a layer shown in FIG. 10
  • FIG. 10 a illustrates a partial cross-sectional view of an exemplary film deposited first by a reduction reaction rate limited mechanism of film growth (denoted by relatively small granules 110 ) and afterward by mass diffusion limited mechanism of film growth (denoted by relatively long and narrow upright granules 112 ).
  • a film structure is typical of conventional electroless plating techniques in which a deposition solution is deposited continuously at one location and at a single temperature throughout the deposition process.
  • FIG. 10 b illustrates an exemplary cross-section of a film deposited exclusively by a reduction reaction rate limited mechanism of film growth (denoted by relatively small granules 114 ).
  • Such film structure may be formed in embodiments in which the temperature of the solution continuously varies during the deposition of the film.
  • FIG. 10 c illustrates an exemplary cross-section of a film deposited by mechanisms of film growth which switch between reduction reaction rate limited and mass diffusion limited (denoted by the mixture of relatively small granules 116 and relatively long and narrow upright granules 118 ).
  • Such a film structure may be formed in embodiments in which the temperature of the solution varies at some periods and at other times is substantially constant.
  • films formed partially or wholly by a reduction reaction rate limited mechanism of film growth include comparatively less gaps than the film formed exclusively by a mass diffusion limited mechanism of film growth depicted in FIG. 10 a .
  • a film deposited by varying the solution temperature profile and/or solution flow rate may advantageously have less pin-holes and in-film growth defects.
  • such films may be smoother.
  • films formed partially or wholly by a reduction reaction rate limited mechanism of film growth may have a surface roughness of approximately 0.5 nm RMS, which is significantly smoother than films having a surface roughness of approximately 2.0 RMS formed exclusively by a mass diffusion limited mechanism of film growth.
  • smaller and fewer gaps within a deposited barrier layer may further aid in inhibiting diffusion of elements therethrough. More specifically, a barrier layer having smaller and few gaps may hinder diffusion of elements from adjacent structures, such as described in reference to FIG. 1 for the configurations of liner layer 28 and cap layer 30 adjacent to metallization structure 22 . Moreover, smaller and fewer gaps may inhibit hydrogen atoms from lodging with the deposited film, reducing occurrences of hydrogen outgassing during subsequent processing which may in turn affect the formation of features overlying the film. In addition, smaller and few gaps allow a denser film to be formed and, as a result, a thinner film may be deposited during a given processing time as compared to films formed by conventional electroless deposition processes.
  • FIG. 11 illustrates a graph of the total processing time versus zone location data taken from Table 3.
  • an exemplary sequence of steps may extend across 9 zones of a microelectronic topography with increasingly longer dispense times programmed for Zone 1 thru Zone 9.
  • Such a sequence and duration of dispenses may be advantageous for negating the edge effect in some embodiments, such as in cases in which Zone 1 refers to the most central zone on the microelectronic topography, Zone 9 refers to the edge most zone on the microelectronic topography, and the other zones are interposed therebetween.
  • Films resulting from such a configuration may have substantially uniform thickness across the microelectronic topography or may have greater thicknesses near the edge of the wafer as compared to near the center of the wafer.
  • the steps may, in some embodiments, be segregated into distinct sets of steps.
  • steps 1-11 may cycle through each of the zones with a different sequence and dispensing times than steps 12-20.
  • a method for depositing the film may include dispensing the deposition solution in a first sequence of steps among the plurality of locations to form a first sub-film across a surface of the microelectronic topography.
  • the method may include dispensing the deposition solution in a second different sequence of steps among the plurality of locations to form a second sub-film across the microelectronic topography and upon the first sub-film.
  • FIG. 12 depicts a flowchart of an exemplary method
  • FIG. 13 illustrates an exemplary system in which a gas is distributed over a plate disposed above a substrate holder configured for supporting a microelectronic topography.
  • the method and system allows portions of a deposition solution in select regions of the microelectronic topography to evaporate (i.e., remove water from the deposition solution) a faster rate than other regions, inducing solution temperature uniformity or variation across the topography. In general, removing water from an electroless plating solution will lower the temperature of the solution.
  • the evaporation of the solution during processing may produce a horizontal variation of elemental concentrations and, in some cases, a vertical variation of elemental concentrations as well.
  • the gas may be configured react with the surface of the microelectronic topography such that contaminants (i.e., debris and/or oxidized metal) may be removed from the surface topography.
  • the gas may be additionally or alternatively configured to regulate concentrations of other gases within the electroless plating chamber.
  • the method may include exposing a microelectronic topography arranged within an electroless plating chamber to a deposition solution. Such an exposure may include immersing the microelectronic topography within a bath of the deposition solution, dispensing the deposition solution upon the microelectronic topography, or a combination thereof.
  • An exemplary configuration of an electroless plating chamber which may be used for the method depicted in FIG. 12 is illustrated in FIG. 13 .
  • electroless plating chamber 130 includes substrate holder 132 upon which a microelectronic topography may be supported. Suspended above substrate holder 132 is dispense arm 134 and plate 136 .
  • dispense arm 134 may include the configurations described in reference to FIGS. 6-8 and, therefore, may be moveable to multiple positions above substrate holder 132 . In other embodiments, however, dispense arm 134 may be fixed. As such, the configurations of electroless plating chamber 130 of FIG. 13 and electroless plating chamber 80 of FIG. 7 may be combined or may be mutually exclusive. In alternative embodiments, the method described in FIG. 12 may be used with an electroless plating chamber having a shower head for dispensing a deposition solution. In other embodiments, the method may be used with an electroless plating chamber which does not include solution dispense arm or shower head, but rather is configured such that a microelectronic topography may be immersed within a deposition solution.
  • the deposition method may include block 122 as shown in FIG. 12 in which a gas is introduced into the electroless deposition chamber above a plate suspended above the microelectronic topography. Such a step may be performed within electroless plating chamber 130 by introducing a gas into gas inlet 138 above plate 136 .
  • electroless plating chamber 130 may further include outlet 139 by which to remove the deposition solution and byproduct gases as shown in FIG. 13 .
  • the gas introduced into electroless plating chamber 130 may include nitrogen and, in some cases, may be specifically the diatomic form of nitrogen (i.e., N 2 ). Such a gas may be particularly applicable for increasing the evaporation rage of the deposition.
  • the gas may be configured to be reactive with the surface of the microelectronic topography such that contaminants (i.e., debris and/or oxidized metal) may be removed from the surface topography.
  • contaminants i.e., debris and/or oxidized metal
  • the gas may be additionally or alternatively configured to regulate concentrations of other gases within the electroless plating chamber.
  • the sequence of steps associated with blocks 120 and 122 is not necessarily limited to the order shown in FIG. 12 .
  • the step of introducing a gas into the electroless plating chamber may sometimes be initiated subsequent to the step of exposing the microelectronic topography to a deposition solution, but the method is not necessarily so restricted.
  • the step of introducing a gas into the electroless plating chamber may alternatively be initiated prior to the step of exposing the microelectronic topography to a deposition solution.
  • the step of introducing a gas into the electroless plating chamber may be initiated at substantially the same time as the step of exposing the microelectronic topography to a deposition solution.
  • the method in FIG. 12 continues to block 124 in which the gas is distributed to regions extending above one or more discrete portions of the microelectronic topography.
  • the distribution of the gas to such regions may be used to invoke evaporation of the deposition solution at the one or more discrete portions of the microelectronic topography.
  • the one or more discrete portions may include the peripheral edge of the microelectronic topography.
  • gas introduced above plate 136 may be directed to the outer edges of plate 136 down to the peripheral edges of the microelectronic topography.
  • Such a route for the gas may be particularly advantageous for negating the edge effect in some embodiments. Films resulting from such a route may have substantially uniform thickness across the microelectronic topography or may have greater thicknesses near the edge of the wafer as compared to near the center of the wafer.
  • plate 136 may be a disc having a diameter slightly smaller than the microelectronic topography being processed.
  • plate 136 may have a diameter between approximately 150 mm and approximately 190 mm for processing 200 mm microelectronic wafers.
  • plate 136 may have a diameter between approximately 250 mm and approximately 290 mm for processing 300 mm microelectronic wafers.
  • Discs of larger or smaller diameters may be used for either sized wafer, depending on the fabrication specifications of the ensuing device.
  • plate 136 may not be a disc and, thus, may be alternatively formed of a different shape including but not limited to a square or a rectangle.
  • plate 136 may, in some embodiments, include holes such that portions in addition or alternative to the peripheral edges of a microelectronic topography may be exposed to the gas and, thus, have portions of a deposition solution thereon evaporate at a faster rate than other portions of the topography.
  • the holes may be of any size and shape necessary for exposing a desired area of the microelectronic topography to the gas introduced through gas inlet 138 .
  • the process of distributing the gas to regions of the microelectronic topography may include rotating plate 136 .
  • Such rotation may advantageously direct gas to the edge and/or openings within plate 136 down to the microelectronic topography.
  • plate 136 maybe rotated in the same direction as substrate holder 132 as shown in FIG. 13 .
  • plate 136 may be rotated in the opposite direction as substrate holder 132 .
  • substrate holder 132 and plate 136 may be independently configured to rotate clockwise and/or counterclockwise.
  • An exemplary range of rotation speed for plate 136 may be between approximately 100 rpm and approximately 500 rpm, although faster or slower rates may be employed.
  • plate 136 and substrate holder 132 may be rotated at the same speed. In other embodiments, however, plate 136 and substrate holder 132 may be rotated at different speeds. In either of such cases, the rate of rotation of plate 136 may, in some embodiments, be optimized with respect to wafer rotation speed and solution flow rate in order to induce solution temperature variation or uniformity across the microelectronic topography.
  • FIG. 14 A plan view of a test wafer having a film with regions of different elemental concentrations and thicknesses is shown in FIG. 14 .
  • a plan view of test wafer 140 is illustrated with multiple zones of different material thicknesses and elemental concentrations deposited using any of the methods and systems described above in reference to FIGS. 3-13 .
  • FIG. 14 illustrates test wafer 140 with an electrolessly deposited film including annulus areas (denoted as zones 1-9), each having comparatively different thicknesses and comparatively different elemental concentrations. Zones 1-9 are generally formed separately and in any order.
  • zones 1-9 may be formed by deposition of the annulus close to wafer edge, followed by deposition of a layer of another thickness within an adjacent annulus closer to wafer center, and so on.
  • FIG. 14 illustrates test wafer 140 having nine zones, the test wafer is not necessarily so limited. In particular, test wafer 140 may include any plurality of zones. In addition, test wafer 140 is not limited to having zones 1-9 of substantially similar widths. As such, in some embodiments, zones 1-9 may be formed with different widths.
  • zones 1-9 may be configured incrementally with respect to their thicknesses as shown in the exemplary partial cross-sectional view of test wafer 140 in FIG. 15 a .
  • zone 1 may be configured to have the thinnest profile
  • zone 9 may include the thickest profile
  • zones 2-8 may include incremental thicknesses therebetween.
  • Exemplary thicknesses for the zones may be approximately 100 nm at zone 9 of, approximately 30 nm at zone 1, thicknesses ranging from approximately 35 nm to approximately 95 nm at zones 2-8. Larger or smaller thicknesses, however, may be employed for any or all of zones 1-9, depending on the design specifications of the ensuing device.
  • FIG. 1 may be configured to have the thinnest profile
  • zone 9 may include the thickest profile
  • zones 2-8 may include incremental thicknesses therebetween.
  • Exemplary thicknesses for the zones may be approximately 100 nm at zone 9 of, approximately 30 nm at zone 1, thicknesses ranging from approximately 35 nm to approximately 95 nm at zones 2-8
  • the thickness of zones 1-9 may not vary incrementally in some embodiments. Such a pattern layout is feasible since each zone is formed separately and the thickness of each region is dependent on the selective distribution of the deposition solution. In such cases, the thicknesses of zones 1-9 may vary between approximately 30 nm and approximately 100 nm, but larger or smaller thicknesses may be employed. Due to the methods and systems described herein, variations of elemental concentrations may be incorporated into zones 1-9.
  • test wafer 140 may generally be used for calibration of thin film metrology equipment such as acoustic wave, X-ray fluorescence, sheet resistance, RBS, and such.
  • Conventional metrology calibrations typically utilize multiple test wafers.
  • a plurality of calibration wafers is often costly due to the costs for both the wafers themselves and for lost production time on manufacturing tools due to qualification and calibration downtime.
  • a single calibration wafer, such as test wafer 140 will allow significant cost advantages.

Abstract

A method is provided which includes dispensing and removing different deposition solutions during an electroless deposition process to form different sub-films of a composite layer. Another method includes forming a film by an electroless deposition process and subsequently annealing the microelectronic topography to induce diffusion of an element within the film. Yet another method includes reiterating different mechanisms of deposition growth, namely interfacial electroless reduction and chemical adsorption, from a single deposition solution to form different sub-films of a composite layer. A microelectronic topography resulting from one or more of the methods includes a film formed in contact with a structure having a bulk concentration of a first element. The film has periodic successions of regions each comprising a region with a concentration of a second element greater than a set amount and a region with a concentration of the second element less than the set amount.

Description

    PRIORITY APPLICATION
  • The present application claims priority to provisional application no. 60/599,975 entitled “Methods and Systems for Processing a Microelectronic Topography” filed Aug. 9, 2004.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention generally relates to methods for processing a microelectronic topography and more particularly to electroless plating processes performed upon microelectronic topographies and structures resulting therefrom.
  • 2. Description of the Related Art
  • The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
  • Electroless plating (also referred to herein as “electroless deposition”) is a process for depositing materials on a catalytic surface from an electrolyte solution without an external source of current. An advantage of an electroless plating process is that it can be selective, i.e., the material can be deposited only onto areas that demonstrate appropriate chemical properties. In particular, local deposition can be performed onto metals that exhibit an affinity to the material being deposited or onto areas pretreated or pre-activated, e.g., with a catalyst. The ratio of the deposition rate on the activated regions to the deposition rate at the non-activated regions is known as the “deposition process selectivity.” For many applications, it is important to provide a deposition of high selectivity. For instance, high deposition selectivity may be advantageous for the formation of metal features within integrated circuits, such as but not limited to contacts, vias, and interconnect lines.
  • Another important characteristic of an electroless plating process is producing a deposition profile which is commensurate with the fabrication specifications of the device. For instance, in some cases, it may be advantageous to have a film deposited with substantially uniform thickness. In cases in which a film is electrolessly deposited across a microelectronic topography, however, obtaining thickness uniformity may be difficult. In particular, some electroless plating techniques are susceptible to the “edge effect” in which portions of a film deposited near the edge of the wafer are thinner than the portions of the film deposited near the center of the wafer. Such an effect also hinders fabrication specifications for depositing films having greater thicknesses near the edge of the wafer as compared to near the center of the wafer.
  • As noted above, electroless plating may be used for the formation of metal features within integrated circuits. In some cases, electroless plating techniques may be particularly favorable for depositing materials into deep and/or narrow holes that cannot be uniformly covered by other deposition techniques, such as sputtering and evaporation, for example. In addition, electroless plating techniques may be advantageous for forming copper features, complementing the trend in the integrated circuit industry of employing copper metallization structures instead of aluminum, tungsten, silicides, or the like. In some microelectronic devices, a barrier layer may be arranged beneath and/or upon a metal feature to prevent elements within the metal feature from respectively diffusing to underlying and overlying layers of the topography. Such barrier layers may, in some embodiments, be formed by electroless plating processes. Although conventional barrier layers are generally sufficient to inhibit most elemental diffusion from a metal feature, some diffusion may still occur. For example, copper atoms are particularly notorious for being able to migrate through barrier layers. The migrated copper atoms can potentially be exposed to oxidation or moisture at the surface of the barrier layer or may tunnel through silicon materials disposed adjacent to the barrier layer, affecting the reliability of the device and, in some cases, causing the device to malfunction.
  • It would, therefore, be desirable to develop methods and systems for fabricating barrier layers which inhibit a greater degree of elemental diffusion from overlying and/or underlying metal features than provided by conventional barrier layers. In addition, it would be beneficial to develop systems and methods for electrolessly depositing films without incurring the edge effect.
  • SUMMARY OF THE INVENTION
  • The problems outlined above may be in large part addressed by methods involving electroless plating processes for the formation of metallic layers and structures within microelectronic topographies. The following are mere exemplary embodiments of the methods and resulting structures and are not to be construed in any way to limit the subject matter of the claims.
  • An embodiment of one of the methods includes positioning the microelectronic topography within an electroless plating chamber, dispensing a first deposition solution upon the microelectronic topography to form a first sub-film, and subsequently removing the first deposition solution from the electroless plating chamber. The method further includes dispensing a second deposition solution upon the microelectronic topography subsequent to the removal of the first deposition solution to form a second sub-film upon and in contact with the first sub-film. The second sub-film includes multiple elements included within the first sub-film.
  • An embodiment of another of the methods includes forming a bulk metallic film upon the microelectronic topography using an electroless plating process. The bulk metallic film includes a bottom portion, a top portion, and an intermediate portion interposed between the bottom and top portions. One of the top and bottom portions includes a higher concentration of a first element than the intermediate portion and the other of the top and bottom portions. The method further includes annealing the microelectronic topography to induce diffusion of the first element within the bulk metallic film such that the intermediate portion comprises a higher concentration of the first element than the bottom and top portions.
  • An embodiment of yet another of the methods includes exposing a microelectronic topography to a deposition solution and forming a first sub-film portion by interfacial electroless reduction of a first element within the deposition solution until a second different element reaches a certain concentration within the deposition solution. The first sub-film includes a higher concentration of the first element than the second element. The method further includes forming a second sub-film portion upon and in contact with the first sub-film portion by chemical adsorption until the first element increases to a particular concentration within the deposition solution. The second sub-film includes a higher concentration of the second element than the first element. In addition, the method includes reiterating the steps of forming the first and second sub-film portions to form a composite film comprising concentration variations of the first and second elements.
  • An embodiment of a microelectronic topography resulting from one or more of the methods includes a structure having a bulk concentration of a first element disposed throughout the structure and a film consisting essentially of one or more elements different than the first element formed in contact with the structure. The film has periodic successions of regions each comprising at least one region with a concentration of a second element greater than a set amount and at least one region with a concentration of the second element less than the set amount.
  • Another embodiment of a microelectronic topography resulting from one or more of the methods includes a conductive structure having a bulk concentration of copper disposed throughout the structure and a film formed in contact with the conductive structure comprising alternating regions of comparatively greater and lesser concentrations of cobalt.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
  • FIG. 1 depicts a partial cross-sectional view of a microelectronic topography having a liner layer and cap layer formed about a metallization structure;
  • FIG. 2 a depicts an exemplary view of at least one of the liner layer and cap layer illustrated in FIG. 1, which may serve as a partial cross-sectional view or a partial plan view;
  • FIG. 2 b depicts another exemplary view of at least one of the liner layer and cap layer illustrated in FIG. 1, which may serve as a partial cross-sectional view or a partial plan view;
  • FIG. 2 c depicts yet another exemplary view of at least one of the liner layer and cap layer illustrated in FIG. 1, which may serve as a partial cross-sectional view or a partial plan view;
  • FIG. 3 depicts a flowchart of a method for forming a composite metallic layer having a variation of elemental concentrations;
  • FIG. 4 depicts a flowchart of an alternative method for forming a composite metallic layer having a variation of elemental concentrations;
  • FIG. 5 depicts a flowchart of another alternative method for forming a composite metallic layer having a variation of elemental concentrations;
  • FIG. 6 depicts a flowchart of yet another alternative method for forming a composite metallic layer having a variation of elemental concentrations;
  • FIG. 7 depicts a plan view of an electroless plating chamber configured for the method outlined in the flowchart of FIG. 6;
  • FIG. 8 depicts a schematic of a computer system which may be coupled to or incorporated within the electroless plating chamber illustrated in FIG. 8;
  • FIG. 9 depicts a plot of solution temperature versus process time for a plurality of different areas of a microelectronic topography;
  • FIG. 10 a depicts a partial cross-sectional view of a microelectronic topography having a film first deposited by a reaction limited mechanism of film growth and further deposited by a mass diffusion limited mechanism of film growth;
  • FIG. 10 b depicts a partial cross-sectional view of a microelectronic topography having a film deposited exclusively by a reaction limited mechanism of film growth;
  • FIG. 10 c depicts a partial cross-sectional view of a microelectronic topography having a film first deposited by a reaction limited mechanism of film growth, followed by a mass diffusion limited mechanism of film growth, and finally by a second reaction limited mechanism of film growth;
  • FIG. 11 depicts a plot of solution dispensing time versus a plurality of different areas of a microelectronic topography;
  • FIG. 12 depicts a flowchart of a method for depositing a film using an electroless deposition chamber;
  • FIG. 13 depicts a cross-sectional view of an electroless plating chamber configured for the method outlined in the flowchart of FIG. 12;
  • FIG. 14 depicts a plan view of an exemplary test wafer having distinct regions each including comparatively different thicknesses and comparatively different elemental concentrations;
  • FIG. 15 a depicts a partial cross-sectional view of the test wafer illustrated in FIG. 14; and
  • FIG. 15 b depicts an alternative partial cross-sectional view of the test wafer illustrated in FIG. 14.
  • While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Turning to the drawings, exemplary methods and systems involving electroless plating processes for the formation of metallic layers and structures within microelectronic topographies are shown. In addition, microelectronic topographies resulting from the use of such methods and systems are shown. For instance, FIG. 1 illustrates a partial cross-sectional view of microelectronic topography 20 having liner layer 28, cap layer 30, as well as other metallic structures which may be formed from the methods and systems described below in reference to FIGS. 3-13. Although the methods and systems described below are specifically discussed in reference to the formation of barrier layers and, therefore, are specific to liner layer 28 and cap layer 30, any of the metallic structures of microelectronic topography 20, including those formed below lower layer 26 and those formed above cap layer 30, may be formed by the methods and systems described below in reference to FIGS. 3-13.
  • As will be described in more detail below, the elemental composition of liner layer 28 and cap layer 30 may be configured to reduce the diffusion of elements from metallization structure 22 to lower layer 26, dielectric layer 24 and any layers formed upon cap layer 30, reducing electromigration within an ensuing device. In addition, cap layer 30 may be configured to prevent oxidation of metallization structure 22. As such, liner layer 28 and cap layer 30 may generally be referred to as barrier layers. Such a reference, however, does not necessarily infer the exclusivity of the aforementioned functions. In particular, liner layer 28 and/or cap layer may additionally or alternatively serve as adhesion layers and/or thermal expansion buffers. Exemplary elemental compositions of liner layer 28 and/or cap layer 30 resulting from the use of the methods and/or systems described in reference to FIGS. 3-13 are shown in FIGS. 2 a-2 c and are discussed in more detail below. It is noted that microelectronic topography 20 is not necessarily limited to having both liner layer 28 and cap layer 30 be formed by the methods and systems described herein. In particular, the methods and systems may be applied to either or both of such layers. In addition, although microelectronic topography 20 is shown including both liner layer 28 and cap layer 30, the topography is not necessarily so limited. In particular, microelectronic topography 20 may alternatively include only one of liner layer 28 and cap layer 30.
  • In general, the term “microelectronic topography” may refer to a substrate resulting from or used for the fabrication of a microelectronic device or circuit, such as an integrated circuit, for example. As such, metallization structure 22 may be any metal feature known for the fabrication of a microelectronic device. For example, metallization structure 22 may, in some embodiments, serve as a contact structure to portions of a semiconductor layer. In such cases, lower layer 26 may include a semiconductor material, such as silicon and may, in some embodiments, be doped either n-type or p-type. More specifically, lower layer 26 may be a monocrystalline silicon substrate or an epitaxial silicon layer grown on a monocrystalline silicon substrate. In addition or alternatively, lower layer 26 may include a silicon on insulator (SOI) layer, which may be formed upon a silicon wafer. In other cases, lower layer 26 may include metallization and/or an interlevel dielectric layer. In such embodiments, metallization structure 22 may serve as a via, an interconnect or any other metallization feature to underlying portions of microelectronic topography 20.
  • In any case, metallization structure 22 may include one or more layers of conductive materials, including but not limited to copper, aluminum, tungsten, titanium, silver, or any alloy of such metals. In some embodiments, the methods and systems described herein may be particularly applicable to microelectronic topographies including a metallization structure having a bulk concentration of copper and, in some cases, consisting essentially of copper. In particular, copper has a relatively low resistivity and, therefore, is often favorable to use for metallization structures in microelectronic devices. As noted above, copper atoms are particularly notorious for their propensity to diffuse through materials. The methods and systems described herein, however, offer manners in which to fabricate barrier layers around copper metallization structures to substantially minimize or eliminate the diffusion of copper to other layers.
  • In some embodiments, metallization structure 22 may, in some embodiments, be fabricated by electroless plating techniques, including those described herein as well as others known in the microelectronic fabrication industry. In other embodiments, metallization structure 22 may be formed by other deposition techniques known in the microelectronic fabrication industry, such as but not limited to sputtering or evaporation. In either case, metallization structure 22 may be formed within a trench formed within dielectric layer 24. Such a fabrication sequence may be particularly advantageous for the incorporation of liner layer 22 within microelectronic topography 20. In other embodiments, dielectric layer 24 may be formed subsequent to and about metallization structure 22.
  • Dielectric layer 24 may include one or more of various dielectric materials used in microelectronic fabrication. For example, dielectric layer 24 may include silicon dioxide (SiO2), silicon nitride (SixNy), silicon dioxide/silicon nitride/silicon dioxide (ONO), silicon carbide, carbon-doped SiO2, or carbonated polymers. In some cases, dielectric layer 24 may be undoped. Alternatively, dielectric layer 24 may be doped to form, for example, low doped borophosphorus silicate glass (BPSG), low doped phosphorus silicate glass (PSG), or fluorinated silicate glass (FSG). In some embodiments, dielectric layer 24 may be formed from a low-permittivity (“low-k”) dielectric, generally known in the art as a dielectric having a dielectric constant of less than about 3.5. One low-k dielectric in current use, which is believed to make a conformal film, is fluorine-doped silicon dioxide. In any case, dielectric layer 24 may have a thickness between approximately 2,000 angstroms and approximately 10,000 angstroms. Larger or smaller thicknesses of dielectric layer 24, however, may be appropriate depending on the microelectronic device being formed.
  • As noted above, the elemental composition of liner layer 28 and cap layer 30 may be configured to reduce the diffusion of elements from metallization structure 22. As such, the selection and arrangement of the elements included within liner layer 28 and cap layer 30 may, in some embodiments, depend on the elements included in metallization structure 22. In embodiments in which metallization structure 22 includes copper, the inclusion of cobalt within liner layer 28 and cap layer 30 may be particularly beneficial since copper has relatively low solubility with cobalt. Other materials which may be additionally or alternatively included within liner layer 28 and cap layer 30 may include phosphorus, boron, tungsten, chromium, molybdenum, nickel, palladium, rhodium, ruthenium, oxygen, and hydrogen.
  • Exemplary alloys which may be employed for liner layer 28 and cap layer 30 include but are not limited to cobalt-tungsten-phosphorus (CoWP), cobalt-tungsten-boron (CoWB), cobalt-tungsten-phosphorus-boron (CoWPB), cobalt-molybdenum-boron (CoMoB), cobalt-molybdenum-phosphorus (CoMoP), cobalt-molybdenum-chromium (CoMoCr), and cobalt-molybdenum-chromium-boron (CoMoCrB). In other embodiments, liner layer 29 and/or cap layer 30 may include single element layers of palladium, rhodium and ruthenium. It is noted that although hydrogen is not listed as an element with such exemplary materials, it may be incorporated therein as a result of the electroless plating process as described in more detail below. In some embodiments, liner layer 29 and cap layer 30 may include the same collection of elements and, in some cases, a similar arrangement of elements. In other cases, however, liner layer 29 and cap layer 30 may include different arrangements of elements and, in some embodiments, a different collection of elements.
  • In some embodiments, liner layer 28 and/or cap layer 30 may include a variation of elemental concentrations throughout the layers to reduce the diffusion of elements from metallization structure 22 therethrough. In particular, liner layer 28 and/or cap layer 30 may include different concentrations of elements in different regions of the layer. Exemplary elemental compositions of liner layer 28 and/or cap layer 30 are shown in FIGS. 2 a-2 c. In some cases, the variation of elements within liner layer 28 and cap layer 30 may be arranged in sub-layers vertically disposed within the films. As such, FIGS. 2 a-2 c may, in some embodiments, illustrate partial cross-sectional views of liner layer 28 and/or cap layer 30. In other cases, the variation of elements may be additionally or alternatively arranged in regions extending horizontally between lateral edges of the films. As such, FIGS. 2 a-2 c may alternatively illustrate partial plan views of the upper surface of cap layer 30. In such embodiments, liner layer 28 may, in some cases, include a similar horizontal variation of elements and, therefore, FIGS. 2 a-2 c may apply to liner layer 28 for horizontal variations of elements as well. In some cases, the variation of element concentrations may vary both horizontally and vertically within the films and, therefore, FIGS. 2 a-2 c may be representative of either a cross-sectional view or a plan view of the layers.
  • As shown in FIG. 2 a, liner layer 28 and/or cap layer 30 may, in some embodiments, include alternating regions of comparatively greater and lesser concentrations of an element. More specifically, FIG. 2 a illustrates an arrangement of atoms of an element (each atom shown as an “x” in FIG. 2 a) which, in an effect, partitions the layer into regions 32 comprising comparatively fewer atoms of the element and regions 34 comprising comparatively greater quantities of atoms of the element. Regions 32 and 34 are disposed along opposing sides of each other and, therefore, alternative through the film. Regions 32 and regions 34 may be differentiated from each other by including concentrations of an element which respectively fit into different ranges of concentrations. For example, in some embodiments, regions 32 may include between approximately 30% and approximately 50% of an element, while regions 34 may include between approximately 5% and approximately 20% of an element. Larger or smaller ranges and magnitudes of elemental concentrations may be employed depending on the element of differing concentration and the design specifications of the device. Consequently, the barrier films disclosed herein are not necessarily limited to the aforementioned values. Since regions 32 and regions 34 are differentiated by different ranges of elemental concentrations, neither regions 32 nor regions 34 need to necessarily include the same concentrations of an element as shown in FIG. 2 a. Noting such a scope of the film, the elemental concentrations of regions 32 and 34 are not necessarily restricted to having different elemental concentrations either. Therefore, in some cases, two or more of the respective regions may include the same elemental concentration.
  • It is noted that elemental atoms other than the one shown in FIG. 2 a may be included within liner layer 28 and cap layer 30. In addition, although FIG. 2 aillustrates variation of only a single element within liner layer 28 and cap layer 30, other elements within the film may vary. In some embodiments, the other elements may vary in a similar manner as element x and, therefore, may be disposed within regions 34 and 32 having comparatively greater and lesser concentrations, respectively. In other embodiments, regions 32 and 34 may include an opposite arrangement of greater and lesser concentrations of the one or more elements. In particular, regions 32 may include a low concentration of element x and a high concentration of another element and vice versa for regions 34. In yet other embodiments, the concentration variation of the other element may not alternate through the film, but may follow its own succession of regions having varying concentrations of the element. In any case, regions 32 and 34 are not restricted to having the same concentration levels of different elemental atoms. In particular, regions 32 and 34 may include different ranges of concentrations for each element. Alternatively, the concentration of other elements may not substantially vary through the film.
  • An alternative arrangement of elements for liner layer 28 and cap layer 30 is illustrated in FIG. 2 b. In particular, FIG. 2 b illustrates liner layer 28 and cap layer 30 having concentration variations of two different elements (atoms of the elements shown as “x” and “o”). As shown in FIG. 2 b, the relative concentrations of the elements do not alternate through the films, but rather are disposed as periodic successions of regions 36. More specifically, periodic successions of regions 36 are shown having three regions with relatively different concentrations of element atoms “x” and “o.” Although periodic successions of regions 36 are shown to include three regions, liner layer 28 and cap layer 30 are not necessarily so restricted. In particular, periodic successions of regions 36 may include any plurality of regions.
  • Each of periodic successions of regions 36 includes at least one region with a concentration of an element greater than a set amount and at least one region with a concentration of the element less than the set amount. The set amounts may generally depend on the individual element and the design specifications of the film and, therefore, may vary between approximately 1% and approximately 99%. Set amounts for the multiple elements within a film are generally independent of each other. As shown in FIG. 2 b, periodic successions of regions 36 may include region 36 a having a greater concentration of elemental atoms “x” and “o” than region 36 b, which includes a greater concentration than region 36 c. In such cases, region 36 a may include a concentration of elemental atoms “x” and “o” greater than a set amount and region 36 c may include a concentration of elemental atoms “x” and “o” less than the set amount. Region 36 b may fit into either of such categories, depending on the design specifications of the film. As such, periodic successions of regions 36 may include a series of regions having incrementally increasing relative concentrations. In other embodiments, regions 36 a, 36 b, and 36 may be arranged in an alternative sequence, such as having regions 36 a or 36 c interposed between the other regions such that progression of elemental concentrations through periodic successions of regions 36 is not incremental.
  • In any case, periodic successions of regions 36 may include regions which are differentiated from each other by respectively different ranges of elemental concentrations. As such, each of regions 36 a (as well as each of regions 36 b and 36 c) do not necessarily need to include the same concentrations of elemental atoms “x” or “o.” Furthermore, periodic successions of regions 36 are not restricted to having the same concentration levels of element atoms “x” and “o.” In particular, regions 36 a, 36 b and 36 c may include different ranges of concentrations for each element. Moreover, the relative level of elemental concentrations among regions 36 a, 36 b, and 36 c may be different for each of the elements respectively associated with atoms “x” and “o.” For example, region 36 a may alternatively include the relatively highest amount of elemental atoms “x” and include the relatively lowest amount of elemental atoms “o” among each succession of regions 36. In other embodiments, region 36 b or 36 c may alternatively include the relatively highest amount of elemental atoms “x” and the relatively lowest amount of elemental atoms “o” among each succession of regions 36.
  • Another alternative composition of elements for liner layer 28 and/or cap layer 30 is illustrated in FIG. 2 c. In particular, FIG. 2 c illustrates liner layer 28 and/or cap layer 30 including region 38 with a relatively high concentration of element “+” interposed between regions 39 having comparatively lower concentrations of the element. As described in more detail below, such an arrangement may be resultant of the method described below in reference to FIG. 4, although it is not necessarily limited to such a method of formation. As with regions 32 and 34 of FIG. 2 a, regions 39 do not necessarily need to include the same concentration of element “+.” Rather, regions 39 may include concentrations of an element which fits into a different range of concentrations than the concentration of region 38. In addition, region 38 is not restricted to being centered within liner layer 28 and cap layer 30.
  • It is noted that liner layer 28 and cap layer 30 are not necessarily restricted to the configurations illustrated in FIGS. 2 a-2 c. In particular, liner layer 28 and cap layer 30 may include any variation of elemental concentrations among distinct regions of the films. In some embodiments, it may be particularly advantageous for at least one of liner layer 28 and cap layer 30 to include a periodic arrangement of concentration levels in order to inhibit diffusion from metallization structure 22. In particular, liner layer 28 and/or cap layer 30 may include different concentrations of one or more elements at regular intervals of the layer as shown in FIGS. 2 a and 2 b, for example. In other embodiments, the variation of elemental concentration shown in FIG. 2 c may be appropriate to inhibit diffusion from metallization structure 22.
  • In general, the elements which are configured to vary within liner layer 28 and/or cap layer 30 may be any of the elements which may be included within the films. In particular, the elements having varying concentrations in liner layer 28 and cap layer 30 may be cobalt, phosphorus, boron, tungsten, chromium, molybdenum, nickel, palladium, rhodium, ruthenium and/or hydrogen. As noted above, copper has relatively low solubility with cobalt and, therefore, it may be advantageous to vary the concentration of cobalt within liner layer 28 and/or cap layer 30 in some embodiments. In particular, a variation of cobalt concentration throughout liner layer 28 and cap layer 30 may substantially reduce the migration of copper through the films compared to embodiments in which the concentration of cobalt is substantially even. In turn, the likelihood of copper atoms reaching surrounding layers may be reduced. In some cases, the level of cobalt concentration may alternate through liner layer 28 and cap layer 30. Consequently, in some cases, liner layer 28 and cap layer 30 may include a composite film of alternating cobalt-rich and cobalt-poor regions.
  • In any case, it may be further advantageous to include a relatively high concentration of cobalt in regions of liner layer 28 and/or cap layer 30 directly adjacent and in contact with metallization structure 22 to improve the adhesion to the copper material. Such an arrangement, however, is not necessarily required and, therefore, microelectronic topography 20 is not intended to be restricted to such a configuration. As noted above, liner layer 28 and cap layer 30 may include periodic regions of different concentrations of other elements as well or alternatively. It is noted that the variation of symbols denoting different elemental atoms in FIGS. 2 a-2 c (i.e., “x,” “o,” and “+”) do not necessarily imply that the different configurations are particular to specific elements or combinations of elements. The differentiation is merely shown to emphasize that different elements may be formed in a periodic manner within barrier layers.
  • Although variations of elemental concentrations within liner layer 28 and cap layer 30 may differ depending on the design specifications of microelectronic topography 20, some exemplary ranges may be applicable to many applications. For instance, an exemplary cobalt concentration variation may be between, for example, approximately 10% and approximately 30%, or more specifically, a variation of approximately 20%. In addition, an exemplary variation of phosphorus concentration may be between approximately 3% and approximately 12% and a variation of boron concentration may be between approximately 1% and approximately 2%. In some cases, liner layer 28 and cap layer 30 may include a concentration variation of molybdenum between approximately 1% and approximately 50%. Larger or smaller variations of concentrations may be employed for any of such elements as well as the other elements listed for liner layer 28 and cap layer 30 and, therefore, the aforementioned limitations do not necessarily limit the range of elemental concentrations within the layers.
  • Several methods are described herein for forming a barrier layer (such as liner layer 28 and/or cap layer 30) with a variation of the components. For example, one method for forming a barrier layer with a vertical variation of elemental concentrations may include depositing a plurality of sub-layers having different concentrations of elements. A flowchart of a method of depositing a plurality of sub-layers having different concentrations of elements is shown in FIG. 3. As shown in blocks 40 and 42 of FIG. 3, the method may include positioning a microelectronic topography within an electroless plating chamber and dispensing a first deposition solution upon the microelectronic topography to form a first sub-layer upon the microelectronic topography. In some embodiments, the process may further include rotating a substrate holder upon which the microelectronic topography is positioned to facilitate the distribution of the first deposition solution across the topography. The first sub-layer may include one or more elements formed within individual concentration ranges.
  • In some embodiments, the distribution of the first deposition solution may be a single continuous flow across the surface of microelectronic topography. In other embodiments, the distribution of the first deposition solution may be a series of fragmented depositions of the solution at different locations extending different distances from a center of the microelectronic topography. Such a technique may induce a horizontal variation of element concentrations within the first sub-layer and, in some cases, subsequent sub-films. Consequently, the ensuing composite layer may include both vertical and horizontal variations of elemental concentrations. An exemplary method and system for dispensing deposition solution in a series of fragmented times and locations are described in more detail below in reference to FIGS. 6-8. In some cases, the method may additionally or alternatively be performed in a chamber configured to induce a variation of evaporation rates across a topography such that a horizontal variation of elemental concentrations within the first and/or subsequent sub-films may be obtained by such a manner. An exemplary method and system for varying evaporation rates across a microelectronic topography during an electroless deposition chamber are described in more detail below in reference to FIGS. 12 and 13.
  • In any case, the method may, in some embodiments, include blocks 43 a and 43 b in which dispensing the deposition solution and/or rotation of the substrate holder (when so applied) is terminated and subsequently resumed during the deposition of the first sub-film. In some embodiments, the processes associated with blocks 43 a and 43 b may be conducted as a single sequence of steps as indicated by the single direction arrow between the blocks. In other cases, the processes associated with blocks 43 a and 43 b may be reiterated multiple times during the deposition process as indicted by the bi-directional arrow between the blocks. In such embodiments, the sequence of steps may end with either of the processes when the method continues onto block 44 even though FIG. 1 illustrates the method continuing on to block 44 from block 43 b. In either case, the sequence of steps may advantageously facilitate a substantial uniform deposition of elemental components across the topography within the first sub-film while still preventing the accumulation of bubbles upon the topography during deposition, as described in more detail below. The sequence of steps may additionally or alternatively be used during the deposition of subsequent sub-films as well. As such, although the overall method described in reference to FIG. 3 is used to fabricate a composite barrier layer with a variation of elemental concentrations (i.e., among the different sub-films), the sub-film layers themselves may be formed to have a substantially uniform distribution and concentration of elements.
  • It is theorized that the adsorption potential of charged molecules within a deposition solution is influenced by the ratio of different surface materials (e.g., amount of conductive surfaces versus dielectric surfaces) within a given area of a topography. In particular, it is theorized that an area with a greater density of conductive structures (i.e., an area with relatively less dielectric surface material) may have a stronger affinity for adsorbing charged molecules than an area of relatively lower density of conductive structures. As a result, the area with the greater density of conductive structures may have a different concentration and distribution of elements than the area with the lesser density of conductive structures. It has been discovered, in conjunction with the development of the methods described herein, that the termination of dispensing the deposition solution and/or the termination of rotating the substrate holder during the deposition of a film may reduce or negate variations of charged molecule adsorption potentials relative to areas of a topography having different densities of surface materials. In particular, it has been found that the termination of one or more of the processes associated with block 43 a allows films having substantially similar distribution and concentration of elements to be deposited across a topography.
  • In some cases, however, the termination processes of block 43 a may cause the formation of bubbles upon the microelectronic topography. The formation of bubbles during electroless deposition processes often cause undesirable random non-uniformity in deposition thickness and, in some cases, cause defects to be formed within the film. The recommencement of dispensing the deposition solution and/or rotating the substrate holder as noted in block 43 b, however, may advantageously remove bubbles formed from the termination processes. As a result, a film having a substantially uniform elemental composition, uniform thickness, a minimal number or no defects may be deposited with the technique described herein.
  • In general, the duration of termination and resumption of the processes described in reference to FIG. 43 a and 43 b may be between approximately 0.5 seconds and approximately 1 minute. Shorter or longer durations, however, may be employed for each of such processes. In some embodiments, it may be advantageous for the termination of the processes to be short, such as between approximately 0.5 seconds and approximately 5 seconds, or more specifically about 2 seconds, to reduce the formation of bubbles during the deposition process. In some cases, it may be beneficial for the termination of the processes to be shorter than the duration for which the processes are resumed. For example, in some embodiments, it may be advantageous to resume the processes for a duration between approximately 15 seconds and approximately 45 seconds, or more specifically about 30 seconds. In other cases, however, the duration of the processes may be the same or the termination of the processes may be longer than the duration for resuming the processes. In yet other embodiments, blocks 43 a and 43 b and the associated termination and resuming processes may be omitted from the method described in reference to FIG. 3. Blocks 43 a and 43 b and the arrows extending to and from it are outlined with dotted lines indicating the steps are optional.
  • In any case, the method may continue by removing the first deposition solution from the electroless plating chamber and subsequently dispensing a second deposition solution upon the microelectronic topography to form second sub-layer upon and in contact with the first sub-layer as respectively noted by blocks 44 and 48 in FIG. 3. As with the formation of the first sub-layer, the disbursement of the second deposition solution may be a single continuous flow or may be a series of fragmented depositions. In addition, the method may, in some embodiments, continue to blocks 43 a and 43 b such that the deposition of the second sub-film includes the termination of dispensing the deposition solution and/or the termination of rotating the substrate holder as similarly described above for the formation of the first sub-film.
  • In any case, the second sub-layer may include multiple elements which are also included within the first sub-layer. In some embodiments, the second sub-layer may consist essentially of the same elements as included in the first sub-layer. In other embodiments, however, the first and second sub-layer may include some different elements. In any case, the second sub-layer may include one or more elements having concentrations within different ranges than employed within the first sub-layer. In other words, a concentration of at least one of the elements within the second sub-layer may differ from a concentration of the same element within the first sub-layer. In this manner, the method induces a vertical variation of elemental concentrations.
  • As shown in FIG. 3, the method may, in some embodiments, include block 46 in which chamber process parameters different than those used for the formation of the previous sub-film are established. The incorporation of block 46 prior to the formation of the second sub-layer, as shown in FIG. 3, may in turn include establishing chamber process parameters different than those used during the formation of the first sub-layer. Such different process parameters may be wholly or partially responsible for the variations of elemental concentrations between the first and second sub-layers. In particular, the change in parameters by which the electroless deposition process is conducted may be sufficient to affect the concentration of elements within the second sub-layer as compared to the first sub-layer. Such influential process parameters may include but are not limited to temperature, pressure, and the type of ambient gas included within the electroless plating chamber.
  • In some embodiments, the first and second depositions solutions may include the same compositions and, therefore, the changes of chamber process parameters may be wholly responsible for the variations of elemental concentrations between the first and second sub-layers. In other embodiments, the first and second depositions solutions may include different compositions and, therefore, the changes of chamber process parameters may be partially responsible for the variations of elemental concentrations between the first and second sub-layers. In yet other embodiments, block 46 may not be employed prior to the formation of the second sub-layer. In such cases, the variation of compositions among the first and second deposition solutions may be wholly responsible for the variation of elemental concentrations between the first and second sub-layers. Block 46 and the arrows extending to and from it are outlined with dotted lines indicating the step is optional and, therefore, block 46 and the associated establishment of different chamber process parameters may be omitted in some cases.
  • Regardless of whether different chamber process parameters are established prior to the formation of the second sub-layer, the second deposition solution may be removed from the electroless plating chamber subsequent to the formation of the second sub-layer as shown by block 50 in FIG. 3. Thereafter, the method may follow several different routes. In particular, the method may, in some embodiments, end at block 58 after the removal of the second deposition solution from the electroless plating chamber. Alternatively, the method may include repeating the steps of dispensing and removing the first deposition solution (described in reference to block 42 and 44 ) to form a third sub-layer upon and in contact with the second sub-layer as shown by block 52 in FIG. 3. As with the second sub-layer, the third sub-layer may include a multiple of the same elements included within the first sub-layer. In addition, the method may, in some embodiments, continue to blocks 43 a and 43 b such that the deposition of the third sub-film includes the termination of dispensing the deposition solution and/or the termination of rotating the substrate holder as similarly described above for the formation of the first sub-film.
  • In some cases, the third sub-layer may consist essentially of the same elements as included in the first sub-layer. In other embodiments, however, the first and third sub-layers may include some different elements. In either case, the third sub-layer may, in some embodiments, include a concentration of at least one element which is closer to a concentration of the same element with the first sub-layer than a concentration of the same element within the second sub-layer. In particular, the third sub-layer may include one or more elements having concentrations within the same ranges as employed within the first sub-layer. In this manner, the method may induce a periodic variation of an element concentration similar to but not limited to the configurations described in reference to FIGS. 2 a and 2 c. In other embodiments, the third sub-layer may include a substantially different concentration of an element included within the first and second sub-layers and, therefore, may be similar to the configuration described in reference to FIG. 2 b.
  • Following an alternative route, the method may include reiterating the steps of dispensing and removing the first deposition solution (described in reference to block 42 and 44) and the steps of dispensing and removing the second deposition solution (described in reference to block 48 and 50) to form additional sub-layers above the second sub-layer as shown in block 54 of FIG. 3. In addition or alternatively, the method may include consecutively dispensing and removing one or more additional deposition solutions different than the first and second deposition solutions to form one or more additional sub-layers above the second sub-layer as noted in block 56. In either case, the additional films may be configured to induce a periodic variation of an elemental concentration with the first and second sub-films similar to but not limited to the configurations described in reference to FIGS. 2 a-2 c.
  • In addition, the processes embodied by blocks 54 and 56 may be repeated any number of times to form the composite barrier layer. For example, the processes may be repeated to form up to approximately 100 sub-film layers. In some embodiments, a composite barrier layer of less than five sub-films may be advantageous to minimize the thickness of the ensuing barrier layer, but is not necessarily limited for such reasons. The thickness of each sub-film formed by the method described in FIG. 3 may be between approximately 0.5 nm and approximately 100 nm, or more specifically between approximately 0.5 nm and approximately 50 nm. Sub-films with larger or smaller thicknesses, however, may be used to form the composite barrier layer described herein. It is noted that the method may, in some embodiments, continue to blocks 43 a and 43 b for any number of the sub-films formed by blocks 54 and 56 and, therefore, the deposition of such sub-films may, in some embodiments, include the termination of dispensing the deposition solution and/or the termination of rotating the substrate holder as similarly described above for the formation of the first sub-film.
  • As shown by the dotted lines to block 46 after the progression of steps through block 50 in FIG. 3, the method may sometimes include establishing chamber process parameters different than those used for the formation of the previous sub-layer after the removal of the second deposition solution. In particular, FIG. 3 shows that the method may, in some embodiments, include block 46 subsequent to block 50 and prior to any of blocks 52, 54, 56 or 58. The incorporation of block 46 subsequent to the formation of the second sub-layer thus may include establishing chamber process parameters different than those used during the formation of the second sub-layer. In some embodiments, the chamber process parameters may further be different from the chamber process parameters used during the formation of the first sub-layer. In such cases, the sub-layer formed upon the second sub-layer may include different elemental concentrations than the first and second sub-layers. In yet other embodiments, the chamber process parameters may be substantially similar to the parameters used during the formation of the first sub-layer such that a composite barrier layer having alternating regions of comparatively greater and lesser concentrations of one or more elements may be formed.
  • As with the optional modification of chamber process parameters prior to the formation of the second sub-layer discussed above, the change of process parameters prior to the formation of additional sub-layers above the second sub-layer may be wholly or partially responsible for the variations of elemental concentrations between the additional sub-layers and the second sub-layer. As such, deposition solutions dispensed upon the microelectronic topography subsequent to the removal of the second deposition solution may include the same or different elemental compositions as the first and second deposition solutions. It is further noted that block 46 may be incorporated into the method directly prior to one or more of the individual additional sub-films referenced with respect to blocks 54 and 56. Reference arrows indicating such possibilities have been omitted from FIG. 3 to simplify the drawing.
  • In general, the process parameters for the deposition of the sub-films with respect to the method depicted in FIG. 3 (as well as the other methods described herein) may depend on the design specifications of the sub-films, such as but not limited to their elemental compositions and thicknesses, for example. Some exemplary process parameters, however, may include deposition solution flows between approximately 0.5 L/min and approximately 10 L/min and, in some embodiments, approximately 2 L/min. In addition, wafer rotating speeds during deposition may be between approximately 1 rpm and approximately 100 rpm and, in some embodiments, approximately 30 rpm. In some embodiments, wafer rotation speeds during the removal of the deposition solutions may be faster, such as between approximately 150 rpm and approximately 2000 rpm and, in some cases, approximately 300 rpm. In this manner, the processing time between deposition cycles may be minimized. For example, in some embodiments, the processing time between deposition cycles may be approximately 5 seconds. The process time to deposit the sub-films, on the other hand, may be between approximately 10 seconds and a few minutes, and more specifically, between approximately 10 seconds and approximately 30 seconds. Furthermore, the temperature at which the electroless deposition process occurs may be between approximately 20° C. and approximately 120° C., or more specifically, between approximately 55° C. and approximately 90° C. In general, larger or smaller temperatures and slower and/or faster deposition flows, wafer rotation speeds, and process cycles times may be used to form the composite barrier layer and, therefore, the methods described herein are not necessarily limited to the aforementioned values.
  • Tables 1 and 2 below outline exemplary compositions of deposition solutions and chamber process parameters associated with the methods described herein, particularly in reference to FIG. 3 but not necessarily so limited. In particular, Tables 1 and 2 outline exemplary compositions of deposition solutions and chamber process parameters for depositing sub-films of a composite barrier layer with a vertical variation, and in some embodiments a horizontal variation, of elemental concentrations. More specifically, Table 1 displays exemplary compositions of deposition solutions and chamber process parameters used to form sub-films of cobalt-tungsten-phosphorus (CoWP), cobalt-tungsten-phosphorus-boron (CoWPB), cobalt-molybdenum-phosphorus (CoMoP), cobalt-molybdenum-phosphorus (CoMoP), and cobalt-molybdenum-chromium-boron (CoMoCrB). Table 2, on the other hand, displays exemplary compositions of deposition solutions and chamber process parameters used to form sub-films of some of such cobalt alloys with relatively high concentrations of W and Mo, such as greater than approximately 25%, for example. Table 2 also displays exemplary compositions of deposition solutions and process parameters used to form ruthenium (Ru) sub-films.
    TABLE 1
    Exemplary Compositions of Deposition Solutions and Chamber Process Parameters
    used to form Films of CoWP, CoWPB, CoWB, CoMoB and CoMoCrB
    Compound CoWP CoWPB CoWB CoMoB CoMoCrB
    Cobalt sulfate heptahydrate 18 g/L 18 g/L 9-28 g/L 3-26 g/L 3-26 g/L
    Dimethylamine borane 0.6 g/L 0.8-6.0 g/L 0.6-6.0 g/L 0.6-6.0 g/L
    Hypophosphorous acid 8 g/L 14 g/L
    Citric acid monohydrate 57 g/L 57 g/L 42-84 g/L 28-84 g/L 28-84 g/L
    Pyrophosphoric acid  0-35.6 g/L 0-35.6 g/L
    Tungsten (VI) oxide 6 g/L 17 g/L 4-17 g/L
    Molybdenum (VI) oxide 0.01-0.45 g/L 0.01-0.45 g/L
    Chromium (III) chloride 0.001-5.0 g/L
    hexahydrate
    Boric acid 24 g/L 16 g/L 0-31 g/L 0-31 g/L 0-31 g/L
    TMAH pH up to 9.4 pH up to 9.4 pH 9.0-9.5 pH = 8.8-9.5 pH = 8.8-9.5
    Maleic acid 0-1.5 g/L 0-1.5 g/L 0-1.5 g/L
    HEDTA 0-2.0 g/L 0-2.0 g/L 0-2.0 g/L
    Temperature 90° C. 90° C. >70° C. >65° C. >65° C.
    Surfactant PPG, RE-610 PPG, RE-610 PPG, RE-610, PPG, RE-610, PPG, RE-610,
    Triton X-100 Triton X-100 Triton X-100
    Deposition rate 15-20 nm/min 15-25 nm/min 20-200 nm/min 20-250 nm/min

    PPG ≡poly-propylene glycol

    RE-610 ≡GAFAC RE-610, complex phosphate esters, manufactured by GAF Corp., New York, New York

    Triton X-100 ≡octylphenoxy polyethoxy ethanol, manufactured by Rohm and Haas, Philadelphia, Pa.
  • TABLE 2
    Exemplary Compositions of Deposition Solutions and Chamber Process
    Parameters used to form Films of CoWPB, CoWB, CoMoB, CoMoCrB and Ru
    CoWPB CoWB CoMoB CoMoCrB
    Compound (high W) (high W) (high Mo) (high Mo) Ru
    Cobalt sulfate heptahydrate 18 g/L 18 g/L 16 g/L 16 g/L
    Ruthenium nitroso chloride 2.36 g/L
    Dimethylamine borane 1.5 g/L 2 g/L 3.0 g/L 3.0 g/L
    Hypophosphorous acid 7 ml/L
    Citric acid monohydrate 84 g/L 84 g/L 63 g/L 63 g/L
    Tungsten(VI) oxide 17 g/L 17 g/L
    Molybdenum(VI) oxide 0.36 g/L 0.36 g/L
    Chromium(III) chloride 1 g/L
    hexahydrate
    Boric acid 15.5 g/L 15.5 g/L 15.5 g/L 15.5 g/L
    NH4OH 31 ml/L
    Hydroxylamine sulfate 0.75 g/L
    Hydrazine sulfate 23 g/L
    Maleic acid 0.38 g/L 1.5 g/L 1.5 g/L
    HEDTA 0.5 g/L 2.0 g/L 2.0 g/L
    EDTA 5 g/L
    Temperature 90° C. >80° C. >70° C. >70° C. >70° C.
    Surfactant PPG, RE-610 PPG, RE-610 PPG, RE-610 PPG, RE-610
    Deposition rate 15-35 nm/min 20-70 nm/min 20-100 nm/min 20-100 nm/min 20-40 nm/min

    PPG ≡poly-propylene glycol

    RE-610 ≡GAFAC RE-610, complex phosphate esters, manufactured by GAP Corp., New York, New York
  • Other noble catalytic metals, such as palladium (Pd) and rhodium (Rh) as well as different combinations of the elements stated above for liner layer 28 and cap layer 30 may additionally or alternatively be formed as sub-film layers for a composite barrier layer formed from the method described in reference to FIG. 3. For example, cobalt-molybdenum-chromium (CoMoCr) may be formed as a sub-film layer of a composite barrier layer. The solution composition for the formation of a CoMoCr layer may include similar concentrations of components as described for CoMoCrB without the inclusion of dimethlylamine borane. As such, the formation of a composite barrier layer described in reference to FIG. 3 is not restricted to the alloys listed in Tables 1 and 2. In addition, the compounds listed in Tables 1 and 2 may be combined for the formation of the same composite barrier layer. In particular, a compound listed in Table 2 may be formed as a sub-film over a sub-film formed from a compound listed in Table 1 or vice versa. For example, cobalt-tungsten-phosphorus having a relative high concentration of tungsten (CoWP high W) listed in Table 2 may be formed over a sub-film of CoWP listed in Table 1. In this manner, a composite barrier layer having a variation of tungsten may be formed. In yet other embodiments, any of the compounds listed in Tables 1 and/or 2 may be formed upon one another to form a composite barrier layer having a variation of elemental concentration.
  • Although not necessarily limited thereto, maleic acid and/or hydroxyethyl ethylenediamine triacetic acid (HEDTA) have been found to serve as effective complexing agents for the deposition of films including cobalt. Moreover, the inclusion of pyrophosphoric acid has been found to be advantageous for forming films including cobalt and molybdenum. In contrast, the inclusion of ethylenediamine triacetic acid (EDTA) has been found to be beneficial as a complexing agent for the deposition of films including ruthenium. Furthermore, the combination of ammonium hydroxide (NH4OH), hydroxlamine sulfate, and hydrazine sulfate has shown to be effective for depositing films including ruthenium. It is noted that the values for such components as well as all other component values listed in Tables 1 and 2 may be altered and still be used to produce sub-films for a composite barrier layer having variations of elemental concentrations. The values listed are merely exemplary.
  • An alternative or additional method used to form a barrier layer having a concentration variation of one or more elements involves an anneal process which diffuses one or more elements to a particular region of the film to create additional interfaces with which to block a diffusion channel. The anneal process may be conducted after the deposition of any layer deposited by electroless plating techniques. In some embodiments, the anneal process may be performed subsequent to the method described above in reference to FIG. 3 to provide additional variation of elemental compositions within a barrier layer. In other cases, the anneal process may be performed subsequent to the methods described below in reference to FIGS. 5, 6 and 12. In yet other embodiments, the anneal process may be performed subsequent to a conventional electroless deposition process. In any case, the anneal method may be particularly advantageous for forming a barrier layer having phosphorus diffused near the middle of the film such that two additional interfaces are formed with which to block a diffusion channel such as shown in FIGS. 2 c, for example. The anneal process, however, may be configured to diffuse other elements in addition or alternative to phosphorus. Furthermore, the anneal process may be configured to diffuse elements in regions of the substrate other than the middle.
  • A flowchart of an exemplary method which incorporates a diffusing anneal process is shown in FIG. 4. In particular, FIG. 4 illustrates a flowchart including block 60 in which a bulk metallic film is formed upon a microelectronic topography using an electroless plating process. The term “bulk metallic film” may generally refer to a film having a majority concentration of metallic elements and, therefore, may refer to a barrier layer formed with a combination of any of the elements mentioned above in reference to liner layer 28 and cap layer 30 of FIG. 1. As noted in block 60 of FIG. 4, the bulk metallic film may be formed having a bottom portion, a top portion, and an intermediate portion interposed between the bottom and top portions. In some embodiments, one of the top and bottom portions may include a higher concentration of at least one element than the intermediate portion and the other of the top and bottom portions. Other variations of element concentrations, however, may be formed for the bulk metallic layer and, therefore, the method is not necessarily restricted to the arrangement of elements among the particular regions of the film recited in block 60 of FIG. 4.
  • In some embodiments, the bulk metallic film may be formed upon and in contact with a metallic structure having a bulk elemental concentration different than the film, such as described for cap layer 30 in FIG. 1 being arranged upon and in contact with metallization structure 22. In such cases, the bottom portion of the bulk metallic film may include a higher concentration of at least one element than the intermediate portion and the top portion. In other embodiments, the bulk metallic film may be formed upon and in contact with a dielectric structure, such as described for liner layer 28 in FIG. 1 being arranged in contact with dielectric layer 24. In such cases, the top portion of the bulk metallic film may include a higher concentration of at least one element than the intermediate portion and the bottom portion.
  • Following the formation of the bulk metallic film, the method continues to block 62 as shown in FIG. 4. Block 62 includes annealing the microelectronic topography to induce diffusion of at least one element within the bulk metallic film such that the intermediate portion comprises a higher concentration of the at least one element than the bottom and top portions. In general, the anneal process may include exposing a bulk metallic film to a temperature between approximately 400° C. and approximately 1000° C. for any predetermined length of time. A duration of at least approximately 10 minutes may be advantageous for ensuring diffusion of a large percentage of the element to the intermediate portion of the bulk metallic film and, in some embodiments, the anneal process may be conducted for a time period up to approximately 2 hours. In some embodiments, the heated environment to which the bulk metallic film is exposed may include one or more elements having a propensity for diffusion into exposed portions of the bulk metallic film, such as phosphorus or boron, for example. In some cases, the element included in the heated environment may be the same as one of the elements diffused into the intermediate portion of the bulk metallic film by the anneal process. In other embodiments, the element included in the heated environment may not be one of the elements diffused into the intermediate portion of the bulk metallic film by the anneal process.
  • An alternative method for forming a barrier layer with a concentration variation of one or more elements is outlined in the flowchart shown in FIG. 5 and involves a balance of different deposition mechanisms activated during a single deposition process. The different deposition mechanisms may be induced by an additive to the deposition solution which slows the adsorption of one or more elements versus other elements in the solution. The slower adsorption rate invokes a deposition process having different mechanisms of film growth which are dependent upon the concentrations of different elements within the deposition solution. As a result, although two elements may be deposited as a mixture within a layer, the concentration of the elements throughout the layer will differ. An exemplary agent which may be used to slow the adsorption of one or more elements within a electroless plating solution may be but it not necessarily limited to pyrophosphoric acid as shown above in Table 1 for the formation of CoMoB and CoMoCrB.
  • The flowchart depicted in FIG. 5 includes block 66 noting the method includes exposing a microelectronic topography to a deposition solution. Such an exposure may include immersing the microelectronic topography within a bath of the deposition solution, dispensing the deposition solution upon the microelectronic topography, or a combination thereof. In addition, the method includes block 68 in which a first sub-film portion having a higher concentration of a first element than a second different element is formed by interfacial electroless reduction of the first element within the deposition solution until the second element reaches a certain concentration within the deposition solution. During such a step, the first element within the deposition solution is deposited at a faster rate than a second element by a mass-diffusion control mechanism. At the point in which the second element reaches a certain concentration within the deposition solution, the deposition mechanism may change such that the second component is deposited as a majority by a self-assembly deposition mechanism. In particular, FIG. 5 includes block 70 in which a second sub-film portion having a higher concentration of the second element than the first element is formed upon and in contact within the first sub-film portion by chemical adsorption. Such a deposition mechanism continues until the first element increases to a particular concentration within the deposition solution. In response thereto, the deposition process reverts back to the mass-diffusion control mechanism to deposit the first element as a majority within a third sub-film portion.
  • As shown in block 72 of FIG. 5, the deposition mechanisms may be reiterated to form a composite barrier layer having alternating regions of relatively higher concentrations of the first and second elements, respectively. The reiteration of the deposition mechanisms may be automatic by the inclusion of the aforementioned additive agent within the deposition solution and the fluctuation of elemental concentrations within the deposition solution. In this manner, the process is cyclic and is self-monitoring. It is noted that subsequent sub-film portions may have slightly different concentrations of the elements as compared to the first and second sub-film portions, but may generally follow an alternating sequence of having relatively greater concentrations of the different elements.
  • In general, the deposition mechanisms may be reiterated any number of times and, therefore, any number of sub-films may be formed by the technique outlined in FIG. 5. In other embodiments, process may be terminated upon the formation of the first and second sub-film portions and, therefore, block 72 may, in some embodiments, be omitted from the method. It is noted that the formation of the first and second sub-films as described in blocks 68 and 70, and any subsequent sub-films may, in some embodiments, include the termination of dispensing the deposition solution upon the microelectronic topography (if applicable) and/or the termination of rotating the substrate holder as similarly described above in regard to blocks 43 a and 43 b of FIG. 3. Such a sequence of steps may advantageously allow sub-films to be formed having substantially uniform elemental composition, uniform thickness, and substantially free of defects.
  • Barrier layer formation involving a balance of deposition mechanisms may be particularly applicable for forming barrier layers with a variation of molybdenum. In particular, molybdenum may be particularly amenable to slow adsorption rates relative to other elements in the presence of an additive agent, such as pyrophosphoric acid, for example. For instance, a barrier film including alternating regions of relatively higher concentrations of cobalt and molybdenum, respectively, may be deposited using the balanced deposition mechanism technique by having majority cobalt portions formed by interfacial electroless reduction and majority molybdenum portions formed by a chemical adsorption. In addition, molybdenum oxide may be particularly suitable for formation from a process of balanced deposition mechanisms. Other elements with molybdenum as well as other combinations of elements may also be formed as a barrier layer using the process of balanced deposition mechanisms and, therefore, the method is not necessarily limited to the fabrication of cobalt-molybdenum alloys or molybdenum oxide.
  • In addition or alternative to the methods described in reference to FIGS. 3-5, other methods for forming barrier layers having a variation of elemental concentrations may include controlling the process solution temperature on the substrate surface. More specifically, other methods may introduce a variation of solution temperature across a substrate to form a barrier film with a variation of elemental concentrations. Typically, the concentration of elements within an electrolessly deposited film is dependent on the temperature at which the deposition takes place. As such, introducing a variation of solution temperature across a substrate may induce a variation of elemental concentrations. One manner in which to control process solution temperature across a substrate is shown and described in reference to FIGS. 6-10. In particular, FIGS. 6-10 illustrate a flowchart outlining a method to control the flow pattern and, thus, the temperature variation of the solution across the substrate surface, systems configured to implement the method, and graphs outlining exemplary process parameters used administer the method. It is noted that the use of the methods and systems described in reference to FIGS. 6-10 are not necessarily mutually exclusive to other methods for forming barrier layers with a variation of elemental concentrations. Rather, the methods and systems may, in some embodiments, be used in combination with any of the methods described in reference to FIGS. 3-5 to form a barrier layer.
  • As shown in the flowchart depicted in FIG. 6, the method may include block 76 in which a microelectronic topography is positioned within an electroless plating chamber. The method further includes block 78 in which a deposition solution is dispensed at a plurality of locations extending different distances from a center of the microelectronic topography each at a different moment in time during an electroless plating process. In particular, when solution distribution in a first zone is completed, the dispensing arm of the electroless deposition chamber moves to another position (not necessarily adjacent to the first zone) and the solution is dispensed thereon. In addition to the placement of dispensing the deposition solution, the amount, rate and duration the solution is dispensed on the microelectronic topography may be controlled. Such a plurality of parameters may generally relate to the flow pattern of the solution across the wafer. Consequently, the method may include regulating a flow pattern of a solution to vary the temperature of the solution across the microelectronic topography and induce a variation of elemental concentrations within a deposited film. An exemplary system for controlling flow patterns of solutions across a substrate is described in more detail below in reference to FIGS. 7 and 8.
  • In addition to controlling the flow pattern of the deposition solution, the method may include altering the temperature of the dispensed solution such that different regions of the substrate are exposed to different solution temperatures. In some embodiments, the exemplary system described in reference to FIGS. 7 and 8 may be configured to dispense the solution at different temperatures across a substrate. In addition or alternatively, heating and/or cooling mechanisms within a substrate holder of the electroless plating chamber may be used to change the temperature of the deposition solution during plating. In any case, solution temperatures for electroless plating operations may generally be regulated between approximately 20° C. and approximately 120° C., or more specifically, between approximately 55° C. and approximately 90° C. Warmer or cooler solution temperatures may be used, however, depending of the fabrication specifications of the process. In some embodiments, the methods of controlling the process solution temperature and/or flow pattern across a substrate may induce a horizontal variation of elemental concentrations. In addition or alternatively, the methods may be used to induce a vertical variation of elemental concentrations. In particular, the method may include altering the flow pattern and/or temperature of the solution as the film is deposited, such that elemental concentrations within the film vary across regions of the microelectronic topography and/or vary with the thickness of the film.
  • Turning to FIG. 7, a top view of microelectronic topography 82 disposed within electroless plating chamber 80 is illustrated. As shown in FIG. 7, electroless plating chamber 80 includes substrate holder 84 supported by platen 86 and surrounded by chamber walls 88. The electroless plating chamber further includes dispensing arm 90 for supplying a deposition solution onto microelectronic topography 82, which resides upon substrate holder 84. The cover of electroless plating chamber 80 is not shown in order to illustrate the alternate positions of dispensing arm 90 relative to microelectronic topography 82. As shown by the dotted line outlines of dispensing arm 90 in FIG. 7, electroless plating chamber 80 may be configured to position dispensing arm 90 above a plurality of locations of microelectronic topography 82. More specifically, dispensing arm 90 may be connected to rotary drive mechanism 94 for positioning the suspended end of dispensing arm 90 among positions 92 a-92 d with respect to fixed axis 96.
  • In this manner, electroless plating chamber 80 may be configured to position dispensing arm 90 over a plurality of locations extending different distances from a center of microelectronic topography 82 each at a different moment in time during an electroless plating process. More specifically, positions of dispensing arm 90 may be controlled for delivering a deposition solution to a specific area of microelectronic topography 82. In embodiments in which substrate holder 84 is configured to rotate microelectronic topography 82 during processing, such an array of different radial positions may advantageously offer full coverage of the microelectronic topography. In particular, solution dispensed from dispense arm 90 may be distributed to cover different radial rings of microelectronic topography 82, which collectively cover the entirety of the topography. Exemplary wafer rotation speed may be between approximately 1 rpm and approximately 100 rpm and, in some embodiments, approximately 30 rpm, but faster or slower rotations speeds may be used. It is noted that the different areas of the microelectronic topography upon which the solution is dispensed by dispense arm 90 may overlap to ensure coverage of the entirety of the topography during processing, but generally the areas cover different regions of the topography and, therefore, are distinct.
  • Although FIG. 7 illustrates dispensing arm 90 positioned in four different locations, electroless plating chamber 80 may be configured to position dispensing arm 90 at any number of different locations greater or less than four. In some cases, positioning dispensing arm 90 in nine different positions has shown to provide sufficient coverage of a deposition solution over an entirety of a microelectronic topography, but the methods and systems described herein are not necessarily so limited. In addition, although positions 92 a-92 d are illustrated with respect the same radial line of microelectronic topography 82, dispense arm 90 may be positioned along different radial lines of microelectronic topography 82. Furthermore, positions 92 a-92 d are not restricted to being evenly spaced with respect to each other. Rather, positions 92 a-92 d may be spaced apart by different distances. Furthermore, dispensing arm 90 may be located at a position not overlying microelectronic topography 82 in some embodiments, as shown by position 92 d in FIG. 7. Although not necessary, such a position of dispense arm 90 may be advantageous for loading microelectronic topography 82 in and out of electroless plating chamber 80. The program instructions used to regulate the distribution of solution from dispense arm 90 described in more detail below may be configured to inhibit solution flow from the dispense arm in such a position.
  • In some embodiments, the positioning of dispense arm 90 may be programmed through a computer system coupled to or incorporated within electroless plating chamber 80. A schematic diagram of an exemplary computer system is illustrated in FIG. 8. As shown in FIG. 8, computer system 100 includes processor 106 and storage medium 102, which in turn includes program instructions 104. The storage medium may include any device for storing program instructions, such as a read-only memory, a random access memory, a magnetic or optical disk, or a magnetic tape. In general, input 28 may be transmitted to processor 106, which may be configured to execute program instructions 104 within storage medium 102 to provide output 109 to electroless plating chamber 80. In some embodiments, program instructions 104 may be configured to exclusively regulate the position of dispense arm 90. In other embodiments, program instructions 104 may also include program instructions for regulating other facets of electroless plating chamber 80, such as but not limited to loading operations, drying operations, and pre-deposition or post-deposition cleaning operations.
  • As shown in FIG. 7, dispense arm 90 may, in some embodiments, include a plurality of different sized nozzles 99. In such cases, program instructions 104 may be configured to selectively dispense a deposition solution through distinct sets of the plurality of different sized nozzles with respect to plurality of positions 92 a-92 c. More specifically, program instructions 104 may be configured to selectively dispense a deposition solution through one or more of nozzles 99 at each of positions 92 a-92 c. In some embodiments, the selected nozzles may differ among all of the positions. In other embodiments, the selection of nozzles may differ for less than all of the positions. In any case, in light of the such adaptations of program instructions 104, block 78 of the method described in reference to FIG. 6 may, in some embodiments, include dispensing the deposition solution through a first nozzle above one of the plurality of locations of the microelectronic topography and may further include dispensing the deposition solution through a second different sized nozzle above another of the plurality of locations.
  • Since nozzles 100 are different sizes, different amounts of solution may be deposited at different locations upon microelectronic topography 82. In addition, different size areas of microelectronic topography 82 may be exposed to the deposition solution at a given time. In general, the diameters of nozzles 100 may be significantly smaller than a wafer diameter (e.g., between approximately ⅛ inch and approximately 1 inch, although other sizes may be used) such that only a portion of wafer is exposed to deposition solution thus creating an area with high density of nucleation sites. In yet other embodiments, dispense arm 90 may not include a plurality of different sized nozzles and, therefore, such an adaptation may be omitted from the methods and systems described in reference to FIGS. 6-8.
  • In addition or alternative to selectively dispensing a deposition solution through different sized nozzles, program instructions 104 may be configured to vary the rate and/or duration at which a deposition solution is dispensed. In this manner, the method, system and program instructions described herein may be configured to vary the amount of solution dispensed upon microelectronic topography 82 in alternative manners than described for varying the distribution of a solution through different sized nozzles. For example, the method described above in reference to FIG. 6 may, in some embodiments, include dispensing the deposition solution at a first rate and/or duration above one the plurality of locations of the microelectronic topography and dispensing the deposition solution at a second different rate and/or duration above another of the plurality of locations of the microelectronic topography. In some embodiments, the selected rate and/or duration may differ among all of the positions. In other embodiments, the selected rate and/or duration may differ for less than all of the positions. In general, deposition solution flow rate may vary between approximately 0.5 L/min and approximately 10.0 L/min and, more specifically between approximately 2.0 L/min and approximately 3.0 L/min. Exemplary durations of flow may generally be between 10 seconds and a few minutes and more specifically between, approximately 30 seconds and approximately 60 seconds, but longer or short durations may be employed. In addition, larger or smaller flow rates may be used.
  • In any case, the selected rates of flow may induce laminar flow of the deposition solution in some embodiments. Laminar flow may be advantageous in some cases, since it is less likely to cause bubbles on the surface of microelectronic topography 82. The occurrence of bubbles upon a microelectronic topography during an electroless deposition process often causes undesirable random non-uniformity in deposition thickness. In other cases, however, the selected rates of flow may induce turbulent flow of the deposition solution. In some embodiments, program instructions 104 may be configured to pulse a deposition solution through dispense arm 90 and, in some cases, pulse a deposition solution at different frequencies with respect to different regions of microelectronic topography 82. Furthermore, program instructions 104 may, in some embodiments, be configured to vary the angle of the line of trajectory from dispense arm 90 such that the solution is not limited to being dispensed perpendicular to the surface of microelectronic topography 82. Varying the angle of the solution trajectory may, in some cases, be particularly advantageous for filling narrow holes within a topography.
  • As shown in FIG. 7, dispense arm 90 may, in some embodiments, include thermocouple 98. In such embodiments, the method, system and program instructions described in reference to FIGS. 6-8 may be configured to dispense deposition solutions at different temperatures with respect to the plurality of locations of dispense arm 90 during processing. In particular, the method described in reference to FIG. 6 may, in some embodiments, include dispensing the deposition solution upon one of the plurality of locations of the microelectronic topography at a first temperature and may further include dispensing the deposition solution upon another of the plurality of locations of the microelectronic topography at a second distinct temperature. In this manner, the method, system and program instructions described in reference to FIGS. 6-8 may introduce solution temperature variation across a microelectronic topography in some embodiments. In particular, a thin layer of the process liquid on a substrate surface generally has low thermal capacity, which allows the temperature of a solution to reduce quickly. Varying the timing at which the solution is distributed as well as varying the temperature at which the solution is dispensed relative to such time-varying distribution may allow the solution temperature across the microelectronic topography to be controlled either for a variation of temperature or temperature uniformity.
  • It is noted that in other embodiments the configuration of the method, system and program instructions to dispense a solution at varying temperatures with respect to different regions of a microelectronic topography may aid in introducing solution temperature uniformity across the microelectronic topography. In particular, since a solution is dispensed at different locations and different times across a topography using the configurations described in reference to FIGS. 6-8, regions of the solution may evaporate at different times affecting the temperature of the solution at such regions. The use of dispense arm 90 and program instructions 104, however, may be optimized to account for such fluctuations among regions of the solution to produce solution temperature uniformity across a microelectronic topography in some embodiments. For example, FIG. 9 illustrates the temperature of a deposition solution with respect to three zones of a microelectronic topography, each respectively corresponding to positions 92 a-92 c of dispense arm 90. As shown in FIG. 9, the temperature of the solution varies at each of the zones due to dispensing the solution at different times with respect to the zones. In particular, while the deposition process at zone 2 is active, the temperature of the solution at zone 1 may drop according to E*H=F*T*S, where E=evaporation rate, H=heat of evaporation, F=solution flow rate, T=solution temperature drop per angle/cycle and S=specific heat of the solution. Collectively, however, the variations of solution temperatures across the zones produce a uniform average temperature across the microelectronic topography.
  • Although solution temperature uniformity may be contrary to the aforementioned objective of forming a film with a variation of elemental concentration, the method, system and program instructions described in reference to FIGS. 6-8 are not necessarily limited to forming a film with a variation of elemental concentration. In particular, the method, system and program instructions may be used to form portions or an entirety of a barrier layer without variations of elemental concentration. In yet other embodiments, one of the methods described in reference to FIGS. 3-5 may be used in combination with the method, system and program instructions described in reference to FIGS. 6-8 to induce a variation of elemental concentration with a barrier layer while incurring solution temperature uniformity across a microelectronic topography.
  • Consequently, program instructions 104 for positioning dispense arm 90 may be configured to provide uniform or non-uniform heat density of the deposition solution across microelectronic topography 82 by regulating dispensing times across different positions. As a result, films deposited using the method, system and program instructions described in reference to FIGS. 6-8 may formed with a uniform thickness profile or with a varying thickness profile. As noted above, solution temperature during an electroless deposition process has a direct effect on the thickness uniformity of the resulting film. Since the method, system and program instructions discussed in reference to FIGS. 6-8 may be configured to induce variation or uniformity of solution temperature across a microelectronic topography, the method, system and program instructions may be configured to induce variation or uniformity with regard to a thickness of a film deposited by electroless deposition techniques.
  • Regardless of whether the method, systems and program instructions described in reference to FIGS. 6-8 induce solution temperature uniformity or variation across a microelectronic topography, the temperature fluctuations among the zones may change mechanism of film growth from mass diffusion limited to reduction reaction rate limited, advantageously producing an amorphous (nanocrystalline) layer with low density of pinholes or growth defects as well as lower minimum film thickness and better surface roughness. Exemplary amorphous layers resulting from changes of film growth mechanisms during an electroless plating process are shown in FIGS. 10 b and 10 c and are compared to a layer shown in FIG. 10 a formed from a conventional electroless plating process. In particular, FIG. 10 a illustrates a partial cross-sectional view of an exemplary film deposited first by a reduction reaction rate limited mechanism of film growth (denoted by relatively small granules 110) and afterward by mass diffusion limited mechanism of film growth (denoted by relatively long and narrow upright granules 112). Such a film structure is typical of conventional electroless plating techniques in which a deposition solution is deposited continuously at one location and at a single temperature throughout the deposition process.
  • FIG. 10 b illustrates an exemplary cross-section of a film deposited exclusively by a reduction reaction rate limited mechanism of film growth (denoted by relatively small granules 114). Such film structure may be formed in embodiments in which the temperature of the solution continuously varies during the deposition of the film. FIG. 10 c illustrates an exemplary cross-section of a film deposited by mechanisms of film growth which switch between reduction reaction rate limited and mass diffusion limited (denoted by the mixture of relatively small granules 116 and relatively long and narrow upright granules 118). Such a film structure may be formed in embodiments in which the temperature of the solution varies at some periods and at other times is substantially constant.
  • As shown in FIGS. 10 b and 10 c, films formed partially or wholly by a reduction reaction rate limited mechanism of film growth include comparatively less gaps than the film formed exclusively by a mass diffusion limited mechanism of film growth depicted in FIG. 10 a. As a result, a film deposited by varying the solution temperature profile and/or solution flow rate may advantageously have less pin-holes and in-film growth defects. In addition, such films may be smoother. In particular, films formed partially or wholly by a reduction reaction rate limited mechanism of film growth may have a surface roughness of approximately 0.5 nm RMS, which is significantly smoother than films having a surface roughness of approximately 2.0 RMS formed exclusively by a mass diffusion limited mechanism of film growth. Furthermore, smaller and fewer gaps within a deposited barrier layer may further aid in inhibiting diffusion of elements therethrough. More specifically, a barrier layer having smaller and few gaps may hinder diffusion of elements from adjacent structures, such as described in reference to FIG. 1 for the configurations of liner layer 28 and cap layer 30 adjacent to metallization structure 22. Moreover, smaller and fewer gaps may inhibit hydrogen atoms from lodging with the deposited film, reducing occurrences of hydrogen outgassing during subsequent processing which may in turn affect the formation of features overlying the film. In addition, smaller and few gaps allow a denser film to be formed and, as a result, a thinner film may be deposited during a given processing time as compared to films formed by conventional electroless deposition processes.
  • An exemplary set of dispensing times and sequence of positions for the distribution of a deposition solution upon a microelectronic topography is noted in Table 3. FIG. 11 illustrates a graph of the total processing time versus zone location data taken from Table 3. As shown in Table 3 and FIG. 11, an exemplary sequence of steps may extend across 9 zones of a microelectronic topography with increasingly longer dispense times programmed for Zone 1 thru Zone 9. Such a sequence and duration of dispenses may be advantageous for negating the edge effect in some embodiments, such as in cases in which Zone 1 refers to the most central zone on the microelectronic topography, Zone 9 refers to the edge most zone on the microelectronic topography, and the other zones are interposed therebetween. Films resulting from such a configuration may have substantially uniform thickness across the microelectronic topography or may have greater thicknesses near the edge of the wafer as compared to near the center of the wafer.
  • As shown in Table 3, the steps may, in some embodiments, be segregated into distinct sets of steps. In particular, steps 1-11 may cycle through each of the zones with a different sequence and dispensing times than steps 12-20. In this manner, a method for depositing the film may include dispensing the deposition solution in a first sequence of steps among the plurality of locations to form a first sub-film across a surface of the microelectronic topography. In addition, the method may include dispensing the deposition solution in a second different sequence of steps among the plurality of locations to form a second sub-film across the microelectronic topography and upon the first sub-film. Although the dispensing times and sequence of steps depicted in Table 3 may be advantageous for some configurations of a microelectronic topography, the dispensing times and sequence of steps may vary from those depicted in Table 3. In particular, such a display of data is merely exemplary.
    TABLE 3
    Sequence of Dispensing Times (in seconds) per Zone of a Microelectronic
    Topography for an Electroless Plating Process
    Zone Zone Zone Zone Zone Zone Zone Zone Zone
    Step
    1 2 3 4 5 6 7 8 9
    1 8
    2 6
    3 3
    4 1
    5 1
    6 1
    7 1
    8 3
    9
    10 5
    11 8
    12 1
    13 1
    14 1
    15 2
    16 1
    17 3
    18 3
    19 6
    20 5
  • An alternative method and system for controlling process solution temperature on a microelectronic topography are shown in FIG. 12 and 13. In particular, FIG. 12 depicts a flowchart of an exemplary method and FIG. 13 illustrates an exemplary system in which a gas is distributed over a plate disposed above a substrate holder configured for supporting a microelectronic topography. As will be described in more detail below, the method and system allows portions of a deposition solution in select regions of the microelectronic topography to evaporate (i.e., remove water from the deposition solution) a faster rate than other regions, inducing solution temperature uniformity or variation across the topography. In general, removing water from an electroless plating solution will lower the temperature of the solution. In cases in which a solution temperature variation is induced, the evaporation of the solution during processing may produce a horizontal variation of elemental concentrations and, in some cases, a vertical variation of elemental concentrations as well. In addition or alternative to evaporating select regions of the microelectronic topography, the gas may be configured react with the surface of the microelectronic topography such that contaminants (i.e., debris and/or oxidized metal) may be removed from the surface topography. Furthermore, the gas may be additionally or alternatively configured to regulate concentrations of other gases within the electroless plating chamber.
  • As shown in block 120 of FIG. 12, the method may include exposing a microelectronic topography arranged within an electroless plating chamber to a deposition solution. Such an exposure may include immersing the microelectronic topography within a bath of the deposition solution, dispensing the deposition solution upon the microelectronic topography, or a combination thereof. An exemplary configuration of an electroless plating chamber which may be used for the method depicted in FIG. 12 is illustrated in FIG. 13. In particular, electroless plating chamber 130 includes substrate holder 132 upon which a microelectronic topography may be supported. Suspended above substrate holder 132 is dispense arm 134 and plate 136. In some embodiments, dispense arm 134 may include the configurations described in reference to FIGS. 6-8 and, therefore, may be moveable to multiple positions above substrate holder 132. In other embodiments, however, dispense arm 134 may be fixed. As such, the configurations of electroless plating chamber 130 of FIG. 13 and electroless plating chamber 80 of FIG. 7 may be combined or may be mutually exclusive. In alternative embodiments, the method described in FIG. 12 may be used with an electroless plating chamber having a shower head for dispensing a deposition solution. In other embodiments, the method may be used with an electroless plating chamber which does not include solution dispense arm or shower head, but rather is configured such that a microelectronic topography may be immersed within a deposition solution.
  • In any case, the deposition method may include block 122 as shown in FIG. 12 in which a gas is introduced into the electroless deposition chamber above a plate suspended above the microelectronic topography. Such a step may be performed within electroless plating chamber 130 by introducing a gas into gas inlet 138 above plate 136. In some embodiments, electroless plating chamber 130 may further include outlet 139 by which to remove the deposition solution and byproduct gases as shown in FIG. 13. In some cases, the gas introduced into electroless plating chamber 130 may include nitrogen and, in some cases, may be specifically the diatomic form of nitrogen (i.e., N2). Such a gas may be particularly applicable for increasing the evaporation rage of the deposition. Other gases which may be applicable for increasing the evaporation rate of the deposition solution, however, may also or alternatively be used. In some embodiments, the gas may be configured to be reactive with the surface of the microelectronic topography such that contaminants (i.e., debris and/or oxidized metal) may be removed from the surface topography. For instance, hydrogen gas or a fluorinated carbon gas at a substantially high temperature, such as greater than 450° C., for example, may be introduced into the chamber to react with the surface of the microelectronic topography. Furthermore, the gas may be additionally or alternatively configured to regulate concentrations of other gases within the electroless plating chamber.
  • It is noted that the sequence of steps associated with blocks 120 and 122 is not necessarily limited to the order shown in FIG. 12. In particular, the step of introducing a gas into the electroless plating chamber may sometimes be initiated subsequent to the step of exposing the microelectronic topography to a deposition solution, but the method is not necessarily so restricted. In some case, the step of introducing a gas into the electroless plating chamber may alternatively be initiated prior to the step of exposing the microelectronic topography to a deposition solution. In other cases, the step of introducing a gas into the electroless plating chamber may be initiated at substantially the same time as the step of exposing the microelectronic topography to a deposition solution.
  • In any case, the method in FIG. 12 continues to block 124 in which the gas is distributed to regions extending above one or more discrete portions of the microelectronic topography. In some embodiments, the distribution of the gas to such regions may be used to invoke evaporation of the deposition solution at the one or more discrete portions of the microelectronic topography. For instance, the one or more discrete portions may include the peripheral edge of the microelectronic topography. In particular, gas introduced above plate 136 may be directed to the outer edges of plate 136 down to the peripheral edges of the microelectronic topography. Such a route for the gas may be particularly advantageous for negating the edge effect in some embodiments. Films resulting from such a route may have substantially uniform thickness across the microelectronic topography or may have greater thicknesses near the edge of the wafer as compared to near the center of the wafer.
  • In some cases, plate 136 may be a disc having a diameter slightly smaller than the microelectronic topography being processed. For example, plate 136 may have a diameter between approximately 150 mm and approximately 190 mm for processing 200 mm microelectronic wafers. Alternatively, plate 136 may have a diameter between approximately 250 mm and approximately 290 mm for processing 300 mm microelectronic wafers. Discs of larger or smaller diameters, however, may be used for either sized wafer, depending on the fabrication specifications of the ensuing device. In some cases, plate 136 may not be a disc and, thus, may be alternatively formed of a different shape including but not limited to a square or a rectangle. Regardless of its shape, plate 136 may, in some embodiments, include holes such that portions in addition or alternative to the peripheral edges of a microelectronic topography may be exposed to the gas and, thus, have portions of a deposition solution thereon evaporate at a faster rate than other portions of the topography. The holes may be of any size and shape necessary for exposing a desired area of the microelectronic topography to the gas introduced through gas inlet 138.
  • In some embodiments, the process of distributing the gas to regions of the microelectronic topography may include rotating plate 136. Such rotation may advantageously direct gas to the edge and/or openings within plate 136 down to the microelectronic topography. In some embodiments, plate 136 maybe rotated in the same direction as substrate holder 132 as shown in FIG. 13. In other embodiments, plate 136 may be rotated in the opposite direction as substrate holder 132. In either case, substrate holder 132 and plate 136 may be independently configured to rotate clockwise and/or counterclockwise. An exemplary range of rotation speed for plate 136 may be between approximately 100 rpm and approximately 500 rpm, although faster or slower rates may be employed. In some embodiments, plate 136 and substrate holder 132 may be rotated at the same speed. In other embodiments, however, plate 136 and substrate holder 132 may be rotated at different speeds. In either of such cases, the rate of rotation of plate 136 may, in some embodiments, be optimized with respect to wafer rotation speed and solution flow rate in order to induce solution temperature variation or uniformity across the microelectronic topography.
  • A plan view of a test wafer having a film with regions of different elemental concentrations and thicknesses is shown in FIG. 14. In particular, a plan view of test wafer 140 is illustrated with multiple zones of different material thicknesses and elemental concentrations deposited using any of the methods and systems described above in reference to FIGS. 3-13. More specifically, FIG. 14 illustrates test wafer 140 with an electrolessly deposited film including annulus areas (denoted as zones 1-9), each having comparatively different thicknesses and comparatively different elemental concentrations. Zones 1-9 are generally formed separately and in any order. In some embodiments, zones 1-9 may be formed by deposition of the annulus close to wafer edge, followed by deposition of a layer of another thickness within an adjacent annulus closer to wafer center, and so on. Although FIG. 14 illustrates test wafer 140 having nine zones, the test wafer is not necessarily so limited. In particular, test wafer 140 may include any plurality of zones. In addition, test wafer 140 is not limited to having zones 1-9 of substantially similar widths. As such, in some embodiments, zones 1-9 may be formed with different widths.
  • In some embodiments, zones 1-9 may be configured incrementally with respect to their thicknesses as shown in the exemplary partial cross-sectional view of test wafer 140 in FIG. 15 a. In particular, zone 1 may be configured to have the thinnest profile, zone 9 may include the thickest profile, and zones 2-8 may include incremental thicknesses therebetween. Exemplary thicknesses for the zones may be approximately 100 nm at zone 9 of, approximately 30 nm at zone 1, thicknesses ranging from approximately 35 nm to approximately 95 nm at zones 2-8. Larger or smaller thicknesses, however, may be employed for any or all of zones 1-9, depending on the design specifications of the ensuing device. As shown in another exemplary cross-sectional profile of test wafer 140 in FIG. 15 b, the thickness of zones 1-9 may not vary incrementally in some embodiments. Such a pattern layout is feasible since each zone is formed separately and the thickness of each region is dependent on the selective distribution of the deposition solution. In such cases, the thicknesses of zones 1-9 may vary between approximately 30 nm and approximately 100 nm, but larger or smaller thicknesses may be employed. Due to the methods and systems described herein, variations of elemental concentrations may be incorporated into zones 1-9.
  • Similar to the variations of thicknesses, the variation of elemental concentration may vary incrementally through zones 1-9 or may vary randomly. Furthermore, the variation of elemental concentration may be independent of the incremental alignment or randomness of thicknesses within the zones. As such, zones 1-9 in either of the configurations of test wafer 140 illustrated in FIGS. 15 a and 15 b may include a random variation of elemental concentrations, an incrementally increasing concentration of elements or an incrementally decreasing concentration of elements. In any case, test wafer 140 may generally be used for calibration of thin film metrology equipment such as acoustic wave, X-ray fluorescence, sheet resistance, RBS, and such. Conventional metrology calibrations typically utilize multiple test wafers. A plurality of calibration wafers, however, is often costly due to the costs for both the wafers themselves and for lost production time on manufacturing tools due to qualification and calibration downtime. A single calibration wafer, such as test wafer 140, will allow significant cost advantages.
  • It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to provide a system and methods involving electroless plating processes for the formation of metallic layers and structures within microelectronic topographies. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. For example, although the process chambers and methods provided herein are frequently described in reference to the deposition of barrier layers, the system and methods are not necessarily restricted to such operations. In particular, the methods and systems described herein may be used for the deposition of other types of layers and as well as other operations such as but not limited to cleaning and drying operations. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments. Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the invention may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this description of the invention. Changes may be made in the elements described herein without departing from the spirit and scope of the invention as described in the following claims.

Claims (43)

1. A microelectronic topography, comprising:
a structure having a bulk concentration of a first element disposed throughout the structure; and
a film consisting essentially of one or more elements different than the first element formed in contact with the structure, wherein the film has periodic successions of regions each comprising:
at least one region with a concentration of a second element greater than a set amount; and
at least one region with a concentration of the second element less than the set amount.
2. The microelectronic topography of claim 1, wherein the periodic successions of regions comprise sub-layers vertically arranged within the film.
3. The microelectronic topography of claim 1, wherein the periodic successions of regions comprise regions horizontally arranged within the film.
4. The microelectronic topography of claim 1, wherein the film is arranged upon the structure.
5. The microelectronic topography of claim 1, wherein the film is arranged beneath the structure.
6. The microelectronic topography of claim 1, wherein the first element comprises copper, and wherein the second element comprises cobalt.
7. The microelectronic topography of claim 6, wherein a variation of the concentrations of cobalt among the periodic successions of regions is between approximately 10% and approximately 30%.
8. The microelectronic topography of claim 1, wherein the second element comprises phosphorus, and wherein a variation of the concentrations of phosphorus among the periodic successions of regions is between approximately 3% and approximately 12%.
9. The microelectronic topography of claim 1, wherein the second element comprises boron, and wherein a variation of the concentrations of boron among the periodic successions of regions is between approximately 1% and approximately 2%.
10. The microelectronic topography of claim 1, wherein the second element comprises molybdenum, and wherein a variation of the concentrations of molybdenum among the periodic successions of regions is between approximately 1% and approximately 50%.
11. The microelectronic topography of claim 1, wherein the second element is selected from a group consisting of hydrogen, tungsten, chromium, nickel, rhodium, ruthenium and palladium.
12. The microelectronic topography of claim 1, wherein the one or more elements comprise cobalt, tungsten, and at least one of boron and phosphorus.
13. The microelectronic topography of claim 1, wherein the one or more elements comprise cobalt, molybdenum, and at least one of chromium and boron.
14. A microelectronic topography, comprising:
a conductive structure having a bulk concentration of copper disposed throughout the structure; and
a film formed in contact with the conductive structure comprising alternating regions of comparatively greater and lesser concentrations of cobalt.
15. The microelectronic topography of claim 14, wherein the alternating regions further comprise comparatively greater and lesser concentrations of one or more elements.
16. The microelectronic topography of claim 14, wherein the one or more elements comprise molybdenum.
17. A method for processing a microelectronic topography, comprising:
positioning the microelectronic topography within an electroless plating chamber;
dispensing a first deposition solution upon the microelectronic topography to form a first sub-film within the electroless plating chamber;
removing the first deposition solution from the electroless plating chamber subsequent to the formation of the first sub-film; and
dispensing a second deposition solution upon the microelectronic topography subsequent to the removal of the first deposition solution to form a second sub-film upon and in contact with the first sub-film, wherein the second sub-film comprises multiple elements included within the first sub-film.
18. The method of claim 17, wherein the second sub-film consists essentially of the same elements as included in the first sub-film.
19. The method of claim 17, wherein a concentration of at least one of the elements within the second sub-film differs from a concentration of the same element within the first sub-film.
20. The method of claim 17, further comprising establishing chamber process parameters different than those used during the formation of the first sub-film prior to the step of dispensing the second deposition solution.
21. The method of claim 20, wherein the first and second deposition solutions comprise substantially equal compositions.
22. The method of claim 17, wherein the first and second deposition solutions comprise substantially different compositions.
23. The method of claim 17, wherein at least one of the first and second deposition solutions comprises maleic acid and a component comprising cobalt.
24. The method of claim 17, wherein at least one of the first and second deposition solutions comprises pyrophosphoric acid and a component comprising cobalt.
25. The method of claim 17, wherein at least one of the first and second deposition solutions comprise hydroxyethyl ethylenediamine triacetic acid and a component comprising cobalt.
26. The method of claim 17, wherein at least one of the first and second deposition solutions comprise ammonium hydroxide and a component comprising ruthenium.
27. The method of claim 17, further comprising terminating and subsequently resuming the step of dispensing the first deposition solution during the formation of the first sub-film.
28. The method of claim 17, further comprising:
rotating a substrate holder upon which the microelectronic topography is positioned within the electroless plating chamber; and
terminating and subsequently resuming the step of rotating the substrate holder during the formation of the first sub-film.
29. The method of claim 17, further comprising:
removing the second deposition solution from the electroless plating chamber subsequent to the formation of the second sub-film; and
repeating the steps of dispensing and removing the first deposition solution subsequent to the removal of the second deposition solution to form a third sub-film upon and in contact with the second sub-film.
30. The method of claim 29, wherein a concentration of at least one of the elements within the third sub-film is closer to a concentration of the same element within the first sub-film than a concentration of the same element within the second sub-film.
31. The method of claim 29, further comprising establishing chamber process parameter settings different than those used during the formation of the first sub-film prior to the step of repeating the steps of dispensing and removing the first deposition solution.
32. The method of claim 17, further comprising:
removing the second deposition solution from the electroless plating chamber subsequent to the formation of the second sub-film; and
reiterating the steps of dispensing and removing the first deposition solution and the steps of dispensing and removing the second deposition solution subsequent to the formation of the second sub-film to form additional sub-films above the second sub-film.
33. The method of claim 17, further comprising:
removing the second deposition solution from the electroless plating chamber subsequent to the formation of the second sub-film; and
consecutively dispensing and removing one or more additional deposition solutions different than the first and second deposition solutions subsequent to the removal of the second deposition solution to form one or more additional sub-films above the second sub-film.
34. A method for processing a microelectronic topography, comprising:
forming a bulk metallic film upon the microelectronic topography using an electroless plating process, wherein the bulk metallic film comprises a bottom portion, a top portion, and an intermediate portion interposed between the bottom and top portions, wherein one of the top and bottom portions comprises a higher concentration of a first element than the intermediate portion and the other of the top and bottom portions; and
annealing the microelectronic topography to induce diffusion of the first element within the bulk metallic film such that the intermediate portion comprises a higher concentration of the first element than the bottom and top portions.
35. The method of claim 34, wherein the step of forming the bulk metallic film comprises forming the bulk metallic film upon and in contact with a metallic structure having a bulk elemental concentration different than the film, and wherein the bottom portion of the bulk metallic film comprises a higher concentration of the first element than the intermediate portion and the top portion prior to the step of annealing the microelectronic topography.
36. The method of claim 34, wherein the step of forming the bulk metallic film comprises forming the bulk metallic film upon and in contact with a dielectric structure, and wherein the top portion of the bulk metallic film comprises a higher concentration of the first element than the intermediate portion and the bottom portion prior to the step of annealing the microelectronic topography.
37. The method of claim 34, wherein the first element comprises phosphorus.
38. The method of claim 34, wherein the step of annealing the microelectronic topography further comprises diffusing one or more other elements through the bulk metallic film such that the intermediate portion comprises a higher concentration of the one or more elements than the bottom and top portions.
39. The method of claim 34, wherein the step of annealing the microelectronic topography comprises exposing the microelectronic topography to a heated environment comprising a second element different from the first element.
40. A method for depositing a film upon a microelectronic topography, comprising:
exposing the microelectronic topography to a deposition solution;
forming a first sub-film portion by interfacial electroless reduction of a first element within the deposition solution until a second different element reaches a certain concentration within the deposition solution, wherein the first sub-film comprises a higher concentration of the first element than the second element;
forming a second sub-film portion upon and in contact with the first sub-film portion by chemical adsorption until the first element increases to a particular concentration within the deposition solution, wherein the second sub-film comprises a higher concentration of the second element than the first element; and
reiterating the steps of forming the first and second sub-film portions to form a composite film comprising concentration variations of the first and second elements.
41. The method of claim 40, wherein the first element is cobalt and the second element is molybdenum.
42. The method of claim 40, wherein the first element is oxygen and the second element is molybdenum.
43. The method of claim 40, wherein the deposition solution comprises an agent to slow the adsorption of the second element during the step of forming the second sub-film portion.
US11/199,620 2004-08-09 2005-08-09 Methods for forming a barrier layer with periodic concentrations of elements and structures resulting therefrom Abandoned US20060029833A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US11/199,620 US20060029833A1 (en) 2004-08-09 2005-08-09 Methods for forming a barrier layer with periodic concentrations of elements and structures resulting therefrom
US13/533,692 US20120263869A1 (en) 2004-08-09 2012-06-26 Methods for Forming a Barrier Layer with Periodic Concentrations of Elements and Structures Resulting Therefrom
US14/080,257 US9953866B1 (en) 2004-08-09 2013-11-14 Methods for forming a barrier layer with periodic concentrations of elements and structures resulting thereform
US15/925,446 US20180218942A1 (en) 2004-08-09 2018-03-19 Methods for forming a barrier layer with periodic concentrations of elements and structures resulting therefrom

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59997504P 2004-08-09 2004-08-09
US11/199,620 US20060029833A1 (en) 2004-08-09 2005-08-09 Methods for forming a barrier layer with periodic concentrations of elements and structures resulting therefrom

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/838,643 Division US8591985B2 (en) 2004-08-09 2010-07-19 Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes
US13/533,692 Division US20120263869A1 (en) 2004-08-09 2012-06-26 Methods for Forming a Barrier Layer with Periodic Concentrations of Elements and Structures Resulting Therefrom

Publications (1)

Publication Number Publication Date
US20060029833A1 true US20060029833A1 (en) 2006-02-09

Family

ID=35406276

Family Applications (13)

Application Number Title Priority Date Filing Date
US11/199,620 Abandoned US20060029833A1 (en) 2004-08-09 2005-08-09 Methods for forming a barrier layer with periodic concentrations of elements and structures resulting therefrom
US11/200,324 Active 2028-11-27 US7779782B2 (en) 2004-08-09 2005-08-09 Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes
US11/199,621 Expired - Fee Related US7714441B2 (en) 2004-08-09 2005-08-09 Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US11/199,657 Expired - Fee Related US7636234B2 (en) 2004-08-09 2005-08-09 Apparatus configurations for affecting movement of fluids within a microelectric topography processing chamber
US12/616,367 Expired - Fee Related US7884033B2 (en) 2004-08-09 2009-11-11 Method of depositing fluids within a microelectric topography processing chamber
US12/719,167 Expired - Fee Related US7897507B2 (en) 2004-08-09 2010-03-08 Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US12/838,607 Abandoned US20100279071A1 (en) 2004-08-09 2010-07-19 Systems and Methods Affecting Profiles of Solutions Dispensed Across Microelectronic Topographies During Electroless Plating Processes
US12/838,643 Active 2025-08-30 US8591985B2 (en) 2004-08-09 2010-07-19 Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes
US12/980,518 Active 2025-08-17 US8143161B2 (en) 2004-08-09 2010-12-29 Method for passivating hardware of a microelectronic topography processing chamber
US13/013,187 Expired - Fee Related US8502381B2 (en) 2004-08-09 2011-01-25 Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US13/533,692 Abandoned US20120263869A1 (en) 2004-08-09 2012-06-26 Methods for Forming a Barrier Layer with Periodic Concentrations of Elements and Structures Resulting Therefrom
US14/080,257 Active 2026-09-02 US9953866B1 (en) 2004-08-09 2013-11-14 Methods for forming a barrier layer with periodic concentrations of elements and structures resulting thereform
US15/925,446 Abandoned US20180218942A1 (en) 2004-08-09 2018-03-19 Methods for forming a barrier layer with periodic concentrations of elements and structures resulting therefrom

Family Applications After (12)

Application Number Title Priority Date Filing Date
US11/200,324 Active 2028-11-27 US7779782B2 (en) 2004-08-09 2005-08-09 Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes
US11/199,621 Expired - Fee Related US7714441B2 (en) 2004-08-09 2005-08-09 Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US11/199,657 Expired - Fee Related US7636234B2 (en) 2004-08-09 2005-08-09 Apparatus configurations for affecting movement of fluids within a microelectric topography processing chamber
US12/616,367 Expired - Fee Related US7884033B2 (en) 2004-08-09 2009-11-11 Method of depositing fluids within a microelectric topography processing chamber
US12/719,167 Expired - Fee Related US7897507B2 (en) 2004-08-09 2010-03-08 Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US12/838,607 Abandoned US20100279071A1 (en) 2004-08-09 2010-07-19 Systems and Methods Affecting Profiles of Solutions Dispensed Across Microelectronic Topographies During Electroless Plating Processes
US12/838,643 Active 2025-08-30 US8591985B2 (en) 2004-08-09 2010-07-19 Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes
US12/980,518 Active 2025-08-17 US8143161B2 (en) 2004-08-09 2010-12-29 Method for passivating hardware of a microelectronic topography processing chamber
US13/013,187 Expired - Fee Related US8502381B2 (en) 2004-08-09 2011-01-25 Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US13/533,692 Abandoned US20120263869A1 (en) 2004-08-09 2012-06-26 Methods for Forming a Barrier Layer with Periodic Concentrations of Elements and Structures Resulting Therefrom
US14/080,257 Active 2026-09-02 US9953866B1 (en) 2004-08-09 2013-11-14 Methods for forming a barrier layer with periodic concentrations of elements and structures resulting thereform
US15/925,446 Abandoned US20180218942A1 (en) 2004-08-09 2018-03-19 Methods for forming a barrier layer with periodic concentrations of elements and structures resulting therefrom

Country Status (2)

Country Link
US (13) US20060029833A1 (en)
WO (2) WO2006020566A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060030157A1 (en) * 2004-08-09 2006-02-09 Ivanov Igor C Methods and apparatus configurations for affecting movement of processing fluids within a microelectronic topography chamber and a method for passivating hardware within a microelectronic topography processing chamber
US20120161320A1 (en) * 2010-12-23 2012-06-28 Akolkar Rohan N Cobalt metal barrier layers
CN102881677A (en) * 2012-09-24 2013-01-16 复旦大学 Alloy copper diffusion barrier layer for copper interconnection and manufacturing method thereof
CN105132979A (en) * 2014-06-02 2015-12-09 朗姆研究公司 Metallization Of The Wafer Edge For Optimized Electroplating Performance On Resistive Substrates

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060138668A1 (en) * 2004-12-27 2006-06-29 Hung-Wen Su Passivation structure for semiconductor devices
US7704306B2 (en) * 2006-10-16 2010-04-27 Enthone Inc. Manufacture of electroless cobalt deposition compositions for microelectronics applications
US7576003B2 (en) * 2006-11-29 2009-08-18 International Business Machines Corporation Dual liner capping layer interconnect structure and method
DE102006056620B4 (en) * 2006-11-30 2010-04-08 Advanced Micro Devices, Inc., Sunnyvale Semiconductor structure and method for its production
US7776729B2 (en) * 2006-11-30 2010-08-17 Intel Corporation Transistor, method of manufacturing same, etchant for use during manufacture of same, and system containing same
DE102007009912B4 (en) * 2007-02-28 2009-06-10 Advanced Micro Devices, Inc., Sunnyvale A method of making a copper-based metallization layer having a conductive cap layer by an advanced integration scheme
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
US8348720B1 (en) 2007-06-19 2013-01-08 Rubicon Technology, Inc. Ultra-flat, high throughput wafer lapping process
US20090039512A1 (en) * 2007-08-08 2009-02-12 International Business Machines Corporation Electromigration resistant interconnect structure
JP4836092B2 (en) * 2008-03-19 2011-12-14 国立大学法人東北大学 Method for forming semiconductor device
US8994179B2 (en) 2008-08-29 2015-03-31 Infineon Technologies Ag Semiconductor device and method for making same
DE102008049775B4 (en) * 2008-09-30 2018-08-09 Globalfoundries Inc. A method of fabricating a metal capping layer having improved etch resistance for copper-based metal regions in semiconductor devices
US9595457B2 (en) * 2008-12-12 2017-03-14 Acm Research (Shanghai) Inc. Methods and apparatus for cleaning semiconductor wafers
JP2010179407A (en) * 2009-02-05 2010-08-19 Elpida Memory Inc Cmp device
EP2415086B1 (en) * 2009-04-03 2019-02-27 OSRAM Opto Semiconductors GmbH Method for producing an optoelectronic component, optoelectronic component, and component arrangement having a plurality of optoelectronic components
US8298948B2 (en) * 2009-11-06 2012-10-30 International Business Machines Corporation Capping of copper interconnect lines in integrated circuit devices
JP2013062417A (en) * 2011-09-14 2013-04-04 Toshiba Corp Supercritical drying method of semiconductor substrate and device
US9293305B2 (en) 2011-10-31 2016-03-22 Lam Research Corporation Mixed acid cleaning assemblies
US20130112462A1 (en) * 2011-11-07 2013-05-09 International Business Machines Corporation Metal Alloy Cap Integration
US8492274B2 (en) 2011-11-07 2013-07-23 International Business Machines Corporation Metal alloy cap integration
US20130284097A1 (en) * 2012-04-25 2013-10-31 Joseph M. Ranish Gas distribution module for insertion in lateral flow chambers
US9472450B2 (en) 2012-05-10 2016-10-18 Samsung Electronics Co., Ltd. Graphene cap for copper interconnect structures
JP5917297B2 (en) * 2012-05-30 2016-05-11 東京エレクトロン株式会社 Plating treatment method, plating treatment apparatus, and storage medium
US8877633B2 (en) * 2013-03-28 2014-11-04 Globalfoundries Inc. Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system
US9723716B2 (en) * 2013-09-27 2017-08-01 Infineon Technologies Ag Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
US9455220B2 (en) 2014-05-31 2016-09-27 Freescale Semiconductor, Inc. Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures
JP6184921B2 (en) * 2014-08-22 2017-08-23 東京エレクトロン株式会社 Plating treatment method, plating treatment apparatus, and storage medium
US9466569B2 (en) * 2014-11-12 2016-10-11 Freescale Semiconductor, Inc. Though-substrate vias (TSVs) and method therefor
JP6815799B2 (en) * 2016-09-13 2021-01-20 東京エレクトロン株式会社 Substrate processing equipment and substrate processing method
TWI762194B (en) * 2017-07-18 2022-04-21 美商應用材料股份有限公司 Methods for depositing blocking layers on metal material surfaces
US11180373B2 (en) 2017-11-29 2021-11-23 Samsung Electronics Co., Ltd. Nanocrystalline graphene and method of forming nanocrystalline graphene
KR102532605B1 (en) * 2018-07-24 2023-05-15 삼성전자주식회사 Interconnect structure having nanocrystalline graphene cap layer and electronic device including the interconnect structure
US11217531B2 (en) 2018-07-24 2022-01-04 Samsung Electronics Co., Ltd. Interconnect structure having nanocrystalline graphene cap layer and electronic device including the interconnect structure
KR20200011821A (en) 2018-07-25 2020-02-04 삼성전자주식회사 Method of directly growing carbon material on substrate
CN110838464B (en) * 2018-08-16 2023-04-25 联华电子股份有限公司 Metal interconnect structure and method for fabricating the same
US11037799B2 (en) 2018-09-26 2021-06-15 Taiwan Semiconductor Manufacturing Co., Ltd Metal heterojunction structure with capping metal layer
KR20210062652A (en) * 2018-09-27 2021-05-31 도쿄엘렉트론가부시키가이샤 Substrate processing apparatus and substrate processing method
KR102601607B1 (en) 2018-10-01 2023-11-13 삼성전자주식회사 Method of forming graphene
KR20200126721A (en) 2019-04-30 2020-11-09 삼성전자주식회사 Graphene structure and method for forming the graphene structure
US11901225B2 (en) * 2021-09-14 2024-02-13 Applied Materials, Inc. Diffusion layers in metal interconnects

Citations (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US5798903A (en) * 1995-12-26 1998-08-25 Bell Communications Research, Inc. Electrode structure for ferroelectric capacitor integrated on silicon
US5942799A (en) * 1997-11-20 1999-08-24 Novellus Systems, Inc. Multilayer diffusion barriers
US5976928A (en) * 1997-11-20 1999-11-02 Advanced Technology Materials, Inc. Chemical mechanical polishing of FeRAM capacitors
US6017437A (en) * 1997-08-22 2000-01-25 Cutek Research, Inc. Process chamber and method for depositing and/or removing material on a substrate
US20010018266A1 (en) * 1999-02-24 2001-08-30 Tongbi Jiang Method for electroless plating a contact pad
US6286525B1 (en) * 1997-05-08 2001-09-11 Dainippon Screen Mfg. Co. Substrate cleaning apparatus and method
US6326287B1 (en) * 1998-09-03 2001-12-04 Seiko Epson Corporation Semiconductor device and method of fabricating the same
US6447933B1 (en) * 2001-04-30 2002-09-10 Advanced Micro Devices, Inc. Formation of alloy material using alternating depositions of alloy doping element and bulk material
US20020167086A1 (en) * 2001-05-08 2002-11-14 Stauf Gregory T. Barrier structures for integration of high K oxides with Cu and AI electrodes
US6498714B1 (en) * 1999-10-05 2002-12-24 Shinko Electric Industries Co., Ltd. Thin film capacitance device and printed circuit board
US6548844B1 (en) * 1999-06-18 2003-04-15 Kabushiki Kaisha Toshiba Capacitor having a structure capable of restraining deterioration of dielectric film, semiconductor device having the capacitor and method of manufacturing the same
US20030075808A1 (en) * 2001-08-13 2003-04-24 Hiroaki Inoue Semiconductor device, method for manufacturing the same, and plating solution
US6570325B2 (en) * 1998-12-16 2003-05-27 Battelle Memorial Institute Environmental barrier material for organic light emitting device and method of making
US6645567B2 (en) * 2001-12-19 2003-11-11 Intel Corporation Electroless plating bath composition and method of using
US20040216841A1 (en) * 2001-10-16 2004-11-04 Kenya Ito Substrate processing apparatus
US20040226654A1 (en) * 2002-12-17 2004-11-18 Akihisa Hongo Substrate processing apparatus and substrate processing method
US6824612B2 (en) * 2001-12-26 2004-11-30 Applied Materials, Inc. Electroless plating system
US20040238960A1 (en) * 2003-05-29 2004-12-02 Lsi Logic Corporation Interconnect integration
US20040248409A1 (en) * 2003-06-03 2004-12-09 Applied Materials, Inc. Selective metal encapsulation schemes
US20050003654A1 (en) * 2002-10-11 2005-01-06 Hiroshi Horikoshi Method of producing semiconductor device
US20050029662A1 (en) * 2003-08-08 2005-02-10 Hiroshi Nakano Semiconductor production method
US6860944B2 (en) * 2003-06-16 2005-03-01 Blue29 Llc Microelectronic fabrication system components and method for processing a wafer using such components
US6913651B2 (en) * 2002-03-22 2005-07-05 Blue29, Llc Apparatus and method for electroless deposition of materials on semiconductor substrates
US20050161338A1 (en) * 2004-01-26 2005-07-28 Applied Materials, Inc. Electroless cobalt alloy deposition process
US20050181226A1 (en) * 2004-01-26 2005-08-18 Applied Materials, Inc. Method and apparatus for selectively changing thin film composition during electroless deposition in a single chamber
US20060030157A1 (en) * 2004-08-09 2006-02-09 Ivanov Igor C Methods and apparatus configurations for affecting movement of processing fluids within a microelectronic topography chamber and a method for passivating hardware within a microelectronic topography processing chamber
US7279423B2 (en) * 2002-10-31 2007-10-09 Intel Corporation Forming a copper diffusion barrier
US7387131B2 (en) * 2002-01-30 2008-06-17 Tokyo Electron Limited Processing apparatus and substrate processing method
US7396759B1 (en) * 2004-11-03 2008-07-08 Novellus Systems, Inc. Protection of Cu damascene interconnects by formation of a self-aligned buffer layer

Family Cites Families (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3887732A (en) * 1970-10-01 1975-06-03 Gen Am Transport Stress controlled electroless nickel deposits
GB1556013A (en) * 1978-04-19 1979-11-14 Carrier Drysys Ltd Paint spraying apparatus
US4224381A (en) * 1978-10-19 1980-09-23 Poly Disc Systems, Inc. Abrasion resistant magnetic record members
US4451507A (en) * 1982-10-29 1984-05-29 Rca Corporation Automatic liquid dispensing apparatus for spinning surface of uniform thickness
US4594995A (en) * 1982-12-14 1986-06-17 Garrison John D Carbonaceous selective absorber for solar thermal energy collection and process for its formation
US4457259A (en) * 1983-03-14 1984-07-03 Rca Corporation Apparatus for spraying a liquid on a spinning surface
JPS61111561A (en) * 1984-10-05 1986-05-29 Fujitsu Ltd Semiconductor device
US4659587A (en) * 1984-10-11 1987-04-21 Hitachi, Ltd. Electroless plating process and process for producing multilayer wiring board
JPS61112320A (en) * 1984-11-07 1986-05-30 Nec Corp Developing treating device for semiconductor substrate
JPS61161175A (en) * 1984-12-29 1986-07-21 Nordson Kk Spraying method of two fluids
US4810520A (en) * 1987-09-23 1989-03-07 Magnetic Peripherals Inc. Method for controlling electroless magnetic plating
KR970006206B1 (en) * 1988-02-10 1997-04-24 도오교오 에레구토론 가부시끼가이샤 Automatic coating system
US4970106A (en) * 1989-06-02 1990-11-13 International Business Machines Corporation Thin film multilayer laminate interconnection board
US5830533A (en) * 1991-05-28 1998-11-03 Microelectronics And Computer Technology Corporation Selective patterning of metallization on a dielectric substrate
KR960005765A (en) * 1994-07-14 1996-02-23 모리시다 요이치 Electroless plating bath and wiring forming method of semiconductor device used for wiring formation of semiconductor device
US6025012A (en) * 1995-09-20 2000-02-15 Matsushita Electric Industrial Co., Ltd. Method and apparatus for determining film thickness control conditions and discharging liquid to a rotating substrate
US5913147A (en) * 1997-01-21 1999-06-15 Advanced Micro Devices, Inc. Method for fabricating copper-aluminum metallization
JPH10226888A (en) 1997-02-19 1998-08-25 Matsushita Electric Ind Co Ltd Electroless nickel plating device
DE19713512C2 (en) * 1997-04-01 2000-01-13 Westfalia Separator Ag Housing of a horizontal solid bowl screw centrifuge
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6100184A (en) * 1997-08-20 2000-08-08 Sematech, Inc. Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
US6248168B1 (en) * 1997-12-15 2001-06-19 Tokyo Electron Limited Spin coating apparatus including aging unit and solvent replacement unit
US6249055B1 (en) * 1998-02-03 2001-06-19 Advanced Micro Devices, Inc. Self-encapsulated copper metallization
WO1999053381A1 (en) * 1998-04-15 1999-10-21 Etec Systems, Inc. Photoresist developer and method of development
JP2000124185A (en) * 1998-10-13 2000-04-28 Dainippon Screen Mfg Co Ltd Substrate treating device
US20040065540A1 (en) * 2002-06-28 2004-04-08 Novellus Systems, Inc. Liquid treatment using thin liquid layer
US6214728B1 (en) * 1998-11-20 2001-04-10 Chartered Semiconductor Manufacturing, Ltd. Method to encapsulate copper plug for interconnect metallization
JP3458063B2 (en) * 1998-11-20 2003-10-20 東京エレクトロン株式会社 Coating device and coating method
US6290865B1 (en) * 1998-11-30 2001-09-18 Applied Materials, Inc. Spin-rinse-drying process for electroplated semiconductor wafers
US6267853B1 (en) * 1999-07-09 2001-07-31 Applied Materials, Inc. Electro-chemical deposition system
US6144099A (en) * 1999-03-30 2000-11-07 Advanced Micro Devices, Inc. Semiconductor metalization barrier
JP2001020091A (en) 1999-07-08 2001-01-23 Ebara Corp Plating device and plating method
US6258223B1 (en) * 1999-07-09 2001-07-10 Applied Materials, Inc. In-situ electroless copper seed layer enhancement in an electroplating system
US6716478B2 (en) * 1999-08-04 2004-04-06 Tokyo Electron Limited Coating film forming apparatus and coating film forming method
US6734559B1 (en) * 1999-09-17 2004-05-11 Advanced Micro Devices, Inc. Self-aligned semiconductor interconnect barrier and manufacturing method therefor
JP2001144263A (en) * 1999-11-11 2001-05-25 Tokyo Ohka Kogyo Co Ltd Dielectric element and manufacturing method of dielectric method
US6514344B2 (en) * 1999-12-16 2003-02-04 Tokyo Electron Limited Film forming unit
JP3979791B2 (en) * 2000-03-08 2007-09-19 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
US6634806B2 (en) * 2000-03-13 2003-10-21 Tokyo Electron Limited Substrate processing method and substrate processing apparatus
US6626996B1 (en) * 2000-03-14 2003-09-30 Pizza Hut, Inc. Pizza sauce dispensing devices and methods
JP2001355074A (en) * 2000-04-10 2001-12-25 Sony Corp Electroless plating method, and apparatus thereof
US6479902B1 (en) * 2000-06-29 2002-11-12 Advanced Micro Devices, Inc. Semiconductor catalytic layer and atomic layer deposition thereof
WO2002004704A2 (en) * 2000-07-11 2002-01-17 Applied Materials, Inc. Method and apparatus for patching electrochemically deposited layers using electroless deposited materials
JP4644924B2 (en) * 2000-10-12 2011-03-09 ソニー株式会社 Semiconductor device and manufacturing method thereof
FR2816759B1 (en) 2000-11-10 2004-11-19 Renault USE OF A PALLADIUM-BASED MEMBRANE IN A FUEL CELL DEVICE
FR2816758B3 (en) * 2000-11-14 2003-04-04 Lionel Girardie COPPER METALLIZATION TECHNIQUE FOR TRANSISTOR CONNECTIONS AND INTERCONNECTIONS
US6674170B1 (en) * 2000-12-18 2004-01-06 Advanced Micro Devices, Inc. Barrier metal oxide interconnect cap in integrated circuits
US6977224B2 (en) * 2000-12-28 2005-12-20 Intel Corporation Method of electroless introduction of interconnect structures
US6413788B1 (en) * 2001-02-28 2002-07-02 Micron Technology, Inc. Keepers for MRAM electrodes
WO2002092877A2 (en) 2001-05-11 2002-11-21 Ebara Corporation Catalyst-imparting treatment solution and electroless plating method
JP3707394B2 (en) * 2001-04-06 2005-10-19 ソニー株式会社 Electroless plating method
JP3754322B2 (en) * 2001-05-24 2006-03-08 東京エレクトロン株式会社 Coating film forming method and apparatus
US6717189B2 (en) * 2001-06-01 2004-04-06 Ebara Corporation Electroless plating liquid and semiconductor device
US6703712B2 (en) * 2001-11-13 2004-03-09 Agere Systems, Inc. Microelectronic device layer deposited with multiple electrolytes
GB2382798A (en) * 2001-12-04 2003-06-11 Qinetiq Ltd Inkjet printer which deposits at least two fluids on a substrate such that the fluids react chemically to form a product thereon
US6515368B1 (en) * 2001-12-07 2003-02-04 Advanced Micro Devices, Inc. Semiconductor device with copper-filled via includes a copper-zinc/alloy film for reduced electromigration of copper
US6605874B2 (en) * 2001-12-19 2003-08-12 Intel Corporation Method of making semiconductor device using an interconnect
US20030143837A1 (en) * 2002-01-28 2003-07-31 Applied Materials, Inc. Method of depositing a catalytic layer
US6528409B1 (en) * 2002-04-29 2003-03-04 Advanced Micro Devices, Inc. Interconnect structure formed in porous dielectric material with minimized degradation and electromigration
US6749689B2 (en) * 2002-04-30 2004-06-15 Advanced Robotic Technologies Controlled reciprocating machine and method
US20060051493A1 (en) * 2002-07-31 2006-03-09 Tella Richard P Apparatus and methods for printing arrays
DE10239351B4 (en) * 2002-08-28 2006-07-27 Amtec Kistler Gmbh Device for applying a coating agent
US6821909B2 (en) * 2002-10-30 2004-11-23 Applied Materials, Inc. Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application
US7485611B2 (en) * 2002-10-31 2009-02-03 Advanced Technology Materials, Inc. Supercritical fluid-based cleaning compositions and methods
US7235483B2 (en) 2002-11-19 2007-06-26 Blue29 Llc Method of electroless deposition of thin metal and dielectric films with temperature controlled stages of film growth
US6770424B2 (en) * 2002-12-16 2004-08-03 Asml Holding N.V. Wafer track apparatus and methods for dispensing fluids with rotatable dispense arms
US7192866B2 (en) 2002-12-19 2007-03-20 Sharp Laboratories Of America, Inc. Source alternating MOCVD processes to deposit tungsten nitride thin films as barrier layers for MOCVD copper interconnects
US7020852B2 (en) * 2003-05-08 2006-03-28 Lsi Logic Corporation Automation of the development, testing, and release of a flow framework and methodology to design integrated circuits
US7883739B2 (en) * 2003-06-16 2011-02-08 Lam Research Corporation Method for strengthening adhesion between dielectric layers formed adjacent to metal layers
US6881437B2 (en) * 2003-06-16 2005-04-19 Blue29 Llc Methods and system for processing a microelectronic topography
KR101493872B1 (en) * 2008-08-20 2015-02-17 삼성전자주식회사 Backgrinding-underfill film, method of the same, semiconductor package and method for formation of the same using the backgrinding-underfill film

Patent Citations (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798903A (en) * 1995-12-26 1998-08-25 Bell Communications Research, Inc. Electrode structure for ferroelectric capacitor integrated on silicon
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US6286525B1 (en) * 1997-05-08 2001-09-11 Dainippon Screen Mfg. Co. Substrate cleaning apparatus and method
US6017437A (en) * 1997-08-22 2000-01-25 Cutek Research, Inc. Process chamber and method for depositing and/or removing material on a substrate
US5942799A (en) * 1997-11-20 1999-08-24 Novellus Systems, Inc. Multilayer diffusion barriers
US5976928A (en) * 1997-11-20 1999-11-02 Advanced Technology Materials, Inc. Chemical mechanical polishing of FeRAM capacitors
US6326287B1 (en) * 1998-09-03 2001-12-04 Seiko Epson Corporation Semiconductor device and method of fabricating the same
US6570325B2 (en) * 1998-12-16 2003-05-27 Battelle Memorial Institute Environmental barrier material for organic light emitting device and method of making
US20010018266A1 (en) * 1999-02-24 2001-08-30 Tongbi Jiang Method for electroless plating a contact pad
US6548844B1 (en) * 1999-06-18 2003-04-15 Kabushiki Kaisha Toshiba Capacitor having a structure capable of restraining deterioration of dielectric film, semiconductor device having the capacitor and method of manufacturing the same
US6498714B1 (en) * 1999-10-05 2002-12-24 Shinko Electric Industries Co., Ltd. Thin film capacitance device and printed circuit board
US6447933B1 (en) * 2001-04-30 2002-09-10 Advanced Micro Devices, Inc. Formation of alloy material using alternating depositions of alloy doping element and bulk material
US20020167086A1 (en) * 2001-05-08 2002-11-14 Stauf Gregory T. Barrier structures for integration of high K oxides with Cu and AI electrodes
US20030075808A1 (en) * 2001-08-13 2003-04-24 Hiroaki Inoue Semiconductor device, method for manufacturing the same, and plating solution
US20040216841A1 (en) * 2001-10-16 2004-11-04 Kenya Ito Substrate processing apparatus
US20040038073A1 (en) * 2001-12-19 2004-02-26 Chebiam Ramanan V. Electroless plating bath composition and method of using
US6645567B2 (en) * 2001-12-19 2003-11-11 Intel Corporation Electroless plating bath composition and method of using
US6824612B2 (en) * 2001-12-26 2004-11-30 Applied Materials, Inc. Electroless plating system
US7387131B2 (en) * 2002-01-30 2008-06-17 Tokyo Electron Limited Processing apparatus and substrate processing method
US6913651B2 (en) * 2002-03-22 2005-07-05 Blue29, Llc Apparatus and method for electroless deposition of materials on semiconductor substrates
US20050003654A1 (en) * 2002-10-11 2005-01-06 Hiroshi Horikoshi Method of producing semiconductor device
US7279423B2 (en) * 2002-10-31 2007-10-09 Intel Corporation Forming a copper diffusion barrier
US20040226654A1 (en) * 2002-12-17 2004-11-18 Akihisa Hongo Substrate processing apparatus and substrate processing method
US20040238960A1 (en) * 2003-05-29 2004-12-02 Lsi Logic Corporation Interconnect integration
US20040248409A1 (en) * 2003-06-03 2004-12-09 Applied Materials, Inc. Selective metal encapsulation schemes
US6860944B2 (en) * 2003-06-16 2005-03-01 Blue29 Llc Microelectronic fabrication system components and method for processing a wafer using such components
US20050029662A1 (en) * 2003-08-08 2005-02-10 Hiroshi Nakano Semiconductor production method
US20050161338A1 (en) * 2004-01-26 2005-07-28 Applied Materials, Inc. Electroless cobalt alloy deposition process
US20050181226A1 (en) * 2004-01-26 2005-08-18 Applied Materials, Inc. Method and apparatus for selectively changing thin film composition during electroless deposition in a single chamber
US20060030157A1 (en) * 2004-08-09 2006-02-09 Ivanov Igor C Methods and apparatus configurations for affecting movement of processing fluids within a microelectronic topography chamber and a method for passivating hardware within a microelectronic topography processing chamber
US20060030143A1 (en) * 2004-08-09 2006-02-09 Ivanov Igor C Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US20060029727A1 (en) * 2004-08-09 2006-02-09 Ivanov Igor C Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes
US7396759B1 (en) * 2004-11-03 2008-07-08 Novellus Systems, Inc. Protection of Cu damascene interconnects by formation of a self-aligned buffer layer

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110097477A1 (en) * 2004-08-09 2011-04-28 Lam Research Corporation Methods and Apparatus Configurations for Affecting Movement of Fluids Within a Microelectronic Topography Processing Chamber and a Method for Passivating Hardware Within a Microelectronic Topography Processing Chamber
US20100279071A1 (en) * 2004-08-09 2010-11-04 Lam Research Corporation Systems and Methods Affecting Profiles of Solutions Dispensed Across Microelectronic Topographies During Electroless Plating Processes
US20060030143A1 (en) * 2004-08-09 2006-02-09 Ivanov Igor C Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US7636234B2 (en) 2004-08-09 2009-12-22 Lam Research Corporation Apparatus configurations for affecting movement of fluids within a microelectric topography processing chamber
US20100055300A1 (en) * 2004-08-09 2010-03-04 Lam Research Corporation Methods and Apparatus Configurations for Affecting Movement of Fluids Within a Microelectronic Topography Processing Chamber and a Method for Passivating Hardware Within a Microelectronic Topography Processing Chamber
US7714441B2 (en) 2004-08-09 2010-05-11 Lam Research Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US20100159208A1 (en) * 2004-08-09 2010-06-24 Lam Research Barrier Layer Configurations and Methods for Processing Microelectronic Topographies Having Barrier Layers
US7779782B2 (en) 2004-08-09 2010-08-24 Lam Research Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes
US20100279002A1 (en) * 2004-08-09 2010-11-04 Lam Research Corporation Systems and Methods Affecting Profiles of Solutions Dispensed Across Microelectronic Topographies During Electroless Plating Processes
US8591985B2 (en) 2004-08-09 2013-11-26 Lam Research Corporation Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes
US7884033B2 (en) 2004-08-09 2011-02-08 Lam Research Method of depositing fluids within a microelectric topography processing chamber
US7897507B2 (en) 2004-08-09 2011-03-01 Lam Research Corporation Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US8143161B2 (en) 2004-08-09 2012-03-27 Lam Research Corporation Method for passivating hardware of a microelectronic topography processing chamber
US20110117328A1 (en) * 2004-08-09 2011-05-19 Lam Research Barrier Layer Configurations and Methods for Processing Microelectronic Topographies Having Barrier Layers
US20060030157A1 (en) * 2004-08-09 2006-02-09 Ivanov Igor C Methods and apparatus configurations for affecting movement of processing fluids within a microelectronic topography chamber and a method for passivating hardware within a microelectronic topography processing chamber
US8502381B2 (en) 2004-08-09 2013-08-06 Lam Research Corporation Barrier layer configurations and methods for processing microelectronic topographies having barrier layers
US20060029727A1 (en) * 2004-08-09 2006-02-09 Ivanov Igor C Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes
US20120161320A1 (en) * 2010-12-23 2012-06-28 Akolkar Rohan N Cobalt metal barrier layers
TWI502646B (en) * 2010-12-23 2015-10-01 Intel Corp Cobalt metal barrier layers
CN102881677A (en) * 2012-09-24 2013-01-16 复旦大学 Alloy copper diffusion barrier layer for copper interconnection and manufacturing method thereof
CN105132979A (en) * 2014-06-02 2015-12-09 朗姆研究公司 Metallization Of The Wafer Edge For Optimized Electroplating Performance On Resistive Substrates
US9761524B2 (en) 2014-06-02 2017-09-12 Lam Research Corporation Metallization of the wafer edge for optimized electroplating performance on resistive substrates
CN105132979B (en) * 2014-06-02 2018-05-08 朗姆研究公司 Metallization for the Waffer edge of the plating performance that optimizes resistive substrate
CN108396351A (en) * 2014-06-02 2018-08-14 朗姆研究公司 The metallization of the Waffer edge of plating performance for optimizing resistive substrate

Also Published As

Publication number Publication date
WO2006020566B1 (en) 2006-03-23
US7884033B2 (en) 2011-02-08
US20060030157A1 (en) 2006-02-09
WO2006020565A3 (en) 2006-06-01
US20120263869A1 (en) 2012-10-18
US7897507B2 (en) 2011-03-01
US20180218942A1 (en) 2018-08-02
US8591985B2 (en) 2013-11-26
US20060029727A1 (en) 2006-02-09
US20100279002A1 (en) 2010-11-04
WO2006020565B1 (en) 2006-08-03
US20110117328A1 (en) 2011-05-19
US9953866B1 (en) 2018-04-24
US7636234B2 (en) 2009-12-22
WO2006020565A2 (en) 2006-02-23
WO2006020566A1 (en) 2006-02-23
US20100159208A1 (en) 2010-06-24
US7714441B2 (en) 2010-05-11
US7779782B2 (en) 2010-08-24
US8502381B2 (en) 2013-08-06
US20100279071A1 (en) 2010-11-04
US20110097477A1 (en) 2011-04-28
US20100055300A1 (en) 2010-03-04
US20060030143A1 (en) 2006-02-09
US8143161B2 (en) 2012-03-27

Similar Documents

Publication Publication Date Title
US20180218942A1 (en) Methods for forming a barrier layer with periodic concentrations of elements and structures resulting therefrom
CN100536105C (en) Methods of fabricating interconnects for semiconductor components
US7262504B2 (en) Multiple stage electroless deposition of a metal layer
US7648913B2 (en) Method of electroless deposition of thin metal and dielectric films with temperature controlled stages of film growth
US7622382B2 (en) Filling narrow and high aspect ratio openings with electroless deposition
US7690324B1 (en) Small-volume electroless plating cell
US20070269981A1 (en) Electroless treatment of noble metal barrier and adhesion layer
JP2005048209A (en) Electroless plating method, electroless plating device, method of fabricating semiconductor device, and fabrication device therefor
US20080090414A1 (en) Manufacture of electroless cobalt deposition compositions for microelectronics applications
US7479687B2 (en) Deep via seed repair using electroless plating chemistry
KR101485506B1 (en) Method for depositing thin film on wafer
JP2004115885A (en) Electroless plating method
KR20090101258A (en) Self-limiting plating method
US7238617B2 (en) Method for fabricating semiconductor device to minimize terminal effect in ECP process
US20050164499A1 (en) Electroless plating method and apparatus
US7344982B2 (en) System and method of selectively depositing Ruthenium films by digital chemical vapor deposition
KR20220052967A (en) Substrate liquid processing method, substrate liquid processing apparatus, and computer-readable recording medium
JP2006057171A (en) Electroless plating apparatus
JPH07283134A (en) Manufacture of semiconductor substrate and semiconductor device
JP2004307998A (en) Electroless plating method and electroless plating equipment

Legal Events

Date Code Title Description
AS Assignment

Owner name: BLUE29, LLC, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IVANOV, IGOR C.;REEL/FRAME:016877/0324

Effective date: 20050809

AS Assignment

Owner name: KLA-TENCOR CORPORATION, CALIFORNIA

Free format text: SECURITY AGREEMENT;ASSIGNOR:BLUE 29, LLC;REEL/FRAME:018323/0734

Effective date: 20060911

Owner name: KLA-TENCOR CORPORATION,CALIFORNIA

Free format text: SECURITY AGREEMENT;ASSIGNOR:BLUE 29, LLC;REEL/FRAME:018323/0734

Effective date: 20060911

AS Assignment

Owner name: LAM RESEARCH CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BLUE29, L.L.C.;REEL/FRAME:019899/0690

Effective date: 20070507

Owner name: LAM RESEARCH CORPORATION,CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BLUE29, L.L.C.;REEL/FRAME:019899/0690

Effective date: 20070507

STCB Information on status: application discontinuation

Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION