US20060025986A1 - Method and system to emulate an M-bit instruction set - Google Patents
Method and system to emulate an M-bit instruction set Download PDFInfo
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- US20060025986A1 US20060025986A1 US11/188,310 US18831005A US2006025986A1 US 20060025986 A1 US20060025986 A1 US 20060025986A1 US 18831005 A US18831005 A US 18831005A US 2006025986 A1 US2006025986 A1 US 2006025986A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/601—Reconfiguration of cache memory
- G06F2212/6012—Reconfiguration of cache memory of operating mode, e.g. cache mode or local memory mode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to processors and more particularly to processors that execute JavaTM bytecodes.
- JavaTM is a programming language that, at the source code level, is similar to object oriented programming languages such as C++.
- JavaTM language source code is compiled into an intermediate representation based on a plurality “bytecodes” that define specific tasks.
- the bytecodes are further compiled to machine language for a particular processor.
- some processors are specifically designed to execute some of the JavaTM bytecodes directly.
- a processor that directly executes JavaTM bytecodes is paired with a general purpose processor so as to accelerate JavaTM program execution in a general or special purpose machine. It would be advantageous to provide accelerations, similar to those seen for directly executed JavaTM bytecodes, in other languages and development environments.
- At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a table to an index location (the index location based on the at least a portion of the instruction), executing a first series of instructions directly executable by the processor (the first series of instructions pointed to by the table at the index location), and thereby emulating execution of the instruction from the first instruction set.
- asserted and “not asserted” are used herein to refer to Boolean conditions.
- An asserted state need not necessarily be a logical 1 or a high voltage state, and thus could equally apply to an asserted being a logical 0 or a low voltage state.
- an asserted state may be a logical 1 and a not-asserted state may be a logical 0, with de-assertion changing the state from a logical 1 to a logical 0.
- an asserted state may be a logic 0 and a not-asserted state may a logical 1 with a de-assertion being a change from a logical 0 to a logical 1.
- FIG. 1 shows a diagram of a system in accordance with embodiments of the invention
- FIG. 2 shows a block diagram of the JSM of FIG. 1 in accordance with embodiments of the invention
- FIG. 3 shows various registers used in the JSM of FIGS. 1 and 2 ;
- FIG. 4 illustrates operation of the JSM to trigger “micro-sequences”
- FIG. 5 (comprising FIGS. 5A and 5B ) illustrates a method in accordance with embodiments of the invention.
- FIG. 6 (comprising FIGS. 6A and 6B ) illustrates a method in accordance with further embodiments of the invention.
- FIG. 7 depicts an illustrative embodiment of the system described herein.
- FIG. 1 shows a system 100 in accordance with embodiments of the invention.
- the system may comprise at least two processors 102 and 104 .
- Processor 102 may be referred to for purposes of this disclosure as a Java Stack Machine (“JSM”) and processor 104 may be referred to as a Main Processor Unit (“MPU”).
- System 100 may also comprise memory 106 coupled to both the JSM 102 and MPU 104 . At least a portion of the memory 106 may be shared by both processors, and if desired, other portions of the memory 106 may be designated as private to one processor or the other.
- System 100 also comprises a Java Virtual Machine (“JVM”) 108 , compiler 110 , and a display 114 .
- the JVM 108 may comprise a combination of software and hardware.
- the software may comprise the compiler 110 and the hardware may comprise the JSM 102 .
- the JVM may comprise a class loader, bytecode verifier, garbage collector, and a bytecode interpreter loop to interpret the bytecodes that are not executed on the JSM processor 102 .
- Other components (not specifically shown) may be included as desired for various applications.
- JavaTM language source code is converted or compiled to a series of bytecodes 112 , with each individual one of the bytecodes referred to as an “opcode.”
- Bytecodes 112 may be provided to the JVM 108 , possibly compiled by compiler 110 , and provided to the JSM 102 and/or MPU 104 for execution.
- the JSM 102 may execute at least some JavaTM bytecodes directly.
- the JVM 108 may also request the MPU 104 to execute one or more JavaTM bytecodes not executed or executable by the JSM 102 .
- the MPU 104 also may execute non-Java instructions.
- the MPU 104 may thus also host an operating system (“O/S”) (not specifically shown) which performs various functions such as system memory management, system task management that schedules the software aspects of the JVM 108 and most or all other native tasks running on the system, management of the display 114 , and receiving input from input devices (not specifically shown).
- O/S operating system
- JavaTM code whether executed on the JSM 102 or MPU 104 , may be used to perform any one of a variety of applications such as multimedia, games or web based applications in the system 100 , while non-JavaTM code, which may comprise the O/S and other native applications, may still run on the system on the MPU 104 .
- JavaTM bytecodes perform stack-based operations. For example, an “IADD” (integer add) Java TM opcode pops two integers off the top of the stack, adds them together, and pushes the sum back on the stack.
- a “simple” opcode is one in which the JSM 102 may perform an immediate operation either in a single cycle (e.g., an IADD opcode) or in several cycles (e.g., “DUP2_X2”).
- a “complex” opcode is one in which several memory accesses may be required to be made within the JVM data structure for various verifications (e.g., NULL pointer, array boundaries).
- a JSM processor 102 in accordance with embodiments of the invention may execute, in addition to the JavaTM bytecodes, a second instruction set other than JavaTM bytecodes.
- the second instruction set may comprise register-based and memory-based operations rather than stack-based operations.
- This second instruction set complements the JavaTM instruction set and, accordingly, may be referred to as a complementary instruction set architecture (“C-ISA”).
- C-ISA complementary instruction set architecture
- complementary it is meant that some complex JavaTM bytecodes may be replaced by a “micro-sequence” comprising C-ISA instructions.
- the execution of JavaTM code may thus be made more efficient and run faster by replacing some opcodes by more efficient micro-sequences of C-ISA instructions, and as discussed more fully below, other instruction sets may be emulated using the mirco-sequences.
- the JSM 102 thus comprises a stack-based architecture for direct execution of JavaTM bytecodes, combined with a register-based architecture for direct execution of memory based micro-sequences of C-ISA instructions. Because various data structures described herein are JVM-dependent, and thus may change from one JVM implementation to another, the software flexibility of the micro-sequence provides a mechanism for various JVM optimizations now known or later developed.
- FIG. 2 shows an illustrative block diagram of the JSM 102 .
- the JSM comprises a core 120 coupled to data storage 122 and instruction storage 130 .
- the components of the core 120 preferably comprise a plurality of registers 140 , address generation units (“AGUs”) 142 and 147 , micro-translation lookaside buffers (micro-TLBs) 144 and 156 , a multi-entry micro-stack 146 , an arithmetic logic unit (“ALU”) 148 , a multiplier 150 , decode logic 152 , and instruction fetch logic 154 .
- AGUs address generation units
- micro-TLBs micro-translation lookaside buffers
- ALU arithmetic logic unit
- Data pointed to by operands of opcodes may be retrieved from data storage 122 or from the micro-stack 146 , and processed by the ALU 148 . Instructions may be fetched from instruction storage 130 by fetch logic 154 and decoded by decode logic 152 .
- the AGUs 142 may be used to calculate addresses based, at least in part, on data contained in the registers 140 .
- AGU 147 couples to the micro-stack 146 and may manage overflow and underflow conditions in the micro-stack 146 .
- the micro-TLBs 144 and 156 perform the function of a cache for the address translation and memory protection information bits that are under the control of the operating system running on the MPU 104 .
- JavaTM bytecodes may pop data from and push data onto the micro-stack 146 , which micro-stack 146 preferably comprises a plurality of gates in the core 120 of the JSM 102 .
- the micro-stack 146 preferably comprises the top x entries of a larger stack that is implemented in data storage 122 .
- the size x of the micro-stack may be the top eight entries in the larger, memory-based stack.
- ALU 148 adds, subtracts, and shifts data.
- the multiplier 150 may be used to multiply two values together in one or more cycles.
- the instruction fetch logic 154 fetches instructions from instruction storage 130 , which instructions may be decoded by decode logic 152 . Because the JSM 102 is configured to process instructions from at least two instruction sets, the decode logic 152 comprises at least two modes of operation, one mode for each instruction set. As such, the decode logic unit 152 may comprise a Java TM mode in which JavaTM bytecodes may be decoded, and a C-ISA mode in which micro-sequences of C-ISA instructions may be decoded.
- the data storage 122 comprises data cache (“D-cache”) 124 and data random access memory (“D-RAM”) 126 .
- the stack (excluding the micro-stack 146 ), arrays and non-critical data may be stored in the D-cache 124 , while local variables and data may be stored in D-RAM 126 .
- the instruction storage 130 may comprise instruction RAM (“I-RAM”) 132 and instruction cache (“I-CACHE”) 134 .
- the I-RAM 132 may be used for opcodes or micro-sequences, and the I-CACHE 134 may be used to store other types of JavaTM bytecode and mixed JavaTM/C-ISA instructions.
- the registers 140 may comprise a plurality of registers designated as R 0 -R 15 .
- Registers R 0 -R 3 , R 5 , R 8 -R 11 and R 13 -R 14 may be used as general purposes (“GP”) registers for any purpose.
- Other registers, and some of the GP registers, may be used for specific purposes.
- registers R 4 and R 12 may each be used to store program counters, with R 4 storing a program counter (“PC”) for a stream of bytecodes, and R 12 storing a micro-program counter (“micro-PC”) for executing micro-sequences.
- PC program counter
- micro-PC micro-program counter
- register R 5 may be used to store the base address of a portion of memory in which Java TM local variables may be stored when used by a JavaTM method.
- the top of the micro-stack 146 can be referenced by the values in registers R 6 and R 7 , and the top of the micro-stack may have a matching address in external memory pointed to by register R 6 .
- the values contained in the micro-stack are the latest updated values, while their corresponding values in external memory may or may not be up to date.
- Register R 7 provides the data value stored at the top of the micro-stack.
- Registers R 8 and R 9 may also be used to hold the address index 0 (“AI 0 ”) and address index 1 (“AI 1 ”).
- Register R 14 may also be used to hold the indirect register index (“IRI”).
- Register R 15 may be used for status and control of the JSM 102 .
- At least one bit (called the “Micro-Sequence-Active” bit, not specifically shown) in status register R 15 is used to indicate whether the JSM 102 is executing by way of a micro-sequence. This bit controls, in particular, which program counter is used (R 4 (PC) or R 12 (micro-PC)) to fetch the next instruction.
- Another bit of the status and control register R 15 (the bit termed herein the “WIDE ENABLE flag” or “WIDE ENABLE bit”, and given the reference number 198 ) is used indicate whether the JavaTM WIDE opcode is treated as a non-executed prefix, or whether the WIDE value 0xC4 (hexadecimal value C4) may be assigned other functions directly executable by the processor or executable by way of a micro-sequence.
- the WIDE ENABLE flag may in other portions of the JSM processor 102 , such as register R 151 in the decode logic 152 ( FIG. 2 ).
- the WIDE ENABLE flag 198 of illustrative register R 15 preferably couples to the decode logic 152 by way of line 196 .
- the decode logic 152 and indeed the processor 102 , treat WIDE as a prefix that modifies the operand width of an opcode that immediately follows the WIDE opcode.
- the WIDE ENABLE flag 198 is not asserted, then the 0xC4 value is treated like other opcodes that may be directly executable by the processor 102 .
- the 0xC4 value can perform any desired functionality, and that functionality need not necessarily be related to operand width. Moreover, the 0xC4 value may then also be utilized as a trigger for execution of a micro-sequence.
- FIG. 4 illustrates the operation of the JSM 102 with regard to triggering of micro-sequences based on JavaTM bytecodes, including the 0xC4 opcode when the WIDE ENABLE flag 198 is not asserted.
- FIG. 4 illustrates the instruction storage 130 , the decode logic 152 , and a micro-sequence vector table 162 .
- the decode logic 152 accesses the instruction storage 130 and a micro-sequence vector table 162 .
- the decode logic 152 retrieves instructions (e.g., instruction 170 ) from instruction storage 130 by way of instruction fetch logic 154 ( FIG. 2 ) and decodes the instructions to determine the type of instruction.
- the decode logic instructs the processor with regard to fetch width regarding the next opcode, and the process starts anew. If, however, the WIDE ENABLE flag 198 is not asserted and the 0xC4 opcode is the fetched opcode, the JSM 102 either directly executes the opcode to perform any desirable function, or triggers a micro-sequence to perform any desirable function.
- the micro-sequence vector table 162 may be implemented in the decode logic 152 , or as separate logic in the JSM 102 .
- the micro-sequence vector table 162 preferably comprises a plurality of entries 164 , such as one entry for each opcode that the JSM may receive. For example, if there are a total of 256 bytecodes, the micro-sequence vector table 162 preferably comprises at least 256 entries.
- Each entry 164 may have at least two fields—a field 166 and an associated field 168 .
- Field 168 may comprise a single bit that indicates whether the instruction 170 is to be directly executed, or whether the associated field 166 contains a reference to a micro-sequence.
- an asserted bit 168 may indicate the corresponding opcode is directly executable by the JSM, and a non-asserted bit 168 may indicate that the associated field 166 contains a reference to a micro-sequence.
- the reference may comprise the full starting address in instruction storage 130 of the micro-sequence, or a part of the starting address that can be concatenated with a base address that may be programmable in the JSM.
- field 166 may provide as many address bits as are required to access the full memory space.
- a register within the JSM registers 140 or preferably within a JSM configuration register accessible through an indirect addressing mechanism using the IRI register, is programmed to hold the base address.
- the vector table 162 may supply only the offset to access the start of the micro-sequence.
- Most or all JSM internal registers 140 and the vector table 162 are accessible by the MPU 104 , and therefore the entries 164 of the vector table 162 may be modified by the JVM as necessary.
- the offset addressing technique may be preferred to reduce the number of bits needed within field 166 .
- At least a portion 180 of the instruction storage 130 may be allocated for storage of micro-sequences and thus the starting address may point to a location in micro-sequence storage 180 at which a particular micro-sequence can be found.
- the portion 180 may be implemented in I-RAM 132 ( FIG. 2 ) accessible by the MPU 104 , which thus allows the micro-sequences to be changed.
- the decode logic 152 uses an opcode, including the 0xC4 opcode when the WIDE ENABLE flag 198 is not asserted, as an index into micro-sequence vector table 162 .
- the decode logic 152 locates the indexed entry 164 , the decode logic 152 examines the associated bit 168 to determine whether the opcode triggers a micro-sequence. If the bit 168 indicates that the opcode can be directly processed and executed by the JSM, then the instruction is so executed.
- the decode logic 152 preferably changes the opcode into a “NOP,” executes the NOP opcode, asserts the micro-sequence-active bit in the status register R 15 (not specifically shown), and begins fetching the first micro-sequence instruction.
- NOP NOP
- Changing the opcode into a NOP while fetching the first instruction of the micro-sequence permits the JSM to process multi-cycle instructions that are further advanced in the pipe without additional latency.
- the micro-sequence-active bit may be asserted at any suitable time, such as when the micro-sequence enters the JSM execution stage (not specifically shown).
- the JSM 102 implements two program counters—the PC 186 (register R 4 ) and the micro-PC 188 (register R 12 ).
- one of these two program counters is the active program counter used to fetch and decode instructions.
- the PC 186 stored in register R 4 may be the active program counter when executing bytecodes.
- the micro-PC 188 stored in register R 12 may be the active program counter when fetching and executing micro-sequences. Asserting the status register's micro-sequence-active bit causes the micro-PC 188 (register R 12 ) to become the active program counter instead of the PC 186 .
- the contents of the field 166 associated with the micro-sequenced opcode is loaded into the micro-PC 188 .
- the JSM 102 begins fetching and decoding the instructions of the micro-sequence.
- the PC 186 preferably is incremented by a suitable value to point the program counter to the next instruction following the opcode that triggered the micro-sequence.
- the micro-sequence-active bit within the status register R 15 may only be changed when the first instruction of the micro-sequence enters the execute phase of JSM 102 pipe.
- the switch from PC 186 to the micro-PC 188 preferably is effective immediately after the micro-sequenced instruction is decoded, thereby reducing the latency.
- the micro-sequence may perform any suitable task, such as emulating an instruction from an instruction set not directly executable by the JSM 102 , and then end with a predetermined instruction from the C-ISA called “RtuS” (return from micro-sequence) that indicates the end of the sequence.
- This C-ISA instruction causes a switch from the micro-PC (register R 12 ) to the PC (register R 4 ).
- the PC 186 was previously incremented so that the value of the PC 186 points to the next instruction to be decoded.
- the JSM 102 directly executes JavaTM bytecodes to accelerate JavaTM program execution. Where execution can be made more efficient using stack-based operations, the JSM 102 may replace direct execution of the JavaTM bytecode with a series of one or more register-based C-ISA instructions. Thus, the JSM 102 directly implements two instruction sets: JavaTM bytecodes; and register-based C-ISA instructions. In accordance with embodiments of the invention, the JSM 102 also emulates a third instruction set.
- the JSM 102 emulates direct execution of the other instruction sets, such as other CPU-independent instructions sets.
- One illustrative CPU-independent instruction set is in the “.NET” (pronounced “dot net”) framework developed by Microsoft Corporation, of Redmond Wash.
- the .NET framework is a platform for creation of web-based services and applications.
- Programs generated under the illustrative .NET framework compile to a CPU-independent instruction set called the Microsoft Intermediate Language (MSIL).
- MSIL Microsoft Intermediate Language
- Programs compiled to MSIL that a user wishes to execute are provided to another program called an execution engine termed the common language runtime (CLR).
- CLR common language runtime
- the JSM 102 emulates direct execution of other instruction sets, such as MSIL, which limits or eliminates the need for an execution engine.
- the instruction set which the JSM 102 emulates may be of an arbitrary number of bits. The feature of emulating an instruction set of an arbitrary number of bits takes the further discussion along two paths: a first path for emulated instruction sets having fewer or the same number of bits as JavaTM bytecodes; and a second path for emulated instruction sets having more bits than JavaTM bytecodes.
- FIG. 5A illustrates a flow diagram of a method to prepare the JSM 102 for emulation of the instruction set having the same or fewer bits than that of JavaTM bytecodes.
- the process starts (block 500 ) and thereafter a set of C-ISA-based emulation programs are written to a memory accessible to the JSM (block 502 ), such as writing micro-sequence storage 180 by MPU 104 .
- each of the C-ISA-based emulation programs are register-based programs designed to emulate an instruction of an instruction set not directly executable by the JSM 102 , such as NET MSIL.
- the vector table 162 FIG.
- the MPU 104 populates the vector table 162 and asserts the micro-sequenced field 168 for each entry.
- the JSM 102 is ready to emulate execution of an instruction set that is not directly executable by the JSM 102 .
- FIG. 5B illustrates a flow diagram of a method to emulate the instruction set once the preparations of FIG. 5A are complete.
- the illustrative process starts (block 505 ) and an instruction from the emulated instruction set is fetched (block 506 ), possibly by the instruction fetch logic 154 ( FIG. 2 ).
- the decode logic 152 uses the fetched instruction as an index into the vector table 162 (block 508 ).
- each instruction of the vector table has its micro-sequenced field 168 asserted
- the decode logic 152 triggers fetching and begins execution (block 510 ) of the C-ISA programs pointed to by the vector table, and in this case each C-ISA program emulates at least one instruction of the instruction of the instruction set not directly executable by the JSM 102 . Thereafter, a determination is made as to whether there are further instructions to emulate (block 512 ). If so, the illustrate method fetches the next instruction (block 506 ), otherwise the illustrative method ends (block 512 ).
- one instruction of an instruction set to be emulated has a value 0xC4, the same as the JavaTM WIDE opcode.
- the decode logic 152 treats the 0xC4 value as an executable code, and use the value as an index into the vector table to determine if the value triggers a micro-sequence. Because of previous preparation for emulating direct execution of an instruction set, the vector table entry at index 0xC4 points to a C-ISA instruction that is executed by the JSM 102 to emulate the instruction having a 0xC4 value.
- the 0xC4 value is merely illustrative, and indexing into the vector table and triggering C-ISA programs occurs for all values of the emulated instruction set.
- the non-supported instruction set is executed without the need for, or at least a reduced need for, an execution engine to translate to machine language.
- the emulated instruction set need not have the same number of bits as Java bytecodes. This gives rise to several alternatives for operation.
- the emulated instruction set could be aligned on a byte boundary, leaving unused bits in the most or least significant positions.
- Another implementation is to have the bits of the emulated instruction set in the middle of the available instruction set size, leaving the pad bits on either end. If the pad bits are allowed to take arbitrary values, multiple full addresses (emulated bits plus pad bits) may point to the same micro-sequences. In some embodiments, the various pad bits are set to zero. Further still, the pad bits could themselves be the operands for the emulated instruction, negating the need for the micro-sequences to fetch operands.
- the illustrative method of FIG. 5 assumes that the instruction set to be emulated has the same or fewer bits than the JavaTM bytecodes set directly executable by the JSM 102 .
- the decode logic 152 using the vector table 162 , can find precisely the C-ISA program that performs the emulation.
- further embodiments of the invention are not limited to emulation of instruction sets having the same or fewer bits than JavaTM bytecodes.
- the instruction to be emulated may have any number of bits greater than that of a JavaTM opcode.
- FIG. 6A illustrates a flow diagram of a method to prepare the JSM 102 for emulation of the instruction set having more bits than that of JavaTM bytecodes.
- the process starts (block 600 ) and thereafter a set of C-ISA-based emulation programs are written to a memory accessible to the JSM (block 602 ).
- each of the C-ISA-based emulation programs are register-based programs designed, at least in part, to emulate instruction of an instruction set not directly executable by the JSM 102 , such as .NET MSIL.
- the vector table 162 FIG.
- the JSM 102 is ready to emulate execution of an instruction set that is not directly executable by the JSM 102 .
- the illustrative process starts (block 605 ), and at least a portion of an instruction from the emulated instruction set is fetched (block 606 ), possibly by the instruction fetch logic 154 ( FIG. 2 ).
- each instruction of the illustrative instruction set to be emulated has more bits than JavaTM bytecodes, in some cases the first N bits of the instruction are fetched. In other cases the last N bits of the instruction are fetched. In illustrative cases where the JSM 102 directly executes JavaTM bytecodes, N may be equal to eight.
- the decode logic 152 uses the portion of the fetched instruction as an index into the vector table 162 (block 608 ). Because each instruction of the vector table has its micro-sequenced field 168 asserted, the decode logic 152 triggers fetching and begins execution (block 609 ) of a C-ISA program pointed to by the vector table. Thereafter, a determination is made as to whether there are more instructions to execute (block 610 ). If so, further instruction portions are fetched (block 606 ). If not, the illustrative method ends (block 612 ).
- the decode logic 152 starts (block 614 ) a C-ISA program, and thereafter the program reads the remaining portion of the instruction to be emulated (block 616 ). In the case where the decode logic 152 indexes into the vector table 162 based on the first N bits, the C-ISA program reads the remaining M-N bits (where M is the number of bits of each instruction of the instruction set to be emulated).
- the C-ISA program reads the first M-N bits of the instruction. Based on the remaining bits read, the C-ISA program branches to further portions of the series of instructions (block 618 ) that emulate the desired instruction. Thereafter, the C-ISA portion of the process ends (block 620 ).
- the non-supported instruction set is executed without the need for, or at least a reduced need for, an execution engine and in spite of the fact that each instruction of the non-supported instruction set has more bits than a primary instruction set of the JSM 102 , such as JavaTM.
- System 100 may be implemented as a mobile cell phone such as that shown in FIG. 7 .
- the mobile communication device includes an integrated keypad 712 and display 714 .
- the JSM processor 102 and MPU processor 104 and other components may be included in electronics package 710 connected to the keypad 712 , display 714 , and radio frequency (“RF”) circuitry 716 .
- the RF circuitry 716 may be connected to an antenna 718 .
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Abstract
Description
- This application claims the benefit of European Patent Application No. 04291918.3, filed Jul. 27, 2004, incorporated by reference herein as if reproduced in full below. This application is related to co-pending and commonly assigned application Serial No. ______ [Attorney Docket No. TI-38598 (1962-23900)] entitled “Method And System To Disable The ‘WIDE’ Prefix.”
- 1. Technical Field of the Invention
- The present invention relates to processors and more particularly to processors that execute Java™ bytecodes.
- 2. Background Information
- Java™ is a programming language that, at the source code level, is similar to object oriented programming languages such as C++. Java™ language source code is compiled into an intermediate representation based on a plurality “bytecodes” that define specific tasks. In some implementations, the bytecodes are further compiled to machine language for a particular processor. In order to speed the execution of Java™ language programs, some processors are specifically designed to execute some of the Java™ bytecodes directly.
- Many times, a processor that directly executes Java™ bytecodes is paired with a general purpose processor so as to accelerate Java™ program execution in a general or special purpose machine. It would be advantageous to provide accelerations, similar to those seen for directly executed Java™ bytecodes, in other languages and development environments.
- The problems noted above are solved in large part by a method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a table to an index location (the index location based on the at least a portion of the instruction), executing a first series of instructions directly executable by the processor (the first series of instructions pointed to by the table at the index location), and thereby emulating execution of the instruction from the first instruction set.
- Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, semiconductor companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”. Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.
- The terms “asserted” and “not asserted” are used herein to refer to Boolean conditions. An asserted state need not necessarily be a logical 1 or a high voltage state, and thus could equally apply to an asserted being a logical 0 or a low voltage state. Thus, in some embodiments an asserted state may be a logical 1 and a not-asserted state may be a logical 0, with de-assertion changing the state from a logical 1 to a logical 0. Equivalently, an asserted state may be a
logic 0 and a not-asserted state may a logical 1 with a de-assertion being a change from a logical 0 to a logical 1. - For a more detailed description of the preferred embodiments of the present invention, reference will now be made to the accompanying drawings, wherein:
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FIG. 1 shows a diagram of a system in accordance with embodiments of the invention; -
FIG. 2 shows a block diagram of the JSM ofFIG. 1 in accordance with embodiments of the invention; -
FIG. 3 shows various registers used in the JSM ofFIGS. 1 and 2 ; -
FIG. 4 illustrates operation of the JSM to trigger “micro-sequences”; -
FIG. 5 (comprisingFIGS. 5A and 5B ) illustrates a method in accordance with embodiments of the invention; and -
FIG. 6 (comprisingFIGS. 6A and 6B ) illustrates a method in accordance with further embodiments of the invention; and -
FIG. 7 depicts an illustrative embodiment of the system described herein. - The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, unless otherwise specified. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiments is meant only to be illustrative of those embodiments, and not intended to intimate that the scope of the disclosure, is limited to those embodiments.
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FIG. 1 shows asystem 100 in accordance with embodiments of the invention. As shown, the system may comprise at least twoprocessors Processor 102 may be referred to for purposes of this disclosure as a Java Stack Machine (“JSM”) andprocessor 104 may be referred to as a Main Processor Unit (“MPU”).System 100 may also comprisememory 106 coupled to both the JSM 102 and MPU 104. At least a portion of thememory 106 may be shared by both processors, and if desired, other portions of thememory 106 may be designated as private to one processor or the other.System 100 also comprises a Java Virtual Machine (“JVM”) 108,compiler 110, and adisplay 114. The JVM 108 may comprise a combination of software and hardware. The software may comprise thecompiler 110 and the hardware may comprise the JSM 102. The JVM may comprise a class loader, bytecode verifier, garbage collector, and a bytecode interpreter loop to interpret the bytecodes that are not executed on the JSMprocessor 102. Other components (not specifically shown) may be included as desired for various applications. - Java™ language source code is converted or compiled to a series of
bytecodes 112, with each individual one of the bytecodes referred to as an “opcode.”Bytecodes 112 may be provided to the JVM 108, possibly compiled bycompiler 110, and provided to the JSM 102 and/or MPU 104 for execution. In accordance with some embodiments of the invention, the JSM 102 may execute at least some Java™ bytecodes directly. When appropriate, however, the JVM 108 may also request the MPU 104 to execute one or more Java™ bytecodes not executed or executable by the JSM 102. In addition to executing compiled Java™ bytecodes, the MPU 104 also may execute non-Java instructions. The MPU 104 may thus also host an operating system (“O/S”) (not specifically shown) which performs various functions such as system memory management, system task management that schedules the software aspects of theJVM 108 and most or all other native tasks running on the system, management of thedisplay 114, and receiving input from input devices (not specifically shown). Java™ code, whether executed on the JSM 102 or MPU 104, may be used to perform any one of a variety of applications such as multimedia, games or web based applications in thesystem 100, while non-Java™ code, which may comprise the O/S and other native applications, may still run on the system on theMPU 104. - Most Java™ bytecodes perform stack-based operations. For example, an “IADD” (integer add) Java TM opcode pops two integers off the top of the stack, adds them together, and pushes the sum back on the stack. A “simple” opcode is one in which the
JSM 102 may perform an immediate operation either in a single cycle (e.g., an IADD opcode) or in several cycles (e.g., “DUP2_X2”). A “complex” opcode is one in which several memory accesses may be required to be made within the JVM data structure for various verifications (e.g., NULL pointer, array boundaries). - A
JSM processor 102 in accordance with embodiments of the invention may execute, in addition to the Java™ bytecodes, a second instruction set other than Java™ bytecodes. In some embodiments, the second instruction set may comprise register-based and memory-based operations rather than stack-based operations. This second instruction set complements the Java™ instruction set and, accordingly, may be referred to as a complementary instruction set architecture (“C-ISA”). By complementary, it is meant that some complex Java™ bytecodes may be replaced by a “micro-sequence” comprising C-ISA instructions. The execution of Java™ code may thus be made more efficient and run faster by replacing some opcodes by more efficient micro-sequences of C-ISA instructions, and as discussed more fully below, other instruction sets may be emulated using the mirco-sequences. TheJSM 102 thus comprises a stack-based architecture for direct execution of Java™ bytecodes, combined with a register-based architecture for direct execution of memory based micro-sequences of C-ISA instructions. Because various data structures described herein are JVM-dependent, and thus may change from one JVM implementation to another, the software flexibility of the micro-sequence provides a mechanism for various JVM optimizations now known or later developed. -
FIG. 2 shows an illustrative block diagram of theJSM 102. As shown, the JSM comprises acore 120 coupled todata storage 122 andinstruction storage 130. The components of the core 120 preferably comprise a plurality ofregisters 140, address generation units (“AGUs”) 142 and 147, micro-translation lookaside buffers (micro-TLBs) 144 and 156, amulti-entry micro-stack 146, an arithmetic logic unit (“ALU”) 148, amultiplier 150, decodelogic 152, and instruction fetchlogic 154. Data pointed to by operands of opcodes may be retrieved fromdata storage 122 or from the micro-stack 146, and processed by theALU 148. Instructions may be fetched frominstruction storage 130 by fetchlogic 154 and decoded bydecode logic 152. TheAGUs 142 may be used to calculate addresses based, at least in part, on data contained in theregisters 140.AGU 147 couples to the micro-stack 146 and may manage overflow and underflow conditions in the micro-stack 146. The micro-TLBs 144 and 156 perform the function of a cache for the address translation and memory protection information bits that are under the control of the operating system running on theMPU 104. - Java™ bytecodes may pop data from and push data onto the micro-stack 146, which micro-stack 146 preferably comprises a plurality of gates in the
core 120 of theJSM 102. The micro-stack 146 preferably comprises the top x entries of a larger stack that is implemented indata storage 122. Although the value of x may be vary in different embodiments, in accordance with at least some embodiments the size x of the micro-stack may be the top eight entries in the larger, memory-based stack. By implementing the micro-stack 146 hardware in thecore 120 of theprocessor 102, access to the data contained in the micro-stack 146 is very fast, although any particular access speed is not a limitation on this disclosure. -
ALU 148 adds, subtracts, and shifts data. Themultiplier 150 may be used to multiply two values together in one or more cycles. The instruction fetchlogic 154 fetches instructions frominstruction storage 130, which instructions may be decoded bydecode logic 152. Because theJSM 102 is configured to process instructions from at least two instruction sets, thedecode logic 152 comprises at least two modes of operation, one mode for each instruction set. As such, thedecode logic unit 152 may comprise a Java TM mode in which Java™ bytecodes may be decoded, and a C-ISA mode in which micro-sequences of C-ISA instructions may be decoded. - The
data storage 122 comprises data cache (“D-cache”) 124 and data random access memory (“D-RAM”) 126. The stack (excluding the micro-stack 146), arrays and non-critical data may be stored in the D-cache 124, while local variables and data may be stored in D-RAM 126. Theinstruction storage 130 may comprise instruction RAM (“I-RAM”) 132 and instruction cache (“I-CACHE”) 134. The I-RAM 132 may be used for opcodes or micro-sequences, and the I-CACHE 134 may be used to store other types of Java™ bytecode and mixed Java™/C-ISA instructions. - Referring now to
FIG. 3 , theregisters 140 may comprise a plurality of registers designated as R0-R15. Registers R0-R3, R5, R8-R11 and R13-R14 may be used as general purposes (“GP”) registers for any purpose. Other registers, and some of the GP registers, may be used for specific purposes. For example, registers R4 and R12 may each be used to store program counters, with R4 storing a program counter (“PC”) for a stream of bytecodes, and R12 storing a micro-program counter (“micro-PC”) for executing micro-sequences. The use of the PC and micro-PC will be explained in greater detail below. In addition to use as a GP register, register R5 may be used to store the base address of a portion of memory in which Java TM local variables may be stored when used by a Java™ method. The top of the micro-stack 146 can be referenced by the values in registers R6 and R7, and the top of the micro-stack may have a matching address in external memory pointed to by register R6. The values contained in the micro-stack are the latest updated values, while their corresponding values in external memory may or may not be up to date. Register R7 provides the data value stored at the top of the micro-stack. Registers R8 and R9 may also be used to hold the address index 0 (“AI0”) and address index 1 (“AI1”). Register R14 may also be used to hold the indirect register index (“IRI”). Register R15 may be used for status and control of theJSM 102. At least one bit (called the “Micro-Sequence-Active” bit, not specifically shown) in status register R15 is used to indicate whether theJSM 102 is executing by way of a micro-sequence. This bit controls, in particular, which program counter is used (R4 (PC) or R12 (micro-PC)) to fetch the next instruction. Another bit of the status and control register R15 (the bit termed herein the “WIDE ENABLE flag” or “WIDE ENABLE bit”, and given the reference number 198) is used indicate whether the Java™ WIDE opcode is treated as a non-executed prefix, or whether the WIDE value 0xC4 (hexadecimal value C4) may be assigned other functions directly executable by the processor or executable by way of a micro-sequence. In alternative embodiments, the WIDE ENABLE flag may in other portions of theJSM processor 102, such as register R151 in the decode logic 152 (FIG. 2 ). - Referring again to
FIG. 2 , theWIDE ENABLE flag 198 of illustrative register R15 (not specifically shown inFIG. 2 ) preferably couples to thedecode logic 152 by way ofline 196. When theWIDE ENABLE flag 198 is asserted, thedecode logic 152, and indeed theprocessor 102, treat WIDE as a prefix that modifies the operand width of an opcode that immediately follows the WIDE opcode. However, when theWIDE ENABLE flag 198 is not asserted, then the 0xC4 value is treated like other opcodes that may be directly executable by theprocessor 102. Thus, when theWIDE ENABLE flag 198 is not asserted the 0xC4 value can perform any desired functionality, and that functionality need not necessarily be related to operand width. Moreover, the 0xC4 value may then also be utilized as a trigger for execution of a micro-sequence. -
FIG. 4 illustrates the operation of theJSM 102 with regard to triggering of micro-sequences based on Java™ bytecodes, including the 0xC4 opcode when theWIDE ENABLE flag 198 is not asserted. In particular,FIG. 4 illustrates theinstruction storage 130, thedecode logic 152, and a micro-sequence vector table 162. Thedecode logic 152 accesses theinstruction storage 130 and a micro-sequence vector table 162. Thedecode logic 152 retrieves instructions (e.g., instruction 170) frominstruction storage 130 by way of instruction fetch logic 154 (FIG. 2 ) and decodes the instructions to determine the type of instruction. If theinstruction 170 is a WIDE opcode, and theWIDE ENABLE flag 198 is asserted, the decode logic instructs the processor with regard to fetch width regarding the next opcode, and the process starts anew. If, however, theWIDE ENABLE flag 198 is not asserted and the 0xC4 opcode is the fetched opcode, theJSM 102 either directly executes the opcode to perform any desirable function, or triggers a micro-sequence to perform any desirable function. - The micro-sequence vector table 162 may be implemented in the
decode logic 152, or as separate logic in theJSM 102. The micro-sequence vector table 162 preferably comprises a plurality ofentries 164, such as one entry for each opcode that the JSM may receive. For example, if there are a total of 256 bytecodes, the micro-sequence vector table 162 preferably comprises at least 256 entries. Eachentry 164 may have at least two fields—afield 166 and an associatedfield 168.Field 168 may comprise a single bit that indicates whether theinstruction 170 is to be directly executed, or whether the associatedfield 166 contains a reference to a micro-sequence. For example, an assertedbit 168 may indicate the corresponding opcode is directly executable by the JSM, and anon-asserted bit 168 may indicate that the associatedfield 166 contains a reference to a micro-sequence. - If the
bit 168 indicates the associatedfield 166 includes a reference to a micro-sequence, the reference may comprise the full starting address ininstruction storage 130 of the micro-sequence, or a part of the starting address that can be concatenated with a base address that may be programmable in the JSM. In the former case,field 166 may provide as many address bits as are required to access the full memory space. In the latter case, a register within the JSM registers 140, or preferably within a JSM configuration register accessible through an indirect addressing mechanism using the IRI register, is programmed to hold the base address. In these embodiments the vector table 162 may supply only the offset to access the start of the micro-sequence. Most or all JSMinternal registers 140 and the vector table 162 are accessible by theMPU 104, and therefore theentries 164 of the vector table 162 may be modified by the JVM as necessary. Although not required, the offset addressing technique may be preferred to reduce the number of bits needed withinfield 166. At least aportion 180 of theinstruction storage 130 may be allocated for storage of micro-sequences and thus the starting address may point to a location inmicro-sequence storage 180 at which a particular micro-sequence can be found. Theportion 180 may be implemented in I-RAM 132 (FIG. 2 ) accessible by theMPU 104, which thus allows the micro-sequences to be changed. - In operation, the
decode logic 152 uses an opcode, including the 0xC4 opcode when theWIDE ENABLE flag 198 is not asserted, as an index into micro-sequence vector table 162. Once thedecode logic 152 locates the indexedentry 164, thedecode logic 152 examines the associatedbit 168 to determine whether the opcode triggers a micro-sequence. If thebit 168 indicates that the opcode can be directly processed and executed by the JSM, then the instruction is so executed. If, however, thebit 168 indicates that the opcode triggers a micro-sequence, then thedecode logic 152 preferably changes the opcode into a “NOP,” executes the NOP opcode, asserts the micro-sequence-active bit in the status register R15 (not specifically shown), and begins fetching the first micro-sequence instruction. Changing the opcode into a NOP while fetching the first instruction of the micro-sequence permits the JSM to process multi-cycle instructions that are further advanced in the pipe without additional latency. The micro-sequence-active bit may be asserted at any suitable time, such as when the micro-sequence enters the JSM execution stage (not specifically shown). - The
JSM 102 implements two program counters—the PC 186 (register R4) and the micro-PC 188 (register R12). In accordance with some embodiments, one of these two program counters is the active program counter used to fetch and decode instructions. ThePC 186 stored in register R4 may be the active program counter when executing bytecodes. The micro-PC 188 stored in register R12 may be the active program counter when fetching and executing micro-sequences. Asserting the status register's micro-sequence-active bit causes the micro-PC 188 (register R12) to become the active program counter instead of thePC 186. Also, the contents of thefield 166 associated with the micro-sequenced opcode is loaded into themicro-PC 188. At this point, theJSM 102 begins fetching and decoding the instructions of the micro-sequence. At or about the time the decode logic begins using themicro-PC 188 from register R12, thePC 186 preferably is incremented by a suitable value to point the program counter to the next instruction following the opcode that triggered the micro-sequence. In at least some embodiments, the micro-sequence-active bit within the status register R15 may only be changed when the first instruction of the micro-sequence enters the execute phase ofJSM 102 pipe. The switch fromPC 186 to themicro-PC 188 preferably is effective immediately after the micro-sequenced instruction is decoded, thereby reducing the latency. - The micro-sequence, including the micro-sequence pointed to based on the 0xC4 opcode, may perform any suitable task, such as emulating an instruction from an instruction set not directly executable by the
JSM 102, and then end with a predetermined instruction from the C-ISA called “RtuS” (return from micro-sequence) that indicates the end of the sequence. This C-ISA instruction causes a switch from the micro-PC (register R12) to the PC (register R4). Preferably, thePC 186 was previously incremented so that the value of thePC 186 points to the next instruction to be decoded. - Thus, the
JSM 102 directly executes Java™ bytecodes to accelerate Java™ program execution. Where execution can be made more efficient using stack-based operations, theJSM 102 may replace direct execution of the Java™ bytecode with a series of one or more register-based C-ISA instructions. Thus, theJSM 102 directly implements two instruction sets: Java™ bytecodes; and register-based C-ISA instructions. In accordance with embodiments of the invention, theJSM 102 also emulates a third instruction set. - In particular, and in accordance with embodiments of the invention, the
JSM 102 emulates direct execution of the other instruction sets, such as other CPU-independent instructions sets. One illustrative CPU-independent instruction set is in the “.NET” (pronounced “dot net”) framework developed by Microsoft Corporation, of Redmond Wash. The .NET framework is a platform for creation of web-based services and applications. Programs generated under the illustrative .NET framework compile to a CPU-independent instruction set called the Microsoft Intermediate Language (MSIL). Programs compiled to MSIL that a user wishes to execute are provided to another program called an execution engine termed the common language runtime (CLR). In accordance with embodiments of the invention, theJSM 102 emulates direct execution of other instruction sets, such as MSIL, which limits or eliminates the need for an execution engine. Further in accordance with embodiments of the invention, the instruction set which theJSM 102 emulates may be of an arbitrary number of bits. The feature of emulating an instruction set of an arbitrary number of bits takes the further discussion along two paths: a first path for emulated instruction sets having fewer or the same number of bits as Java™ bytecodes; and a second path for emulated instruction sets having more bits than Java™ bytecodes. -
FIG. 5A illustrates a flow diagram of a method to prepare theJSM 102 for emulation of the instruction set having the same or fewer bits than that of Java™ bytecodes. The process starts (block 500) and thereafter a set of C-ISA-based emulation programs are written to a memory accessible to the JSM (block 502), such as writingmicro-sequence storage 180 byMPU 104. In the illustrative case ofFIG. 5 , each of the C-ISA-based emulation programs are register-based programs designed to emulate an instruction of an instruction set not directly executable by theJSM 102, such as NET MSIL. Thereafter, the vector table 162 (FIG. 4 ) is populated with pointers to each emulation program, and the micro-sequenced field 168 (FIG. 4 ) for each entry is asserted (block 503), and the preparation processor ends (block 504). In some embodiments, theMPU 104 populates the vector table 162 and asserts themicro-sequenced field 168 for each entry. At this point, theJSM 102 is ready to emulate execution of an instruction set that is not directly executable by theJSM 102. -
FIG. 5B illustrates a flow diagram of a method to emulate the instruction set once the preparations ofFIG. 5A are complete. After preparing theJSM 102 for emulation of the instruction set (FIG. 5A ), the illustrative process starts (block 505) and an instruction from the emulated instruction set is fetched (block 506), possibly by the instruction fetch logic 154 (FIG. 2 ). Thereafter, thedecode logic 152 uses the fetched instruction as an index into the vector table 162 (block 508). Because each instruction of the vector table has itsmicro-sequenced field 168 asserted, thedecode logic 152 triggers fetching and begins execution (block 510) of the C-ISA programs pointed to by the vector table, and in this case each C-ISA program emulates at least one instruction of the instruction of the instruction set not directly executable by theJSM 102. Thereafter, a determination is made as to whether there are further instructions to emulate (block 512). If so, the illustrate method fetches the next instruction (block 506), otherwise the illustrative method ends (block 512). - For purposes of illustration, assume that one instruction of an instruction set to be emulated has a value 0xC4, the same as the Java™ WIDE opcode. Assuming the
WIDE ENABLE flag 198 is not asserted, thedecode logic 152 treats the 0xC4 value as an executable code, and use the value as an index into the vector table to determine if the value triggers a micro-sequence. Because of previous preparation for emulating direct execution of an instruction set, the vector table entry at index 0xC4 points to a C-ISA instruction that is executed by theJSM 102 to emulate the instruction having a 0xC4 value. The 0xC4 value is merely illustrative, and indexing into the vector table and triggering C-ISA programs occurs for all values of the emulated instruction set. Thus, the non-supported instruction set is executed without the need for, or at least a reduced need for, an execution engine to translate to machine language. - As mentioned, the emulated instruction set need not have the same number of bits as Java bytecodes. This gives rise to several alternatives for operation. For example, the emulated instruction set could be aligned on a byte boundary, leaving unused bits in the most or least significant positions. Another implementation is to have the bits of the emulated instruction set in the middle of the available instruction set size, leaving the pad bits on either end. If the pad bits are allowed to take arbitrary values, multiple full addresses (emulated bits plus pad bits) may point to the same micro-sequences. In some embodiments, the various pad bits are set to zero. Further still, the pad bits could themselves be the operands for the emulated instruction, negating the need for the micro-sequences to fetch operands.
- The illustrative method of
FIG. 5 assumes that the instruction set to be emulated has the same or fewer bits than the Java™ bytecodes set directly executable by theJSM 102. In this circumstance, thedecode logic 152, using the vector table 162, can find precisely the C-ISA program that performs the emulation. However, further embodiments of the invention are not limited to emulation of instruction sets having the same or fewer bits than Java™ bytecodes. In the further embodiments, the instruction to be emulated may have any number of bits greater than that of a Java™ opcode. -
FIG. 6A illustrates a flow diagram of a method to prepare theJSM 102 for emulation of the instruction set having more bits than that of Java™ bytecodes. In particular, the process starts (block 600) and thereafter a set of C-ISA-based emulation programs are written to a memory accessible to the JSM (block 602). In the illustrative case ofFIG. 6A , each of the C-ISA-based emulation programs are register-based programs designed, at least in part, to emulate instruction of an instruction set not directly executable by theJSM 102, such as .NET MSIL. Thereafter, the vector table 162 (FIG. 4 ) is populated with pointers to each emulation program, and the micro-sequenced field 168 (FIG. 4 ) for each entry is asserted (block 603), and the illustrative method ends. At this point, theJSM 102 is ready to emulate execution of an instruction set that is not directly executable by theJSM 102. - Referring to
FIG. 6B , after preparing theJSM 102 for emulation of the instruction set (FIG. 6A ), the illustrative process starts (block 605), and at least a portion of an instruction from the emulated instruction set is fetched (block 606), possibly by the instruction fetch logic 154 (FIG. 2 ). Keeping in mind that each instruction of the illustrative instruction set to be emulated has more bits than Java™ bytecodes, in some cases the first N bits of the instruction are fetched. In other cases the last N bits of the instruction are fetched. In illustrative cases where theJSM 102 directly executes Java™ bytecodes, N may be equal to eight. Thereafter, thedecode logic 152 uses the portion of the fetched instruction as an index into the vector table 162 (block 608). Because each instruction of the vector table has itsmicro-sequenced field 168 asserted, thedecode logic 152 triggers fetching and begins execution (block 609) of a C-ISA program pointed to by the vector table. Thereafter, a determination is made as to whether there are more instructions to execute (block 610). If so, further instruction portions are fetched (block 606). If not, the illustrative method ends (block 612). - Because the portion of the instruction fetched does not fully identify the instruction of the instruction set, executing the series of instructions pointed by the vector table triggers further action on the part of the C-ISA program to identify the instruction. Still referring to
FIG. 6 , thedecode logic 152 starts (block 614) a C-ISA program, and thereafter the program reads the remaining portion of the instruction to be emulated (block 616). In the case where thedecode logic 152 indexes into the vector table 162 based on the first N bits, the C-ISA program reads the remaining M-N bits (where M is the number of bits of each instruction of the instruction set to be emulated). In the case where thedecode logic 152 indexes into the vector table 162 based on the last N bits, the C-ISA program reads the first M-N bits of the instruction. Based on the remaining bits read, the C-ISA program branches to further portions of the series of instructions (block 618) that emulate the desired instruction. Thereafter, the C-ISA portion of the process ends (block 620). Thus, the non-supported instruction set is executed without the need for, or at least a reduced need for, an execution engine and in spite of the fact that each instruction of the non-supported instruction set has more bits than a primary instruction set of theJSM 102, such as Java™. -
System 100 may be implemented as a mobile cell phone such as that shown inFIG. 7 . As shown, the mobile communication device includes anintegrated keypad 712 anddisplay 714. TheJSM processor 102 andMPU processor 104 and other components may be included inelectronics package 710 connected to thekeypad 712,display 714, and radio frequency (“RF”)circuitry 716. TheRF circuitry 716 may be connected to anantenna 718. - While the various embodiments of the invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. The embodiments described herein are illustrative only, and are not intended to be limiting. Many variations and modifications of the invention disclosed herein are possible and are within the scope of the invention. For example, any instruction set of any size may be emulated by the
JSM 102, not just NET CLR. Each and every claim is incorporated into the specification as an embodiment of the present invention.
Claims (20)
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US11/188,827 Active 2026-08-09 US7493476B2 (en) | 2004-07-27 | 2005-07-25 | Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence |
US11/188,670 Active 2031-03-01 US8380906B2 (en) | 2004-07-27 | 2005-07-25 | Method and system for implementing interrupt service routines |
US11/188,311 Active 2026-10-10 US7533250B2 (en) | 2004-07-27 | 2005-07-25 | Automatic operand load, modify and store |
US11/188,309 Abandoned US20060026407A1 (en) | 2004-07-27 | 2005-07-25 | Delegating tasks between multiple processor cores |
US11/188,411 Active 2028-03-27 US7606977B2 (en) | 2004-07-27 | 2005-07-25 | Context save and restore with a stack-based memory structure |
US11/188,310 Active 2029-05-11 US8046748B2 (en) | 2004-07-27 | 2005-07-25 | Method and system to emulate an M-bit instruction set |
US11/188,592 Active 2029-02-28 US8024554B2 (en) | 2004-07-27 | 2005-07-25 | Modifying an instruction stream using one or more bits to replace an instruction or to replace an instruction and to subsequently execute the replaced instruction |
US11/189,245 Abandoned US20060026126A1 (en) | 2004-07-27 | 2005-07-26 | Method and system for making a java system call |
US11/189,422 Active 2029-04-16 US7743384B2 (en) | 2004-07-27 | 2005-07-26 | Method and system for implementing an interrupt handler |
US11/189,211 Active 2028-02-02 US8024716B2 (en) | 2004-07-27 | 2005-07-26 | Method and apparatus for code optimization |
US11/189,637 Active 2028-06-25 US7752610B2 (en) | 2004-07-27 | 2005-07-26 | Method and system for thread abstraction |
US11/189,410 Active 2027-04-17 US7543285B2 (en) | 2004-07-27 | 2005-07-26 | Method and system of adaptive dynamic compiler resolution |
US11/189,367 Active 2026-10-25 US7624382B2 (en) | 2004-07-27 | 2005-07-26 | Method and system of control flow graph construction |
US11/189,411 Abandoned US20060026580A1 (en) | 2004-07-27 | 2005-07-26 | Method and related system of dynamic compiler resolution |
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US11/116,897 Abandoned US20060026397A1 (en) | 2004-07-27 | 2005-04-28 | Pack instruction |
US11/116,918 Abandoned US20060026398A1 (en) | 2004-07-27 | 2005-04-28 | Unpack instruction |
US11/116,522 Active 2029-06-29 US8185666B2 (en) | 2004-07-27 | 2005-04-28 | Compare instruction |
US11/135,796 Abandoned US20060026392A1 (en) | 2004-07-27 | 2005-05-24 | Method and system of informing a micro-sequence of operand width |
US11/186,063 Abandoned US20060026183A1 (en) | 2004-07-27 | 2005-07-21 | Method and system provide concurrent access to a software object |
US11/186,330 Abandoned US20060026394A1 (en) | 2004-07-27 | 2005-07-21 | Optimizing data manipulation in media processing applications |
US11/186,271 Active 2029-06-12 US7930689B2 (en) | 2004-07-27 | 2005-07-21 | Method and system for accessing indirect memories |
US11/186,239 Active 2027-12-15 US7574584B2 (en) | 2004-07-27 | 2005-07-21 | Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine |
US11/186,315 Active 2030-12-08 US8516496B2 (en) | 2004-07-27 | 2005-07-21 | Storing contexts for thread switching |
US11/186,036 Active 2030-06-19 US8078842B2 (en) | 2004-07-27 | 2005-07-21 | Removing local RAM size limitations when executing software code |
US11/186,062 Abandoned US20060023517A1 (en) | 2004-07-27 | 2005-07-21 | Method and system for dynamic address translation |
US11/187,199 Abandoned US20060026200A1 (en) | 2004-07-27 | 2005-07-22 | Method and system for shared object data member zones |
US11/188,503 Active 2027-01-25 US7587583B2 (en) | 2004-07-27 | 2005-07-25 | Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode |
US11/188,336 Abandoned US20060026401A1 (en) | 2004-07-27 | 2005-07-25 | Method and system to disable the "wide" prefix |
US11/188,667 Abandoned US20060026312A1 (en) | 2004-07-27 | 2005-07-25 | Emulating a direct memory access controller |
US11/188,504 Active 2026-10-13 US7500085B2 (en) | 2004-07-27 | 2005-07-25 | Identifying code for compilation |
US11/188,491 Active 2027-06-12 US7546437B2 (en) | 2004-07-27 | 2005-07-25 | Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses |
US11/188,550 Abandoned US20060026201A1 (en) | 2004-07-27 | 2005-07-25 | Method and system for multiple object representation |
US11/188,923 Abandoned US20060026322A1 (en) | 2004-07-27 | 2005-07-25 | Interrupt management in dual core processors |
US11/188,668 Active 2026-05-05 US7260682B2 (en) | 2004-07-27 | 2005-07-25 | Cache memory usable as scratch pad storage |
US11/188,502 Active 2029-03-09 US7757223B2 (en) | 2004-07-27 | 2005-07-25 | Method and system to construct a data-flow analyzer for a bytecode verifier |
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US11/188,311 Active 2026-10-10 US7533250B2 (en) | 2004-07-27 | 2005-07-25 | Automatic operand load, modify and store |
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US11/188,411 Active 2028-03-27 US7606977B2 (en) | 2004-07-27 | 2005-07-25 | Context save and restore with a stack-based memory structure |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080049690A1 (en) * | 2006-08-23 | 2008-02-28 | Motorola, Inc. | Downlink control channel signaling in wireless communication systems |
Families Citing this family (282)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4386732B2 (en) | 2002-01-08 | 2009-12-16 | セブン ネットワークス, インコーポレイテッド | Mobile network connection architecture |
US7917468B2 (en) | 2005-08-01 | 2011-03-29 | Seven Networks, Inc. | Linking of personal information management data |
US7853563B2 (en) | 2005-08-01 | 2010-12-14 | Seven Networks, Inc. | Universal data aggregation |
US8468126B2 (en) | 2005-08-01 | 2013-06-18 | Seven Networks, Inc. | Publishing data in an information community |
US7249128B2 (en) * | 2003-08-05 | 2007-07-24 | International Business Machines Corporation | Performance prediction system with query mining |
EP1622009A1 (en) * | 2004-07-27 | 2006-02-01 | Texas Instruments Incorporated | JSM architecture and systems |
US8010082B2 (en) | 2004-10-20 | 2011-08-30 | Seven Networks, Inc. | Flexible billing architecture |
WO2006045102A2 (en) | 2004-10-20 | 2006-04-27 | Seven Networks, Inc. | Method and apparatus for intercepting events in a communication system |
US7706781B2 (en) | 2004-11-22 | 2010-04-27 | Seven Networks International Oy | Data security in a mobile e-mail service |
US7643818B2 (en) * | 2004-11-22 | 2010-01-05 | Seven Networks, Inc. | E-mail messaging to/from a mobile terminal |
FI117152B (en) | 2004-12-03 | 2006-06-30 | Seven Networks Internat Oy | E-mail service provisioning method for mobile terminal, involves using domain part and further parameters to generate new parameter set in list of setting parameter sets, if provisioning of e-mail service is successful |
WO2006061463A1 (en) * | 2004-12-10 | 2006-06-15 | Seven Networks International Oy | Database synchronization |
FI120165B (en) * | 2004-12-29 | 2009-07-15 | Seven Networks Internat Oy | Synchronization of a database through a mobile network |
US7877703B1 (en) | 2005-03-14 | 2011-01-25 | Seven Networks, Inc. | Intelligent rendering of information in a limited display environment |
US8438633B1 (en) | 2005-04-21 | 2013-05-07 | Seven Networks, Inc. | Flexible real-time inbox access |
US7796742B1 (en) | 2005-04-21 | 2010-09-14 | Seven Networks, Inc. | Systems and methods for simplified provisioning |
US7200700B2 (en) * | 2005-05-19 | 2007-04-03 | Inventec Corporation | Shared-IRQ user defined interrupt signal handling method and system |
WO2006136661A1 (en) * | 2005-06-21 | 2006-12-28 | Seven Networks International Oy | Network-initiated data transfer in a mobile network |
WO2006136660A1 (en) | 2005-06-21 | 2006-12-28 | Seven Networks International Oy | Maintaining an ip connection in a mobile network |
US8069166B2 (en) | 2005-08-01 | 2011-11-29 | Seven Networks, Inc. | Managing user-to-user contact with inferred presence information |
US7895597B2 (en) * | 2005-09-15 | 2011-02-22 | Nokia Corporation | Method, apparatus and computer program product enabling full pre-emptive scheduling of green threads on a virtual machine |
US8261024B1 (en) * | 2005-09-15 | 2012-09-04 | Oracle America, Inc. | Address level synchronization of shared data |
US7590774B2 (en) * | 2005-12-01 | 2009-09-15 | Kabushiki Kaisha Toshiba | Method and system for efficient context swapping |
US7873953B1 (en) * | 2006-01-20 | 2011-01-18 | Altera Corporation | High-level language code sequence optimization for implementing programmable chip designs |
US8265349B2 (en) * | 2006-02-07 | 2012-09-11 | Qualcomm Incorporated | Intra-mode region-of-interest video object segmentation |
US7769395B2 (en) | 2006-06-20 | 2010-08-03 | Seven Networks, Inc. | Location-based operations and messaging |
KR100809294B1 (en) | 2006-03-10 | 2008-03-07 | 삼성전자주식회사 | Apparatus and method for executing thread scheduling in virtual machine |
US7538760B2 (en) * | 2006-03-30 | 2009-05-26 | Apple Inc. | Force imaging input device and system |
KR20070109432A (en) * | 2006-05-11 | 2007-11-15 | 삼성전자주식회사 | Apparatus and method for kernel aware debugging |
US7594094B2 (en) | 2006-05-19 | 2009-09-22 | International Business Machines Corporation | Move data facility with optional specifications |
US20080001717A1 (en) * | 2006-06-20 | 2008-01-03 | Trevor Fiatal | System and method for group management |
US8176491B1 (en) * | 2006-08-04 | 2012-05-08 | Oracle America, Inc. | Fast synchronization of simple synchronized methods |
US7885112B2 (en) | 2007-09-07 | 2011-02-08 | Sandisk Corporation | Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages |
US9069547B2 (en) | 2006-09-22 | 2015-06-30 | Intel Corporation | Instruction and logic for processing text strings |
US7844959B2 (en) * | 2006-09-29 | 2010-11-30 | Microsoft Corporation | Runtime optimization of distributed execution graph |
US8201142B2 (en) * | 2006-09-29 | 2012-06-12 | Microsoft Corporation | Description language for structured graphs |
US20080082644A1 (en) * | 2006-09-29 | 2008-04-03 | Microsoft Corporation | Distributed parallel computing |
US8292689B2 (en) * | 2006-10-02 | 2012-10-23 | Mattel, Inc. | Electronic playset |
US20080148241A1 (en) * | 2006-10-11 | 2008-06-19 | Scott Thomas Jones | Method and apparatus for profiling heap objects |
WO2008047180A1 (en) * | 2006-10-20 | 2008-04-24 | Freescale Semiconductor, Inc. | System and method for fetching an information unit |
US8069440B2 (en) * | 2006-10-27 | 2011-11-29 | Oracle America, Inc. | Adaptive code through self steered execution |
US8190861B2 (en) * | 2006-12-04 | 2012-05-29 | Texas Instruments Incorporated | Micro-sequence based security model |
US20080141268A1 (en) * | 2006-12-12 | 2008-06-12 | Tirumalai Partha P | Utility function execution using scout threads |
US8429623B2 (en) * | 2007-01-16 | 2013-04-23 | Oracle America Inc. | Processing engine for enabling a set of code intended for a first platform to be executed on a second platform |
US8468494B2 (en) * | 2007-01-22 | 2013-06-18 | Oracle Taleo Llc | In-line editor |
US7698534B2 (en) * | 2007-02-21 | 2010-04-13 | Arm Limited | Reordering application code to improve processing performance |
US7949848B2 (en) * | 2007-03-08 | 2011-05-24 | Arm Limited | Data processing apparatus, method and computer program product for reducing memory usage of an object oriented program |
US8693494B2 (en) | 2007-06-01 | 2014-04-08 | Seven Networks, Inc. | Polling |
US8805425B2 (en) | 2007-06-01 | 2014-08-12 | Seven Networks, Inc. | Integrated messaging |
US10452820B2 (en) * | 2007-06-26 | 2019-10-22 | International Business Machines Corporation | Thread-based software license management |
US20090031109A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Apparatus and method for fast microcode patch from memory |
US20090031107A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | On-chip memory providing for microcode patch overlay and constant update functions |
US20090031090A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Apparatus and method for fast one-to-many microcode patch |
US20090031110A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Microcode patch expansion mechanism |
US20090031108A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Configurable fuse mechanism for implementing microcode patches |
US20090031103A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Mechanism for implementing a microcode patch during fabrication |
US20090031121A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Apparatus and method for real-time microcode patch |
US7752424B2 (en) * | 2007-08-08 | 2010-07-06 | Arm Limited | Null value checking instruction |
EP2203814A4 (en) * | 2007-09-19 | 2012-11-07 | Kpit Cummins Infosystems Ltd | Mechanism to enable plug and play hardware components for semi-automatic software migration |
US8453143B2 (en) * | 2007-09-19 | 2013-05-28 | Vmware, Inc. | Reducing the latency of virtual interrupt delivery in virtual machines |
US8336031B2 (en) * | 2007-09-28 | 2012-12-18 | Texas Instruments Incorporated | Method and system of performing thread scheduling |
US20090112570A1 (en) * | 2007-10-26 | 2009-04-30 | Microsoft Corporation | Declarative model interpretation |
US9798524B1 (en) * | 2007-12-04 | 2017-10-24 | Axway, Inc. | System and method for exposing the dynamic web server-side |
US8364181B2 (en) | 2007-12-10 | 2013-01-29 | Seven Networks, Inc. | Electronic-mail filtering for mobile devices |
US8793305B2 (en) | 2007-12-13 | 2014-07-29 | Seven Networks, Inc. | Content delivery to a mobile device from a content service |
US9002828B2 (en) | 2007-12-13 | 2015-04-07 | Seven Networks, Inc. | Predictive content delivery |
US8281109B2 (en) * | 2007-12-27 | 2012-10-02 | Intel Corporation | Compressed instruction format |
US8291388B2 (en) | 2008-01-09 | 2012-10-16 | International Business Machines Corporation | System, method and program for executing a debugger |
US8107921B2 (en) | 2008-01-11 | 2012-01-31 | Seven Networks, Inc. | Mobile virtual network operator |
US20090182657A1 (en) | 2008-01-15 | 2009-07-16 | Omx Technology Ab | Distributed ranking and matching of messages |
DE102008005124A1 (en) * | 2008-01-18 | 2009-07-23 | Kuka Roboter Gmbh | Computer system, control device for a machine, in particular for an industrial robot, and industrial robots |
US8862657B2 (en) | 2008-01-25 | 2014-10-14 | Seven Networks, Inc. | Policy based content service |
US20090193338A1 (en) | 2008-01-28 | 2009-07-30 | Trevor Fiatal | Reducing network and battery consumption during content delivery and playback |
JP2009181558A (en) * | 2008-02-01 | 2009-08-13 | Panasonic Corp | Program conversion device |
US8356289B2 (en) * | 2008-03-26 | 2013-01-15 | Avaya Inc. | Efficient encoding of instrumented data in real-time concurrent systems |
US8205196B2 (en) * | 2008-04-08 | 2012-06-19 | Broadcom Corporation | Systems and methods for using operating system (OS) virtualisation for minimizing power consumption in mobile phones |
FR2930447B1 (en) * | 2008-04-25 | 2010-07-30 | Sod Conseils Rech Applic | THERAPEUTIC USE OF AT LEAST ONE BOTULINUM NEUROTOXIN FOR THE TREATMENT OF PAIN IN THE CASE OF DIABETIC NEUROPATHY |
US8359587B2 (en) * | 2008-05-01 | 2013-01-22 | Oracle America, Inc. | Runtime profitability control for speculative automatic parallelization |
US8677337B2 (en) * | 2008-05-01 | 2014-03-18 | Oracle America, Inc. | Static profitability control for speculative automatic parallelization |
US8739141B2 (en) * | 2008-05-19 | 2014-05-27 | Oracle America, Inc. | Parallelizing non-countable loops with hardware transactional memory |
US8140820B2 (en) * | 2008-05-21 | 2012-03-20 | Arm Limited | Data processing apparatus and method for handling address translation for access requests issued by processing circuitry |
US7870257B2 (en) * | 2008-06-02 | 2011-01-11 | International Business Machines Corporation | Enhancing real-time performance for java application serving |
US8787947B2 (en) | 2008-06-18 | 2014-07-22 | Seven Networks, Inc. | Application discovery on mobile devices |
WO2009153621A1 (en) * | 2008-06-19 | 2009-12-23 | Freescale Semiconductor, Inc. | A system, method and computer program product for scheduling processor entity tasks in a multiple-processing entity system |
US9058206B2 (en) * | 2008-06-19 | 2015-06-16 | Freescale emiconductor, Inc. | System, method and program product for determining execution flow of the scheduler in response to setting a scheduler control variable by the debugger or by a processing entity |
US8966490B2 (en) * | 2008-06-19 | 2015-02-24 | Freescale Semiconductor, Inc. | System, method and computer program product for scheduling a processing entity task by a scheduler in response to a peripheral task completion indicator |
US8078158B2 (en) | 2008-06-26 | 2011-12-13 | Seven Networks, Inc. | Provisioning applications for a mobile device |
US9135054B1 (en) * | 2008-07-16 | 2015-09-15 | Apple Inc. | Method and apparatus to migrate stacks for thread execution |
CN102105905B (en) * | 2008-08-07 | 2013-07-17 | 三菱电机株式会社 | Semiconductor integrated circuit device, remote controller for air conditioner |
US8407678B2 (en) * | 2008-08-27 | 2013-03-26 | Red Hat, Inc. | Method of array interception using data-flow analysis |
US8276009B2 (en) | 2008-09-05 | 2012-09-25 | Broadcom Corporation | Operating system (OS) virtualisation and processor utilization thresholds for minimizing power consumption in mobile phones |
US9675443B2 (en) | 2009-09-10 | 2017-06-13 | Johnson & Johnson Vision Care, Inc. | Energized ophthalmic lens including stacked integrated components |
US8909759B2 (en) | 2008-10-10 | 2014-12-09 | Seven Networks, Inc. | Bandwidth measurement |
US8645923B1 (en) * | 2008-10-31 | 2014-02-04 | Symantec Corporation | Enforcing expected control flow in program execution |
US8612929B2 (en) * | 2008-12-10 | 2013-12-17 | Oracle America, Inc. | Compiler implementation of lock/unlock using hardware transactional memory |
US8806457B2 (en) * | 2008-12-15 | 2014-08-12 | Apple Inc. | Deferred constant pool generation |
US8528001B2 (en) * | 2008-12-15 | 2013-09-03 | Oracle America, Inc. | Controlling and dynamically varying automatic parallelization |
US7712093B1 (en) | 2009-03-19 | 2010-05-04 | International Business Machines Corporation | Determining intra-procedural object flow using enhanced stackmaps |
US7685586B1 (en) | 2009-03-19 | 2010-03-23 | International Business Machines Corporation | Global escape analysis using instantiated type analysis |
US8195923B2 (en) * | 2009-04-07 | 2012-06-05 | Oracle America, Inc. | Methods and mechanisms to support multiple features for a number of opcodes |
US7996595B2 (en) | 2009-04-14 | 2011-08-09 | Lstar Technologies Llc | Interrupt arbitration for multiprocessors |
US8260996B2 (en) * | 2009-04-24 | 2012-09-04 | Empire Technology Development Llc | Interrupt optimization for multiprocessors |
US8321614B2 (en) * | 2009-04-24 | 2012-11-27 | Empire Technology Development Llc | Dynamic scheduling interrupt controller for multiprocessors |
US8549404B2 (en) * | 2009-04-30 | 2013-10-01 | Apple Inc. | Auditioning tools for a media editing application |
DE102009019891B3 (en) * | 2009-05-04 | 2010-11-25 | Texas Instruments Deutschland Gmbh | Microcontroller- or microprocessor unit for multiple current consumption modes, has register or memory, which contains bit fields for defining selected current consumption modes |
US8458676B2 (en) * | 2009-06-30 | 2013-06-04 | International Business Machines Corporation | Executing platform-independent code on multi-core heterogeneous processors |
US8561046B2 (en) * | 2009-09-14 | 2013-10-15 | Oracle America, Inc. | Pipelined parallelization with localized self-helper threading |
US20110087861A1 (en) * | 2009-10-12 | 2011-04-14 | The Regents Of The University Of Michigan | System for High-Efficiency Post-Silicon Verification of a Processor |
US8234431B2 (en) * | 2009-10-13 | 2012-07-31 | Empire Technology Development Llc | Interrupt masking for multi-core processors |
KR101612780B1 (en) * | 2009-11-13 | 2016-04-18 | 삼성전자주식회사 | Computing system and method for controling memory of computing system |
US20110131381A1 (en) * | 2009-11-27 | 2011-06-02 | Advanced Micro Devices, Inc. | Cache scratch-pad and method therefor |
US9009692B2 (en) * | 2009-12-26 | 2015-04-14 | Oracle America, Inc. | Minimizing register spills by using register moves |
US8578355B1 (en) * | 2010-03-19 | 2013-11-05 | Google Inc. | Scenario based optimization |
US9043731B2 (en) | 2010-03-30 | 2015-05-26 | Seven Networks, Inc. | 3D mobile user interface with configurable workspace management |
US8752058B1 (en) | 2010-05-11 | 2014-06-10 | Vmware, Inc. | Implicit co-scheduling of CPUs |
US20120005450A1 (en) * | 2010-07-02 | 2012-01-05 | International Business Machines Corporation | User control of file data and metadata blocks |
EP2599003B1 (en) | 2010-07-26 | 2018-07-11 | Seven Networks, LLC | Mobile network traffic coordination across multiple applications |
WO2012018556A2 (en) | 2010-07-26 | 2012-02-09 | Ari Backholm | Mobile application traffic optimization |
US8838783B2 (en) | 2010-07-26 | 2014-09-16 | Seven Networks, Inc. | Distributed caching for resource and mobile network traffic management |
US9077630B2 (en) | 2010-07-26 | 2015-07-07 | Seven Networks, Inc. | Distributed implementation of dynamic wireless traffic policy |
US20120030652A1 (en) * | 2010-07-30 | 2012-02-02 | Jakub Jelinek | Mechanism for Describing Values of Optimized Away Parameters in a Compiler-Generated Debug Output |
KR101983006B1 (en) | 2010-08-27 | 2019-05-29 | 사우디 아람코 테크놀로지스 컴퍼니 | Polymer compositions and methods |
US8484314B2 (en) | 2010-11-01 | 2013-07-09 | Seven Networks, Inc. | Distributed caching in a wireless network of content delivered for a mobile application over a long-held request |
US8843153B2 (en) | 2010-11-01 | 2014-09-23 | Seven Networks, Inc. | Mobile traffic categorization and policy for network use optimization while preserving user experience |
US8204953B2 (en) | 2010-11-01 | 2012-06-19 | Seven Networks, Inc. | Distributed system for cache defeat detection and caching of content addressed by identifiers intended to defeat cache |
US8166164B1 (en) | 2010-11-01 | 2012-04-24 | Seven Networks, Inc. | Application and network-based long poll request detection and cacheability assessment therefor |
WO2012060995A2 (en) | 2010-11-01 | 2012-05-10 | Michael Luna | Distributed caching in a wireless network of content delivered for a mobile application over a long-held request |
GB2499534B (en) | 2010-11-01 | 2018-09-19 | Seven Networks Llc | Caching adapted for mobile application behavior and network conditions |
US9060032B2 (en) | 2010-11-01 | 2015-06-16 | Seven Networks, Inc. | Selective data compression by a distributed traffic management system to reduce mobile data traffic and signaling traffic |
US9330196B2 (en) | 2010-11-01 | 2016-05-03 | Seven Networks, Llc | Wireless traffic management system cache optimization using http headers |
WO2012061430A2 (en) | 2010-11-01 | 2012-05-10 | Michael Luna | Distributed management of keep-alive message signaling for mobile network resource conservation and optimization |
TW201220048A (en) * | 2010-11-05 | 2012-05-16 | Realtek Semiconductor Corp | for enhancing access efficiency of cache memory |
CA2798523C (en) | 2010-11-22 | 2015-02-24 | Seven Networks, Inc. | Aligning data transfer to optimize connections established for transmission over a wireless network |
EP3422775A1 (en) | 2010-11-22 | 2019-01-02 | Seven Networks, LLC | Optimization of resource polling intervals to satisfy mobile device requests |
US9323551B2 (en) * | 2011-01-07 | 2016-04-26 | International Business Machines Corporation | Modifying code sequence with replacement parts of which non-beginning parts trigger exception when jumped to |
US9325662B2 (en) | 2011-01-07 | 2016-04-26 | Seven Networks, Llc | System and method for reduction of mobile network traffic used for domain name system (DNS) queries |
US9135037B1 (en) | 2011-01-13 | 2015-09-15 | Google Inc. | Virtual network protocol |
US8874888B1 (en) | 2011-01-13 | 2014-10-28 | Google Inc. | Managed boot in a cloud system |
US9405637B2 (en) | 2011-01-18 | 2016-08-02 | Texas Instruments Incorporated | Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting |
US8745329B2 (en) * | 2011-01-20 | 2014-06-03 | Google Inc. | Storing data across a plurality of storage nodes |
CN103339604B (en) * | 2011-01-31 | 2016-10-26 | 株式会社索思未来 | Program creating device, program creating method, processor device and multicomputer system |
US8950862B2 (en) | 2011-02-28 | 2015-02-10 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus for an ophthalmic lens with functional insert layers |
US8533796B1 (en) | 2011-03-16 | 2013-09-10 | Google Inc. | Providing application programs with access to secured resources |
US9063818B1 (en) | 2011-03-16 | 2015-06-23 | Google Inc. | Automated software updating based on prior activity |
US9237087B1 (en) | 2011-03-16 | 2016-01-12 | Google Inc. | Virtual machine name resolution |
US9698129B2 (en) | 2011-03-18 | 2017-07-04 | Johnson & Johnson Vision Care, Inc. | Stacked integrated component devices with energization |
US10451897B2 (en) | 2011-03-18 | 2019-10-22 | Johnson & Johnson Vision Care, Inc. | Components with multiple energization elements for biomedical devices |
US9233513B2 (en) | 2011-03-18 | 2016-01-12 | Johnson & Johnson Vision Care, Inc. | Apparatus for manufacturing stacked integrated component media inserts for ophthalmic devices |
US9110310B2 (en) | 2011-03-18 | 2015-08-18 | Johnson & Johnson Vision Care, Inc. | Multiple energization elements in stacked integrated component devices |
US9804418B2 (en) | 2011-03-21 | 2017-10-31 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus for functional insert with power layer |
WO2012129650A1 (en) * | 2011-03-25 | 2012-10-04 | Nanospeed Diagnostics Inc. | Lateral flow immunoassay for detecting vitamins |
US9053037B2 (en) * | 2011-04-04 | 2015-06-09 | International Business Machines Corporation | Allocating cache for use as a dedicated local storage |
GB2505103B (en) | 2011-04-19 | 2014-10-22 | Seven Networks Inc | Social caching for device resource sharing and management cross-reference to related applications |
US8621075B2 (en) | 2011-04-27 | 2013-12-31 | Seven Metworks, Inc. | Detecting and preserving state for satisfying application requests in a distributed proxy and cache system |
US8832228B2 (en) | 2011-04-27 | 2014-09-09 | Seven Networks, Inc. | System and method for making requests on behalf of a mobile device based on atomic processes for mobile network traffic relief |
EP2737742A4 (en) | 2011-07-27 | 2015-01-28 | Seven Networks Inc | Automatic generation and distribution of policy information regarding malicious mobile traffic in a wireless network |
US20130089721A1 (en) | 2011-08-02 | 2013-04-11 | Tracy Paolilli | Non-iridescent film with polymeric particles in primer layer |
US9075979B1 (en) | 2011-08-11 | 2015-07-07 | Google Inc. | Authentication based on proximity to mobile device |
US8966198B1 (en) | 2011-09-01 | 2015-02-24 | Google Inc. | Providing snapshots of virtual storage devices |
US8977755B2 (en) | 2011-12-06 | 2015-03-10 | Seven Networks, Inc. | Mobile device and method to utilize the failover mechanism for fault tolerance provided for mobile traffic management and network/device resource conservation |
US8958293B1 (en) | 2011-12-06 | 2015-02-17 | Google Inc. | Transparent load-balancing for cloud computing services |
US8918503B2 (en) | 2011-12-06 | 2014-12-23 | Seven Networks, Inc. | Optimization of mobile traffic directed to private networks and operator configurability thereof |
US9277443B2 (en) | 2011-12-07 | 2016-03-01 | Seven Networks, Llc | Radio-awareness of mobile device for sending server-side control signals using a wireless network optimized transport protocol |
US9009250B2 (en) | 2011-12-07 | 2015-04-14 | Seven Networks, Inc. | Flexible and dynamic integration schemas of a traffic management system with various network operators for network traffic alleviation |
US9832095B2 (en) | 2011-12-14 | 2017-11-28 | Seven Networks, Llc | Operation modes for mobile traffic optimization and concurrent management of optimized and non-optimized traffic |
US8861354B2 (en) | 2011-12-14 | 2014-10-14 | Seven Networks, Inc. | Hierarchies and categories for management and deployment of policies for distributed wireless traffic optimization |
US9021021B2 (en) | 2011-12-14 | 2015-04-28 | Seven Networks, Inc. | Mobile network reporting and usage analytics system and method aggregated using a distributed traffic optimization system |
WO2013095337A1 (en) * | 2011-12-19 | 2013-06-27 | Intel Corporation | A system and deterministic method for servicing msi interrupts using direct cache access |
US8800009B1 (en) | 2011-12-30 | 2014-08-05 | Google Inc. | Virtual machine service access |
WO2013103988A1 (en) | 2012-01-05 | 2013-07-11 | Seven Networks, Inc. | Detection and management of user interactions with foreground applications on a mobile device in distributed caching |
US8857983B2 (en) | 2012-01-26 | 2014-10-14 | Johnson & Johnson Vision Care, Inc. | Ophthalmic lens assembly having an integrated antenna structure |
US8983860B1 (en) | 2012-01-30 | 2015-03-17 | Google Inc. | Advertising auction system |
US9203864B2 (en) | 2012-02-02 | 2015-12-01 | Seven Networks, Llc | Dynamic categorization of applications for network access in a mobile network |
US9326189B2 (en) | 2012-02-03 | 2016-04-26 | Seven Networks, Llc | User as an end point for profiling and optimizing the delivery of content and data in a wireless network |
CN103294517B (en) * | 2012-02-22 | 2018-05-11 | 国际商业机器公司 | Stack overflow protective device, stack protection method, dependent compilation device and computing device |
US9483303B2 (en) * | 2012-02-29 | 2016-11-01 | Red Hat, Inc. | Differential stack-based symmetric co-routines |
US8677449B1 (en) | 2012-03-19 | 2014-03-18 | Google Inc. | Exposing data to virtual machines |
US9973335B2 (en) * | 2012-03-28 | 2018-05-15 | Intel Corporation | Shared buffers for processing elements on a network device |
US8812695B2 (en) | 2012-04-09 | 2014-08-19 | Seven Networks, Inc. | Method and system for management of a virtual network connection without heartbeat messages |
WO2013155208A1 (en) | 2012-04-10 | 2013-10-17 | Seven Networks, Inc. | Intelligent customer service/call center services enhanced using real-time and historical mobile application and traffic-related statistics collected by a distributed caching system in a mobile network |
CN103377132B (en) * | 2012-04-16 | 2016-02-10 | 群联电子股份有限公司 | The method in diode-capacitor storage space, Memory Controller and memorizer memory devices |
US9134980B1 (en) * | 2012-05-01 | 2015-09-15 | Amazon Technologies, Inc. | Compiler optimization in a computing environment |
JP2015521171A (en) * | 2012-05-02 | 2015-07-27 | ベドウキアン リサーチ, インコーポレイテッド | Death of bed bugs |
US9135170B2 (en) | 2012-05-15 | 2015-09-15 | Futurewei Technologies, Inc. | Memory mapping and translation for arbitrary number of memory units |
JP6050721B2 (en) * | 2012-05-25 | 2016-12-21 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US9367292B2 (en) * | 2012-06-11 | 2016-06-14 | Empire Technology Development Llc | Modulating dynamic optimizations of a computer program |
US8775631B2 (en) | 2012-07-13 | 2014-07-08 | Seven Networks, Inc. | Dynamic bandwidth adjustment for browsing or streaming activity in a wireless network based on prediction of user behavior when interacting with mobile applications |
CN102929981B (en) * | 2012-10-17 | 2016-09-21 | Tcl通力电子(惠州)有限公司 | Multimedia scanning file indexing means and device |
US9161258B2 (en) | 2012-10-24 | 2015-10-13 | Seven Networks, Llc | Optimized and selective management of policy deployment to mobile clients in a congested network to prevent further aggravation of network congestion |
KR20140054948A (en) * | 2012-10-30 | 2014-05-09 | 한국전자통신연구원 | Tool composition for supporting opencl application software development for embedded system and method thereof |
US9311243B2 (en) | 2012-11-30 | 2016-04-12 | Intel Corporation | Emulated message signaled interrupts in multiprocessor systems |
US10235208B2 (en) * | 2012-12-11 | 2019-03-19 | Nvidia Corporation | Technique for saving and restoring thread group operating state |
US20140177497A1 (en) | 2012-12-20 | 2014-06-26 | Seven Networks, Inc. | Management of mobile device radio state promotion and demotion |
US8930920B2 (en) * | 2012-12-31 | 2015-01-06 | Oracle International Corporation | Self-optimizing interpreter and snapshot compilation |
US9250954B2 (en) * | 2013-01-17 | 2016-02-02 | Xockets, Inc. | Offload processor modules for connection to system memory, and corresponding methods and systems |
US9271238B2 (en) | 2013-01-23 | 2016-02-23 | Seven Networks, Llc | Application or context aware fast dormancy |
US8874761B2 (en) | 2013-01-25 | 2014-10-28 | Seven Networks, Inc. | Signaling optimization in a wireless network for traffic utilizing proprietary and non-proprietary protocols |
US9326185B2 (en) | 2013-03-11 | 2016-04-26 | Seven Networks, Llc | Mobile network congestion recognition for optimization of mobile traffic |
US9424165B2 (en) * | 2013-03-14 | 2016-08-23 | Applied Micro Circuits Corporation | Debugging processor hang situations using an external pin |
CN104079613B (en) * | 2013-03-29 | 2018-04-13 | 国际商业机器公司 | Method and system for sharing application program object between multi-tenant |
US9065765B2 (en) | 2013-07-22 | 2015-06-23 | Seven Networks, Inc. | Proxy server associated with a mobile carrier for enhancing mobile traffic management in a mobile network |
CN103632099B (en) * | 2013-09-29 | 2016-08-17 | 广州华多网络科技有限公司 | The Native api function acquisition methods do not derived and device |
GB2519103B (en) * | 2013-10-09 | 2020-05-06 | Advanced Risc Mach Ltd | Decoding a complex program instruction corresponding to multiple micro-operations |
US9539005B2 (en) | 2013-11-08 | 2017-01-10 | C.R. Bard, Inc. | Surgical fastener deployment system |
CN104679585B (en) * | 2013-11-28 | 2017-10-24 | 中国航空工业集团公司第六三一研究所 | Floating-point context switching method |
CN104699627B (en) * | 2013-12-06 | 2019-05-07 | 上海芯豪微电子有限公司 | A kind of caching system and method |
KR102219288B1 (en) | 2013-12-09 | 2021-02-23 | 삼성전자 주식회사 | Memory device supporting both cache and memory mode and operating method of the same |
US9542211B2 (en) * | 2014-03-26 | 2017-01-10 | Intel Corporation | Co-designed dynamic language accelerator for a processor |
US9336047B2 (en) | 2014-06-30 | 2016-05-10 | International Business Machines Corporation | Prefetching of discontiguous storage locations in anticipation of transactional execution |
US9348643B2 (en) | 2014-06-30 | 2016-05-24 | International Business Machines Corporation | Prefetching of discontiguous storage locations as part of transactional execution |
US9448939B2 (en) | 2014-06-30 | 2016-09-20 | International Business Machines Corporation | Collecting memory operand access characteristics during transactional execution |
US9710271B2 (en) | 2014-06-30 | 2017-07-18 | International Business Machines Corporation | Collecting transactional execution characteristics during transactional execution |
US9600286B2 (en) | 2014-06-30 | 2017-03-21 | International Business Machines Corporation | Latent modification instruction for transactional execution |
US9941547B2 (en) | 2014-08-21 | 2018-04-10 | Johnson & Johnson Vision Care, Inc. | Biomedical energization elements with polymer electrolytes and cavity structures |
US10361405B2 (en) | 2014-08-21 | 2019-07-23 | Johnson & Johnson Vision Care, Inc. | Biomedical energization elements with polymer electrolytes |
US10361404B2 (en) | 2014-08-21 | 2019-07-23 | Johnson & Johnson Vision Care, Inc. | Anodes for use in biocompatible energization elements |
US9793536B2 (en) | 2014-08-21 | 2017-10-17 | Johnson & Johnson Vision Care, Inc. | Pellet form cathode for use in a biocompatible battery |
US9599842B2 (en) | 2014-08-21 | 2017-03-21 | Johnson & Johnson Vision Care, Inc. | Device and methods for sealing and encapsulation for biocompatible energization elements |
US9715130B2 (en) | 2014-08-21 | 2017-07-25 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form separators for biocompatible energization elements for biomedical devices |
US10627651B2 (en) | 2014-08-21 | 2020-04-21 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form biocompatible energization primary elements for biomedical devices with electroless sealing layers |
US9383593B2 (en) | 2014-08-21 | 2016-07-05 | Johnson & Johnson Vision Care, Inc. | Methods to form biocompatible energization elements for biomedical devices comprising laminates and placed separators |
US10381687B2 (en) | 2014-08-21 | 2019-08-13 | Johnson & Johnson Vision Care, Inc. | Methods of forming biocompatible rechargable energization elements for biomedical devices |
US9811464B2 (en) * | 2014-12-11 | 2017-11-07 | Intel Corporation | Apparatus and method for considering spatial locality in loading data elements for execution |
US20160357965A1 (en) * | 2015-06-04 | 2016-12-08 | Ut Battelle, Llc | Automatic clustering of malware variants based on structured control flow |
CN104965409B (en) * | 2015-06-19 | 2017-06-09 | 北京甘为科技发展有限公司 | A kind of industrial circulating water system energy consumption self-learning optimization control method |
US9941146B2 (en) * | 2015-07-15 | 2018-04-10 | Chip Solutions, LLC | Semiconductor device and method |
US10417056B2 (en) | 2015-08-04 | 2019-09-17 | Oracle International Corporation | Systems and methods for performing concurrency restriction and throttling over contended locks |
US10104090B2 (en) | 2015-08-25 | 2018-10-16 | Oracle International Corporation | Restrictive access control for modular reflection |
US10503502B2 (en) * | 2015-09-25 | 2019-12-10 | Intel Corporation | Data element rearrangement, processors, methods, systems, and instructions |
GB2543304B (en) * | 2015-10-14 | 2020-10-28 | Advanced Risc Mach Ltd | Move prefix instruction |
US10620957B2 (en) * | 2015-10-22 | 2020-04-14 | Texas Instruments Incorporated | Method for forming constant extensions in the same execute packet in a VLIW processor |
JP2017130527A (en) * | 2016-01-19 | 2017-07-27 | 力祥半導體股▲フン▼有限公司UBIQ Semiconductor Corp. | Semiconductor device |
US10345620B2 (en) | 2016-02-18 | 2019-07-09 | Johnson & Johnson Vision Care, Inc. | Methods and apparatus to form biocompatible energization elements incorporating fuel cells for biomedical devices |
US10394528B2 (en) | 2016-03-30 | 2019-08-27 | Oracle International Corporation | Returning a runtime type loaded from an archive in a module system |
US10191753B2 (en) | 2016-03-30 | 2019-01-29 | Oracle International Corporation | Generating verification metadata and verifying a runtime type based on verification metadata |
US20170300521A1 (en) * | 2016-04-18 | 2017-10-19 | Sap Se | Concurrent accessing and processing of data during upgrade |
US10387142B2 (en) | 2016-09-16 | 2019-08-20 | Oracle International Corporation | Using annotation processors defined by modules with annotation processors defined by non-module code |
US10282184B2 (en) | 2016-09-16 | 2019-05-07 | Oracle International Corporation | Metadata application constraints within a module system based on modular dependencies |
US10262208B2 (en) * | 2016-09-23 | 2019-04-16 | Microsoft Technology Licensing, Llc | Automatic selection of cinemagraphs |
US10327200B2 (en) | 2016-09-28 | 2019-06-18 | Intel Corporation | Communication network management system and method |
US10565024B2 (en) * | 2016-10-19 | 2020-02-18 | Oracle International Corporation | Generic concurrency restriction |
KR20180071463A (en) * | 2016-12-19 | 2018-06-28 | 삼성전자주식회사 | Semiconductor memory device |
US10114795B2 (en) * | 2016-12-30 | 2018-10-30 | Western Digital Technologies, Inc. | Processor in non-volatile storage memory |
US10891326B2 (en) | 2017-01-05 | 2021-01-12 | International Business Machines Corporation | Representation of a data analysis using a flow graph |
US10318250B1 (en) * | 2017-03-17 | 2019-06-11 | Symantec Corporation | Systems and methods for locating functions for later interception |
US10848410B2 (en) | 2017-03-29 | 2020-11-24 | Oracle International Corporation | Ranking service implementations for a service interface |
US10782979B2 (en) | 2017-04-18 | 2020-09-22 | International Business Machines Corporation | Restoring saved architected registers and suppressing verification of registers to be restored |
US10572265B2 (en) | 2017-04-18 | 2020-02-25 | International Business Machines Corporation | Selecting register restoration or register reloading |
US10540184B2 (en) | 2017-04-18 | 2020-01-21 | International Business Machines Corporation | Coalescing store instructions for restoration |
US10838733B2 (en) | 2017-04-18 | 2020-11-17 | International Business Machines Corporation | Register context restoration based on rename register recovery |
US10489382B2 (en) * | 2017-04-18 | 2019-11-26 | International Business Machines Corporation | Register restoration invalidation based on a context switch |
US10552164B2 (en) | 2017-04-18 | 2020-02-04 | International Business Machines Corporation | Sharing snapshots between restoration and recovery |
US10545766B2 (en) | 2017-04-18 | 2020-01-28 | International Business Machines Corporation | Register restoration using transactional memory register snapshots |
US11010192B2 (en) | 2017-04-18 | 2021-05-18 | International Business Machines Corporation | Register restoration using recovery buffers |
US10740108B2 (en) | 2017-04-18 | 2020-08-11 | International Business Machines Corporation | Management of store queue based on restoration operation |
US10649785B2 (en) | 2017-04-18 | 2020-05-12 | International Business Machines Corporation | Tracking changes to memory via check and recovery |
US10963261B2 (en) | 2017-04-18 | 2021-03-30 | International Business Machines Corporation | Sharing snapshots across save requests |
US10564977B2 (en) | 2017-04-18 | 2020-02-18 | International Business Machines Corporation | Selective register allocation |
US10388039B2 (en) | 2017-05-31 | 2019-08-20 | International Business Machines Corporation | Accelerating data-driven scientific discovery |
WO2019040892A1 (en) * | 2017-08-24 | 2019-02-28 | Lutron Electronics Co., Inc. | Stack safety for independently defined operations |
US10497774B2 (en) * | 2017-10-23 | 2019-12-03 | Blackberry Limited | Small-gap coplanar tunable capacitors and methods for manufacturing thereof |
JP6870106B2 (en) * | 2017-11-06 | 2021-05-12 | 本田技研工業株式会社 | Molding method of resin molded product unit and resin molded product unit |
US10664181B2 (en) | 2017-11-14 | 2020-05-26 | International Business Machines Corporation | Protecting in-memory configuration state registers |
US10698686B2 (en) * | 2017-11-14 | 2020-06-30 | International Business Machines Corporation | Configurable architectural placement control |
US10761751B2 (en) | 2017-11-14 | 2020-09-01 | International Business Machines Corporation | Configuration state registers grouped based on functional affinity |
US10761983B2 (en) * | 2017-11-14 | 2020-09-01 | International Business Machines Corporation | Memory based configuration state registers |
US10558366B2 (en) | 2017-11-14 | 2020-02-11 | International Business Machines Corporation | Automatic pinning of units of memory |
US10592164B2 (en) | 2017-11-14 | 2020-03-17 | International Business Machines Corporation | Portions of configuration state registers in-memory |
US10642757B2 (en) | 2017-11-14 | 2020-05-05 | International Business Machines Corporation | Single call to perform pin and unpin operations |
US10552070B2 (en) * | 2017-11-14 | 2020-02-04 | International Business Machines Corporation | Separation of memory-based configuration state registers based on groups |
US10901738B2 (en) | 2017-11-14 | 2021-01-26 | International Business Machines Corporation | Bulk store and load operations of configuration state registers |
US10635602B2 (en) * | 2017-11-14 | 2020-04-28 | International Business Machines Corporation | Address translation prior to receiving a storage reference using the address to be translated |
US10496437B2 (en) | 2017-11-14 | 2019-12-03 | International Business Machines Corporation | Context switch by changing memory pointers |
US11416251B2 (en) * | 2017-11-16 | 2022-08-16 | Arm Limited | Apparatus for storing, reading and modifying constant values |
US20190163492A1 (en) * | 2017-11-28 | 2019-05-30 | International Business Machines Corporation | Employing a stack accelerator for stack-type accesses |
US10613842B2 (en) * | 2018-04-30 | 2020-04-07 | International Business Machines Corporation | Simplifying a control flow graph based on profiling data |
WO2019229538A2 (en) * | 2018-05-30 | 2019-12-05 | 赛灵思公司 | Data conversion structure, method and on-chip implementation thereof |
US11106463B2 (en) | 2019-05-24 | 2021-08-31 | Texas Instruments Incorporated | System and method for addressing data in memory |
US11080227B2 (en) * | 2019-08-08 | 2021-08-03 | SambaNova Systems, Inc. | Compiler flow logic for reconfigurable architectures |
JP2021166010A (en) * | 2020-04-08 | 2021-10-14 | 富士通株式会社 | Operation processing device |
BR112022024535A2 (en) * | 2020-05-30 | 2023-01-31 | Huawei Tech Co Ltd | PROCESSOR, PROCESSING METHOD, AND RELATED DEVICE |
CN115421864B (en) * | 2022-09-14 | 2023-04-28 | 北京计算机技术及应用研究所 | Universal PowerPC architecture processor instruction set virtualization simulation method |
Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5507030A (en) * | 1991-03-07 | 1996-04-09 | Digitial Equipment Corporation | Successive translation, execution and interpretation of computer program having code at unknown locations due to execution transfer instructions having computed destination addresses |
US5551015A (en) * | 1988-12-06 | 1996-08-27 | Lucent Technologies Inc. | Method and apparatus for direct conversion of programs in object code form between different hardware architecture computer systems |
US5560013A (en) * | 1994-12-06 | 1996-09-24 | International Business Machines Corporation | Method of using a target processor to execute programs of a source architecture that uses multiple address spaces |
US5781750A (en) * | 1994-01-11 | 1998-07-14 | Exponential Technology, Inc. | Dual-instruction-set architecture CPU with hidden software emulation mode |
US5892966A (en) * | 1997-06-27 | 1999-04-06 | Sun Microsystems, Inc. | Processor complex for executing multimedia functions |
US5909578A (en) * | 1996-09-30 | 1999-06-01 | Hewlett-Packard Company | Use of dynamic translation to burst profile computer applications |
US5937193A (en) * | 1996-11-27 | 1999-08-10 | Vlsi Technology, Inc. | Circuit arrangement for translating platform-independent instructions for execution on a hardware platform and method thereof |
US6026485A (en) * | 1996-01-24 | 2000-02-15 | Sun Microsystems, Inc. | Instruction folding for a stack-based machine |
US6075942A (en) * | 1998-05-04 | 2000-06-13 | Sun Microsystems, Inc. | Encoding machine-specific optimization in generic byte code by using local variables as pseudo-registers |
US6205540B1 (en) * | 1998-06-19 | 2001-03-20 | Franklin Electronic Publishers Incorporated | Processor with enhanced instruction set |
US6480952B2 (en) * | 1998-05-26 | 2002-11-12 | Advanced Micro Devices, Inc. | Emulation coprocessor |
US20040024999A1 (en) * | 2002-07-30 | 2004-02-05 | Texas Instruments Incorporated | Micro-sequence execution in a processor |
US6941545B1 (en) * | 1999-01-28 | 2005-09-06 | Ati International Srl | Profiling of computer programs executing in virtual memory systems |
US6954923B1 (en) * | 1999-01-28 | 2005-10-11 | Ati International Srl | Recording classification of instructions executed by a computer |
US7020766B1 (en) * | 2000-05-30 | 2006-03-28 | Intel Corporation | Processing essential and non-essential code separately |
US7047394B1 (en) * | 1999-01-28 | 2006-05-16 | Ati International Srl | Computer for execution of RISC and CISC instruction sets |
US7069545B2 (en) * | 2000-12-29 | 2006-06-27 | Intel Corporation | Quantization and compression for computation reuse |
US7093239B1 (en) * | 2000-07-14 | 2006-08-15 | Internet Security Systems, Inc. | Computer immune system and method for detecting unwanted code in a computer system |
US7194732B2 (en) * | 2003-06-26 | 2007-03-20 | Hewlett-Packard Development Company, L.P. | System and method for facilitating profiling an application |
US7254806B1 (en) * | 1999-08-30 | 2007-08-07 | Ati International Srl | Detecting reordered side-effects |
US7739673B2 (en) * | 2000-01-07 | 2010-06-15 | Sony Computer Entertainment Inc. | Multiple stage program recompiler using information flow determination |
US7899661B2 (en) * | 2006-02-16 | 2011-03-01 | Synopsys, Inc. | Run-time switching for simulation with dynamic run-time accuracy adjustment |
Family Cites Families (258)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4080650A (en) | 1976-07-28 | 1978-03-21 | Bell Telephone Laboratories, Incorporated | Facilitating return from an on-line debugging program to a target program breakpoint |
US4258419A (en) * | 1978-12-29 | 1981-03-24 | Bell Telephone Laboratories, Incorporated | Data processing apparatus providing variable operand width operation |
US4484271A (en) * | 1979-01-31 | 1984-11-20 | Honeywell Information Systems Inc. | Microprogrammed system having hardware interrupt apparatus |
US4312034A (en) * | 1979-05-21 | 1982-01-19 | Motorola, Inc. | ALU and Condition code control unit for data processor |
US4268419A (en) * | 1979-11-16 | 1981-05-19 | Uop Inc. | Support matrices for immobilized enzymes |
US4398243A (en) * | 1980-04-25 | 1983-08-09 | Data General Corporation | Data processing system having a unique instruction processor system |
US4598365A (en) * | 1983-04-01 | 1986-07-01 | Honeywell Information Systems Inc. | Pipelined decimal character execution unit |
US5021991A (en) * | 1983-04-18 | 1991-06-04 | Motorola, Inc. | Coprocessor instruction format |
US4729094A (en) * | 1983-04-18 | 1988-03-01 | Motorola, Inc. | Method and apparatus for coordinating execution of an instruction by a coprocessor |
JPH0827716B2 (en) * | 1985-10-25 | 1996-03-21 | 株式会社日立製作所 | Data processing device and data processing method |
US5155807A (en) * | 1986-02-24 | 1992-10-13 | International Business Machines Corporation | Multi-processor communications channel utilizing random access/sequential access memories |
JPS62221732A (en) * | 1986-03-24 | 1987-09-29 | Nec Corp | Register saving and recovery system |
US4821183A (en) | 1986-12-04 | 1989-04-11 | International Business Machines Corporation | A microsequencer circuit with plural microprogrom instruction counters |
US5142628A (en) * | 1986-12-26 | 1992-08-25 | Hitachi, Ltd. | Microcomputer system for communication |
US5119484A (en) * | 1987-02-24 | 1992-06-02 | Digital Equipment Corporation | Selections between alternate control word and current instruction generated control word for alu in respond to alu output and current instruction |
US5099417A (en) * | 1987-03-13 | 1992-03-24 | Texas Instruments Incorporated | Data processing device with improved direct memory access |
US5142677A (en) * | 1989-05-04 | 1992-08-25 | Texas Instruments Incorporated | Context switching devices, systems and methods |
US5822578A (en) * | 1987-12-22 | 1998-10-13 | Sun Microsystems, Inc. | System for inserting instructions into processor instruction stream in order to perform interrupt processing |
JPH0652521B2 (en) * | 1988-11-30 | 1994-07-06 | 株式会社日立製作所 | Information processing system |
JP3063006B2 (en) * | 1989-02-08 | 2000-07-12 | インテル・コーポレーション | Microprogrammed computer device and method for addressing microcode sequence memory |
US5167028A (en) * | 1989-11-13 | 1992-11-24 | Lucid Corporation | System for controlling task operation of slave processor by switching access to shared memory banks by master processor |
US5390329A (en) * | 1990-06-11 | 1995-02-14 | Cray Research, Inc. | Responding to service requests using minimal system-side context in a multiprocessor environment |
US5522072A (en) * | 1990-09-04 | 1996-05-28 | At&T Corp. | Arrangement for efficiently transferring program execution between subprograms |
US5826101A (en) * | 1990-09-28 | 1998-10-20 | Texas Instruments Incorporated | Data processing device having split-mode DMA channel |
US5390304A (en) * | 1990-09-28 | 1995-02-14 | Texas Instruments, Incorporated | Method and apparatus for processing block instructions in a data processor |
US5537574A (en) * | 1990-12-14 | 1996-07-16 | International Business Machines Corporation | Sysplex shared data coherency method |
US5276835A (en) * | 1990-12-14 | 1994-01-04 | International Business Machines Corporation | Non-blocking serialization for caching data in a shared cache |
US5410710A (en) * | 1990-12-21 | 1995-04-25 | Intel Corporation | Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems |
US5613128A (en) * | 1990-12-21 | 1997-03-18 | Intel Corporation | Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller |
WO1992022029A1 (en) * | 1991-05-24 | 1992-12-10 | British Technology Group Usa, Inc. | Optimizing compiler for computers |
CA2067576C (en) * | 1991-07-10 | 1998-04-14 | Jimmie D. Edrington | Dynamic load balancing for a multiprocessor pipeline |
US5355483A (en) * | 1991-07-18 | 1994-10-11 | Next Computers | Asynchronous garbage collection |
US5274815A (en) * | 1991-11-01 | 1993-12-28 | Motorola, Inc. | Dynamic instruction modifying controller and operation method |
US5187644A (en) * | 1991-11-14 | 1993-02-16 | Compaq Computer Corporation | Compact portable computer having an expandable full size keyboard with extendable supports |
EP0551531A1 (en) * | 1991-12-20 | 1993-07-21 | International Business Machines Corporation | Apparatus for executing ADD/SUB operations between IEEE standard floating-point numbers |
US5309567A (en) * | 1992-01-24 | 1994-05-03 | C-Cube Microsystems | Structure and method for an asynchronous communication protocol between master and slave processors |
US5257215A (en) * | 1992-03-31 | 1993-10-26 | Intel Corporation | Floating point and integer number conversions in a floating point adder |
JP2786574B2 (en) * | 1992-05-06 | 1998-08-13 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Method and apparatus for improving the performance of out-of-order load operations in a computer system |
US5272660A (en) * | 1992-06-01 | 1993-12-21 | Motorola, Inc. | Method and apparatus for performing integer and floating point division using a single SRT divider in a data processor |
ATE173877T1 (en) * | 1992-06-29 | 1998-12-15 | Elonex Technologies Inc | MODULAR PORTABLE CALCULATOR |
US5426783A (en) * | 1992-11-02 | 1995-06-20 | Amdahl Corporation | System for processing eight bytes or less by the move, pack and unpack instruction of the ESA/390 instruction set |
US5384722A (en) * | 1993-03-10 | 1995-01-24 | Intel Corporation | Apparatus and method for determining the Manhattan distance between two points |
US5459798A (en) * | 1993-03-19 | 1995-10-17 | Intel Corporation | System and method of pattern recognition employing a multiprocessing pipelined apparatus with private pattern memory |
US5825921A (en) * | 1993-03-19 | 1998-10-20 | Intel Corporation | Memory transfer apparatus and method useful within a pattern recognition system |
US5829007A (en) * | 1993-06-24 | 1998-10-27 | Discovision Associates | Technique for implementing a swing buffer in a memory array |
EP0651320B1 (en) * | 1993-10-29 | 2001-05-23 | Advanced Micro Devices, Inc. | Superscalar instruction decoder |
US5490272A (en) * | 1994-01-28 | 1996-02-06 | International Business Machines Corporation | Method and apparatus for creating multithreaded time slices in a multitasking operating system |
JPH07281890A (en) * | 1994-04-06 | 1995-10-27 | Mitsubishi Electric Corp | Instruction set and its executing method by microcomputer |
GB2289353B (en) * | 1994-05-03 | 1997-08-27 | Advanced Risc Mach Ltd | Data processing with multiple instruction sets |
JP3619939B2 (en) * | 1994-09-26 | 2005-02-16 | 株式会社ルネサステクノロジ | Central processing unit |
US5634046A (en) * | 1994-09-30 | 1997-05-27 | Microsoft Corporation | General purpose use of a stack pointer register |
US5634076A (en) * | 1994-10-04 | 1997-05-27 | Analog Devices, Inc. | DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer |
JP3494489B2 (en) * | 1994-11-30 | 2004-02-09 | 株式会社ルネサステクノロジ | Instruction processing unit |
EP0795153A4 (en) * | 1994-12-02 | 2001-11-14 | Intel Corp | Microprocessor with packing operation of composite operands |
US5613162A (en) * | 1995-01-04 | 1997-03-18 | Ast Research, Inc. | Method and apparatus for performing efficient direct memory access data transfers |
US5638525A (en) * | 1995-02-10 | 1997-06-10 | Intel Corporation | Processor capable of executing programs that contain RISC and CISC instructions |
US5708815A (en) * | 1995-05-05 | 1998-01-13 | Intel Corporation | DMA emulation via interrupt muxing |
JP3218932B2 (en) | 1995-07-06 | 2001-10-15 | 株式会社日立製作所 | Data prefetch code generation method |
US6643765B1 (en) * | 1995-08-16 | 2003-11-04 | Microunity Systems Engineering, Inc. | Programmable processor with group floating point operations |
US5953241A (en) * | 1995-08-16 | 1999-09-14 | Microunity Engeering Systems, Inc. | Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction |
US5933847A (en) * | 1995-09-28 | 1999-08-03 | Canon Kabushiki Kaisha | Selecting erase method based on type of power supply for flash EEPROM |
US5774737A (en) * | 1995-10-13 | 1998-06-30 | Matsushita Electric Industrial Co., Ltd. | Variable word length very long instruction word instruction processor with word length register or instruction number register |
US6035123A (en) * | 1995-11-08 | 2000-03-07 | Digital Equipment Corporation | Determining hardware complexity of software operations |
US5727227A (en) * | 1995-11-20 | 1998-03-10 | Advanced Micro Devices | Interrupt coprocessor configured to process interrupts in a computer system |
US5850555A (en) * | 1995-12-19 | 1998-12-15 | Advanced Micro Devices, Inc. | System and method for validating interrupts before presentation to a CPU |
US5894578A (en) * | 1995-12-19 | 1999-04-13 | Advanced Micro Devices, Inc. | System and method for using random access memory in a programmable interrupt controller |
US5892956A (en) * | 1995-12-19 | 1999-04-06 | Advanced Micro Devices, Inc. | Serial bus for transmitting interrupt information in a multiprocessing system |
US5850558A (en) * | 1995-12-19 | 1998-12-15 | Advanced Micro Devices | System and method for referencing interrupt request information in a programmable interrupt controller |
US5727217A (en) * | 1995-12-20 | 1998-03-10 | Intel Corporation | Circuit and method for emulating the functionality of an advanced programmable interrupt controller |
US6038643A (en) * | 1996-01-24 | 2000-03-14 | Sun Microsystems, Inc. | Stack management unit and method for a processor having a stack |
JP2000501217A (en) * | 1996-01-24 | 2000-02-02 | サン・マイクロシステムズ・インコーポレイテッド | Processor that accelerated array access boundary check |
US5842017A (en) * | 1996-01-29 | 1998-11-24 | Digital Equipment Corporation | Method and apparatus for forming a translation unit |
JPH09212371A (en) * | 1996-02-07 | 1997-08-15 | Nec Corp | Register saving and restoring system |
US5761515A (en) * | 1996-03-14 | 1998-06-02 | International Business Machines Corporation | Branch on cache hit/miss for compiler-assisted miss delay tolerance |
US5983313A (en) * | 1996-04-10 | 1999-11-09 | Ramtron International Corporation | EDRAM having a dynamically-sized cache memory and associated method |
US5923877A (en) * | 1996-05-01 | 1999-07-13 | Electronic Data Systems Corporation | Object-oriented programming memory management framework and method |
US5889999A (en) * | 1996-05-15 | 1999-03-30 | Motorola, Inc. | Method and apparatus for sequencing computer instruction execution in a data processing system |
US5778236A (en) * | 1996-05-17 | 1998-07-07 | Advanced Micro Devices, Inc. | Multiprocessing interrupt controller on I/O bus |
US5754884A (en) * | 1996-05-20 | 1998-05-19 | Advanced Micro Devices | Method for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA controller |
US6711667B1 (en) * | 1996-06-28 | 2004-03-23 | Legerity, Inc. | Microprocessor configured to translate instructions from one instruction set to another, and to store the translated instructions |
WO1998006030A1 (en) * | 1996-08-07 | 1998-02-12 | Sun Microsystems | Multifunctional execution unit |
US6061711A (en) * | 1996-08-19 | 2000-05-09 | Samsung Electronics, Inc. | Efficient context saving and restoring in a multi-tasking computing system environment |
US6438573B1 (en) * | 1996-10-09 | 2002-08-20 | Iowa State University Research Foundation, Inc. | Real-time programming method |
US6052699A (en) * | 1996-12-11 | 2000-04-18 | Lucent Technologies Inc. | Garbage collection without fine-grain synchronization |
US5796972A (en) * | 1997-01-14 | 1998-08-18 | Unisys Corporation | Method and apparatus for performing microcode paging during instruction execution in an instruction processor |
US6167488A (en) * | 1997-03-31 | 2000-12-26 | Sun Microsystems, Inc. | Stack caching circuit with overflow/underflow unit |
US6003038A (en) * | 1997-03-31 | 1999-12-14 | Sun Microsystems, Inc. | Object-oriented processor architecture and operating method |
US5875336A (en) * | 1997-03-31 | 1999-02-23 | International Business Machines Corporation | Method and system for translating a non-native bytecode to a set of codes native to a processor within a computer system |
US5898850A (en) * | 1997-03-31 | 1999-04-27 | International Business Machines Corporation | Method and system for executing a non-native mode-sensitive instruction within a computer system |
US6049810A (en) * | 1997-04-23 | 2000-04-11 | Sun Microsystems, Inc. | Method and apparatus for implementing a write barrier of a garbage collected heap |
US6199075B1 (en) * | 1997-05-30 | 2001-03-06 | Sun Microsystems, Inc. | Method and apparatus for generational garbage collection of a heap memory shared by multiple processors |
US5983337A (en) | 1997-06-12 | 1999-11-09 | Advanced Micro Devices, Inc. | Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction |
US6006321A (en) * | 1997-06-13 | 1999-12-21 | Malleable Technologies, Inc. | Programmable logic datapath that may be used in a field programmable device |
US6321323B1 (en) * | 1997-06-27 | 2001-11-20 | Sun Microsystems, Inc. | System and method for executing platform-independent code on a co-processor |
US6240440B1 (en) * | 1997-06-30 | 2001-05-29 | Sun Microsystems Incorporated | Method and apparatus for implementing virtual threads |
US6513156B2 (en) * | 1997-06-30 | 2003-01-28 | Sun Microsystems, Inc. | Interpreting functions utilizing a hybrid of virtual and native machine instructions |
US6078744A (en) * | 1997-08-01 | 2000-06-20 | Sun Microsystems | Method and apparatus for improving compiler performance during subsequent compilations of a source program |
US6366876B1 (en) * | 1997-09-29 | 2002-04-02 | Sun Microsystems, Inc. | Method and apparatus for assessing compatibility between platforms and applications |
US6006301A (en) * | 1997-09-30 | 1999-12-21 | Intel Corporation | Multi-delivery scheme interrupt router |
US6233733B1 (en) * | 1997-09-30 | 2001-05-15 | Sun Microsystems, Inc. | Method for generating a Java bytecode data flow graph |
DE69839913D1 (en) * | 1997-10-02 | 2008-10-02 | Koninkl Philips Electronics Nv | DATA PROCESSING DEVICE FOR PROCESSING COMMAND |
US6085208A (en) * | 1997-10-23 | 2000-07-04 | Advanced Micro Devices, Inc. | Leading one prediction unit for normalizing close path subtraction results within a floating point arithmetic unit |
US6061770A (en) * | 1997-11-04 | 2000-05-09 | Adaptec, Inc. | System and method for real-time data backup using snapshot copying with selective compaction of backup data |
US6341342B1 (en) * | 1997-11-04 | 2002-01-22 | Compaq Information Technologies Group, L.P. | Method and apparatus for zeroing a transfer buffer memory as a background task |
US6862650B1 (en) * | 1997-11-14 | 2005-03-01 | International Business Machines Corporation | Data processing system and method for managing memory of an interpretive system |
US6021484A (en) * | 1997-11-14 | 2000-02-01 | Samsung Electronics Co., Ltd. | Dual instruction set architecture |
US6066181A (en) * | 1997-12-08 | 2000-05-23 | Analysis & Technology, Inc. | Java native interface code generator |
US6009261A (en) * | 1997-12-16 | 1999-12-28 | International Business Machines Corporation | Preprocessing of stored target routines for emulating incompatible instructions on a target processor |
US6081665A (en) * | 1997-12-19 | 2000-06-27 | Newmonics Inc. | Method for efficient soft real-time execution of portable byte code computer programs |
US6192368B1 (en) * | 1998-02-11 | 2001-02-20 | International Business Machines Corporation | Apparatus and method for automatically propagating a change made to at least one of a plurality of objects to at least one data structure containing data relating to the plurality of objects |
US5999732A (en) * | 1998-03-23 | 1999-12-07 | Sun Microsystems, Inc. | Techniques for reducing the cost of dynamic class initialization checks in compiled code |
US6594708B1 (en) * | 1998-03-26 | 2003-07-15 | Sun Microsystems, Inc. | Apparatus and method for object-oriented memory system |
US6052739A (en) * | 1998-03-26 | 2000-04-18 | Sun Microsystems, Inc. | Method and apparatus for object-oriented interrupt system |
US6374286B1 (en) * | 1998-04-06 | 2002-04-16 | Rockwell Collins, Inc. | Real time processor capable of concurrently running multiple independent JAVA machines |
US6915307B1 (en) * | 1998-04-15 | 2005-07-05 | Inktomi Corporation | High performance object cache |
US6115777A (en) * | 1998-04-21 | 2000-09-05 | Idea Corporation | LOADRS instruction and asynchronous context switch |
US6275903B1 (en) * | 1998-04-22 | 2001-08-14 | Sun Microsystems, Inc. | Stack cache miss handling |
US6192442B1 (en) * | 1998-04-29 | 2001-02-20 | Intel Corporation | Interrupt controller |
US6148316A (en) * | 1998-05-05 | 2000-11-14 | Mentor Graphics Corporation | Floating point unit equipped also to perform integer addition as well as floating point to integer conversion |
US6397242B1 (en) * | 1998-05-15 | 2002-05-28 | Vmware, Inc. | Virtualization system including a virtual machine monitor for a computer with a segmented architecture |
US6745384B1 (en) | 1998-05-29 | 2004-06-01 | Microsoft Corporation | Anticipatory optimization with composite folding |
US6219678B1 (en) * | 1998-06-25 | 2001-04-17 | Sun Microsystems, Inc. | System and method for maintaining an association for an object |
US6202147B1 (en) * | 1998-06-29 | 2001-03-13 | Sun Microsystems, Inc. | Platform-independent device drivers |
EP0969377B1 (en) * | 1998-06-30 | 2009-01-07 | International Business Machines Corporation | Method of replication-based garbage collection in a multiprocessor system |
US6854113B1 (en) * | 1998-08-28 | 2005-02-08 | Borland Software Corporation | Mixed-mode execution for object-oriented programming languages |
US6008621A (en) * | 1998-10-15 | 1999-12-28 | Electronic Classroom Furniture Systems | Portable computer charging system and storage cart |
US20020108025A1 (en) * | 1998-10-21 | 2002-08-08 | Nicholas Shaylor | Memory management unit for java environment computers |
US6684323B2 (en) * | 1998-10-27 | 2004-01-27 | Stmicroelectronics, Inc. | Virtual condition codes |
US6519594B1 (en) * | 1998-11-14 | 2003-02-11 | Sony Electronics, Inc. | Computer-implemented sharing of java classes for increased memory efficiency and communication method |
GB9825102D0 (en) * | 1998-11-16 | 1999-01-13 | Insignia Solutions Plc | Computer system |
US6115719A (en) * | 1998-11-20 | 2000-09-05 | Revsoft Corporation | Java compatible object oriented component data structure |
US6718457B2 (en) * | 1998-12-03 | 2004-04-06 | Sun Microsystems, Inc. | Multiple-thread processor for threaded software applications |
US6530075B1 (en) * | 1998-12-03 | 2003-03-04 | International Business Machines Corporation | JIT/compiler Java language extensions to enable field performance and serviceability |
US20020073398A1 (en) * | 1998-12-14 | 2002-06-13 | Jeffrey L. Tinker | Method and system for modifying executable code to add additional functionality |
US7013456B1 (en) * | 1999-01-28 | 2006-03-14 | Ati International Srl | Profiling execution of computer programs |
US7111290B1 (en) * | 1999-01-28 | 2006-09-19 | Ati International Srl | Profiling program execution to identify frequently-executed portions and to assist binary translation |
US6385764B1 (en) * | 1999-01-29 | 2002-05-07 | International Business Machines Corporation | Method and apparatus for improving invocation speed of Java methods |
US6412109B1 (en) * | 1999-01-29 | 2002-06-25 | Sun Microsystems, Inc. | Method for optimizing java bytecodes in the presence of try-catch blocks |
US6848111B1 (en) * | 1999-02-02 | 2005-01-25 | Sun Microsystems, Inc. | Zero overhead exception handling |
US6260157B1 (en) * | 1999-02-16 | 2001-07-10 | Kurt Schurecht | Patching of a read only memory |
US6738846B1 (en) * | 1999-02-23 | 2004-05-18 | Sun Microsystems, Inc. | Cooperative processing of tasks in a multi-threaded computing system |
US6308253B1 (en) * | 1999-03-31 | 2001-10-23 | Sony Corporation | RISC CPU instructions particularly suited for decoding digital signal processing applications |
US6412029B1 (en) * | 1999-04-29 | 2002-06-25 | Agere Systems Guardian Corp. | Method and apparatus for interfacing between a digital signal processor and a baseband circuit for wireless communication system |
US6412108B1 (en) * | 1999-05-06 | 2002-06-25 | International Business Machines Corporation | Method and apparatus for speeding up java methods prior to a first execution |
US6510493B1 (en) * | 1999-07-15 | 2003-01-21 | International Business Machines Corporation | Method and apparatus for managing cache line replacement within a computer system |
US6535958B1 (en) * | 1999-07-15 | 2003-03-18 | Texas Instruments Incorporated | Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access |
US6510352B1 (en) * | 1999-07-29 | 2003-01-21 | The Foxboro Company | Methods and apparatus for object-based process control |
US6341318B1 (en) * | 1999-08-10 | 2002-01-22 | Chameleon Systems, Inc. | DMA data streaming |
US7000222B1 (en) * | 1999-08-19 | 2006-02-14 | International Business Machines Corporation | Method, system, and program for accessing variables from an operating system for use by an application program |
US6507947B1 (en) * | 1999-08-20 | 2003-01-14 | Hewlett-Packard Company | Programmatic synthesis of processor element arrays |
US6418540B1 (en) * | 1999-08-27 | 2002-07-09 | Lucent Technologies Inc. | State transfer with throw-away thread |
US6671707B1 (en) * | 1999-10-19 | 2003-12-30 | Intel Corporation | Method for practical concurrent copying garbage collection offering minimal thread block times |
US6418489B1 (en) * | 1999-10-25 | 2002-07-09 | Motorola, Inc. | Direct memory access controller and method therefor |
SE9903890L (en) * | 1999-10-28 | 2001-02-12 | Appeal Virtual Machines Ab | Process for streamlining a data processing process using a virtual machine and using a garbage collection procedure |
US6711739B1 (en) * | 1999-11-08 | 2004-03-23 | Sun Microsystems, Inc. | System and method for handling threads of execution |
US6477666B1 (en) * | 1999-11-22 | 2002-11-05 | International Business Machines Corporation | Automatic fault injection into a JAVA virtual machine (JVM) |
EP1111511B1 (en) * | 1999-12-06 | 2017-09-27 | Texas Instruments France | Cache with multiple fill modes |
EP1107123B1 (en) | 1999-12-06 | 2007-11-21 | Texas Instruments France | Smart cache |
US6668287B1 (en) * | 1999-12-15 | 2003-12-23 | Transmeta Corporation | Software direct memory access |
US6691308B1 (en) * | 1999-12-30 | 2004-02-10 | Stmicroelectronics, Inc. | Method and apparatus for changing microcode to be executed in a processor |
JP2001243079A (en) * | 2000-03-02 | 2001-09-07 | Omron Corp | Information processing system |
US6618737B2 (en) * | 2000-03-09 | 2003-09-09 | International Business Machines Corporation | Speculative caching of individual fields in a distributed object system |
US7171543B1 (en) * | 2000-03-28 | 2007-01-30 | Intel Corp. | Method and apparatus for executing a 32-bit application by confining the application to a 32-bit address space subset in a 64-bit processor |
US7093102B1 (en) * | 2000-03-29 | 2006-08-15 | Intel Corporation | Code sequence for vector gather and scatter |
US7086066B2 (en) * | 2000-03-31 | 2006-08-01 | Schlumbergersema Telekom Gmbh & Co. Kg | System and method for exception handling |
US6408383B1 (en) * | 2000-05-04 | 2002-06-18 | Sun Microsystems, Inc. | Array access boundary check by executing BNDCHK instruction with comparison specifiers |
US20030105945A1 (en) * | 2001-11-01 | 2003-06-05 | Bops, Inc. | Methods and apparatus for a bit rake instruction |
US7159223B1 (en) * | 2000-05-12 | 2007-01-02 | Zw Company, Llc | Methods and systems for applications to interact with hardware |
US20020099902A1 (en) * | 2000-05-12 | 2002-07-25 | Guillaume Comeau | Methods and systems for applications to interact with hardware |
US20020099863A1 (en) * | 2000-06-02 | 2002-07-25 | Guillaume Comeau | Software support layer for processors executing interpreted language applications |
US6735687B1 (en) * | 2000-06-15 | 2004-05-11 | Hewlett-Packard Development Company, L.P. | Multithreaded microprocessor with asymmetrical central processing units |
US6662359B1 (en) * | 2000-07-20 | 2003-12-09 | International Business Machines Corporation | System and method for injecting hooks into Java classes to handle exception and finalization processing |
US6704860B1 (en) * | 2000-07-26 | 2004-03-09 | International Business Machines Corporation | Data processing system and method for fetching instruction blocks in response to a detected block sequence |
EP1182565B1 (en) | 2000-08-21 | 2012-09-05 | Texas Instruments France | Cache and DMA with a global valid bit |
US6816921B2 (en) * | 2000-09-08 | 2004-11-09 | Texas Instruments Incorporated | Micro-controller direct memory access (DMA) operation with adjustable word size transfers and address alignment/incrementing |
US7000227B1 (en) | 2000-09-29 | 2006-02-14 | Intel Corporation | Iterative optimizing compiler |
GB2367653B (en) * | 2000-10-05 | 2004-10-20 | Advanced Risc Mach Ltd | Restarting translated instructions |
US6684232B1 (en) * | 2000-10-26 | 2004-01-27 | International Business Machines Corporation | Method and predictor for streamlining execution of convert-to-integer operations |
US6993754B2 (en) * | 2001-11-13 | 2006-01-31 | Hewlett-Packard Development Company, L.P. | Annotations to executable images for improved dynamic optimization functions |
GB0027053D0 (en) * | 2000-11-06 | 2000-12-20 | Ibm | A computer system with two heaps in contiguous storage |
EP1211598A1 (en) * | 2000-11-29 | 2002-06-05 | Texas Instruments Incorporated | Data processing apparatus, system and method |
US7085705B2 (en) * | 2000-12-21 | 2006-08-01 | Microsoft Corporation | System and method for the logical substitution of processor control in an emulated computing environment |
US7185330B1 (en) | 2001-01-05 | 2007-02-27 | Xilinx, Inc. | Code optimization method and system |
US6988167B2 (en) * | 2001-02-08 | 2006-01-17 | Analog Devices, Inc. | Cache system with DMA capabilities and method for operating same |
US20020161957A1 (en) * | 2001-02-09 | 2002-10-31 | Guillaume Comeau | Methods and systems for handling interrupts |
US7080373B2 (en) * | 2001-03-07 | 2006-07-18 | Freescale Semiconductor, Inc. | Method and device for creating and using pre-internalized program files |
US6775763B2 (en) * | 2001-03-09 | 2004-08-10 | Koninklijke Philips Electronics N.V. | Bytecode instruction processor with switch instruction handling logic |
FR2822256B1 (en) * | 2001-03-13 | 2003-05-30 | Gemplus Card Int | VERIFICATION OF CONFORMITY OF ACCESS TO OBJECTS IN A DATA PROCESSING SYSTEM WITH A SECURITY POLICY |
GB2373349B (en) * | 2001-03-15 | 2005-02-23 | Proksim Software Inc | Data definition language |
US7184003B2 (en) * | 2001-03-16 | 2007-02-27 | Dualcor Technologies, Inc. | Personal electronics device with display switching |
US7017154B2 (en) | 2001-03-23 | 2006-03-21 | International Business Machines Corporation | Eliminating store/restores within hot function prolog/epilogs using volatile registers |
US6452426B1 (en) * | 2001-04-16 | 2002-09-17 | Nagesh Tamarapalli | Circuit for switching between multiple clocks |
US7032158B2 (en) * | 2001-04-23 | 2006-04-18 | Quickshift, Inc. | System and method for recognizing and configuring devices embedded on memory modules |
US20020166004A1 (en) * | 2001-05-02 | 2002-11-07 | Kim Jason Seung-Min | Method for implementing soft-DMA (software based direct memory access engine) for multiple processor systems |
US6574708B2 (en) * | 2001-05-18 | 2003-06-03 | Broadcom Corporation | Source controlled cache allocation |
GB2376097B (en) * | 2001-05-31 | 2005-04-06 | Advanced Risc Mach Ltd | Configuration control within data processing systems |
GB2376100B (en) * | 2001-05-31 | 2005-03-09 | Advanced Risc Mach Ltd | Data processing using multiple instruction sets |
US7152223B1 (en) * | 2001-06-04 | 2006-12-19 | Microsoft Corporation | Methods and systems for compiling and interpreting one or more associations between declarations and implementations in a language neutral fashion |
US6961941B1 (en) * | 2001-06-08 | 2005-11-01 | Vmware, Inc. | Computer configuration for resource management in systems including a virtual machine |
US20030200343A1 (en) * | 2001-07-02 | 2003-10-23 | Globespan Virata Incorporated | Communications system using rings architecture |
JP2004536405A (en) | 2001-07-16 | 2004-12-02 | ユキング レン | Embedded software update system |
US7107439B2 (en) * | 2001-08-10 | 2006-09-12 | Mips Technologies, Inc. | System and method of controlling software decompression through exceptions |
US7434030B2 (en) * | 2001-09-12 | 2008-10-07 | Renesas Technology Corp. | Processor system having accelerator of Java-type of programming language |
US6944724B2 (en) * | 2001-09-14 | 2005-09-13 | Sun Microsystems, Inc. | Method and apparatus for decoupling tag and data accesses in a cache memory |
EP1446718A2 (en) * | 2001-09-25 | 2004-08-18 | Koninklijke Philips Electronics N.V. | Software support for virtual machine interpreter (vmi) acceleration hardware |
FR2831289B1 (en) * | 2001-10-19 | 2004-01-23 | St Microelectronics Sa | MICROPROCESSOR WITH EXTENDED ADDRESSABLE SPACE |
US7003778B2 (en) * | 2001-10-24 | 2006-02-21 | Sun Microsystems, Inc. | Exception handling in java computing environments |
US6915513B2 (en) * | 2001-11-29 | 2005-07-05 | Hewlett-Packard Development Company, L.P. | System and method for dynamically replacing code |
US7062762B2 (en) * | 2001-12-12 | 2006-06-13 | Texas Instruments Incorporated | Partitioning symmetric nodes efficiently in a split register file architecture |
US7363467B2 (en) * | 2002-01-03 | 2008-04-22 | Intel Corporation | Dependence-chain processing using trace descriptors having dependency descriptors |
US6912649B2 (en) * | 2002-03-13 | 2005-06-28 | International Business Machines Corporation | Scheme to encode predicted values into an instruction stream/cache without additional bits/area |
US7131120B2 (en) * | 2002-05-16 | 2006-10-31 | Sun Microsystems, Inc. | Inter Java virtual machine (JVM) resource locking mechanism |
US7065613B1 (en) * | 2002-06-06 | 2006-06-20 | Maxtor Corporation | Method for reducing access to main memory using a stack cache |
US6957322B1 (en) * | 2002-07-25 | 2005-10-18 | Advanced Micro Devices, Inc. | Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion |
EP1387249B1 (en) * | 2002-07-31 | 2019-03-13 | Texas Instruments Incorporated | RISC processor having a stack and register architecture |
EP1391821A3 (en) * | 2002-07-31 | 2007-06-06 | Texas Instruments Inc. | A multi processor computing system having a java stack machine and a risc based processor |
US7051177B2 (en) * | 2002-07-31 | 2006-05-23 | International Business Machines Corporation | Method for measuring memory latency in a hierarchical memory system |
US7237236B2 (en) * | 2002-08-22 | 2007-06-26 | International Business Machines Corporation | Method and apparatus for automatically determining optimum placement of privileged code locations in existing code |
GB2392515B (en) * | 2002-08-28 | 2005-08-17 | Livedevices Ltd | Improvements relating to stack usage in computer-related operating systems |
US7165156B1 (en) * | 2002-09-06 | 2007-01-16 | 3Pardata, Inc. | Read-write snapshots |
US7146607B2 (en) * | 2002-09-17 | 2006-12-05 | International Business Machines Corporation | Method and system for transparent dynamic optimization in a multiprocessing environment |
US7246346B2 (en) * | 2002-09-17 | 2007-07-17 | Microsoft Corporation | System and method for persisting dynamically generated code in a directly addressable and executable storage medium |
US7313797B2 (en) * | 2002-09-18 | 2007-12-25 | Wind River Systems, Inc. | Uniprocessor operating system design facilitating fast context switching |
US7200721B1 (en) * | 2002-10-09 | 2007-04-03 | Unisys Corporation | Verification of memory operations by multiple processors to a shared memory |
US20040083467A1 (en) * | 2002-10-29 | 2004-04-29 | Sharp Laboratories Of America, Inc. | System and method for executing intermediate code |
US7155708B2 (en) * | 2002-10-31 | 2006-12-26 | Src Computers, Inc. | Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation |
KR100503077B1 (en) * | 2002-12-02 | 2005-07-21 | 삼성전자주식회사 | A java execution device and a java execution method |
US7194736B2 (en) * | 2002-12-10 | 2007-03-20 | Intel Corporation | Dynamic division optimization for a just-in-time compiler |
US6883074B2 (en) * | 2002-12-13 | 2005-04-19 | Sun Microsystems, Inc. | System and method for efficient write operations for repeated snapshots by copying-on-write to most recent snapshot |
US7383550B2 (en) * | 2002-12-23 | 2008-06-03 | International Business Machines Corporation | Topology aware grid services scheduler architecture |
JPWO2004079583A1 (en) * | 2003-03-05 | 2006-06-08 | 富士通株式会社 | Data transfer control device and DMA data transfer control method |
JP3899046B2 (en) * | 2003-03-20 | 2007-03-28 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Compiler device, compiler program, recording medium, and compiling method |
JP3992102B2 (en) * | 2003-06-04 | 2007-10-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Compiler device, compilation method, compiler program, and recording medium |
JP2004318628A (en) * | 2003-04-18 | 2004-11-11 | Hitachi Industries Co Ltd | Processor unit |
US7051146B2 (en) * | 2003-06-25 | 2006-05-23 | Lsi Logic Corporation | Data processing systems including high performance buses and interfaces, and associated communication methods |
US7917734B2 (en) * | 2003-06-30 | 2011-03-29 | Intel Corporation | Determining length of instruction with multiple byte escape code based on information from other than opcode byte |
US7073007B1 (en) * | 2003-07-22 | 2006-07-04 | Cisco Technology, Inc. | Interrupt efficiency across expansion busses |
US20050028132A1 (en) * | 2003-07-31 | 2005-02-03 | Srinivasamurthy Venugopal K. | Application specific optimization of interpreters for embedded systems |
US7610473B2 (en) * | 2003-08-28 | 2009-10-27 | Mips Technologies, Inc. | Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor |
US7207038B2 (en) * | 2003-08-29 | 2007-04-17 | Nokia Corporation | Constructing control flows graphs of binary executable programs at post-link time |
US7328436B2 (en) * | 2003-09-15 | 2008-02-05 | Motorola, Inc. | Dynamic allocation of internal memory at runtime |
US20050071611A1 (en) | 2003-09-30 | 2005-03-31 | International Business Machines Corporation | Method and apparatus for counting data accesses and instruction executions that exceed a threshold |
US20050086662A1 (en) * | 2003-10-21 | 2005-04-21 | Monnie David J. | Object monitoring system in shared object space |
US7631307B2 (en) * | 2003-12-05 | 2009-12-08 | Intel Corporation | User-programmable low-overhead multithreading |
US7401328B2 (en) * | 2003-12-18 | 2008-07-15 | Lsi Corporation | Software-implemented grouping techniques for use in a superscalar data processing system |
US7380039B2 (en) * | 2003-12-30 | 2008-05-27 | 3Tera, Inc. | Apparatus, method and system for aggregrating computing resources |
US7370180B2 (en) * | 2004-03-08 | 2008-05-06 | Arm Limited | Bit field extraction with sign or zero extend |
US7802080B2 (en) * | 2004-03-24 | 2010-09-21 | Arm Limited | Null exception handling |
US20050262487A1 (en) * | 2004-05-11 | 2005-11-24 | International Business Machines Corporation | System, apparatus, and method for identifying authorization requirements in component-based systems |
US7376674B2 (en) * | 2004-05-14 | 2008-05-20 | Oracle International Corporation | Storage of multiple pre-modification short duration copies of database information in short term memory |
JP2005338987A (en) * | 2004-05-25 | 2005-12-08 | Fujitsu Ltd | Exception test support program and device |
EP1622009A1 (en) * | 2004-07-27 | 2006-02-01 | Texas Instruments Incorporated | JSM architecture and systems |
US20060031820A1 (en) * | 2004-08-09 | 2006-02-09 | Aizhong Li | Method for program transformation and apparatus for COBOL to Java program transformation |
US7818723B2 (en) * | 2004-09-07 | 2010-10-19 | Sap Ag | Antipattern detection processing for a multithreaded application |
US7194606B2 (en) * | 2004-09-28 | 2007-03-20 | Hewlett-Packard Development Company, L.P. | Method and apparatus for using predicates in a processing device |
US7370129B2 (en) * | 2004-12-15 | 2008-05-06 | Microsoft Corporation | Retry strategies for use in a streaming environment |
US20060236000A1 (en) * | 2005-04-15 | 2006-10-19 | Falkowski John T | Method and system of split-streaming direct memory access |
US7877740B2 (en) * | 2005-06-13 | 2011-01-25 | Hewlett-Packard Development Company, L.P. | Handling caught exceptions |
-
2004
- 2004-07-27 EP EP04291918A patent/EP1622009A1/en not_active Withdrawn
-
2005
- 2005-04-28 US US11/116,893 patent/US20060026396A1/en not_active Abandoned
- 2005-04-28 US US11/116,897 patent/US20060026397A1/en not_active Abandoned
- 2005-04-28 US US11/116,918 patent/US20060026398A1/en not_active Abandoned
- 2005-04-28 US US11/116,522 patent/US8185666B2/en active Active
- 2005-05-24 US US11/135,796 patent/US20060026392A1/en not_active Abandoned
- 2005-07-21 US US11/186,063 patent/US20060026183A1/en not_active Abandoned
- 2005-07-21 US US11/186,330 patent/US20060026394A1/en not_active Abandoned
- 2005-07-21 US US11/186,271 patent/US7930689B2/en active Active
- 2005-07-21 US US11/186,239 patent/US7574584B2/en active Active
- 2005-07-21 US US11/186,315 patent/US8516496B2/en active Active
- 2005-07-21 US US11/186,036 patent/US8078842B2/en active Active
- 2005-07-21 US US11/186,062 patent/US20060023517A1/en not_active Abandoned
- 2005-07-22 US US11/187,199 patent/US20060026200A1/en not_active Abandoned
- 2005-07-25 US US11/188,503 patent/US7587583B2/en active Active
- 2005-07-25 US US11/188,336 patent/US20060026401A1/en not_active Abandoned
- 2005-07-25 US US11/188,667 patent/US20060026312A1/en not_active Abandoned
- 2005-07-25 US US11/188,504 patent/US7500085B2/en active Active
- 2005-07-25 US US11/188,491 patent/US7546437B2/en active Active
- 2005-07-25 US US11/188,550 patent/US20060026201A1/en not_active Abandoned
- 2005-07-25 US US11/188,923 patent/US20060026322A1/en not_active Abandoned
- 2005-07-25 US US11/188,668 patent/US7260682B2/en active Active
- 2005-07-25 US US11/188,502 patent/US7757223B2/en active Active
- 2005-07-25 US US11/188,551 patent/US9201807B2/en active Active
- 2005-07-25 US US11/188,827 patent/US7493476B2/en active Active
- 2005-07-25 US US11/188,670 patent/US8380906B2/en active Active
- 2005-07-25 US US11/188,311 patent/US7533250B2/en active Active
- 2005-07-25 US US11/188,309 patent/US20060026407A1/en not_active Abandoned
- 2005-07-25 US US11/188,411 patent/US7606977B2/en active Active
- 2005-07-25 US US11/188,310 patent/US8046748B2/en active Active
- 2005-07-25 US US11/188,592 patent/US8024554B2/en active Active
- 2005-07-26 US US11/189,245 patent/US20060026126A1/en not_active Abandoned
- 2005-07-26 US US11/189,422 patent/US7743384B2/en active Active
- 2005-07-26 US US11/189,211 patent/US8024716B2/en active Active
- 2005-07-26 US US11/189,637 patent/US7752610B2/en active Active
- 2005-07-26 US US11/189,410 patent/US7543285B2/en active Active
- 2005-07-26 US US11/189,367 patent/US7624382B2/en active Active
- 2005-07-26 US US11/189,411 patent/US20060026580A1/en not_active Abandoned
Patent Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5551015A (en) * | 1988-12-06 | 1996-08-27 | Lucent Technologies Inc. | Method and apparatus for direct conversion of programs in object code form between different hardware architecture computer systems |
US5507030A (en) * | 1991-03-07 | 1996-04-09 | Digitial Equipment Corporation | Successive translation, execution and interpretation of computer program having code at unknown locations due to execution transfer instructions having computed destination addresses |
US5781750A (en) * | 1994-01-11 | 1998-07-14 | Exponential Technology, Inc. | Dual-instruction-set architecture CPU with hidden software emulation mode |
US5560013A (en) * | 1994-12-06 | 1996-09-24 | International Business Machines Corporation | Method of using a target processor to execute programs of a source architecture that uses multiple address spaces |
US6026485A (en) * | 1996-01-24 | 2000-02-15 | Sun Microsystems, Inc. | Instruction folding for a stack-based machine |
US5909578A (en) * | 1996-09-30 | 1999-06-01 | Hewlett-Packard Company | Use of dynamic translation to burst profile computer applications |
US5937193A (en) * | 1996-11-27 | 1999-08-10 | Vlsi Technology, Inc. | Circuit arrangement for translating platform-independent instructions for execution on a hardware platform and method thereof |
US5892966A (en) * | 1997-06-27 | 1999-04-06 | Sun Microsystems, Inc. | Processor complex for executing multimedia functions |
US6075942A (en) * | 1998-05-04 | 2000-06-13 | Sun Microsystems, Inc. | Encoding machine-specific optimization in generic byte code by using local variables as pseudo-registers |
US6480952B2 (en) * | 1998-05-26 | 2002-11-12 | Advanced Micro Devices, Inc. | Emulation coprocessor |
US6205540B1 (en) * | 1998-06-19 | 2001-03-20 | Franklin Electronic Publishers Incorporated | Processor with enhanced instruction set |
US6941545B1 (en) * | 1999-01-28 | 2005-09-06 | Ati International Srl | Profiling of computer programs executing in virtual memory systems |
US6954923B1 (en) * | 1999-01-28 | 2005-10-11 | Ati International Srl | Recording classification of instructions executed by a computer |
US7047394B1 (en) * | 1999-01-28 | 2006-05-16 | Ati International Srl | Computer for execution of RISC and CISC instruction sets |
US7254806B1 (en) * | 1999-08-30 | 2007-08-07 | Ati International Srl | Detecting reordered side-effects |
US7739673B2 (en) * | 2000-01-07 | 2010-06-15 | Sony Computer Entertainment Inc. | Multiple stage program recompiler using information flow determination |
US7020766B1 (en) * | 2000-05-30 | 2006-03-28 | Intel Corporation | Processing essential and non-essential code separately |
US7093239B1 (en) * | 2000-07-14 | 2006-08-15 | Internet Security Systems, Inc. | Computer immune system and method for detecting unwanted code in a computer system |
US7069545B2 (en) * | 2000-12-29 | 2006-06-27 | Intel Corporation | Quantization and compression for computation reuse |
US20040024999A1 (en) * | 2002-07-30 | 2004-02-05 | Texas Instruments Incorporated | Micro-sequence execution in a processor |
US7194732B2 (en) * | 2003-06-26 | 2007-03-20 | Hewlett-Packard Development Company, L.P. | System and method for facilitating profiling an application |
US7899661B2 (en) * | 2006-02-16 | 2011-03-01 | Synopsys, Inc. | Run-time switching for simulation with dynamic run-time accuracy adjustment |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080049690A1 (en) * | 2006-08-23 | 2008-02-28 | Motorola, Inc. | Downlink control channel signaling in wireless communication systems |
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