US20060006390A1 - Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same - Google Patents
Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same Download PDFInfo
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- US20060006390A1 US20060006390A1 US11/000,837 US83704A US2006006390A1 US 20060006390 A1 US20060006390 A1 US 20060006390A1 US 83704 A US83704 A US 83704A US 2006006390 A1 US2006006390 A1 US 2006006390A1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 134
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 134
- 239000010409 thin film Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 145
- 238000000034 method Methods 0.000 claims abstract description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000013532 laser treatment Methods 0.000 claims description 25
- 238000002425 crystallisation Methods 0.000 claims description 15
- 230000008025 crystallization Effects 0.000 claims description 15
- 238000007711 solidification Methods 0.000 claims description 12
- 230000008023 solidification Effects 0.000 claims description 12
- 230000003746 surface roughness Effects 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 64
- 239000010408 film Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000001459 lithography Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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- H01L21/02518—Deposited layers
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices
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- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
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Abstract
A method for forming a polysilicon structure is provided. An amorphous silicon structure with a first amorphous silicon region and a second amorphous silicon region is formed in a first region and a second region of a substrate, respectively. The first amorphous silicon region is thinner than the second amorphous silicon region. The amorphous silicon structure is crystallized to form the polysilicon structure with a first polysilicon region and a second polysilicon region corresponding to the first amorphous silicon region and the second amorphous silicon region.
Description
- The present invention relates to a low temperature polysilicon film and in particular to a polysilicon structure formed by crystallization of an amorphous silicon structure, methods for forming the same, and devices utilizing the film.
- Typically, thin film transistors (TFTs) are used as the active devices in active matrix flat panel displays. For example, TFTs are employed to drive the liquid crystal display (LCD) or the organic light emitting display (OLED).
- Conventionally, hydrogenated amorphous silicon (α-Si:H) is used as the semiconductor film (active layer) of a TFT. Polysilicon, however, may provide higher electron transmission than amorphous silicon due to more regular crystal orientation. Thus a development trend is to utilize the polysilicon instead of amorphous silicon in TFT technology.
- Typically, there are three methods for forming the thin polysilicon film. In a first method, the polysilicon film is formed by deposition. In this method, the polysilicon film requires a sufficient thickness, so as to grow large grains. Thus, the polysilicon film has a poor surface uniformity that adversely affects the formation of the subsequent gate insulating layer. Moreover, the deposition temperature is high (600° C.), which also adversely affects the fabrication of the device. In a second method, thermal treatment is performed on an amorphous silicon layer, so as to transfer to a polysilicon layer. In this method, the polysilicon layer may be less thick and have a better surface uniformity. However, a high deposition temperature (600° C.) and long deposition duration are required and the thermal budget increases. As a result, throughput and device reliability suffer. In a third method, perform a laser treatment to transfer an amorphous silicon layer into a polysilicon layer. The method is the most commonly used.
- The polysilicon TFT display comprises a display region and a driving circuit region, wherein the switching devices on the driving circuit region require higher switching rate and readability. That is, the switching devices on the driving circuit region preferably have higher electron transmission and better sub-threshold swing. A polysilicon layer with large grain size can provide such electronic characteristics. Additionally, current leakage in, the display region must be low. If the surface roughness of the polysilicon layer is too high, poor coverage of the gate insulating layer thereon results, thus increasing current leakage. If the grain size of the polysilicon layer is small, low surface roughness results, improving the coverage of the gate insulating layer thereon and reducing current leakage. That is, in order to improve the electronic characteristics of the polysilicon TFT display, the polysilicon layer on the driving circuit region must have a relatively large grain size and that on the display region a relatively small grain size.
- In order to form a polysilicon film with different grain sizes on the driving circuit region and the display region, respectively, for fabrication of the polysilicon TFT display, the driving circuit region and the display region must be respectively treated. For example, a laser treatment with a relatively low scanning rate is performed on the amorphous silicon layer on the driving circuit region, to form the polysilicon layer with a relatively large grain size. The laser treatment with a relatively high scanning rate is subsequently performed on the amorphous silicon layer on the display region, to form the polysilicon layer with relatively small grain size. The problems presented by laser alignment and mask changes may reduce yield and throughput. Thus, an improved method for forming polysilicon layers with different grain sizes is desirable.
- Embodiments of the invention provide a polysilicon structure on a substrate. The polysilicon structure comprises a first polysilicon region and a second polysilicon region. A thickness of the first polysilicon region is less than that of the second a thickness and a grain size of the first polysilicon region is larger than that of the second polysilicon region.
- Embodiments of the invention additionally provide a method for forming a polysilicon structure. A substrate having a first region and a second region is provided. An amorphous silicon structure with a first amorphous silicon region and a second amorphous silicon region is formed in the first region and the second region, respectively. The first amorphous silicon region is thinner than the second amorphous silicon region. The amorphous silicon structure is crystallized to form the polysilicon structure with a first polysilicon region and a second polysilicon region corresponding to the first and second amorphous silicon regions, respectively.
- Embodiments of the invention further provide a method for forming a polysilicon structure. A substrate having a first region, a second region, and a third region is provided. An amorphous silicon layer with a first amorphous silicon region, a second amorphous silicon region, and a third amorphous silicon region, is formed on the substrate, in which the first, second and third amorphous silicon regions, are respectively in the first region, the second region and the third region. The first amorphous silicon region is thinner than the second amorphous silicon region, which is thinner than the third amorphous silicon region. The amorphous silicon structure is crystallized to form the polysilicon structure with a first polysilicon region, a second polysilicon region and a third polysilicon region corresponding to the first, second and third amorphous silicon regions, respectively.
- Embodiments of the invention still further provide a flat panel display. The display comprises a first transistor and a second transistor. The first transistor is disposed on the substrate and comprises a first polysilicon region serving as a first active region. The second transistor is disposed on the substrate and comprises a second polysilicon region serving as a second active region. Moreover, the first polysilicon region is thinner than the second polysilicon region and a grain size of the first polysilicon region is larger than that of the second polysilicon region.
- Embodiments of the invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the invention.
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FIGS. 1A to 1C are cross-sections of a method for forming a polysilicon structure of the first embodiment of the present invention. -
FIGS. 2A to 2D are cross-sections of a method for forming a polysilicon structure of the second embodiment of the present invention. -
FIGS. 3A to 3B are cross-sections of a method for forming a polysilicon structure of the third embodiment of the present invention. -
FIGS. 4A to 4C are cross-sections of a method for forming thin film transistors for a flat panel display of the fourth embodiment of the present invention. - In the first embodiment, as shown in
FIG. 1A , asubstrate 100 comprising adriving circuit region 1 and adisplay region 2 is provided. A firstamorphous silicon layer 110 is formed on thesubstrate 100 corresponding to thedisplay region 2 of thesubstrate 100 by deposition, lithography, and etching. For example, an amorphous silicon layer (not shown) is formed by chemical vapor deposition (CVD). Thereafter, lithography and etching are performed on the amorphous silicon layer to form the firstamorphous silicon layer 110 in thedisplay region 2 of thesubstrate 100, wherein the etching may comprise wet or dry etching. - A second amorphous silicon layer 120 is subsequently formed on the
substrate 100 corresponding to thedriving circuit region 1 of thesubstrate 100 and covers the firstamorphous silicon layer 110 in thedisplay region 2, as shown inFIG. 1B . As a result, an amorphous silicon structure with a firstamorphous silicon region 121 a in thedriving circuit region 1 and a second amorphous silicon region 121 b in thedisplay region 2 is formed on thesubstrate 100. The difference in thickness between the firstamorphous silicon region 121 a in thedriving circuit region 1 and the second amorphous silicon region 121 b in thedisplay region 2 must be maintained within a specific range. If the difference in thickness of the firstamorphous silicon region 121 a and the second amorphous silicon region 121 b is too low, the difference in grain size therebetween is small, thus, the electronic characteristics of the polysilicon TFT are reduced. Conversely, if the difference in thickness of the firstamorphous silicon region 121 a and the second amorphous silicon region 121 b is too high, further adjustment of process conditions is required, such as the ion implanting energy and dosage, complicating the process. Therefore, the difference in thickness must be maintained within a range of about 100 to 1000 Å, and preferably 200 to 400 Å. - The amorphous silicon structure is crystallized. That is, crystallization is simultaneously performed on the first and second
amorphous silicon regions 121 a and 121 b, such that the amorphous silicon structure is transferred into apolysilicon structure 130 with afirst polysilicon region 130 a and asecond polysilicon region 130 b corresponding to the firstamorphous silicon region 121 a and a second amorphous silicon region 121 b, respectively, as shown inFIG. 1C . In some embodiments, the crystallization may comprise a laser treatment that employs, for example, an excimer laser, continuous wave laser (CW laser), or laser beam pulse. Moreover, the laser treatment may comprise lateral solidification (LS), sequential lateral solidification (SLS), continuous grain silicon (CGS), or metal induced lateral crystallization (MILC). - Since the thickness of the second amorphous silicon layer 120 in the
driving circuit region 1 is less than the total thickness of the first and second amorphous silicon layers 110 and 120 in thedisplay region 2, the meltability of the second amorphous silicon layer 120 in thedriving circuit region 1 after the laser treatment, is higher than that of the first and second amorphous silicon layers 110 and 120 in thedisplay region 2. Accordingly, thefirst polysilicon region 130 a in thedriving circuit region 1 can be formed with larger grain size, thereby effectively improving electron mobility and sub-threshold swing. Conversely, since the total thickness of the first and second amorphous silicon layers 110 and 120 in thedisplay region 2 is thicker than that of the second amorphous silicon layer 120 in thedriving circuit region 1, the meltability of the first and second amorphous silicon layers 110 and 120 in thedisplay region 2 after the laser treatment, is lower than that of the second amorphous silicon layer 120 in thedriving circuit region 1. Accordingly, thesecond polysilicon region 130 b in thedisplay region 2 can be formed with smaller grain size, thereby lowering the surface roughness of thepolysilicon layer 130 in thedisplay region 2 to reduce current leakage. In the first embodiment, the mentioned potential advantages can be obtained with one laser treatment procedure, eliminating problems presented by laser alignment and mask changes, thus reducing process time. - In the second embodiment, as shown in
FIG. 2A , asubstrate 200 comprising adriving circuit region 3 and adisplay region 4 is provided. A firstamorphous silicon layer 210 is formed on thesubstrate 200. For example, theamorphous silicon layer 210 is formed by chemical vapor deposition (CVD). - Thereafter, the first
amorphous silicon layer 210 in thedriving circuit region 3 is partially removed by lithography and etching to form the firstamorphous silicon layer 210 with differing thicknesses respectively in thedriving circuit region 3 and displayregion 4, as shown inFIG. 2B . Here, the etching may comprise wet or dry etching. Moreover, the difference in thickness between the firstamorphous silicon layer 210 in thedriving circuit region 3 and that in thedisplay region 4 must be maintained within a specific range. - A second
amorphous silicon layer 220 is subsequently formed on the firstamorphous silicon layer 210 in thedriving circuit region 3 and thedisplay region 4, as shown inFIG. 2C . As a result, an amorphous silicon structure with a firstamorphous silicon region 221 a in thedriving circuit region 3 and a secondamorphous silicon region 221 b in thedisplay region 4 is formed on thesubstrate 100. Since the difference in thickness between the firstamorphous silicon layer 210 in thedriving circuit region 3 and that in thedisplay region 4 is maintained within a specific range, the difference in thickness can be maintained within a specific range after forming the secondamorphous silicon layer 220 on the firstamorphous silicon layer 210. As mentioned, if the difference in thickness is too low, the difference in grain size between the subsequently formed polysilicon silicon layer in thedriving circuit region 3 and that in thedisplay region 4 is small, reducing the electronic characteristics of the polysilicon TFT. Conversely, if the difference in thickness is too high, further adjustment of process conditions is required, such as the ion implanting energy and dosage, complicating the process. Thus, the difference in thickness must be maintained within a range of about 100 to 1000 Å, and preferably 200 to 400 Å. - The amorphous silicon structure is crystallized. That is, crystallization is simultaneously performed on the first and second
amorphous silicon regions polysilicon structure 230 with afirst polysilicon region 230 a and asecond polysilicon region 230 b corresponding to the firstamorphous silicon region 221 a and a secondamorphous silicon region 221 b, respectively, as shown inFIG. 2D . In the second embodiment, the crystallization may comprise a laser treatment that employs, for example, an excimer laser, continuous wave laser (CW laser), or laser beam pulse. Moreover, the laser treatment may comprise lateral solidification (LS), sequential lateral solidification (SLS), continuous grain silicon (CGS), or metal induced lateral crystallization (MILC). - Since the thickness of the second
amorphous silicon layer 220 in thedriving circuit region 3 is less than the total thickness of the first and second amorphous silicon layers 210 and 220 in thedisplay region 4, the meltability of the secondamorphous silicon layer 220 in thedriving circuit region 3 after the laser treatment, is higher than that of the first and second amorphous silicon layers 210 and 220 in thedisplay region 4. Accordingly, thefirst polysilicon region 230 a in thedriving circuit region 3 can be formed with larger grain size, thereby effectively improving electron mobility and sub-threshold swing. Conversely, since the total thickness of the first and second amorphous silicon layers 210 and 220 in thedisplay region 4 is greater than that of the secondamorphous silicon layer 220 in thedriving circuit region 3, the meltability of the first and second amorphous silicon layers 210 and 220 in thedisplay region 4 after the laser treatment, is lower than that of theamorphous silicon layer 220 in thedriving circuit region 3. Accordingly, thesecond polysilicon region 230 b on thedisplay region 4 can be formed with smaller grain size, thereby lowering the surface roughness of thepolysilicon layer 230 in thedisplay region 4 to reduce current leakage. In the second embodiment, the mentioned potential advantages can be obtained with one laser treatment procedure, eliminating problems presented by laser alignment and mask changes, thus reducing process time. - In the third embodiment, as shown in
FIG. 3A , asubstrate 300 comprising afirst region 5, asecond region 6 and athird region 7 is provided. Anamorphous silicon structure 310 with a firstamorphous silicon region 310 a in thefirst region 5, a secondamorphous silicon region 310 b in thesecond region 6 and a thirdamorphous silicon region 310 c in thethird region 7 is formed on thesubstrate 300, wherein the thicknesses of theamorphous silicon structure 310 in the first, second, andthird regions amorphous silicon region 310 a in thefirst region 5 has a thickness less than that of the thirdamorphous silicon region 310 c in thethird region 7, and the secondamorphous silicon region 310 b in thesecond region 6 has a thickness between that of the first and thirdamorphous silicon regions third regions - The difference in thickness between the
amorphous silicon structure 310 in thefirst region 5 and thethird region 7 must be maintained within a specific range. If the difference in thickness is too low, the difference in grain size between the subsequently formed polysilicon silicon structure in different regions is small, thus the electronic characteristics of the polysilicon TFT are reduced. Conversely, if the difference in thickness is too high, further adjustment of process conditions is required, such as the ion implanting energy and dosage, complicating the process. In the third embodiment, the difference in thickness may be maintained within a range of about 100 to 1000 Å, and preferably 200 to 400 Å. - The
amorphous silicon structure 310 is crystallized. That is, crystallization is simultaneously performed on the first, second, and thirdamorphous silicon regions amorphous silicon structure 310 is transferred into apolysilicon structure 330 with afirst polysilicon region 330 a, asecond polysilicon region 330 b, and athird polysilicon region 330 c corresponding to the first, second, and thirdamorphous silicon regions FIG. 3B . In the third embodiments, the crystallization may comprise a laser treatment that employs, for example, an excimer laser, continuous wave laser (CW laser), or laser beam pulse. Moreover, the laser treatment may comprise lateral solidification (LS), sequential lateral solidification (SLS), continuous grain silicon (CGS), or metal induced lateral crystallization (MILC). - Since the thicknesses (surface levels) of the
amorphous silicon structure 310 in the first, second, andthird regions amorphous silicon structure 310 in the first, second, andthird regions polysilicon layer 330 in the first, second, andthird regions polysilicon structure 330 with different grain sizes indifferent regions amorphous silicon structure 310 having different thicknesses indifferent regions - In the fourth embodiment, as
FIG. 4C illustrates, thin film transistors for a flat panel display are provided. The thin film transistors are disposed on asubstrate 400 comprising adriving circuit region 8 and a display region 9. Apolysilicon structure 430 with afirst polysilicon region 410 a and asecond polysilicon region 410 b is disposed on thesubstrate 400. The first andsecond polysilicon regions first polysilicon region 430 a in thedriving circuit region 8 is thinner, has a larger grain size, and a higher surface roughness than that of thesecond polysilicon region 430 b in the display region 9, thereby improving electron mobility and sub-threshold swing of the thin film transistor in thedriving circuit region 8 and reducing current leakage of the thin film transistor in the display region 9. -
FIGS. 4A to 4C illustrate a method for forming thin film transistors for a flat panel display of the fourth embodiment of the present invention. As shown inFIG. 4A , asubstrate 400 comprising adriving circuit region 8 and a display region 9 is provided. Abuffer layer 405 is subsequently formed on thesubstrate 400. Anamorphous silicon structure 410 with a firstamorphous silicon region 410 a and a secondamorphous silicon region 410 b is formed on thebuffer layer 405. The firstamorphous silicon layer 410 a in thedriving circuit region 8 has a thickness less than that of the secondamorphous silicon region 410 b in the display region 9. The difference in thickness between theamorphous silicon structure 410 in thedriving circuit region 8 and that in the display region 9 may be maintained within a specific range. For example, the difference in thickness may be maintained within a range of about 100 to 1000 Å, and preferably 200 to 400 Å. - Thereafter, crystallization is simultaneously performed on the
amorphous silicon structure 410 in thedriving circuit region 8 and the display region 9, such that theamorphous silicon structure 410 is transferred into apolysilicon structure 430, as shown inFIG. 4B . In this embodiment, the crystallization may comprise a laser treatment which employs, for example, an excimer laser, continuous wave laser (CW laser), or laser beam pulse. Moreover, the laser treatment may comprise lateral solidification (LS), sequential lateral solidification (SLS), continuous grain silicon (CGS), or metal induced lateral crystallization (MILC). -
Gate insulating layer 440 is formed on thepolysilicon structure 430.Gates 450 is subsequently formed on thegate insulating layer 440, as shown inFIG. 4B . Thereafter, ion implantation is performed on thepolysilicon layer 430 using thegates 450 as masks to form sources S, drains D, and channels C. - An interlayer dielectric (ILD)
layer 460 is formed on thegate insulating layer 440 and covers thegates 450. Next, interconnects 470 are formed in theILD layer 460, as shown inFIG. 4C . Finally, processes for fabricating the flat panel display are then successively proceeded and the flat panel display (not shown) is complete. - While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.
Claims (34)
1. A polysilicon structure comprising:
a substrate; and
a polysilicon layer formed on the substrate, wherein the polysilicon layer comprises a first region and a second region, wherein the thickness of the first region is smaller than the thickness of the second region, and a grain size of the first region is larger than a grain size of the second region.
2. The polysilicon structure as claimed in claim 1 , wherein the difference in thickness between the first region and the second region is about 100 to 1000 Å.
3. The polysilicon structure as claimed in claim 1 , wherein the difference in thickness between the first region and the second region is about 200 to 400 Å.
4. The polysilicon structure as claimed in claim 1 , wherein the first region has a surface roughness higher than that of the second region.
5. The polysilicon structure as claimed in claim 1 , wherein the polysilicon layer further comprises a third region, and the thickness of the third region is between those of the first region and the second region.
6. The polysilicon structure as claimed in claim 5 , wherein a grain size of the third region is between those of the first region and the second region.
7. The polysilicon structure as claimed in claim 5 , wherein the third polysilicon region has a surface roughness between those of the first and second polysilicon regions.
8. A method for forming a polysilicon structure, comprising:
providing a substrate having a first region and a second region;
forming an amorphous silicon structure on the substrate with a first amorphous silicon region in the first region and a second amorphous silicon region in the second region, wherein the first amorphous silicon region is thinner than the second amorphous silicon region; and
crystallizing the amorphous silicon structure to form the polysilicon structure with a first polysilicon region and a second polysilicon region corresponding to the first amorphous silicon region and the second amorphous silicon region, respectively.
9. The method as claimed in claim 8 , wherein the formation of the amorphous silicon structure further comprises:
forming a first amorphous silicon layer in the second region; and
forming a second amorphous silicon layer in the first region and covering the first amorphous silicon layer.
10. The method as claimed in claim 9 , wherein the first amorphous silicon layer is formed by chemical vapor deposition.
11. The method as claimed in claim 9 , wherein the second amorphous silicon layer is formed by chemical vapor deposition.
12. The method as claimed in claim 8 , wherein the formation of the amorphous silicon structure further comprises:
forming a first amorphous silicon layer in the first and second regions;
partially removing the first amorphous silicon layer in the first region; and
forming a second amorphous silicon layer on the partially removed first amorphous silicon layer.
13. The method as claimed in claim 12 , wherein the first amorphous silicon layer is formed by chemical vapor deposition.
14. The method as claimed in claim 12 , wherein the first amorphous silicon layer in the first region is partially removed by etching.
15. The method as claimed in claim 12 , wherein the second amorphous silicon layer is formed by chemical vapor deposition.
16. The method as claimed in claim 8 , wherein the crystallizing comprises a laser treatment.
17. The method as claimed in claim 16 , wherein the laser treatment employs an excimer laser, continuous wave laser, or laser beam pulse.
18. The method as claimed in claim 16 , wherein the laser treatment comprises lateral solidification, sequential lateral solidification, continuous grain silicon, or metal induced lateral crystallization.
19. A method for forming a polysilicon structure, comprising:
providing a substrate having a first region, a second region, and a third region;
forming an amorphous silicon structure on the substrate with a first amorphous silicon region in the first region, a second amorphous silicon region in the second region, and a third amorphous silicon region in the third region, wherein the first amorphous silicon region is thinner than the second amorphous silicon region which is thinner than the third amorphous silicon region; and
crystallizing the amorphous silicon structure to form the polysilicon structure with a first polysilicon region, a second region, and a third polysilicon region corresponding to the first amorphous silicon region, a second amorphous silicon region, and a third amorphous silicon region, respectively.
20. The method as claimed in claim 19 , wherein the difference in thickness between the first polysilicon region and the third polysilicon region is about 100 to 1000 Å.
21. The method as claimed in claim 19 , wherein the difference in thickness between the first polysilicon region and the third polysilicon region is about 200 to 400 Å.
22. The method as claimed in claim 19 , wherein the difference in thickness between the first polysilicon region and the second polysilicon region is about 100 to 1000 Å.
23. The method as claimed in claim 19 , wherein the difference in thickness between the first polysilicon region and the second polysilicon region is about 200 to 400 Å.
24. The method as claimed in claim 19 , wherein the difference in thickness between the second polysilicon region and the third polysilicon region is about 100 to 1000 Å.
25. The method as claimed in claim 19 , wherein the difference in thickness between the second polysilicon region and the third polysilicon region is about 200 to 400 Å.
26. The method as claimed in claim 19 , wherein the first polysilicon region has a grain size larger than that of the second polysilicon region which has a grain size larger than that of the third polysilicon region.
27. The method as claimed in claim 19 , wherein the first polysilicon region has a surface roughness higher than that of the second polysilicon region which has a surface roughness higher than that of the third polysilicon region.
28. The method as claimed in claim 19 , wherein the crystallizing comprises a laser treatment.
29. The method as claimed in claim 28 , wherein the laser treatment employs an excimer laser, continuous wave laser, or laser beam pulse.
30. The method as claimed in claim 28 , wherein the laser treatment comprises lateral solidification, sequential lateral solidification, continuous grain silicon, or metal induced lateral crystallization.
31. A thin film transistor panel, comprising:
a substrate;
a first transistor disposed on the substrate and comprising a first polysilicon region serving as a first active region; and
a second transistor disposed on the substrate and comprising a second polysilicon region serving as a second active region;
wherein the first polysilicon region is thinner than the second polysilicon region and a grain size of the first polysilicon region is larger than that of the second polysilicon region.
32. The panel as claimed in claim 31 , wherein the difference in thickness between the first polysilicon region and the second polysilicon region is about 100 to 1000 Å.
33. The panel as claimed in claim 31 , wherein the difference in thickness between the first polysilicon region and the second polysilicon region is about 200 to 400 Å.
34. The panel as claimed in claim 31 , wherein the first polysilicon region has a surface roughness higher than that of the second polysilicon region.
Priority Applications (2)
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US11/689,668 US7303981B2 (en) | 2004-07-09 | 2007-03-22 | Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same |
US11/689,687 US20070176180A1 (en) | 2004-07-09 | 2007-03-22 | Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same |
Applications Claiming Priority (2)
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TW093120581A TWI285783B (en) | 2004-07-09 | 2004-07-09 | Poly silicon layer structure and forming method thereof |
TW93120581 | 2004-07-09 |
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US11/689,668 Division US7303981B2 (en) | 2004-07-09 | 2007-03-22 | Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same |
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US11/689,687 Abandoned US20070176180A1 (en) | 2004-07-09 | 2007-03-22 | Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same |
US11/689,668 Active US7303981B2 (en) | 2004-07-09 | 2007-03-22 | Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same |
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US11/689,668 Active US7303981B2 (en) | 2004-07-09 | 2007-03-22 | Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same |
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Cited By (2)
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US20070166898A1 (en) * | 2004-07-09 | 2007-07-19 | Au Optronics Corp. | Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same |
US20210327902A1 (en) * | 2020-04-17 | 2021-10-21 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor wafer with devices having different top layer thicknesses |
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US8294222B2 (en) * | 2008-12-23 | 2012-10-23 | International Business Machines Corporation | Band edge engineered Vt offset device |
US8816473B2 (en) | 2012-04-05 | 2014-08-26 | International Business Machines Corporation | Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication |
TWI552344B (en) * | 2013-12-03 | 2016-10-01 | 財團法人國家實驗研究院 | Transistor device structure and method for manufacturing the same |
KR102233669B1 (en) * | 2014-07-28 | 2021-03-31 | 삼성디스플레이 주식회사 | Display substrate, method of manufacturing a display substrate and organic light emitting display device having a display substrate |
KR102293732B1 (en) * | 2014-10-08 | 2021-08-27 | 삼성디스플레이 주식회사 | Thin film transistor substrate, display apparatus comprising the same, method for manufacturing thin film transistor substrate, and method for manufacturing display apparatus |
CN105336766A (en) * | 2015-10-22 | 2016-02-17 | 上海华虹宏力半导体制造有限公司 | Method for locally thinning SOI top layer silicon thickness |
CN105206569A (en) | 2015-10-23 | 2015-12-30 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
CN105489637B (en) * | 2015-11-27 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | The forming method of semiconductor structure |
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Also Published As
Publication number | Publication date |
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US20070176180A1 (en) | 2007-08-02 |
US20070166898A1 (en) | 2007-07-19 |
TW200602776A (en) | 2006-01-16 |
US7303981B2 (en) | 2007-12-04 |
TWI285783B (en) | 2007-08-21 |
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