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Publication numberUS20050285140 A1
Publication typeApplication
Application numberUS 10/875,141
Publication date29 Dec 2005
Filing date23 Jun 2004
Priority date23 Jun 2004
Also published asUS8569146, US20070161206, US20110117724
Publication number10875141, 875141, US 2005/0285140 A1, US 2005/285140 A1, US 20050285140 A1, US 20050285140A1, US 2005285140 A1, US 2005285140A1, US-A1-20050285140, US-A1-2005285140, US2005/0285140A1, US2005/285140A1, US20050285140 A1, US20050285140A1, US2005285140 A1, US2005285140A1
InventorsChih-Hsin Ko, Yee-Chia Yeo, Wen-Chin Lee, Chung-Hu Ge
Original AssigneeChih-Hsin Ko, Yee-Chia Yeo, Wen-Chin Lee, Chung-Hu Ge
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Isolation structure for strained channel transistors
US 20050285140 A1
Abstract
A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.
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Claims(25)
1. A strained channel transistor with at least one isolation structure, the transistor being formed on a semiconductor substrate comprising a strained silicon layer overlying a tensile strain forming buffer layer, the isolation structure comprising:
an active region formed in the semiconductor substrate; and
at least one nitrogen-containing liner isolation region next to the active region.
2. The transistor according to claim 1, wherein the isolation region is a shallow trench isolation region with a trench depth in the range of 2000 to 6000 angstroms.
3. The transistor according to claim 1, wherein the nitrogen-containing liner has a thickness in the range of 10 to 500 angstroms.
4. The transistor according to claim 1, wherein a channel region is formed in the strained silicon layer of the active region with a source or drain region formed between the channel region and the isolation region.
5. The transistor according to claim 1, wherein the tensile strain forming buffer layer is a relaxed silicon-germanium layer.
6. The transistor according to claim 5, wherein the substrate further comprises a graded silicon-germanium buffer layer underlying the relaxed silicon-germanium layer, the graded silicon-germanium buffer layer overlying a silicon substrate.
7. The transistor according to claim 1, wherein the isolation region further comprises an oxide liner underlying the nitrogen-containing liner.
8. The transistor according to claim 1, wherein the isolation region includes a gap filler material.
9. The transistor according to claim 1, wherein the nitrogen-containing liner comprises at least one of silicon nitride, silicon oxynitride, or nitrogen-doped silicon oxide.
10. The transistor according to claim 1, wherein the nitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).
11. The transistor according to claim 1, wherein a in-plane tensile strain of a channel region of the active region is between 0.1% to 2%.
12. A method of forming an isolation structure for strained channel transistors comprising:
providing a semiconductor substrate comprising a strained silicon layer overlying a strain forming buffer layer;
forming a trench in the semiconductor substrate;
forming a nitrogen-containing liner in the trench; and
filling the trench with a gap filler material,
wherein the nitrogen-containing liner reduces a compressive strain asserted on the strained silicon layer by the gap filler material contained therein.
13. The method according to claim 12, wherein the nitrogen-containing liner is comprised of silicon nitride or silicon oxynitride.
14. The method according to claim 12, wherein the nitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).
15. The method according to claim 12, wherein the nitrogen-containing liner has a thickness in the range of 10 to 500 angstroms.
16. The method according to claim 12, further comprising the step of, after the step of forming the trench, of forming a silicon oxide liner underlying the nitrogen-containing liner.
17. The method according to claim 16, wherein the step of forming the silicon oxide liner is a thermal oxidation step or a chemical vapor deposition step.
18. The method according to claim 12, further comprising the step, after the step of forming the trench, of performing a corner rounding process step.
19. The method according to claim 18, wherein the corner rounding process step is an anneal at a temperature in the range of 700 to 950 degrees Celsius in a gaseous ambient, the gaseous ambient.
20. The method according to claim 18, further comprising a step, after the step of corner rounding, of forming a silicon oxide liner.
21. The method according to claim 18, wherein the step of forming the silicon oxide liner is a thermal oxidation step or a chemical vapor deposition step.
22. The method according to claim 18, wherein forming the trench in the semiconductor substrate further includes forming a pull back of the opening of the trench.
23. The method according to claim 22, wherein the pull back is in the range of 50 to 1000 angstroms.
24. The method according to claim 22, wherein the pull back is formed by a chemical treatment with a wet etch process in hot acid at a temperature in the range of 150 to 180 degrees Celsius.
25. The method according to claim 24, wherein the chemical treatment further includes a wet etch process in dilute hydrochloric acid.
Description
    TECHNICAL FIELD
  • [0001]
    The present disclosure relates generally to the field of semiconductor devices, and more particularly to strained channel transistors with enhanced performance using improved isolation regions and the method for making same.
  • BACKGROUND
  • [0002]
    Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed performance, density, and cost per unit function of integrated circuits over the past few decades. To enhance transistor performance further, strain may be introduced in the transistor channel for improving carrier mobility. Therefore, strain-induced mobility enhancement is another way to improve transistor performance in addition to device scaling. Several existing approaches of introducing strain in the transistor channel region have been proposed.
  • [0003]
    There are several existing approaches of introducing strain in the transistor channel region to enhance further transistor performance. In one conventional approach, a relaxed silicon germanium (SiGe) buffer layer 102 is provided beneath the channel region, as shown in FIG. 1(a). The relaxed SiGe buffer layer 102 has a larger lattice constant compared to relaxed Si 104, and a thin layer of epitaxial Si 106 grown on relaxed SiGe 102 will have its lattice stretched in the lateral direction, i.e. it will be under biaxial tensile strain. This is illustrated in FIG. 1(b). Therefore, a transistor formed on the epitaxial strained silicon layer 106 will have a channel region that is under biaxial tensile strain. In this approach, the relaxed SiGe buffer layer 102 can be thought of as a stressor that introduces strain in the channel region. The stressor, in this case, is placed below the transistor channel region. Significant mobility enhancement has been reported for both electrons and holes in bulk transistors using a silicon channel under biaxial tensile strain. In the abovementioned approach, the epitaxial silicon layer 106 is strained before the formation of the transistor. Therefore, there are concerns about possible strain relaxation upon subsequent CMOS processing where high temperatures are used. An example of a high temperature process step in CMOS processing is the formation of an isolation structure, such as shallow trench isolation, to electrically isolate devices from one another.
  • [0004]
    In a conventional shallow trench isolation process 200, as shown in FIG. 2, a silicon oxide liner 202 is typically thermally grown at temperatures ranging from 900 to 1100 degrees Celsius. The high temperatures can potentially cause strain relaxation and reduce the tensile strain in the tensile strained silicon channel region 204. By using the conventional oxide-filled trench isolation structure 206 with the strained silicon substrate 208, as shown in FIG. 2, the trench isolation structure 206 contributes a significant compressive strain component 210 to the channel region 204. The compressive strain component 210 contributed by the oxide-filled trench isolation structure 206 cancels out a portion of the tensile strain component of the tensile strained silicon substrate 208 constituting the channel region 204. With the reduction of the tensile strain in the channel region 204 of the transistor, the strain-induced performance enhancement is reduced significantly. The compressive strain results from sidewall oxidation and volume expansion of the silicon oxide material in the trench.
  • [0005]
    What is needed is an improved isolation structure for strained channel transistors and the method for making same.
  • SUMMARY OF INVENTION
  • [0006]
    In view of the foregoing, the present disclosure provides a system and method for forming an improved isolation structure for strained channel transistors.
  • [0007]
    In one example, an isolation structure is formed comprising a trench filled with a silicon oxide liner, a nitrogen-containing liner, and a gap filler. In another example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region. The nitrogen-containing liner minimizes confined volume expansion and reduces compressive stress in the surrounding active region.
  • [0008]
    The present disclosure provide isolation structures with reduced compressive strain contribution and reduced thermal budget in a tensile strained silicon substrate. Another object of the present disclosure is to teach a method of engineering the strain in the channel of the tensile strained transistor by engineering the isolation structure to improve transistor performance.
  • [0009]
    These and other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the disclosure.
  • BRIEF DESCRIPTION OF DRAWINGS
  • [0010]
    The present disclosure will be more clearly understood after reference to the following detailed description of preferred embodiments read in conjunction with the drawings, wherein:
  • [0011]
    FIGS. 1(a)-(b) illustrate the cross-section of a conventional strained silicon transistor with a relaxed SiGe and the illustration of the origin of strain in the Si/SiGe hetero-structure, respectively.
  • [0012]
    FIG. 2 illustrates a transistor formed in an active region isolated shallow trench isolation (STI).
  • [0013]
    FIGS. 3(a)-(b) illustrate a novel low-stress isolation structure for the strained silicon transistor according to one example of the present disclosure.
  • [0014]
    FIGS. 4(a)-(e) illustrate a first method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
  • [0015]
    FIGS. 5(a)-(e) illustrate a second method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
  • [0016]
    FIGS. 6(a)-(e) illustrate a third method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • [0017]
    As illustrated below, the structure of and methods are disclosed below for the manufacture of an improved isolation structure with reduced compression strain contribution to the channel region and/or reduced thermal budget. Several embodiments are shown as illustrated examples.
  • First Embodiment
  • [0018]
    FIG. 3(a) illustrates a first structure embodiment of the present disclosure. The isolation structure 300 illustrated in FIG. 3(a) comprises a trench 302 filled with a silicon oxide liner 304, a nitrogen-containing liner 306, and a gap filler 308. The depth of the trench 302 is in the range of 2000 to 6000 angstroms. The nitrogen-containing liner 306 contributes to the reduction of compressive strain contribution to the channel region 310. The nitrogen-containing liner 306 acts as an oxidation mask, preventing further oxidation of the trench sidewalls 312 in subsequent processing steps where, because of its slow diffusion rate in the nitrogen-containing liner 306, oxygen is present in the processing ambient. The nitrogen-containing liner 306 minimizes confined volume expansion and reduces compressive stress in the surrounding active region. Prior art tensile strained silicon transistors do not employ the nitrogen-containing liner 306 and as a result have reduced tensile strain and compromised transistor performance. According to one preferred embodiment of this disclosure, the nitrogen-containing liner 306 is comprised of silicon nitride, Si3N4. The nitrogen-containing liner 306 may also be comprised of a silicon oxynitride SiOxNy material or a nitrogen-doped silicon oxide material, where the atomic percentage of nitrogen in the nitrogen-containing liner 306 may be in the range of 5 to 60 percent (%). It is understood, however, that other materials with oxygen diffusion rates lower than that of silicon oxide may be used. By employing an isolation structure 300 with a nitrogen-containing liner 306, the compressive strain contribution by the isolation structure 300 to the channel region 310 is reduced, so that the channel region 310 is entirely or almost entirely strained by the relaxed silicon-germanium (SiGe) layer 314 underlying the channel region 310. The present embodiment provides a strained silicon layer 316 totally tensile strained by the underlying relaxed SiGe layer 314 and can be negligibly compressive-strained by the isolation structure 300.
  • Second Embodiment
  • [0019]
    FIG. 3(b) illustrates a second structure embodiment of the present disclosure. The second structure embodiment of FIG. 3(b) differs from the first structure embodiment described above and illustrated in FIG. 3(a) in that the nitrogen-containing liner 306 in FIG. 3(b) is in direct contact with the trench sidewall surface 312. In other words, the silicon oxide liner 304 of the first embodiment in FIG. 3(a) is not used in this embodiment. By eliminating the silicon oxide liner 304, this structure further reduces the thermal budget associated with the isolation structure 300 formation process and further improves the ability of the nitrogen-containing liner 306 to block oxidation of the trench sidewall surface 312. In addition, it is also possible that the nitrogen-containing liner 306 may exert a beneficial strain on the channel region 310. For example, the nitrogen-containing liner 306 itself may be formed under tensile stress, and therefore induces a vertical compressive strain on the region of the strained silicon layer 316 in its immediate vicinity. This vertical compressive strain provides an additional biaxial tensile strain component to the channel region 310. Therefore, the preferred embodiment of FIG. 3(b) reduces the compressive strain contribution by the isolation structure 300 on the channel region 310 and potentially could strengthen the in-plane tensile strain component 318 that is beneficial to the strained channel transistor 320 for additional boost in speed performance.
  • Third Embodiment
  • [0020]
    FIGS. 4(a)-(e) illustrate a first method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and reduced compressive strain contribution by the isolation structure to the channel region. The isolation structure 400 preferably comprises a nitrogen-containing liner 402 in direct contact with the trench sidewall surface 404. The nitrogen-containing liner 402 can be a single silicon nitride layer or a silicon oxynitride layer 406. The nitrogen content of the nitrogen-containing liner 402 may be in the range of 5 to 60 percent (%) by atomic percentage. A substrate comprising a strained silicon layer 408 overlying a relaxed silicon-germanium (SiGe) layer 410 is used as the starting material. Such a substrate may further comprise a grade SiGe buffer layer 412, and may further comprise a silicon substrate 414 underlying the grade SiGe buffer layer 412. A first patterned mask is formed on the substrate, and the trenches 416 are etched into the substrate, as shown in FIG. 4(a). The first patterned mask is preferably comprised of a silicon nitride layer 406 overlying a pad oxide layer 418. The pad oxide layer 418 is preferably comprised of silicon oxide. A conventional anisotropic plasma etching with fluorine chemistry is used to etch the isolation trenches 416.
  • [0021]
    FIG. 4(b) illustrates the formation of a nitrogen-containing liner 402. The nitrogen-containing liner 402 may be formed by low-pressure chemical vapor deposition (LPCVD), for example. The nitrogen-containing liner 402 is preferably formed to a thickness of about 10 to 500 angstroms, although smaller or larger thicknesses than the specified range may be used. The nitrogen-containing liner 402 is preferably a high tensile stress conformal nitride, Si3N4, liner. The chemical vapor deposition process may use precursor gases such as ammonia and silane. The typical deposition temperature is between 550 and 900 degrees Celsius. A trench filing material, the gap filler 420, preferably silicon oxide, is filled into the trenches 416. The gap filler 420 may be a combination of trench filling materials, such as a combination of CVD silicon oxide and CVD poly-crystalline silicon. After deposition, the gap filler 420 is densified by either a pyrogenic oxidation anneal at a temperature of 800 degrees Celsius or a conventional annealing step in argon ambient at 1000 degree Celsius.
  • [0022]
    The cross-section in FIG. 4(c) illustrates the chemical mechanical polishing step performed to planarize the surface of the wafer. The first patterned mask can be removed. In the preferred embodiment, the first patterned mask comprises a silicon nitride or pad nitride on a silicon oxide stack or pad oxide. The cross-section in FIG. 4(d) illustrates the removal of the first patterned mask by an etch in hot phosphoric acid followed by an etch in dilute hydrofluoric acid. It thus exposes the nitrogen-containing liner 402 through two recesses 403. The strained Si areas 408 on both sides of the trench are now covered by the pad oxide 418. Although not shown, if there are materials between the relaxed Si and the pad oxide layer, they can also be removed.
  • [0023]
    The cross-section in FIG. 4(e) illustrates the stripping of the pad oxide 418 by aqueous HF. Transistors may then be formed in the active regions with a surface comprising the strained silicon layer 408.
  • Fourth Embodiment
  • [0024]
    FIGS. 5(a)-(e) illustrate a second method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and compressive strain contribution by the isolation structure to the channel region. The isolation structure 500 preferably comprises a nitrogen-containing liner 502 overlying a silicon oxide liner 504. In this method embodiment, the silicon oxide liner 504 is formed by chemical vapor deposition, preferably plasma-enhanced chemical vapor deposition (PECVD). The silicon oxide liner 504 is in direct contact with the trench sidewall surface 506. A substrate comprising a strained silicon layer 508 overlying a relaxed silicon-germanium (SiGe) layer 510 is used as the starting material. The starting substrate may further comprise a silicon substrate 512 underlying a graded SiGe buffer layer 514. A first patterned mask is formed on the substrate, and trenches 516 are etched into the substrate, as illustrated in FIG. 5(a). The first patterned mask is preferably comprised of a silicon nitride layer 518 overlying a pad oxide layer 520. The pad oxide layer 520 is preferably comprised of silicon oxide. A conventional anisotropic plasma etching with fluorine chemistry is used to etch the isolation trenches 516. Following the formation of the trenches 516, the wafer may be subject to a chemical treatment to result in a pull back of the first patterned mask. The pull back distance 522, as illustrated in FIG. 5(a), may be in the range of 50 to 1000 angstroms. The chemical treatment may be a wet etch process in hot phosphoric acid at a temperature in the range of 150 to 180 degrees Celsius. The chemical treatment may further comprise a wet etch in dilute hydrochloric acid. A corner rounding process may be performed producing rounded corners 524. The rounded corners 524 may be convex rounded corners (top corners at the trench 516 edge) or concave rounded corners (bottom corners at the trench 516 bottom). The corner rounding process is preferably an annealing process at temperatures in the range of 700 to 950 degrees Celsius in a gaseous ambient. The gaseous ambient may be comprised of hydrogen, helium, neon, argon, xenon, or any combination thereof.
  • [0025]
    The cross-section illustrated in FIG. 5(b) involves the deposition of the silicon oxide liner 504, the deposition of the nitrogen-containing liner 502, and the deposition of the gap filler material 526. The gap filler material 526 is preferably silicon oxide.
  • [0026]
    A planarization step, preferably using a chemical mechanical polishing process, is performed. The resulting cross-section is illustrated in FIG. 5(c). The pad nitride 518 is then removed. The resulting cross-section is illustrated in FIG. 5(d). The pad oxide 520 is then removed. The resulting cross-section is illustrated in FIG. 5(e). Transistors may then be formed in the active regions with a surface comprising the strained silicon layer 506.
  • Fifth Embodiment
  • [0027]
    FIGS. 6(a)-(e) illustrate a third method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and compressive strain contribution by the isolation structure to the channel region. The isolation structure 600 comprises a nitrogen-containing liner 602 overlying a silicon oxide liner 604. The third method embodiment differs from the second method embodiment of the present disclosure in that the silicon oxide liner 604 of the third method embodiment is formed by a thermal oxidation process. The thermally grown silicon oxide liner 604 is in direct contact with the trench sidewall surface 606. Since the growth of the thermal oxide results in rounded corners, the corner rounding process is optional. A substrate comprising a strained silicon layer 608 overlying a relaxed silicon-germanium (SiGe) layer 610 is used as the starting material. A first patterned mask is formed on the substrate, and trenches 612 are etched into the substrate, as illustrated in FIG. 6(a). The first patterned mask is preferably comprised of a silicon nitride layer 614 overlying a pad oxide layer 616. The pad oxide layer 616 is preferably comprised of silicon oxide. A conventional anistropic plasma etching with fluorine chemistry is used to etch the isolation trenches 612. Following the formation of the trenches 612, the wafer may be subject to a chemical treatment resulting in a pull back of the first patterned mask. The pull back distance 618, as indicated in FIG. 6(a), may be in the range of 50 to 1000 angstroms. The chemical treatment may be a wet etch process in hot phosphoric acid at a temperature in the range of 150 to 180 degrees Celsius. The chemical treatment may further comprise a wet etch in dilute hydrochloric acid. A corner rounding process as previously described may optionally be performed.
  • [0028]
    The cross-section illustrated in FIG. 6(b) involves the thermal growth of a silicon oxide liner 604, the deposition of the nitrogen-containing liner 602, and the deposition of the gap filler material 620. The gap filler material 620 is preferably silicon oxide.
  • [0029]
    A planarization step, preferably using a chemical mechanical polishing process, is performed. The resulting cross-section is illustrated in FIG. 6(c). The pad nitride 614 is then removed. The resulting cross-section is illustrated in FIG. 6(d). The pad oxide 616 is then removed. The resulting cross-section is illustrated in FIG. 6(e). Transistors may then be formed in the active regions with a surface comprising the strained silicon layer 608.
  • [0030]
    The above disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components, and processes are described to help clarify the present disclosure. These are, of course, merely examples and are not intended to limit the present disclosure from that described in the claims. For example, while a shallow trench isolation is illustrated, it is understood that the present disclosure may be extended to other isolation structures, which are improvements of the shallow trench isolation structure. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense.
  • [0031]
    While the present disclosure has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure, as set forth in the following claims.
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8686544 *13 Nov 20061 Apr 2014Panasonic CorporationSemiconductor device
US901810815 Mar 201328 Apr 2015Applied Materials, Inc.Low shrinkage dielectric films
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Classifications
U.S. Classification257/192, 257/E21.633, 257/E29.056, 257/E21.642, 257/E21.546
International ClassificationH01L31/0328, H01L21/8238, H01L21/762, H01L29/10
Cooperative ClassificationH01L29/1054, H01L21/823481, H01L21/76224, H01L21/823807, H01L21/823878, H01L29/7848, H01L29/7846, H01L21/823412
European ClassificationH01L29/78R6, H01L21/8234U, H01L21/8234C, H01L29/78R4, H01L29/10D2B4, H01L21/8238U, H01L21/762C, H01L21/8238C
Legal Events
DateCodeEventDescription
23 Jun 2004ASAssignment
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING, CO. LTD., TAIW
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KO, CHIH-HSIN;YEO, YEE-CHIA;LEE, WEN-CHIN;AND OTHERS;REEL/FRAME:015519/0350;SIGNING DATES FROM 20040524 TO 20040525