US20050285140A1 - Isolation structure for strained channel transistors - Google Patents
Isolation structure for strained channel transistors Download PDFInfo
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- US20050285140A1 US20050285140A1 US10/875,141 US87514104A US2005285140A1 US 20050285140 A1 US20050285140 A1 US 20050285140A1 US 87514104 A US87514104 A US 87514104A US 2005285140 A1 US2005285140 A1 US 2005285140A1
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- 238000002955 isolation Methods 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 47
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000000945 filler Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 35
- 229910052710 silicon Inorganic materials 0.000 claims description 35
- 239000010703 silicon Substances 0.000 claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 29
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000013459 approach Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000007858 starting material Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000001698 pyrogenic effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Definitions
- the present disclosure relates generally to the field of semiconductor devices, and more particularly to strained channel transistors with enhanced performance using improved isolation regions and the method for making same.
- MOSFET metal-oxide-semiconductor field-effect transistor
- size reduction of the metal-oxide-semiconductor field-effect transistor has enabled the continued improvement in speed performance, density, and cost per unit function of integrated circuits over the past few decades.
- strain may be introduced in the transistor channel for improving carrier mobility. Therefore, strain-induced mobility enhancement is another way to improve transistor performance in addition to device scaling.
- Several existing approaches of introducing strain in the transistor channel region have been proposed.
- a relaxed silicon germanium (SiGe) buffer layer 102 is provided beneath the channel region, as shown in FIG. 1 ( a ).
- the relaxed SiGe buffer layer 102 has a larger lattice constant compared to relaxed Si 104 , and a thin layer of epitaxial Si 106 grown on relaxed SiGe 102 will have its lattice stretched in the lateral direction, i.e. it will be under biaxial tensile strain. This is illustrated in FIG. 1 ( b ). Therefore, a transistor formed on the epitaxial strained silicon layer 106 will have a channel region that is under biaxial tensile strain.
- the relaxed SiGe buffer layer 102 can be thought of as a stressor that introduces strain in the channel region.
- the stressor in this case, is placed below the transistor channel region.
- Significant mobility enhancement has been reported for both electrons and holes in bulk transistors using a silicon channel under biaxial tensile strain.
- the epitaxial silicon layer 106 is strained before the formation of the transistor. Therefore, there are concerns about possible strain relaxation upon subsequent CMOS processing where high temperatures are used.
- An example of a high temperature process step in CMOS processing is the formation of an isolation structure, such as shallow trench isolation, to electrically isolate devices from one another.
- a silicon oxide liner 202 is typically thermally grown at temperatures ranging from 900 to 1100 degrees Celsius. The high temperatures can potentially cause strain relaxation and reduce the tensile strain in the tensile strained silicon channel region 204 .
- the trench isolation structure 206 contributes a significant compressive strain component 210 to the channel region 204 .
- the compressive strain component 210 contributed by the oxide-filled trench isolation structure 206 cancels out a portion of the tensile strain component of the tensile strained silicon substrate 208 constituting the channel region 204 .
- the strain-induced performance enhancement is reduced significantly.
- the compressive strain results from sidewall oxidation and volume expansion of the silicon oxide material in the trench.
- the present disclosure provides a system and method for forming an improved isolation structure for strained channel transistors.
- an isolation structure comprising a trench filled with a silicon oxide liner, a nitrogen-containing liner, and a gap filler.
- an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler.
- the nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.
- the nitrogen-containing liner minimizes confined volume expansion and reduces compressive stress in the surrounding active region.
- FIGS. 1 ( a )-( b ) illustrate the cross-section of a conventional strained silicon transistor with a relaxed SiGe and the illustration of the origin of strain in the Si/SiGe hetero-structure, respectively.
- FIG. 2 illustrates a transistor formed in an active region isolated shallow trench isolation (STI).
- STI shallow trench isolation
- FIGS. 3 ( a )-( b ) illustrate a novel low-stress isolation structure for the strained silicon transistor according to one example of the present disclosure.
- FIGS. 4 ( a )-( e ) illustrate a first method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
- FIGS. 5 ( a )-( e ) illustrate a second method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
- FIGS. 6 ( a )-( e ) illustrate a third method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
- FIG. 3 ( a ) illustrates a first structure embodiment of the present disclosure.
- the isolation structure 300 illustrated in FIG. 3 ( a ) comprises a trench 302 filled with a silicon oxide liner 304 , a nitrogen-containing liner 306 , and a gap filler 308 .
- the depth of the trench 302 is in the range of 2000 to 6000 angstroms.
- the nitrogen-containing liner 306 contributes to the reduction of compressive strain contribution to the channel region 310 .
- the nitrogen-containing liner 306 acts as an oxidation mask, preventing further oxidation of the trench sidewalls 312 in subsequent processing steps where, because of its slow diffusion rate in the nitrogen-containing liner 306 , oxygen is present in the processing ambient.
- the nitrogen-containing liner 306 minimizes confined volume expansion and reduces compressive stress in the surrounding active region. Prior art tensile strained silicon transistors do not employ the nitrogen-containing liner 306 and as a result have reduced tensile strain and compromised transistor performance.
- the nitrogen-containing liner 306 is comprised of silicon nitride, Si 3 N 4 .
- the nitrogen-containing liner 306 may also be comprised of a silicon oxynitride SiO x N y material or a nitrogen-doped silicon oxide material, where the atomic percentage of nitrogen in the nitrogen-containing liner 306 may be in the range of 5 to 60 percent (%).
- the compressive strain contribution by the isolation structure 300 to the channel region 310 is reduced, so that the channel region 310 is entirely or almost entirely strained by the relaxed silicon-germanium (SiGe) layer 314 underlying the channel region 310 .
- the present embodiment provides a strained silicon layer 316 totally tensile strained by the underlying relaxed SiGe layer 314 and can be negligibly compressive-strained by the isolation structure 300 .
- FIG. 3 ( b ) illustrates a second structure embodiment of the present disclosure.
- the second structure embodiment of FIG. 3 ( b ) differs from the first structure embodiment described above and illustrated in FIG. 3 ( a ) in that the nitrogen-containing liner 306 in FIG. 3 ( b ) is in direct contact with the trench sidewall surface 312 .
- the silicon oxide liner 304 of the first embodiment in FIG. 3 ( a ) is not used in this embodiment.
- this structure further reduces the thermal budget associated with the isolation structure 300 formation process and further improves the ability of the nitrogen-containing liner 306 to block oxidation of the trench sidewall surface 312 .
- the nitrogen-containing liner 306 may exert a beneficial strain on the channel region 310 .
- the nitrogen-containing liner 306 itself may be formed under tensile stress, and therefore induces a vertical compressive strain on the region of the strained silicon layer 316 in its immediate vicinity. This vertical compressive strain provides an additional biaxial tensile strain component to the channel region 310 . Therefore, the preferred embodiment of FIG. 3 ( b ) reduces the compressive strain contribution by the isolation structure 300 on the channel region 310 and potentially could strengthen the in-plane tensile strain component 318 that is beneficial to the strained channel transistor 320 for additional boost in speed performance.
- FIGS. 4 ( a )-( e ) illustrate a first method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and reduced compressive strain contribution by the isolation structure to the channel region.
- the isolation structure 400 preferably comprises a nitrogen-containing liner 402 in direct contact with the trench sidewall surface 404 .
- the nitrogen-containing liner 402 can be a single silicon nitride layer or a silicon oxynitride layer 406 .
- the nitrogen content of the nitrogen-containing liner 402 may be in the range of 5 to 60 percent (%) by atomic percentage.
- a substrate comprising a strained silicon layer 408 overlying a relaxed silicon-germanium (SiGe) layer 410 is used as the starting material.
- Such a substrate may further comprise a grade SiGe buffer layer 412 , and may further comprise a silicon substrate 414 underlying the grade SiGe buffer layer 412 .
- a first patterned mask is formed on the substrate, and the trenches 416 are etched into the substrate, as shown in FIG. 4 ( a ).
- the first patterned mask is preferably comprised of a silicon nitride layer 406 overlying a pad oxide layer 418 .
- the pad oxide layer 418 is preferably comprised of silicon oxide.
- a conventional anisotropic plasma etching with fluorine chemistry is used to etch the isolation trenches 416 .
- FIG. 4 ( b ) illustrates the formation of a nitrogen-containing liner 402 .
- the nitrogen-containing liner 402 may be formed by low-pressure chemical vapor deposition (LPCVD), for example.
- LPCVD low-pressure chemical vapor deposition
- the nitrogen-containing liner 402 is preferably formed to a thickness of about 10 to 500 angstroms, although smaller or larger thicknesses than the specified range may be used.
- the nitrogen-containing liner 402 is preferably a high tensile stress conformal nitride, Si 3 N 4 , liner.
- the chemical vapor deposition process may use precursor gases such as ammonia and silane.
- the typical deposition temperature is between 550 and 900 degrees Celsius.
- a trench filing material, the gap filler 420 is filled into the trenches 416 .
- the gap filler 420 may be a combination of trench filling materials, such as a combination of CVD silicon oxide and CVD poly-crystalline silicon. After deposition, the gap filler 420 is densified by either a pyrogenic oxidation anneal at a temperature of 800 degrees Celsius or a conventional annealing step in argon ambient at 1000 degree Celsius.
- the cross-section in FIG. 4 ( c ) illustrates the chemical mechanical polishing step performed to planarize the surface of the wafer.
- the first patterned mask can be removed.
- the first patterned mask comprises a silicon nitride or pad nitride on a silicon oxide stack or pad oxide.
- the cross-section in FIG. 4 ( d ) illustrates the removal of the first patterned mask by an etch in hot phosphoric acid followed by an etch in dilute hydrofluoric acid. It thus exposes the nitrogen-containing liner 402 through two recesses 403 .
- the strained Si areas 408 on both sides of the trench are now covered by the pad oxide 418 .
- FIG. 4 ( e ) illustrates the stripping of the pad oxide 418 by aqueous HF. Transistors may then be formed in the active regions with a surface comprising the strained silicon layer 408 .
- FIGS. 5 ( a )-( e ) illustrate a second method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and compressive strain contribution by the isolation structure to the channel region.
- the isolation structure 500 preferably comprises a nitrogen-containing liner 502 overlying a silicon oxide liner 504 .
- the silicon oxide liner 504 is formed by chemical vapor deposition, preferably plasma-enhanced chemical vapor deposition (PECVD).
- PECVD plasma-enhanced chemical vapor deposition
- the silicon oxide liner 504 is in direct contact with the trench sidewall surface 506 .
- a substrate comprising a strained silicon layer 508 overlying a relaxed silicon-germanium (SiGe) layer 510 is used as the starting material.
- the starting substrate may further comprise a silicon substrate 512 underlying a graded SiGe buffer layer 514 .
- a first patterned mask is formed on the substrate, and trenches 516 are etched into the substrate, as illustrated in FIG. 5 ( a ).
- the first patterned mask is preferably comprised of a silicon nitride layer 518 overlying a pad oxide layer 520 .
- the pad oxide layer 520 is preferably comprised of silicon oxide.
- a conventional anisotropic plasma etching with fluorine chemistry is used to etch the isolation trenches 516 .
- the wafer may be subject to a chemical treatment to result in a pull back of the first patterned mask.
- the pull back distance 522 as illustrated in FIG.
- the chemical treatment may be a wet etch process in hot phosphoric acid at a temperature in the range of 150 to 180 degrees Celsius.
- the chemical treatment may further comprise a wet etch in dilute hydrochloric acid.
- a corner rounding process may be performed producing rounded corners 524 .
- the rounded corners 524 may be convex rounded corners (top corners at the trench 516 edge) or concave rounded corners (bottom corners at the trench 516 bottom).
- the corner rounding process is preferably an annealing process at temperatures in the range of 700 to 950 degrees Celsius in a gaseous ambient.
- the gaseous ambient may be comprised of hydrogen, helium, neon, argon, xenon, or any combination thereof.
- the cross-section illustrated in FIG. 5 ( b ) involves the deposition of the silicon oxide liner 504 , the deposition of the nitrogen-containing liner 502 , and the deposition of the gap filler material 526 .
- the gap filler material 526 is preferably silicon oxide.
- a planarization step preferably using a chemical mechanical polishing process, is performed.
- the resulting cross-section is illustrated in FIG. 5 ( c ).
- the pad nitride 518 is then removed.
- the resulting cross-section is illustrated in FIG. 5 ( d ).
- the pad oxide 520 is then removed.
- the resulting cross-section is illustrated in FIG. 5 ( e ).
- Transistors may then be formed in the active regions with a surface comprising the strained silicon layer 506 .
- FIGS. 6 ( a )-( e ) illustrate a third method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and compressive strain contribution by the isolation structure to the channel region.
- the isolation structure 600 comprises a nitrogen-containing liner 602 overlying a silicon oxide liner 604 .
- the third method embodiment differs from the second method embodiment of the present disclosure in that the silicon oxide liner 604 of the third method embodiment is formed by a thermal oxidation process.
- the thermally grown silicon oxide liner 604 is in direct contact with the trench sidewall surface 606 . Since the growth of the thermal oxide results in rounded corners, the corner rounding process is optional.
- a substrate comprising a strained silicon layer 608 overlying a relaxed silicon-germanium (SiGe) layer 610 is used as the starting material.
- a first patterned mask is formed on the substrate, and trenches 612 are etched into the substrate, as illustrated in FIG. 6 ( a ).
- the first patterned mask is preferably comprised of a silicon nitride layer 614 overlying a pad oxide layer 616 .
- the pad oxide layer 616 is preferably comprised of silicon oxide.
- a conventional anistropic plasma etching with fluorine chemistry is used to etch the isolation trenches 612 .
- the wafer may be subject to a chemical treatment resulting in a pull back of the first patterned mask.
- the pull back distance 618 may be in the range of 50 to 1000 angstroms.
- the chemical treatment may be a wet etch process in hot phosphoric acid at a temperature in the range of 150 to 180 degrees Celsius.
- the chemical treatment may further comprise a wet etch in dilute hydrochloric acid.
- a corner rounding process as previously described may optionally be performed.
- the cross-section illustrated in FIG. 6 ( b ) involves the thermal growth of a silicon oxide liner 604 , the deposition of the nitrogen-containing liner 602 , and the deposition of the gap filler material 620 .
- the gap filler material 620 is preferably silicon oxide.
- a planarization step preferably using a chemical mechanical polishing process, is performed.
- the resulting cross-section is illustrated in FIG. 6 ( c ).
- the pad nitride 614 is then removed.
- the resulting cross-section is illustrated in FIG. 6 ( d ).
- the pad oxide 616 is then removed.
- the resulting cross-section is illustrated in FIG. 6 ( e ).
- Transistors may then be formed in the active regions with a surface comprising the strained silicon layer 608 .
Abstract
A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.
Description
- The present disclosure relates generally to the field of semiconductor devices, and more particularly to strained channel transistors with enhanced performance using improved isolation regions and the method for making same.
- Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed performance, density, and cost per unit function of integrated circuits over the past few decades. To enhance transistor performance further, strain may be introduced in the transistor channel for improving carrier mobility. Therefore, strain-induced mobility enhancement is another way to improve transistor performance in addition to device scaling. Several existing approaches of introducing strain in the transistor channel region have been proposed.
- There are several existing approaches of introducing strain in the transistor channel region to enhance further transistor performance. In one conventional approach, a relaxed silicon germanium (SiGe)
buffer layer 102 is provided beneath the channel region, as shown inFIG. 1 (a). The relaxedSiGe buffer layer 102 has a larger lattice constant compared torelaxed Si 104, and a thin layer ofepitaxial Si 106 grown on relaxed SiGe 102 will have its lattice stretched in the lateral direction, i.e. it will be under biaxial tensile strain. This is illustrated inFIG. 1 (b). Therefore, a transistor formed on the epitaxialstrained silicon layer 106 will have a channel region that is under biaxial tensile strain. In this approach, the relaxedSiGe buffer layer 102 can be thought of as a stressor that introduces strain in the channel region. The stressor, in this case, is placed below the transistor channel region. Significant mobility enhancement has been reported for both electrons and holes in bulk transistors using a silicon channel under biaxial tensile strain. In the abovementioned approach, theepitaxial silicon layer 106 is strained before the formation of the transistor. Therefore, there are concerns about possible strain relaxation upon subsequent CMOS processing where high temperatures are used. An example of a high temperature process step in CMOS processing is the formation of an isolation structure, such as shallow trench isolation, to electrically isolate devices from one another. - In a conventional shallow
trench isolation process 200, as shown inFIG. 2 , asilicon oxide liner 202 is typically thermally grown at temperatures ranging from 900 to 1100 degrees Celsius. The high temperatures can potentially cause strain relaxation and reduce the tensile strain in the tensile strainedsilicon channel region 204. By using the conventional oxide-filledtrench isolation structure 206 with thestrained silicon substrate 208, as shown inFIG. 2 , thetrench isolation structure 206 contributes a significantcompressive strain component 210 to thechannel region 204. Thecompressive strain component 210 contributed by the oxide-filledtrench isolation structure 206 cancels out a portion of the tensile strain component of the tensilestrained silicon substrate 208 constituting thechannel region 204. With the reduction of the tensile strain in thechannel region 204 of the transistor, the strain-induced performance enhancement is reduced significantly. The compressive strain results from sidewall oxidation and volume expansion of the silicon oxide material in the trench. - What is needed is an improved isolation structure for strained channel transistors and the method for making same.
- In view of the foregoing, the present disclosure provides a system and method for forming an improved isolation structure for strained channel transistors.
- In one example, an isolation structure is formed comprising a trench filled with a silicon oxide liner, a nitrogen-containing liner, and a gap filler. In another example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region. The nitrogen-containing liner minimizes confined volume expansion and reduces compressive stress in the surrounding active region.
- The present disclosure provide isolation structures with reduced compressive strain contribution and reduced thermal budget in a tensile strained silicon substrate. Another object of the present disclosure is to teach a method of engineering the strain in the channel of the tensile strained transistor by engineering the isolation structure to improve transistor performance.
- These and other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the disclosure.
- The present disclosure will be more clearly understood after reference to the following detailed description of preferred embodiments read in conjunction with the drawings, wherein:
- FIGS. 1(a)-(b) illustrate the cross-section of a conventional strained silicon transistor with a relaxed SiGe and the illustration of the origin of strain in the Si/SiGe hetero-structure, respectively.
-
FIG. 2 illustrates a transistor formed in an active region isolated shallow trench isolation (STI). - FIGS. 3(a)-(b) illustrate a novel low-stress isolation structure for the strained silicon transistor according to one example of the present disclosure.
- FIGS. 4(a)-(e) illustrate a first method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
- FIGS. 5(a)-(e) illustrate a second method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
- FIGS. 6(a)-(e) illustrate a third method of manufacturing a novel low-stress isolation structure for the strained silicon transistor according to another example of the present disclosure.
- As illustrated below, the structure of and methods are disclosed below for the manufacture of an improved isolation structure with reduced compression strain contribution to the channel region and/or reduced thermal budget. Several embodiments are shown as illustrated examples.
-
FIG. 3 (a) illustrates a first structure embodiment of the present disclosure. Theisolation structure 300 illustrated inFIG. 3 (a) comprises atrench 302 filled with asilicon oxide liner 304, a nitrogen-containingliner 306, and agap filler 308. The depth of thetrench 302 is in the range of 2000 to 6000 angstroms. The nitrogen-containingliner 306 contributes to the reduction of compressive strain contribution to thechannel region 310. The nitrogen-containingliner 306 acts as an oxidation mask, preventing further oxidation of thetrench sidewalls 312 in subsequent processing steps where, because of its slow diffusion rate in the nitrogen-containingliner 306, oxygen is present in the processing ambient. The nitrogen-containingliner 306 minimizes confined volume expansion and reduces compressive stress in the surrounding active region. Prior art tensile strained silicon transistors do not employ the nitrogen-containingliner 306 and as a result have reduced tensile strain and compromised transistor performance. According to one preferred embodiment of this disclosure, the nitrogen-containingliner 306 is comprised of silicon nitride, Si3N4. The nitrogen-containingliner 306 may also be comprised of a silicon oxynitride SiOxNy material or a nitrogen-doped silicon oxide material, where the atomic percentage of nitrogen in the nitrogen-containingliner 306 may be in the range of 5 to 60 percent (%). It is understood, however, that other materials with oxygen diffusion rates lower than that of silicon oxide may be used. By employing anisolation structure 300 with a nitrogen-containingliner 306, the compressive strain contribution by theisolation structure 300 to thechannel region 310 is reduced, so that thechannel region 310 is entirely or almost entirely strained by the relaxed silicon-germanium (SiGe)layer 314 underlying thechannel region 310. The present embodiment provides astrained silicon layer 316 totally tensile strained by the underlyingrelaxed SiGe layer 314 and can be negligibly compressive-strained by theisolation structure 300. -
FIG. 3 (b) illustrates a second structure embodiment of the present disclosure. The second structure embodiment ofFIG. 3 (b) differs from the first structure embodiment described above and illustrated inFIG. 3 (a) in that the nitrogen-containingliner 306 inFIG. 3 (b) is in direct contact with thetrench sidewall surface 312. In other words, thesilicon oxide liner 304 of the first embodiment inFIG. 3 (a) is not used in this embodiment. By eliminating thesilicon oxide liner 304, this structure further reduces the thermal budget associated with theisolation structure 300 formation process and further improves the ability of the nitrogen-containingliner 306 to block oxidation of thetrench sidewall surface 312. In addition, it is also possible that the nitrogen-containingliner 306 may exert a beneficial strain on thechannel region 310. For example, the nitrogen-containingliner 306 itself may be formed under tensile stress, and therefore induces a vertical compressive strain on the region of thestrained silicon layer 316 in its immediate vicinity. This vertical compressive strain provides an additional biaxial tensile strain component to thechannel region 310. Therefore, the preferred embodiment ofFIG. 3 (b) reduces the compressive strain contribution by theisolation structure 300 on thechannel region 310 and potentially could strengthen the in-planetensile strain component 318 that is beneficial to thestrained channel transistor 320 for additional boost in speed performance. - FIGS. 4(a)-(e) illustrate a first method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and reduced compressive strain contribution by the isolation structure to the channel region. The
isolation structure 400 preferably comprises a nitrogen-containing liner 402 in direct contact with the trench sidewall surface 404. The nitrogen-containing liner 402 can be a single silicon nitride layer or a silicon oxynitride layer 406. The nitrogen content of the nitrogen-containing liner 402 may be in the range of 5 to 60 percent (%) by atomic percentage. A substrate comprising a strained silicon layer 408 overlying a relaxed silicon-germanium (SiGe)layer 410 is used as the starting material. Such a substrate may further comprise a grade SiGe buffer layer 412, and may further comprise a silicon substrate 414 underlying the grade SiGe buffer layer 412. A first patterned mask is formed on the substrate, and the trenches 416 are etched into the substrate, as shown inFIG. 4 (a). The first patterned mask is preferably comprised of a silicon nitride layer 406 overlying a pad oxide layer 418. The pad oxide layer 418 is preferably comprised of silicon oxide. A conventional anisotropic plasma etching with fluorine chemistry is used to etch the isolation trenches 416. -
FIG. 4 (b) illustrates the formation of a nitrogen-containing liner 402. The nitrogen-containing liner 402 may be formed by low-pressure chemical vapor deposition (LPCVD), for example. The nitrogen-containing liner 402 is preferably formed to a thickness of about 10 to 500 angstroms, although smaller or larger thicknesses than the specified range may be used. The nitrogen-containing liner 402 is preferably a high tensile stress conformal nitride, Si3N4, liner. The chemical vapor deposition process may use precursor gases such as ammonia and silane. The typical deposition temperature is between 550 and 900 degrees Celsius. A trench filing material, thegap filler 420, preferably silicon oxide, is filled into the trenches 416. Thegap filler 420 may be a combination of trench filling materials, such as a combination of CVD silicon oxide and CVD poly-crystalline silicon. After deposition, thegap filler 420 is densified by either a pyrogenic oxidation anneal at a temperature of 800 degrees Celsius or a conventional annealing step in argon ambient at 1000 degree Celsius. - The cross-section in
FIG. 4 (c) illustrates the chemical mechanical polishing step performed to planarize the surface of the wafer. The first patterned mask can be removed. In the preferred embodiment, the first patterned mask comprises a silicon nitride or pad nitride on a silicon oxide stack or pad oxide. The cross-section inFIG. 4 (d) illustrates the removal of the first patterned mask by an etch in hot phosphoric acid followed by an etch in dilute hydrofluoric acid. It thus exposes the nitrogen-containing liner 402 through two recesses 403. The strained Si areas 408 on both sides of the trench are now covered by the pad oxide 418. Although not shown, if there are materials between the relaxed Si and the pad oxide layer, they can also be removed. - The cross-section in
FIG. 4 (e) illustrates the stripping of the pad oxide 418 by aqueous HF. Transistors may then be formed in the active regions with a surface comprising the strained silicon layer 408. - FIGS. 5(a)-(e) illustrate a second method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and compressive strain contribution by the isolation structure to the channel region. The
isolation structure 500 preferably comprises a nitrogen-containing liner 502 overlying a silicon oxide liner 504. In this method embodiment, the silicon oxide liner 504 is formed by chemical vapor deposition, preferably plasma-enhanced chemical vapor deposition (PECVD). The silicon oxide liner 504 is in direct contact with the trench sidewall surface 506. A substrate comprising a strained silicon layer 508 overlying a relaxed silicon-germanium (SiGe)layer 510 is used as the starting material. The starting substrate may further comprise a silicon substrate 512 underlying a graded SiGe buffer layer 514. A first patterned mask is formed on the substrate, and trenches 516 are etched into the substrate, as illustrated inFIG. 5 (a). The first patterned mask is preferably comprised of a silicon nitride layer 518 overlying apad oxide layer 520. Thepad oxide layer 520 is preferably comprised of silicon oxide. A conventional anisotropic plasma etching with fluorine chemistry is used to etch the isolation trenches 516. Following the formation of the trenches 516, the wafer may be subject to a chemical treatment to result in a pull back of the first patterned mask. The pull back distance 522, as illustrated inFIG. 5 (a), may be in the range of 50 to 1000 angstroms. The chemical treatment may be a wet etch process in hot phosphoric acid at a temperature in the range of 150 to 180 degrees Celsius. The chemical treatment may further comprise a wet etch in dilute hydrochloric acid. A corner rounding process may be performed producing rounded corners 524. The rounded corners 524 may be convex rounded corners (top corners at the trench 516 edge) or concave rounded corners (bottom corners at the trench 516 bottom). The corner rounding process is preferably an annealing process at temperatures in the range of 700 to 950 degrees Celsius in a gaseous ambient. The gaseous ambient may be comprised of hydrogen, helium, neon, argon, xenon, or any combination thereof. - The cross-section illustrated in
FIG. 5 (b) involves the deposition of the silicon oxide liner 504, the deposition of the nitrogen-containing liner 502, and the deposition of the gap filler material 526. The gap filler material 526 is preferably silicon oxide. - A planarization step, preferably using a chemical mechanical polishing process, is performed. The resulting cross-section is illustrated in
FIG. 5 (c). The pad nitride 518 is then removed. The resulting cross-section is illustrated inFIG. 5 (d). Thepad oxide 520 is then removed. The resulting cross-section is illustrated inFIG. 5 (e). Transistors may then be formed in the active regions with a surface comprising the strained silicon layer 506. - FIGS. 6(a)-(e) illustrate a third method embodiment of the present disclosure, describing a process flow for forming strained silicon transistors with reduced thermal budget and compressive strain contribution by the isolation structure to the channel region. The
isolation structure 600 comprises a nitrogen-containing liner 602 overlying a silicon oxide liner 604. The third method embodiment differs from the second method embodiment of the present disclosure in that the silicon oxide liner 604 of the third method embodiment is formed by a thermal oxidation process. The thermally grown silicon oxide liner 604 is in direct contact with the trench sidewall surface 606. Since the growth of the thermal oxide results in rounded corners, the corner rounding process is optional. A substrate comprising a strained silicon layer 608 overlying a relaxed silicon-germanium (SiGe)layer 610 is used as the starting material. A first patterned mask is formed on the substrate, and trenches 612 are etched into the substrate, as illustrated inFIG. 6 (a). The first patterned mask is preferably comprised of a silicon nitride layer 614 overlying a pad oxide layer 616. The pad oxide layer 616 is preferably comprised of silicon oxide. A conventional anistropic plasma etching with fluorine chemistry is used to etch the isolation trenches 612. Following the formation of the trenches 612, the wafer may be subject to a chemical treatment resulting in a pull back of the first patterned mask. The pull back distance 618, as indicated inFIG. 6 (a), may be in the range of 50 to 1000 angstroms. The chemical treatment may be a wet etch process in hot phosphoric acid at a temperature in the range of 150 to 180 degrees Celsius. The chemical treatment may further comprise a wet etch in dilute hydrochloric acid. A corner rounding process as previously described may optionally be performed. - The cross-section illustrated in
FIG. 6 (b) involves the thermal growth of a silicon oxide liner 604, the deposition of the nitrogen-containing liner 602, and the deposition of thegap filler material 620. Thegap filler material 620 is preferably silicon oxide. - A planarization step, preferably using a chemical mechanical polishing process, is performed. The resulting cross-section is illustrated in
FIG. 6 (c). The pad nitride 614 is then removed. The resulting cross-section is illustrated inFIG. 6 (d). The pad oxide 616 is then removed. The resulting cross-section is illustrated inFIG. 6 (e). Transistors may then be formed in the active regions with a surface comprising the strained silicon layer 608. - The above disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components, and processes are described to help clarify the present disclosure. These are, of course, merely examples and are not intended to limit the present disclosure from that described in the claims. For example, while a shallow trench isolation is illustrated, it is understood that the present disclosure may be extended to other isolation structures, which are improvements of the shallow trench isolation structure. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense.
- While the present disclosure has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure, as set forth in the following claims.
Claims (25)
1. A strained channel transistor with at least one isolation structure, the transistor being formed on a semiconductor substrate comprising a strained silicon layer overlying a tensile strain forming buffer layer, the isolation structure comprising:
an active region formed in the semiconductor substrate; and
at least one nitrogen-containing liner isolation region next to the active region.
2. The transistor according to claim 1 , wherein the isolation region is a shallow trench isolation region with a trench depth in the range of 2000 to 6000 angstroms.
3. The transistor according to claim 1 , wherein the nitrogen-containing liner has a thickness in the range of 10 to 500 angstroms.
4. The transistor according to claim 1 , wherein a channel region is formed in the strained silicon layer of the active region with a source or drain region formed between the channel region and the isolation region.
5. The transistor according to claim 1 , wherein the tensile strain forming buffer layer is a relaxed silicon-germanium layer.
6. The transistor according to claim 5 , wherein the substrate further comprises a graded silicon-germanium buffer layer underlying the relaxed silicon-germanium layer, the graded silicon-germanium buffer layer overlying a silicon substrate.
7. The transistor according to claim 1 , wherein the isolation region further comprises an oxide liner underlying the nitrogen-containing liner.
8. The transistor according to claim 1 , wherein the isolation region includes a gap filler material.
9. The transistor according to claim 1 , wherein the nitrogen-containing liner comprises at least one of silicon nitride, silicon oxynitride, or nitrogen-doped silicon oxide.
10. The transistor according to claim 1 , wherein the nitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).
11. The transistor according to claim 1 , wherein a in-plane tensile strain of a channel region of the active region is between 0.1% to 2%.
12. A method of forming an isolation structure for strained channel transistors comprising:
providing a semiconductor substrate comprising a strained silicon layer overlying a strain forming buffer layer;
forming a trench in the semiconductor substrate;
forming a nitrogen-containing liner in the trench; and
filling the trench with a gap filler material,
wherein the nitrogen-containing liner reduces a compressive strain asserted on the strained silicon layer by the gap filler material contained therein.
13. The method according to claim 12 , wherein the nitrogen-containing liner is comprised of silicon nitride or silicon oxynitride.
14. The method according to claim 12 , wherein the nitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).
15. The method according to claim 12 , wherein the nitrogen-containing liner has a thickness in the range of 10 to 500 angstroms.
16. The method according to claim 12 , further comprising the step of, after the step of forming the trench, of forming a silicon oxide liner underlying the nitrogen-containing liner.
17. The method according to claim 16 , wherein the step of forming the silicon oxide liner is a thermal oxidation step or a chemical vapor deposition step.
18. The method according to claim 12 , further comprising the step, after the step of forming the trench, of performing a corner rounding process step.
19. The method according to claim 18 , wherein the corner rounding process step is an anneal at a temperature in the range of 700 to 950 degrees Celsius in a gaseous ambient, the gaseous ambient.
20. The method according to claim 18 , further comprising a step, after the step of corner rounding, of forming a silicon oxide liner.
21. The method according to claim 18 , wherein the step of forming the silicon oxide liner is a thermal oxidation step or a chemical vapor deposition step.
22. The method according to claim 18 , wherein forming the trench in the semiconductor substrate further includes forming a pull back of the opening of the trench.
23. The method according to claim 22 , wherein the pull back is in the range of 50 to 1000 angstroms.
24. The method according to claim 22 , wherein the pull back is formed by a chemical treatment with a wet etch process in hot acid at a temperature in the range of 150 to 180 degrees Celsius.
25. The method according to claim 24 , wherein the chemical treatment further includes a wet etch process in dilute hydrochloric acid.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/875,141 US20050285140A1 (en) | 2004-06-23 | 2004-06-23 | Isolation structure for strained channel transistors |
TW094121052A TWI268539B (en) | 2004-06-23 | 2005-06-23 | Improved isolation structure for strained channel transistors |
US11/586,936 US20070161206A1 (en) | 2003-04-25 | 2006-10-26 | Isolation structure for strained channel transistors |
US13/013,296 US8569146B2 (en) | 2003-04-25 | 2011-01-25 | Isolation structure for strained channel transistors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/875,141 US20050285140A1 (en) | 2004-06-23 | 2004-06-23 | Isolation structure for strained channel transistors |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/423,513 Continuation-In-Part US6882025B2 (en) | 2003-04-25 | 2003-04-25 | Strained-channel transistor and methods of manufacture |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/586,936 Division US20070161206A1 (en) | 2003-04-25 | 2006-10-26 | Isolation structure for strained channel transistors |
Publications (1)
Publication Number | Publication Date |
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US20050285140A1 true US20050285140A1 (en) | 2005-12-29 |
Family
ID=35504679
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/875,141 Abandoned US20050285140A1 (en) | 2003-04-25 | 2004-06-23 | Isolation structure for strained channel transistors |
US11/586,936 Abandoned US20070161206A1 (en) | 2003-04-25 | 2006-10-26 | Isolation structure for strained channel transistors |
US13/013,296 Expired - Lifetime US8569146B2 (en) | 2003-04-25 | 2011-01-25 | Isolation structure for strained channel transistors |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/586,936 Abandoned US20070161206A1 (en) | 2003-04-25 | 2006-10-26 | Isolation structure for strained channel transistors |
US13/013,296 Expired - Lifetime US8569146B2 (en) | 2003-04-25 | 2011-01-25 | Isolation structure for strained channel transistors |
Country Status (2)
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US (3) | US20050285140A1 (en) |
TW (1) | TWI268539B (en) |
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CN111933570A (en) * | 2020-10-09 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Manufacturing method of shallow trench isolation structure and shallow trench isolation structure formed by same |
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US9318370B2 (en) * | 2011-08-04 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-k dielectric liners in shallow trench isolations |
KR20170065271A (en) * | 2015-12-03 | 2017-06-13 | 삼성전자주식회사 | A semiconductor device and methods of manufacturing the same |
CN111128852B (en) * | 2018-10-30 | 2023-05-05 | 台湾积体电路制造股份有限公司 | Silicon-on-insulator structure, semiconductor structure and method for forming semiconductor structure |
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US6933518B2 (en) * | 2001-09-24 | 2005-08-23 | Amberwave Systems Corporation | RF circuits including transistors having strained material layers |
US6960781B2 (en) * | 2003-03-07 | 2005-11-01 | Amberwave Systems Corporation | Shallow trench isolation process |
US6882025B2 (en) * | 2003-04-25 | 2005-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained-channel transistor and methods of manufacture |
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Also Published As
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TWI268539B (en) | 2006-12-11 |
US8569146B2 (en) | 2013-10-29 |
TW200601424A (en) | 2006-01-01 |
US20110117724A1 (en) | 2011-05-19 |
US20070161206A1 (en) | 2007-07-12 |
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