US20050272208A1 - Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique - Google Patents
Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique Download PDFInfo
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Definitions
- This invention relates to semiconductor power devices and their fabrication, and more specifically to low-voltage vertical MOSFET power devices.
- the personal portable electronics field including such devices as cellular phones and notebook computers, has experienced explosive growth.
- the systematic reduction of supply voltage accompanied by a corresponding decrease in device feature size and high system performance, has become a primary focus for the development of more advanced power devices.
- the voltage scaling of the total system requires that the power MOSFETs used in power management circuitry can be efficiently turned on and off at a low gate drive voltage.
- the power semiconductor switches should have a low level threshold voltage (less than 1.0 volts). See FIG. 1 .
- the prior art uses a low implant dose in P-well 30 plus a thinner gate oxide 40 .
- This approach achieves a low gate rating, but it may result in a high channel leakage current and a poor high-temperature performance. Due to the low total net charges of the well, this approach also makes the device susceptible to punch-through breakdown. In addition, the doping in the channel is non-uniform.
- FIG. 2 Another recently-disclosed prior-art technique (shown in FIG. 2 ) employs the P-type epi-layer 70 forming the channel region of the device.
- the drift region 25 of the device is formed by implanting the opposite-type dopant into the trench bottom 55 , followed by a thermal annealing step. Consequently, the doping concentration of the channel region is determined by the doping concentration of the epi-layer 70 , and the doping profile along the device channel is uniform. This yields a higher total net charge located in the well for a given threshold voltage. Thus, the device's performance and off-state breakdown characteristics are expected to be improved.
- adjacent drift regions 25 clearly are not allowed to merge. The regions are kept separated to provide so-called “bulk resurf”, so that the on-resistance of the device drift region 25 can be dramatically reduced [1]-[3].
- the on-resistance contribution from the drift region 25 is a very small portion of the total on-resistance.
- the most significant component of the device on-resistance is the resistance of the device channel region.
- the most efficient approach is to reduce the device unit cell pitch and increase the channel density.
- the non-merging condition imposed on the drift regions 25 as taught in the prior art limits the minimum cell pitch and maximum channel density that the device can employ.
- the on-resistance of the prior art is high when used for a low voltage application.
- the invention merges together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench.
- the merged drift regions permit use of a very small cell pitch, resulting in a very high channel density and a consequent significant reduction in the channel resistance.
- the implant dose and the annealing parameters of the drift region By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform.
- the invention's threshold voltage is reduced, its channel resistance is lowered, and its drift region on-resistance is also lowered.
- the invention incorporates a new edge termination design, so that the PN junction formed by the P epi-layer and the N + substrate can be terminated at the edge of the die.
- the more heavily P-type epitaxial layer of FIG. 2 reduces on resistance.
- the separated drift regions of FIG. 2 provide depletion regions to sustain a higher reverse voltage across the device.
- the requirement of the separated drift regions inherently reduces the density of the cells in a device.
- the invention provides low on resistance by using a more highly doped P-type epitaxial layer and has a higher cell density by allowing the drift regions to merge. Even with merged drift regions there is still adequate depletion to support high reverse biases.
- the P-doping in the channel is more constant than the doping in prior art channels with epitaxial layers and separated drift zones.
- the invention provides devices with greater cell density and lower junction capacitance than devices made with separated resurf regions.
- FIG. 1 shows a typical prior art device using a low implant dose and a thinner gate oxide.
- FIG. 2 shows a typical prior art device using an epi-layer forming the channel region of the device.
- FIG. 3 shows the invention in a first embodiment with significant reduction of channel resistance.
- FIG. 4 shows the invention in a second embodiment with further significant reduction of channel resistance.
- FIG. 5 shows the invention in a third embodiment with still further significant reduction of channel resistance.
- FIG. 5 a shows a comparison of the three embodiments shown in FIGS. 3, 4 , and 5 .
- FIGS. 6 through 10 show the important steps in fabrication of the invention.
- FIG. 11 shows the invention's doping profile along the trench sidewall.
- FIG. 12 shows the doping profile along the trench sidewall for a prior art device.
- FIG. 13 shows the contours of doping concentration in the invention.
- FIG. 14 shows the most commonly used edge termination in prior art devices.
- FIG. 15 shows the edge termination used in the invention.
- the invention's device comprises an N + -type substrate 10 , N-type drift regions 27 , a P-type epi-layer 72 , trenches 80 , gate oxide 40 , polysilicon 50 , BPSG 60 , N + -type source regions 37 , and P + -type body regions 75 .
- the illustrated conductivity types may of course be reversed as needed.
- the invention merges together the implanted drift regions 27 .
- the prior art of FIG. 2 keeps the regions separated to provide a bulk resurf effect that lowers the on resistance and increases the depletion of the drift region during reverse votage conditions to raise the limits of the sustaining reverse voltage.
- the invention produces a shorter, more-level boundary 90 a between P-type epi-layer 72 and drift region 27 as shown in FIG. 3 .
- the invention reduces significantly the surface area between the epi-layer and the drift region, and separates the epi-layer completely from the substrate. Merging the drift regions permits use of a very small cell pitch and results in a very high channel density.
- the invention achieves a significant reduction in the channel resistance.
- the channel length of the device can be controlled by preferably choosing one or more parameters, including and not limited to the implant dose and implant as well as the temperature and time of the annealing step for driving in the implanted dopants.
- a shorter channel can be achieved by increasing the driven time after the drift region implant.
- the shorter channel length produces a significant decrease in the channel resistance.
- FIGS. 3, 4 , and 5 in which the driven time changes from 10 min ( FIG. 3 ), to 20 min ( FIG. 4 ), and to 30 min ( FIG. 5 ).
- the driven time changes from 10 min ( FIG. 3 ), to 20 min ( FIG. 4 ), and to 30 min ( FIG. 5 ).
- the driven time changes from 10 min ( FIG. 3 ), to 20 min ( FIG. 4 ), and to 30 min ( FIG. 5 ).
- the progressive increase in thickness of the drift region 27 and the flattening of the boundary 90 a , 90 b , 90 c between the drift region and the overlying epi-layer 72 .
- the device forward current spreading inside the drift region is progressively more efficient as the driven time increases (see FIG. 3 to FIG. 5 in order) due to a wider spreading area. Consequently, the on-resistance of the drift region is also lowered
- the forward conduction characteristics of the devices in FIG. 3 , FIG. 4 and FIG. 5 have been simulated by using the finite element method.
- the modeled device on-resistance was extracted from the simulation results.
- the on-resistance per unit area of devices of FIGS. 3, 4 , and 5 are 0.22 m ⁇ /cm 2 , 0.18 m ⁇ /cm 2 and 0.15 m ⁇ /cm 2 respectively.
- the cell pitch of all the devices is 2.0 microns.
- the body-diode of the new device proposed in this invention as illustrated in FIGS. 3, 4 , 5 , and 5 a has significantly less PN junction area.
- the base width of the parasitic BJT of the new device's body-diode becomes more even.
- the body-diode of the inventive device provides improved forward conduction and reverse recovery characteristics.
- FIGS. 6-10 Devices including the invention are made with the inventive process illustrated in FIGS. 6-10 .
- the process begins with an N+ substrate 10 of silicon or other suitable semiconductor material.
- a p-type epitaxial layer 72 is grown on the substrate 10 in a manner well known in the art.
- Trenches 110 for holding gate structures are opened by covering the epitaxial layer 72 with a suitable mask.
- a hard mask 100 of silicon dioxide is either deposited or thermally grown on the top of the epitaxial layer 72 .
- a layer of photoresist is deposited on the oxide 100 and then patterned to exposed portions of the oxide. The exposed portions of the oxide 100 are removed by a suitable etch to expose portions of the epitaxial layer 72 where the trenches 100 will be formed.
- the substrate 10 is then etched to remove epitaxial material from the substrate and form the trenches 110 .
- a relatively thin gate oxide layer 120 is thermally grown on the exposed sidewall and floor surfaces of the trenches. Then the substrate is implanted with N-typed dopants 130 , such as phosphorous or arsenic.
- the residual oxide mask 100 on the epitaxial layer 72 blocks the N-type dopants from entering the upper surface of that layer.
- the thinner oxide layer 120 on the sidewalls and floors of the trenches allow the implanted N-type ions 130 to enter the epitaxial layer 72 in regions proximate the floors of the trenches.
- the hard mask 100 is removed from the surface and the implanted ions 130 are driven in by an annealing operation.
- the drive-in step diffuses the N-type ions in a vertical direction enough to reach the N+ substrate and in a lateral direction to extend across the lower portion of the epitaxial layer 72 and form an unbroken N-type drift region 27 along the bottom of the epitaxial layer 72 .
- the height of the N-type region 27 depends upon a number of factors, including and not limited to, the type of dopant used the implant energy, the concentration, and the annealing or drive-in time. One or more of the factors are adjusted to achieve the desired net concentration and height of the region 27 .
- the remaining process steps are standard, including filling the trenches with doped polysilicon, followed by etching a recess in the polysilicon, deposition of an inter-level r-dielectric layer (such as BPSG) fill 60 and etch back to form the self-isolated buried polysilicon gate. Standard procedures may be used to create the P+ body 75 and the N+ source 37 , followed by front-side and back-side metallizations.
- an inter-level r-dielectric layer such as BPSG
- FIG. 11 gives the doping profile 200 along the trench sidewall of the device disclosed in this invention, showing the profile through N + source region 237 , P-type epi-layer 272 (channel), N-type drift region 227 , and N + substrate 210 .
- FIG. 12 gives the doping profile 201 along the same location of the prior art device, showing the profile through N + source region 237 , P-well 230 (channel), epi-layer 220 , and N + substrate 210 .
- the channel length and the channel doping concentration have been properly designed so that both devices exhibit non-punch-through breakdown characteristics.
- the drain-source breakdown voltages are 35 volts and 34 volts respectively for the new device of FIG. 11 and the standard device of FIG. 12 .
- the threshold voltage of the new device is about 0.7 volts, but 2.0 volts for the standard device.
- FIG. 13 shows the contours of doping concentration inside the new device, through N + source regions 237 , P + body regions 275 , P-type epi-layer 272 (channel), and N-type drift region 227 .
- Gate oxide 40 , polysilicon 50 , and BPSG 60 are shown for clarity. It is evident that the doping concentration is almost constant in the channel region 272 .
- the edge termination used for the conventional device of FIG. 1 can not be applied to the new device disclosed in this invention or the prior art of FIG. 2 .
- FIG. 14 the most frequently used edge termination in conventional low voltage MOSFET is depicted in FIG. 14 , with source metal 337 , gate runner metal 350 , BPSG 360 , field oxide 340 , channel stopper metal 380 , N+ channel stop 338 , epi-layer 20 , and substrate 10 .
- this invention provides a new edge termination as shown in FIG. 15 .
- the edge of the die is etched away and a field oxide 340 is grown over the etched edge.
- a layer of doped polysilicon 370 is formed on the field oxide followed by insulating BPSG layer 360 . Openings are made in that layer for the metal gate runner 350 to contact the polysilicon plate layer 370 .
- An N+ drift contact region 338 is formed on the lower outer edge of the die for contacting the edge drift region 27 .
- a channel stopper metal layer 380 contacts the region 338 through suitable openings in the field oxide 340 , polysilicon layer 370 and BPSG layer 360 . This new edge termination is produced by using the same process flow as the active device.
- the new edge termination has a more efficient utilization of silicon area, due to the fact that the partials of the polysilicon field plate 370 and the metal gap between metal strips 350 and 380 are located along the trench sidewall.
- the electric field spreads more into the P epilayer. Consequently, for a given breakdown voltage, the new edge termination presents a smaller lateral dimension than the conventional one.
Abstract
Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.
Description
- This is a continuation of U.S. patent application Ser. No. 10/795,723 filed Mar. 5, 2004 which is a divisional application of U.S. patent application Ser. No. 10/138,913 filed May 3, 2005.
- This invention relates to semiconductor power devices and their fabrication, and more specifically to low-voltage vertical MOSFET power devices.
- Recently, the personal portable electronics field, including such devices as cellular phones and notebook computers, has experienced explosive growth. The systematic reduction of supply voltage, accompanied by a corresponding decrease in device feature size and high system performance, has become a primary focus for the development of more advanced power devices. The voltage scaling of the total system requires that the power MOSFETs used in power management circuitry can be efficiently turned on and off at a low gate drive voltage. In order to meet this requirement, the power semiconductor switches should have a low level threshold voltage (less than 1.0 volts). See
FIG. 1 . To lower the threshold voltage, the prior art uses a low implant dose in P-well 30 plus athinner gate oxide 40. This approach achieves a low gate rating, but it may result in a high channel leakage current and a poor high-temperature performance. Due to the low total net charges of the well, this approach also makes the device susceptible to punch-through breakdown. In addition, the doping in the channel is non-uniform. - Another recently-disclosed prior-art technique (shown in
FIG. 2 ) employs the P-type epi-layer 70 forming the channel region of the device. Thedrift region 25 of the device is formed by implanting the opposite-type dopant into thetrench bottom 55, followed by a thermal annealing step. Consequently, the doping concentration of the channel region is determined by the doping concentration of the epi-layer 70, and the doping profile along the device channel is uniform. This yields a higher total net charge located in the well for a given threshold voltage. Thus, the device's performance and off-state breakdown characteristics are expected to be improved. In this prior art,adjacent drift regions 25 clearly are not allowed to merge. The regions are kept separated to provide so-called “bulk resurf”, so that the on-resistance of thedevice drift region 25 can be dramatically reduced [1]-[3]. - As is well-known in the art, for low voltage power devices (for example, 30 volts or less) the on-resistance contribution from the
drift region 25 is a very small portion of the total on-resistance. The most significant component of the device on-resistance is the resistance of the device channel region. In order to lower the channel resistance, the most efficient approach is to reduce the device unit cell pitch and increase the channel density. Unfortunately, the non-merging condition imposed on thedrift regions 25 as taught in the prior art limits the minimum cell pitch and maximum channel density that the device can employ. As the result, the on-resistance of the prior art is high when used for a low voltage application. In addition, it is clear fromFIG. 2 that the prior art creates more PN junction area of the device's body-diode, resulting in a high output capacitance. Also, the parasitic BJT of the body-diode has a significantly non-uniform base width. This will degrade the body-diode forward conduction and reverse recovery characteristics. [4] - The invention merges together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench. The merged drift regions permit use of a very small cell pitch, resulting in a very high channel density and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the invention's threshold voltage is reduced, its channel resistance is lowered, and its drift region on-resistance is also lowered. To implement the merged drift regions, the invention incorporates a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.
- When compared to the prior art devices of
FIG. 1 , the more heavily P-type epitaxial layer ofFIG. 2 reduces on resistance. In addition, the separated drift regions ofFIG. 2 provide depletion regions to sustain a higher reverse voltage across the device. However, the requirement of the separated drift regions inherently reduces the density of the cells in a device. The invention provides low on resistance by using a more highly doped P-type epitaxial layer and has a higher cell density by allowing the drift regions to merge. Even with merged drift regions there is still adequate depletion to support high reverse biases. With the invention, the P-doping in the channel is more constant than the doping in prior art channels with epitaxial layers and separated drift zones. The invention provides devices with greater cell density and lower junction capacitance than devices made with separated resurf regions. -
FIG. 1 shows a typical prior art device using a low implant dose and a thinner gate oxide. -
FIG. 2 shows a typical prior art device using an epi-layer forming the channel region of the device. -
FIG. 3 shows the invention in a first embodiment with significant reduction of channel resistance. -
FIG. 4 shows the invention in a second embodiment with further significant reduction of channel resistance. -
FIG. 5 shows the invention in a third embodiment with still further significant reduction of channel resistance. -
FIG. 5 a shows a comparison of the three embodiments shown inFIGS. 3, 4 , and 5. -
FIGS. 6 through 10 show the important steps in fabrication of the invention. -
FIG. 11 shows the invention's doping profile along the trench sidewall. -
FIG. 12 shows the doping profile along the trench sidewall for a prior art device. -
FIG. 13 shows the contours of doping concentration in the invention. -
FIG. 14 shows the most commonly used edge termination in prior art devices. -
FIG. 15 shows the edge termination used in the invention. - This invention addresses and resolves the problems of the prior art devices described above. See
FIG. 3 . The invention's device comprises an N+-type substrate 10, N-type drift regions 27, a P-type epi-layer 72,trenches 80,gate oxide 40,polysilicon 50, BPSG 60, N+-type source regions 37, and P+-type body regions 75. The illustrated conductivity types may of course be reversed as needed. By contrast with the prior art, the invention merges together the implanteddrift regions 27. The prior art ofFIG. 2 keeps the regions separated to provide a bulk resurf effect that lowers the on resistance and increases the depletion of the drift region during reverse votage conditions to raise the limits of the sustaining reverse voltage. Instead of the long, slantedboundary 90 between P-type epi-layer 70 and driftregion 25 as shown inFIG. 2 , the invention produces a shorter, more-level boundary 90 a between P-type epi-layer 72 and driftregion 27 as shown inFIG. 3 . In effect, the invention reduces significantly the surface area between the epi-layer and the drift region, and separates the epi-layer completely from the substrate. Merging the drift regions permits use of a very small cell pitch and results in a very high channel density. Thus, the invention achieves a significant reduction in the channel resistance. Furthermore, the channel length of the device can be controlled by preferably choosing one or more parameters, including and not limited to the implant dose and implant as well as the temperature and time of the annealing step for driving in the implanted dopants. - As an example, a shorter channel can be achieved by increasing the driven time after the drift region implant. The shorter channel length produces a significant decrease in the channel resistance. This is depicted in
FIGS. 3, 4 , and 5, in which the driven time changes from 10 min (FIG. 3 ), to 20 min (FIG. 4 ), and to 30 min (FIG. 5 ). Note the progressive increase in thickness of thedrift region 27, and the flattening of theboundary layer 72. In addition, the device forward current spreading inside the drift region is progressively more efficient as the driven time increases (seeFIG. 3 toFIG. 5 in order) due to a wider spreading area. Consequently, the on-resistance of the drift region is also lowered. To help make clear the differences,FIG. 5 a shows the three different cases in one illustration. - The forward conduction characteristics of the devices in
FIG. 3 ,FIG. 4 andFIG. 5 have been simulated by using the finite element method. The modeled device on-resistance was extracted from the simulation results. The on-resistance per unit area of devices ofFIGS. 3, 4 , and 5 are 0.22 mΩ/cm2, 0.18 mΩ/cm2 and 0.15 mΩ/cm2 respectively. The cell pitch of all the devices is 2.0 microns. Additionally, when compared to the prior art shown inFIG. 2 , the body-diode of the new device proposed in this invention as illustrated inFIGS. 3, 4 , 5, and 5 a has significantly less PN junction area. Also, the base width of the parasitic BJT of the new device's body-diode becomes more even. The body-diode of the inventive device provides improved forward conduction and reverse recovery characteristics. - In the fabrication process described in the following paragraphs, a 30V N-Channel trench-gated power MOSFET is used as an example to demonstrate the realization of the concept disclosed in this invention. Only the important process steps are illustrated.
- Devices including the invention are made with the inventive process illustrated in
FIGS. 6-10 . The process begins with anN+ substrate 10 of silicon or other suitable semiconductor material. A p-type epitaxial layer 72 is grown on thesubstrate 10 in a manner well known in the art.Trenches 110 for holding gate structures are opened by covering theepitaxial layer 72 with a suitable mask. In one embodiment ahard mask 100 of silicon dioxide is either deposited or thermally grown on the top of theepitaxial layer 72. A layer of photoresist is deposited on theoxide 100 and then patterned to exposed portions of the oxide. The exposed portions of theoxide 100 are removed by a suitable etch to expose portions of theepitaxial layer 72 where thetrenches 100 will be formed. Thesubstrate 10 is then etched to remove epitaxial material from the substrate and form thetrenches 110. - Next, a relatively thin
gate oxide layer 120 is thermally grown on the exposed sidewall and floor surfaces of the trenches. Then the substrate is implanted with N-typeddopants 130, such as phosphorous or arsenic. Theresidual oxide mask 100 on theepitaxial layer 72 blocks the N-type dopants from entering the upper surface of that layer. Thethinner oxide layer 120 on the sidewalls and floors of the trenches allow the implanted N-type ions 130 to enter theepitaxial layer 72 in regions proximate the floors of the trenches. - Turing to
FIG. 9 , thehard mask 100 is removed from the surface and the implantedions 130 are driven in by an annealing operation. The drive-in step diffuses the N-type ions in a vertical direction enough to reach the N+ substrate and in a lateral direction to extend across the lower portion of theepitaxial layer 72 and form an unbroken N-type drift region 27 along the bottom of theepitaxial layer 72. Those skilled in the art will understand that the height of the N-type region 27 depends upon a number of factors, including and not limited to, the type of dopant used the implant energy, the concentration, and the annealing or drive-in time. One or more of the factors are adjusted to achieve the desired net concentration and height of theregion 27. - See
FIG. 10 . The remaining process steps are standard, including filling the trenches with doped polysilicon, followed by etching a recess in the polysilicon, deposition of an inter-level r-dielectric layer (such as BPSG) fill 60 and etch back to form the self-isolated buried polysilicon gate. Standard procedures may be used to create theP+ body 75 and theN+ source 37, followed by front-side and back-side metallizations. - The detailed process described in the previous paragraphs has been simulated and verified. The prior art shown in
FIG. 1 was also simulated for comparison.FIG. 11 gives thedoping profile 200 along the trench sidewall of the device disclosed in this invention, showing the profile through N+ source region 237, P-type epi-layer 272 (channel), N-type drift region 227, and N+ substrate 210.FIG. 12 gives thedoping profile 201 along the same location of the prior art device, showing the profile through N+ source region 237, P-well 230 (channel), epi-layer 220, and N+ substrate 210. The channel length and the channel doping concentration have been properly designed so that both devices exhibit non-punch-through breakdown characteristics. The drain-source breakdown voltages are 35 volts and 34 volts respectively for the new device ofFIG. 11 and the standard device ofFIG. 12 . However, the threshold voltage of the new device is about 0.7 volts, but 2.0 volts for the standard device.FIG. 13 shows the contours of doping concentration inside the new device, through N+ source regions 237, P+ body regions 275, P-type epi-layer 272 (channel), and N-type drift region 227.Gate oxide 40,polysilicon 50, andBPSG 60 are shown for clarity. It is evident that the doping concentration is almost constant in thechannel region 272. - Finally, it is important to point out that in the new device the PN junction formed by the P epi-layer and the N+ substrate does not terminate at the silicon surface. As a consequence, the edge termination used for the conventional device of
FIG. 1 can not be applied to the new device disclosed in this invention or the prior art ofFIG. 2 . Currently, the most frequently used edge termination in conventional low voltage MOSFET is depicted inFIG. 14 , withsource metal 337,gate runner metal 350,BPSG 360,field oxide 340,channel stopper metal 380,N+ channel stop 338, epi-layer 20, andsubstrate 10. In order to address this issue, this invention provides a new edge termination as shown inFIG. 15 . The edge of the die is etched away and afield oxide 340 is grown over the etched edge. A layer of dopedpolysilicon 370 is formed on the field oxide followed by insulatingBPSG layer 360. Openings are made in that layer for themetal gate runner 350 to contact thepolysilicon plate layer 370. An N+drift contact region 338 is formed on the lower outer edge of the die for contacting theedge drift region 27. A channelstopper metal layer 380 contacts theregion 338 through suitable openings in thefield oxide 340,polysilicon layer 370 andBPSG layer 360. This new edge termination is produced by using the same process flow as the active device. The new edge termination has a more efficient utilization of silicon area, due to the fact that the partials of thepolysilicon field plate 370 and the metal gap betweenmetal strips FIG. 1 , the electric field spreads more into the P epilayer. Consequently, for a given breakdown voltage, the new edge termination presents a smaller lateral dimension than the conventional one. - [1] Coe, U.S. Pat. No. 4,754,310, 1988.
- [2] Chen, U.S. Pat. No. 5,216,275, 1993.
- [3] Tihanyi, U.S. Pat. No. 5,438,215, 1995.
- [4] Jun Zeng, C. Frank Wheatley, Rick Stokes, Chris Kocon, and Stan Benczkowski, “Optimization of the body-diode of power MOSFETs for high efficient synchronous rectification,” ISPSD '2000, pp. 145-148.
- From the above descriptions, figures and narratives, the invention's advantages in providing a low-voltage high-density trench-gated power MOSFET device should be clear.
- Although the description, operation and illustrative material above contain much specificity, these specificities should not be construed as limiting the scope of the invention but as merely providing illustrations and examples of some of the preferred embodiments of this invention.
- Thus the scope of the invention should be determined by the appended claims and their legal equivalents, rather than by the examples given above.
Claims (2)
1. A method for manufacturing a power mosfet comprising the steps of:
forming a gate trench mask with open and closed regions on the surface of a semiconductor substrate;
removing semiconductor material from areas exposed by the open regions of the trench mask to form a plurality of gate trenches;
forming a sacrificial gate oxide layer on the sidewalls of the trenches;
implanting the substrate with a drift region implant that penetrates the oxide on the floors of the trenches and is stopped on the surface of the substrate by the residual trench mask;
diffusing the drift region implant to form a continuous drift layer and define the length of the gate and to form a continuous lightly doped drift region extending between sidewalls of the trenches and from the drain layer toward the source region and along a lower portion of the trench sidewalls to provide a variable, lightly doped concentration that gradually decreases in density from the sidewalls of the trenches toward a plane about midway between the trenches;
removing the trench mask and the sacrificial oxide and forming a gate oxide on the surface of the trench;
depositing a layer of polysilicon on the surface of the substrate and in the trenches;
removing the polysilicon from the surface of the semiconductor substrate and leaving enough polysilicon in the gate trenches to form gates in the trenches;
implanting the substrate with a source dopant to form source regions in the surface of the semiconductor substrate and to increase the conductivity of the polysilicon in the trenches to form gate regions in the trenches;
depositing a layer of BPSG on the substrate;
removing at least apart of the BPSG layer to expose portions of the surface having the source implant;
depositing and patterning a conductive layer over the surface of the substrate to form electrical contacts to the source regions.
2. The method of claim 1 further comprising the steps of:
etching a step having a vertical face and a horizontal ledge on the edge of the die while etching the trenches;
forming a gate runner on an upper surface proximate the vertical face;
forming a heavily doped channel stop region in the horizontal ledge at the edged of the die with dopants of the same polarity as the source region; and
forming a metal contact layer over and in contact with the channel stop region.
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US11/866,072 US7633102B2 (en) | 2002-05-03 | 2007-10-02 | Low voltage high density trench-gated power device with uniformly doped channel and its edge termination |
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US10/138,913 US6784505B2 (en) | 2002-05-03 | 2002-05-03 | Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique |
US10/795,723 US6946348B2 (en) | 2002-05-03 | 2004-03-05 | Low voltage high density trench-gated power device with uniformity doped channel and its edge termination technique |
US11/204,552 US20050272208A1 (en) | 2002-05-03 | 2005-08-16 | Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique |
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US10/795,723 Expired - Lifetime US6946348B2 (en) | 2002-05-03 | 2004-03-05 | Low voltage high density trench-gated power device with uniformity doped channel and its edge termination technique |
US11/204,552 Abandoned US20050272208A1 (en) | 2002-05-03 | 2005-08-16 | Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100213527A1 (en) * | 2009-02-25 | 2010-08-26 | Sunil Shim | Integrated Circuit Memory Devices Having Selection Transistors with Nonuniform Threshold Voltage Characteristics |
Families Citing this family (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6291298B1 (en) * | 1999-05-25 | 2001-09-18 | Advanced Analogic Technologies, Inc. | Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses |
US7202102B2 (en) * | 2001-11-27 | 2007-04-10 | Jds Uniphase Corporation | Doped absorption for enhanced responsivity for high speed photodiodes |
US6784505B2 (en) * | 2002-05-03 | 2004-08-31 | Fairchild Semiconductor Corporation | Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique |
US7557395B2 (en) * | 2002-09-30 | 2009-07-07 | International Rectifier Corporation | Trench MOSFET technology for DC-DC converter applications |
US6812486B1 (en) * | 2003-02-20 | 2004-11-02 | National Semiconductor Corporation | Conductive structure and method of forming the structure |
US7019358B2 (en) * | 2003-07-31 | 2006-03-28 | Clare, Inc. | High voltage semiconductor device having an increased breakdown voltage relative to its on-resistance |
TWI256676B (en) * | 2004-03-26 | 2006-06-11 | Siliconix Inc | Termination for trench MIS device having implanted drain-drift region |
US7268395B2 (en) * | 2004-06-04 | 2007-09-11 | International Rectifier Corporation | Deep trench super switch device |
US7132344B1 (en) * | 2004-12-03 | 2006-11-07 | National Semiconductor Corporation | Super self-aligned BJT with base shorted field plate and method of fabricating |
US7671439B2 (en) * | 2005-02-11 | 2010-03-02 | Alpha & Omega Semiconductor, Ltd. | Junction barrier Schottky (JBS) with floating islands |
US7737522B2 (en) * | 2005-02-11 | 2010-06-15 | Alpha & Omega Semiconductor, Ltd. | Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction |
US8093651B2 (en) * | 2005-02-11 | 2012-01-10 | Alpha & Omega Semiconductor Limited | MOS device with integrated schottky diode in active region contact trench |
US8362547B2 (en) * | 2005-02-11 | 2013-01-29 | Alpha & Omega Semiconductor Limited | MOS device with Schottky barrier controlling layer |
US8283723B2 (en) * | 2005-02-11 | 2012-10-09 | Alpha & Omega Semiconductor Limited | MOS device with low injection diode |
US7285822B2 (en) | 2005-02-11 | 2007-10-23 | Alpha & Omega Semiconductor, Inc. | Power MOS device |
US7948029B2 (en) | 2005-02-11 | 2011-05-24 | Alpha And Omega Semiconductor Incorporated | MOS device with varying trench depth |
US20070029573A1 (en) * | 2005-08-08 | 2007-02-08 | Lin Cheng | Vertical-channel junction field-effect transistors having buried gates and methods of making |
CN100454519C (en) * | 2005-10-11 | 2009-01-21 | 尔必达存储器株式会社 | Semiconductor device and manufacturing method thereof |
US7560787B2 (en) * | 2005-12-22 | 2009-07-14 | Fairchild Semiconductor Corporation | Trench field plate termination for power devices |
US7473976B2 (en) * | 2006-02-16 | 2009-01-06 | Fairchild Semiconductor Corporation | Lateral power transistor with self-biasing electrodes |
JP2008053276A (en) * | 2006-08-22 | 2008-03-06 | Nec Electronics Corp | Method of manufacturing semiconductor device |
JP5198752B2 (en) * | 2006-09-28 | 2013-05-15 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP2008103378A (en) * | 2006-10-17 | 2008-05-01 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
US8035159B2 (en) * | 2007-04-30 | 2011-10-11 | Alpha & Omega Semiconductor, Ltd. | Device structure and manufacturing method using HDP deposited source-body implant block |
CN101315894B (en) * | 2007-05-30 | 2010-05-26 | 上海华虹Nec电子有限公司 | Method for raising puncture voltage between two polysilicons of groove type double-layer grid power MOS |
TWI355078B (en) | 2007-07-16 | 2011-12-21 | Nanya Technology Corp | Transistor structure and method of making the same |
CN101350363B (en) * | 2007-07-16 | 2011-06-22 | 南亚科技股份有限公司 | Transistor structure and preparation method thereof |
KR101630734B1 (en) | 2007-09-21 | 2016-06-16 | 페어차일드 세미컨덕터 코포레이션 | Power device |
CN101656213B (en) * | 2008-08-19 | 2012-09-26 | 尼克森微电子股份有限公司 | Trench gate metal oxide semiconductor field effect transistor and manufacturing method thereof |
CN101764061B (en) * | 2008-12-26 | 2012-05-30 | 马克斯半导体股份有限公司 | Power metal-oxide-semiconductor field effect transistor structure and processing method thereof |
TWI396240B (en) * | 2009-05-08 | 2013-05-11 | Anpec Electronics Corp | Method of fabricating power semiconductor device |
US8330214B2 (en) * | 2009-05-28 | 2012-12-11 | Maxpower Semiconductor, Inc. | Power semiconductor device |
US20110198689A1 (en) * | 2010-02-17 | 2011-08-18 | Suku Kim | Semiconductor devices containing trench mosfets with superjunctions |
JP6008377B2 (en) * | 2010-03-03 | 2016-10-19 | ルネサスエレクトロニクス株式会社 | P-channel power MOSFET |
US8378392B2 (en) * | 2010-04-07 | 2013-02-19 | Force Mos Technology Co., Ltd. | Trench MOSFET with body region having concave-arc shape |
TWI453827B (en) * | 2010-08-20 | 2014-09-21 | Csmc Technologies Fab1 Co Ltd | Vertical NPN transistor and its manufacturing method |
CN102468169A (en) * | 2010-11-01 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | N-channel metal oxide semiconductor (NMOS) transistor and formation method thereof |
CN103329268B (en) * | 2011-03-17 | 2016-06-29 | 富士电机株式会社 | Semiconductor device and the method manufacturing it |
US8362585B1 (en) | 2011-07-15 | 2013-01-29 | Alpha & Omega Semiconductor, Inc. | Junction barrier Schottky diode with enforced upper contact structure and method for robust packaging |
JP6290526B2 (en) | 2011-08-24 | 2018-03-07 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
US8872278B2 (en) | 2011-10-25 | 2014-10-28 | Fairchild Semiconductor Corporation | Integrated gate runner and field implant termination for trench devices |
CN103241705B (en) * | 2012-02-03 | 2015-12-09 | 中国科学院微电子研究所 | Silicon corrosion local termination layer preparation method |
JP2013258327A (en) * | 2012-06-13 | 2013-12-26 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
WO2014061075A1 (en) * | 2012-10-15 | 2014-04-24 | トヨタ自動車株式会社 | Semiconductor device and method for manufacturing same |
US20140306284A1 (en) * | 2013-04-12 | 2014-10-16 | Infineon Technologies Austria Ag | Semiconductor Device and Method for Producing the Same |
CN107112361B (en) * | 2015-02-12 | 2020-09-25 | 株式会社日立制作所 | Semiconductor device and method for manufacturing the same, power conversion device, three-phase motor system, automobile, and railway vehicle |
US9524994B2 (en) | 2015-04-14 | 2016-12-20 | Semiconductor Components Industries, Llc | Image sensor pixels with multiple compartments |
CN106328697B (en) * | 2015-07-02 | 2019-02-15 | 无锡华润上华科技有限公司 | Semiconductor devices and its manufacturing method with trench gate structure |
US10600911B2 (en) | 2017-09-26 | 2020-03-24 | Nxp Usa, Inc. | Field-effect transistor and method therefor |
US10522677B2 (en) | 2017-09-26 | 2019-12-31 | Nxp Usa, Inc. | Field-effect transistor and method therefor |
US10424646B2 (en) | 2017-09-26 | 2019-09-24 | Nxp Usa, Inc. | Field-effect transistor and method therefor |
DE102017124872B4 (en) * | 2017-10-24 | 2021-02-18 | Infineon Technologies Ag | Method for manufacturing an IGBT with dV / dt controllability |
WO2019117248A1 (en) | 2017-12-14 | 2019-06-20 | 富士電機株式会社 | Semiconductor device |
US10600879B2 (en) | 2018-03-12 | 2020-03-24 | Nxp Usa, Inc. | Transistor trench structure with field plate structures |
CN109037337A (en) * | 2018-06-28 | 2018-12-18 | 华为技术有限公司 | A kind of power semiconductor and manufacturing method |
US10833174B2 (en) | 2018-10-26 | 2020-11-10 | Nxp Usa, Inc. | Transistor devices with extended drain regions located in trench sidewalls |
US10749023B2 (en) | 2018-10-30 | 2020-08-18 | Nxp Usa, Inc. | Vertical transistor with extended drain region |
US10749028B2 (en) | 2018-11-30 | 2020-08-18 | Nxp Usa, Inc. | Transistor with gate/field plate structure |
US11387348B2 (en) | 2019-11-22 | 2022-07-12 | Nxp Usa, Inc. | Transistor formed with spacer |
US11329156B2 (en) | 2019-12-16 | 2022-05-10 | Nxp Usa, Inc. | Transistor with extended drain region |
US11075110B1 (en) | 2020-03-31 | 2021-07-27 | Nxp Usa, Inc. | Transistor trench with field plate structure |
US11217675B2 (en) | 2020-03-31 | 2022-01-04 | Nxp Usa, Inc. | Trench with different transverse cross-sectional widths |
CN111697080A (en) * | 2020-07-21 | 2020-09-22 | 江苏长晶科技有限公司 | Semiconductor unit cell, manufacturing method and semiconductor device |
CN113745339B (en) * | 2021-09-07 | 2022-08-19 | 无锡新洁能股份有限公司 | High-reliability power semiconductor device and manufacturing method thereof |
CN116193865B (en) * | 2023-04-26 | 2023-09-19 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
CN117373914A (en) * | 2023-12-08 | 2024-01-09 | 芯联集成电路制造股份有限公司 | Transistor device and manufacturing method thereof, semiconductor integrated circuit and manufacturing method thereof |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4754310A (en) * | 1980-12-10 | 1988-06-28 | U.S. Philips Corp. | High voltage semiconductor device |
US5072266A (en) * | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
US5216275A (en) * | 1991-03-19 | 1993-06-01 | University Of Electronic Science And Technology Of China | Semiconductor power devices with alternating conductivity type high-voltage breakdown regions |
US5569949A (en) * | 1992-09-02 | 1996-10-29 | Texas Instruments Incorporated | Area efficient high voltage MOSFETs with vertical RESURF drift regions |
US5665996A (en) * | 1994-12-30 | 1997-09-09 | Siliconix Incorporated | Vertical power mosfet having thick metal layer to reduce distributed resistance |
US5674766A (en) * | 1994-12-30 | 1997-10-07 | Siliconix Incorporated | Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer |
US6040212A (en) * | 1996-08-16 | 2000-03-21 | Fairchild Korea Semiconductor, Ltd. | Methods of forming trench-gate semiconductor devices using sidewall implantation techniques to control threshold voltage |
US6462376B1 (en) * | 1999-01-11 | 2002-10-08 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Power MOS element and method for producing the same |
US20030205758A1 (en) * | 2002-05-03 | 2003-11-06 | Jun Zeng | Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique |
US20060011976A1 (en) * | 2004-03-26 | 2006-01-19 | Siliconix Incorporated | Termination for trench MIS device having implanted drain-drift region |
US20060038223A1 (en) * | 2001-07-03 | 2006-02-23 | Siliconix Incorporated | Trench MOSFET having drain-drift region comprising stack of implanted regions |
US20060273383A1 (en) * | 2005-06-06 | 2006-12-07 | M-Mos Sdn. Bhd. | High density hybrid MOSFET device |
US20060273382A1 (en) * | 2005-06-06 | 2006-12-07 | M-Mos Sdn. Bhd. | High density trench MOSFET with low gate resistance and reduced source contact space |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2912508B2 (en) * | 1992-11-13 | 1999-06-28 | シャープ株式会社 | Method of manufacturing vertical MOS transistor |
US5448090A (en) * | 1994-08-03 | 1995-09-05 | International Business Machines Corporation | Structure for reducing parasitic leakage in a memory array with merged isolation and node trench construction |
US5770878A (en) * | 1996-04-10 | 1998-06-23 | Harris Corporation | Trench MOS gate device |
AU3724197A (en) * | 1996-07-19 | 1998-02-10 | Siliconix Incorporated | High density trench dmos transistor with trench bottom implant |
US6084264A (en) * | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
US6177333B1 (en) * | 1999-01-14 | 2001-01-23 | Micron Technology, Inc. | Method for making a trench isolation for semiconductor devices |
US20010001494A1 (en) * | 1999-04-01 | 2001-05-24 | Christopher B. Kocon | Power trench mos-gated device and process for forming same |
EP1170803A3 (en) | 2000-06-08 | 2002-10-09 | Siliconix Incorporated | Trench gate MOSFET and method of making the same |
WO2002069394A1 (en) * | 2001-02-27 | 2002-09-06 | Fairchild Semiconductor Corporation | Process for depositing and planarizing bpsg for dense trench mosfet application |
US6657254B2 (en) * | 2001-11-21 | 2003-12-02 | General Semiconductor, Inc. | Trench MOSFET device with improved on-resistance |
-
2002
- 2002-05-03 US US10/138,913 patent/US6784505B2/en not_active Expired - Lifetime
-
2003
- 2003-04-08 TW TW092108053A patent/TWI225285B/en not_active IP Right Cessation
- 2003-04-10 CN CNB038100193A patent/CN100565932C/en not_active Expired - Fee Related
- 2003-04-10 JP JP2004502327A patent/JP4771694B2/en not_active Expired - Fee Related
- 2003-04-10 CN CNB2007101064087A patent/CN100547808C/en not_active Expired - Fee Related
- 2003-04-10 WO PCT/US2003/011235 patent/WO2003094200A2/en active Application Filing
- 2003-04-10 DE DE10392617T patent/DE10392617T5/en not_active Withdrawn
- 2003-04-10 AU AU2003228499A patent/AU2003228499A1/en not_active Abandoned
- 2003-04-10 CN CN2009101791216A patent/CN101673768B/en not_active Expired - Fee Related
-
2004
- 2004-03-05 US US10/795,723 patent/US6946348B2/en not_active Expired - Lifetime
-
2005
- 2005-08-16 US US11/204,552 patent/US20050272208A1/en not_active Abandoned
-
2007
- 2007-10-02 US US11/866,072 patent/US7633102B2/en not_active Expired - Fee Related
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4754310A (en) * | 1980-12-10 | 1988-06-28 | U.S. Philips Corp. | High voltage semiconductor device |
US5072266A (en) * | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
US5216275A (en) * | 1991-03-19 | 1993-06-01 | University Of Electronic Science And Technology Of China | Semiconductor power devices with alternating conductivity type high-voltage breakdown regions |
US5569949A (en) * | 1992-09-02 | 1996-10-29 | Texas Instruments Incorporated | Area efficient high voltage MOSFETs with vertical RESURF drift regions |
US5665996A (en) * | 1994-12-30 | 1997-09-09 | Siliconix Incorporated | Vertical power mosfet having thick metal layer to reduce distributed resistance |
US5674766A (en) * | 1994-12-30 | 1997-10-07 | Siliconix Incorporated | Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer |
US6040212A (en) * | 1996-08-16 | 2000-03-21 | Fairchild Korea Semiconductor, Ltd. | Methods of forming trench-gate semiconductor devices using sidewall implantation techniques to control threshold voltage |
US6462376B1 (en) * | 1999-01-11 | 2002-10-08 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Power MOS element and method for producing the same |
US20060038223A1 (en) * | 2001-07-03 | 2006-02-23 | Siliconix Incorporated | Trench MOSFET having drain-drift region comprising stack of implanted regions |
US20030205758A1 (en) * | 2002-05-03 | 2003-11-06 | Jun Zeng | Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique |
US20060011976A1 (en) * | 2004-03-26 | 2006-01-19 | Siliconix Incorporated | Termination for trench MIS device having implanted drain-drift region |
US20060019448A1 (en) * | 2004-03-26 | 2006-01-26 | Siliconix Incorporated | Termination for trench MIS device having implanted drain-drift region |
US20060273383A1 (en) * | 2005-06-06 | 2006-12-07 | M-Mos Sdn. Bhd. | High density hybrid MOSFET device |
US20060273382A1 (en) * | 2005-06-06 | 2006-12-07 | M-Mos Sdn. Bhd. | High density trench MOSFET with low gate resistance and reduced source contact space |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100213527A1 (en) * | 2009-02-25 | 2010-08-26 | Sunil Shim | Integrated Circuit Memory Devices Having Selection Transistors with Nonuniform Threshold Voltage Characteristics |
US8319275B2 (en) * | 2009-02-25 | 2012-11-27 | Samsung Electronics Co., Ltd. | Integrated circuit memory devices having selection transistors with nonuniform threshold voltage characteristics |
US8637920B2 (en) | 2009-02-25 | 2014-01-28 | Samsung Electronics Co., Ltd. | Semiconductor memory devices having selection transistors with nonuniform threshold voltage characteristics |
US9012977B2 (en) | 2009-02-25 | 2015-04-21 | Samsung Electronics Co., Ltd. | Semiconductor memory devices having selection transistors with nonuniform threshold voltage characteristics |
Also Published As
Publication number | Publication date |
---|---|
WO2003094200A3 (en) | 2004-05-27 |
TWI225285B (en) | 2004-12-11 |
US20030205758A1 (en) | 2003-11-06 |
JP4771694B2 (en) | 2011-09-14 |
US6946348B2 (en) | 2005-09-20 |
CN1650437A (en) | 2005-08-03 |
WO2003094200A2 (en) | 2003-11-13 |
US20080023759A1 (en) | 2008-01-31 |
US20040171198A1 (en) | 2004-09-02 |
CN100547808C (en) | 2009-10-07 |
US7633102B2 (en) | 2009-12-15 |
US6784505B2 (en) | 2004-08-31 |
TW200306646A (en) | 2003-11-16 |
CN101673768B (en) | 2013-02-06 |
CN100565932C (en) | 2009-12-02 |
JP2005524975A (en) | 2005-08-18 |
CN101673768A (en) | 2010-03-17 |
DE10392617T5 (en) | 2005-07-21 |
AU2003228499A8 (en) | 2003-11-17 |
AU2003228499A1 (en) | 2003-11-17 |
CN101071826A (en) | 2007-11-14 |
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