US20050230035A1 - Thin film forming apparatus and thin film forming method - Google Patents
Thin film forming apparatus and thin film forming method Download PDFInfo
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- US20050230035A1 US20050230035A1 US11/127,381 US12738105A US2005230035A1 US 20050230035 A1 US20050230035 A1 US 20050230035A1 US 12738105 A US12738105 A US 12738105A US 2005230035 A1 US2005230035 A1 US 2005230035A1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2924/01055—Cesium [Cs]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/18—Deposition of organic active material using non-liquid printing techniques, e.g. thermal transfer printing from a donor sheet
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/17—Surface bonding means and/or assemblymeans with work feeding or handling means
- Y10T156/1702—For plural parts or plural areas of single part
- Y10T156/1705—Lamina transferred to base from adhered flexible web or sheet type carrier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
Abstract
Apparatus for forming a thin film pattern on the surface of a substrate. This apparatus is provided with: a transfer member having a thin film carrying surface which carries a thin film pattern; and a thin film transfer mechanism for joining the transfer member to a substrate for transferring, to the substrate, the thin film pattern on the thin film carrying surface. The thin film pattern may be a wiring film pattern. A gelatinous film may previously be formed on the substrate, and the thin film pattern may be transferred as embedded in the gelatinous film.
Description
- 1. Field of the Invention
- The present invention relates to thin film forming apparatus for and thin film forming method of forming a thin film pattern or a plurality of thin films on a surface of any of a variety of substrates such as a semiconductor wafer, a glass substrate for a liquid-crystal-display-panel, a glass substrate for a plasma-display-panel, a photo mask substrate, a print-circuit board and the like.
- 2. Description of Related Art
- A damascene method is known as an example of the method of forming a metallic wiring such as a copper wiring or the like on a surface of a semiconductor wafer (hereinafter simply referred to as wafer).
FIGS. 11A to 11D show a wiring forming process according to the damascene method. - Formed on the
wafer 1 is aninsulating film 2, on which there are pattern-formed resists 3 havingopenings 3 a corresponding to a metallic wiring pattern to be formed (FIG. 11A ). With the use of the resists 3 as masks, etching is conducted, thus forming, in theinsulating film 2, openings or recessportions 2 a corresponding to the wiring pattern to be formed (FIG. 11B ). - Then, a wiring
metallic film 4 is formed all over the surface of thewafer 1 in such thickness that the openings or recessportions 2 a are entirely buried (FIG. 11C ). Then, according to a CMP (chemical mechanical polishing) method, themetallic film 4 is ground or polished until the surface of theinsulating film 2 is exposed. This formsmetallic wiring patterns 4W embedded in the openings or recessportions 2 a in theinsulating film 2 as shown inFIG. 11D . - However, the wiring forming process above-mentioned requires not only patterning with photolithography applied to the
insulating film 2 on thewafer 1, but also grinding or polishing the entire surface of the wiringmetallic film 4 according to the CMP method. This makes the process complicated, disadvantageously increasing the wiring pattern forming cost. - On the other hand, a transfer method is known as an example of the method of forming an interlayer insulating film on the surface of a semiconductor wafer. According to this transfer method, another sheet different from the semiconductor wafer is coated at its surface with an interlayer insulating film material, thus forming a coated film. This sheet having the coated film formed thereon and the semiconductor wafer are laminated on each other. Then, only the sheet is separated from the semiconductor wafer, thus transferring the coated film from the sheet to the semiconductor wafer.
- The use of the thin film forming method according to this transfer method, can eliminate the problem of voids encountered with forming of an SOG (Spin On Glass) layer with the use of a spin-coater. Further, a flat interlayer insulating film can be formed without a flattening processing such as a CMP method or the like.
- In a recent semiconductor integrated circuit having a complicated arrangement, however, a number of thin films are formed on the surface of the substrate as typically seen in the case where multi-layer wirings are formed on a semiconductor substrate. In such a case, when there is used the prior art above-mentioned in which only one-type thin film is transferred, at one time, from the sheet to the semiconductor wafer, it is required to execute the transferring processing many times. This complicates the production process, thus disadvantageously increasing the semiconductor production cost.
- It is a first object of the present invention to provide a thin film forming apparatus capable of forming a thin film pattern on a substrate with a simple and economical process.
- It is a second object of the present invention to provide a thin film forming method capable of forming a thin film pattern on a substrate with a simple and economical process.
- It is a third object of the present invention to provide a substrate processing apparatus capable of forming a thin film pattern on a substrate with a simple and economical process.
- It is a fourth object of the present invention to provide a thin film forming apparatus capable of transferring a plurality of thin films to a substrate with a fewer number of transfer times, thereby simplifying the process to accordingly reduce the thin film forming processing cost.
- It is a fifth object of the present invention to provide a thin film forming method capable of transferring a plurality of thin films to a substrate with a fewer number of transfer times, thereby simplifying the process to accordingly reduce the thin film forming processing cost.
- A first thin film forming apparatus according to the present invention, is arranged to form a thin film pattern on the surface of a substrate, and comprises: a transfer member having a thin film carrying surface which carries a thin film pattern; and a thin film transfer mechanism for joining the transfer member and a substrate to each other for transferring, to the substrate, the thin film pattern on the thin film carrying surface.
- A first thin film forming method according to the present invention, is arranged to form a thin film pattern on the surface of a substrate, and comprises the steps of: forming a thin film pattern on a thin film carrying surface of a transfer member; and joining the transfer member and a substrate to each other for transferring, to the substrate, the thin film pattern on the thin film carrying surface.
- The substrate may be a substrate on which a fine wiring pattern or device is to be formed. Examples of the substrate include a semiconductor substrate, a glass substrate for a liquid-crystal-display-panel, a glass substrate for a plasma-display-panel, a print-circuit board and the like.
- The thin film pattern formed on the substrate surface may be a wiring film pattern. This wiring film pattern may be a sunken wiring film pattern to be embedded in a film (insulating film or the like) formed on the substrate.
- For example, provision may be made such that a gelatinous film (insulating film or the like) is previously formed on the substrate, and that the substrate and the transfer member are joined to each other to transfer, to the substrate, the thin film pattern (wiring film pattern or the like) on the transfer member so that the thin film pattern is embedded in the gelatinous film thereon.
- The transfer member may be provided on a surface thereof with a recess portion and a projecting portion, and the thin film carrying surface may be formed on the surface of the projecting portion.
- The transfer member may have a flat surface and the thin film pattern may be formed on a predetermined area of the flat surface.
- When the thin film pattern is a metallic film pattern (wiring film pattern or the like), the thin film pattern can be formed on the transfer member by a plating method (either electroless plating or electroplating).
- According to the present invention, a substrate and the transfer member which carries a thin film pattern, are joined to each other for transferring, to the substrate, the thin film pattern on the transfer member, thus enabling the thin film pattern to be formed on the substrate. Accordingly, when a desired thin film pattern is previously formed on the transfer member, the thin film pattern can be formed on the substrate without a photolithography processing executed on the substrate.
- Further, when a gelatinous film is previously formed on the substrate, the thin film pattern on the transfer member can be transferred to the substrate such that the thin film pattern is embedded in the gelatinous film. Accordingly, the wiring film pattern embedded in the insulating film can be formed without for example a CMP process required.
- A second thin film forming apparatus according to the present invention, is arranged to form a plurality of thin films on a substrate, and comprises: a transfer member which carries a plurality of thin films; and a transfer mechanism for joining the transfer member and the substrate to each other for collectively transferring, to the substrate, a plurality of thin films carried by the transfer member.
- A second thin film forming method according to the present invention, is arranged to form a plurality of thin films on a substrate, and comprises the steps of: forming a plurality of thin films on a surface of a transfer member; and joining, to the substrate, the transfer member having the plurality of thin films formed thereon for collectively transferring the plurality of thin films to the substrate.
- The substrate may be a semiconductor wafer, a glass substrate for a liquid-crystal-display-panel, a glass substrate for a plasma-display-panel, a print-circuit board or the like. Further, the substrate may be an interposer serving as an insulating substrate to be used for re-wiring in a chip-size-package(CSP)-type semiconductor device.
- The plurality of thin films may comprise films of different types to be formed in the same layer on the substrate. For example, the plurality of thin films may comprise an insulating film and a conductive film (wiring film) to be formed in the same layer.
- The plurality of thin films may comprise thin films to be formed in different layers. In such a case, the thin films laminated in a plurality of layers are collectively transferred to the substrate from the transfer member.
- According to the present invention, a plurality of thin films are previously formed on the surface of the transfer member, and these thin films are collectively transferred to the substrate surface. This reduces the number of transfer processing times. This not only improves the productivity, but also remarkably reduces the cost required for the thin film forming processing.
- These and other features, objects, advantages and effects of the present invention will be more fully apparent from the following detailed description set forth below when taken in conjunction with the accompanying drawings.
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FIG. 1A toFIG. 1C are schematic section views illustrating a wiring forming method according to an embodiment of the present invention; -
FIG. 2A toFIG. 2C are section views illustrating an example of the process of forming a metallic wiring pattern on the surface of a transfer member; -
FIG. 3A andFIG. 3B are section views illustrating an example of a metallic-wiring-film-pattern forming method when the base material of the transfer member is made of a conductive material such as metal or the like; -
FIG. 4 is a schematic plan view illustrating the layout of a substrate processing apparatus for executing the wiring forming process above-mentioned; -
FIG. 5 is a schematic view illustrating an example of the arrangement of the transfer processing section; -
FIG. 6A andFIG. 6B are views illustrating the arrangement of the transfer member used in another embodiment of the present invention; -
FIG. 7A toFIG. 7C are schematic section views illustrating a thin film forming method according to a further embodiment of the present invention; -
FIG. 8 is a schematic view illustrating the arrangement of a transfer processing apparatus for transferring a thin film layer from the transfer sheet to the wafer; -
FIG. 9A toFIG. 9C are schematic section views illustrating a thin film forming method according to still another embodiment of the present invention; -
FIG. 10 is a schematic section view of a chip-size-package(CSP)-type semiconductor device, illustrating a still further embodiment of the present invention; and -
FIG. 11A toFIG. 11D is a schematic section view illustrating a wiring forming process according to a damascene method. -
FIG. 1A toFIG. 1C are schematic section views illustrating a wiring forming method according to an embodiment of the present invention. First, there is prepared a semiconductor wafer (hereinafter simply referred to as wafer) 20 provided on the surface thereof with a gelatinous insulatingfilm 21. Further, there is prepared atransfer member 30 having a surface on which projection-recess patterns are formed. The projectingportions 31 of thetransfer member 30 have surfaces serving as thin-film carrying faces 31 a. Metallicwiring film patterns 32 are formed on the thin-film carrying faces 31 a. The projectingportions 31 of thetransfer member 30 are formed in patterns corresponding to the wiring patterns to be formed on thewafer 20. Accordingly, the metallicwiring film patterns 32 are also formed in the wiring patterns to be formed on thewafer 20. - As shown in
FIG. 1A , thewafer 20 and thetransfer member 30 are disposed with the insulatingfilm 21 and the metallicwiring film patterns 32 being opposite to each other. Then, thetransfer member 30 and thewafer 20 are joined to each other as shown inFIG. 1B . Since the insulatingfilm 21 is a gelatinous film, the metallicwiring film patterns 32 come into the inside of the insulatingfilm 21 from the surface thereof. - Then, the
wafer 20 and thetransfer member 30 are separated from each other as shown inFIG. 1C . Accordingly, the metallicwiring film patterns 32 are transferred to thewafer 20 from thetransfer member 30 and embedded in the insulatingfilm 21. -
FIG. 2A toFIG. 2C are section views illustrating an example of the process of forming the metallicwiring film patterns 32 on the surface of thetransfer member 30. First, resists 34 are embedded inrecess portions 33 in the surface of thetransfer member 30 as shown inFIG. 2A . Then, thetransfer member 30 in the state inFIG. 2A is immersed in a plating solution such that the metallicwiring film patterns 32 are grown on the thin-film carrying faces 31 a by an electroless plating method. - As shown in
FIG. 2C , the resists 34 are then exfoliated, thus obtaining thetransfer member 30 in which the metallicwiring film patterns 32 are selectively being formed on the thin-film carrying faces 31 a of the projectingportions 31. - This process of growing the metallic
wiring film patterns 32 by an electroless plating method, is particularly effective for the case where the base material of thetransfer member 30 is an insulating material of quartz for example. - The projection-recess patterns on the surface of the
transfer member 30 can be formed by a normal photolithography. More specifically, resist films corresponding to the patterns of the projectingportions 31 are formed on the surface of theflat transfer member 30, and with the resist films serving as masks, etching is conducted, thus forming therecess portions 33. Thereafter, when the resist films are exfoliated, there is obtained thetransfer member 30 having the projectingportions 31 corresponding to the desired wiring patterns. -
FIG. 3A andFIG. 3B are section views illustrating an example of a method of forming the metallicwiring film patterns 32 when the base material of thetransfer member 30 is made of a conductive material such as metal. First, as shown in FIG. 3A,seed films 35 are formed on the thin-film carrying faces 31 a of the projectingportions 31 by a sputter method or a CVD (chemical vapor deposition) method. Thetransfer member 30 in the state shown inFIG. 3A is immersed in a plating solution, and electroplating is conducted with thetransfer member 30 connected to oneelectrode 37. Thus, metallicwiring film patterns 32 each having the desired film thickness can be grown on the thin-film carrying faces 31 a on which theseed films 35 are formed. -
FIG. 4 is a schematic plan view illustrating the layout of a substrate processing apparatus for executing the wiring forming process above-mentioned. This substrate processing apparatus has anindexer section 40 and asubstrate processing section 50 in combination therewith. - The
indexer section 40 has acassette placing section 41 in which there can be placed, as arranged along a predetermined cassette arrangement direction, cassettes CS in each of which a plurality oftransfer members 30 can be housed, and cassettes CW in each of which a plurality ofwafers 20 can be housed. Theindexer section 40 further has anindexer robot 42 which is arranged to take out atransfer member 30 or awafer 20 from a cassette placed in thecassette placing section 41 and to hand it to thesubstrate processing section 50, and which is also arranged to receive a usedtransfer member 30 or a treatedwafer 20 from thesubstrate processing section 50 and to house it in the cassette CS or CW. - The
substrate processing section 50 comprisesplating processing sections 51A, 51B for forming the metallicwiring film patterns 32 on the surface of atransfer member 30, aheating processing section 52 in which hot plates (HP) for heating a wafer W and cool plates (CP) for cooling the same to an ambient temperature, are stacked in multiple stages, acoating processing section 53 such as a spin coater or the like for coating the surface of awafer 20 with a gelatinous insulatingfilm 21, and atransfer processing section 54 for joining awafer 20 and atransfer member 30 to each other. - The
substrate processing section 50 further comprises amain conveyance robot 55 for carrying awafer 20 or atransfer member 30 in and out from theplating processing sections 51A, 51B, theheating processing section 52, thecoating processing section 53 and thetransfer processing section 54. Themain conveyance robot 55 is arranged to receive anunused transfer member 30 from theindexer robot 42, to carry it in theplating processing section 51A or 51B, to receive a platedtransfer member 30 from theplating processing section 51A or 51B, and to carry it in thetransfer processing section 54. Thetransfer member 30 after used in thetransfer processing section 54, is carried out and then transferred to theindexer robot 42 by themain conveyance robot 55. Then, theindexer robot 42 houses thistransfer member 30 in a cassette CS. - On the other hand, an
untreated wafer 20 is taken out from a cassette CW and transferred to themain conveyance robot 55 by theindexer robot 42. Themain conveyance robot 55 first carries thewafer 20 in thecoating processing section 53, where thewafer 20 is coated with the material film of the insulatingfilm 21. As necessary, thewafer 20 thus coated is carried in theheating processing section 52, where thewafer 20 is subjected to heating and cooling processings. In the manner above-mentioned, the gelatinous insulatingfilm 21 is formed on the surface of thewafer 20. - Thereafter, the
main conveyance robot 55 takes out thewafer 20 from theheating processing section 52 and carries it in thetransfer processing section 54. At thetransfer processing section 54, the processings shown inFIG. 1A toFIG. 1C , are executed so that the metallicwiring film patterns 32 are transferred from the surface of thetransfer member 30 to thewafer 20. As necessary, thewafer 20 having the metallicwiring film patterns 32 transferred thereto, is carried in theheating processing section 52, where thewafer 20 is subjected to a heating processing for hardening the insulatingfilm 21. Thereafter, thewafer 20 is cooled to an ambient temperature, and then carried out by themain conveyance robot 55. This treatedwafer 20 is transferred to theindexer robot 42 and then housed in a cassette CW. -
FIG. 5 is a schematic view illustrating an example of the arrangement of thetransfer processing section 54. Thistransfer processing section 54 comprises astationary stage 61 which suctions and holds atransfer member 30 with the projectingportions 31 faced downwardly, and amovable stage 62 which suctions and holds awafer 20 with the insulatingfilm 21 faced upwardly. Thestationary stage 61 and themovable stage 62 may respectively be arranged to suctions and holds atransfer member 30 and awafer 20 by an electrostatic chucking method or a vacuum chucking method. - The
stationary stage 61 and themovable stage 62 respectively have holding faces 61 a and 62 a which suctions and holds atransfer member 30 and awafer 20, respectively. These stationary andmovable stages movable stage 62 is aball nut 64 threadedly connected to a vertically extendingball screw 63. Thisball nut 64 is fixed to abracket 67 which is vertically guided bylinear guides motor 68 is transferred to theball screw 63. Accordingly, the forward/reverse rotation of themotor 68 causes theball screw 63 to be rotated so that themovable stage 62 connected to theball nut 64 is vertically moved. This enables themovable stage 62 to be moved toward and away from thestationary stage 61. - With the
stationary stage 61 suctioning and holding atransfer member 30 carrying the metallicwiring film patterns 32 and with themovable stage 62 suctioning and holding awafer 20 provided on the surface thereof with the gelatinous insulatingfilm 21, themovable stage 62 is upwardly moved and brought close to thestationary stage 61. This makes thewafer 20 and thetransfer member 30 stick together, thus providing the state shown inFIG. 1B . - Thereafter, the
motor 68 is inversely rotated to separate themovable stage 62 from thestationary stage 61. This transfers the metallicwiring film patterns 32 to thewafer 20 side. - According to the embodiment having the arrangement above-mentioned, the previously formed metallic
wiring film patterns 32 can be embedded in the insulatingfilm 21 on thewafer 20 with no photolithography processing executed on thewafer 20. Further, a CMP processing is neither required. Accordingly, compared to a conventional damascene method, the wiring patterns can be formed on awafer 20 with an extremely simple process, enabling the semiconductor production cost to be reduced. -
FIG. 6A andFIG. 6B are views illustrating the arrangement of atransfer member 70 used in another embodiment of the present invention. Thistransfer member 70 is used instead of thetransfer member 30 above-mentioned, and is not provided on either surface with projection-recess portions.Seed films 72 corresponding to the patterns of metallicwiring film patterns 32, are formed on one surface (thin film carrying surface) 71 of thetransfer member 70 by a sputtering or CVD method. Thereafter, the metallicwiring film patterns 32 are grown on theseed films 72 by an electroless plating or electroplating method. The electroless plating method is suitably applied when the base material of thetransfer member 70 is an insulating material such as quartz or the like, and the electroplating is suitably applied when the base material of thetransfer member 70 is a conductive material such as metal or the like. - The description has been made of an example in which the metallic wiring film patterns are transferred from a transfer member to a wafer. However, there can also be executed, in a similar manner, a processing in which other thin film patterns than the metallic wiring film patterns are transferred from a transfer member to a substrate.
- In the embodiment above-mentioned, the description has been made of an example in which the metallic
wiring film patterns 32 are embedded in the insulatingfilm 21 on thewafer 20. However, the insulatingfilm 21 may previously be solidified and the metallicwiring film patterns 32 may be transferred as being protuberant on the surface of the insulatingfilm 21. - In the embodiment above-mentioned, a semiconductor wafer is used as an example of the substrate. However, there can also be executed, in a similar manner, a processing of forming thin film patterns on any of a variety of substrates to be treated, such as a glass substrate for a liquid-crystal-display-panel, a glass substrate for a plasma-display-panel, a print-circuit board and the like.
- Examples of the metal which forms the metallic
wiring film patterns 32 in the embodiments above-mentioned, include copper, aluminum, titan, tungsten and a mixture thereof. - Examples of the material which forms the insulating
film 21, include an organic insulating film, a low dielectric interlayer insulating film, SOD (Spin On Dielectric), SOG and the like. - Further, provision may be made such that there is prepared a flat plate having an area larger than the pattern forming portion of the
wafer 20, that this flat plate is mounted, instead of thetransfer member 30, on thestationary stage 61 of thetransfer processing section 54, and that the top of thewafer 20 having the metallicwiring film patterns 32 embedded in the insulatingfilm 21, is pressed against this flat plate. In such an arrangement, the flatness of the top of the insulatingfilm 21 can further be increased. Preferably, the flat plate is a polished quartz plate. - Provision may be made such that in
FIG. 4 , a flattening processing section having an arrangement identical with that of thetransfer processing section 54, is disposed between thecoating processing section 53 and thetransfer processing section 54, and that only embedding of the metallicwiring film patterns 32 in the insulatingfilm 21 is executed at thetransfer processing section 54, while only flattening of the insulatingfilm 21 by the flat plate is executed at the flattening processing section. Such an arrangement improves the throughput. - It is preferable that heating means such as a heater is disposed at the
stationary stage 61 and themovable stage 62 at the flattening processing section, and that the flat plate is heated and the insulatingfilm 21 is heated through thewafer 20, while the insulatingfilm 21 is pressed against the flat plate. - Even though provision is not made such that a flat plate is disposed at the flattening processing section, the
stationary stage 61 itself may be made of quartz or the like and the surface coming in contact with the insulatingfilm 21 may be flattened. - In the
transfer processing section 54 inFIG. 5 , thetransfer member 30 is held by thestationary stage 61 and thewafer 20 is held by themovable stage 62. However, provision may be made such that thewafer 20 is held by thestationary stage 61 and thetransfer member 30 is held by themovable stage 62. - In the
transfer processing section 54 inFIG. 5 , thestationary stage 61 is disposed above themovable stage 62. However, the stationary stage may be disposed under the movable stage. - Provision may be made such that the both stages respectively holding the
transfer member 30 and thewafer 20 are movable, and that these movable stages are moved toward or away from each other to transfer the thin film patterns on thetransfer member 30 to thewafer 20. - The two stages respectively holding the
transfer member 30 and thewafer 20, are not necessarily disposed opposite in a vertical direction, but may be disposed opposite in a horizontal direction. -
FIG. 7A toFIG. 7C are schematic section views illustrating a thin film forming method according to a further embodiment of the present invention. A semiconductor wafer (hereinafter simply referred to as wafer) 120 is disposed opposite to atransfer sheet 130 made of fluoroplastics or the like. Thetransfer sheet 130 is made in a circle slightly larger than that of thewafer 120. Thetransfer sheet 130 has a carryingface 130 a to be opposite to thewafer 120. A multi-layer wiring thin-film structure 140 is carried by the carryingface 130 a. Thewafer 120 has anactive face 120 a which is disposed as opposite to the multi-layer wiring thin-film structure 140. - The multi-layer wiring thin-
film structure 140 is composed of a plurality of thin film layers 141, 142, 143 in lamination. All thin film layers 141, 142, 143 are to be formed, in lamination, on theactive face 120 a of thewafer 120. Actually, these thin film layers 141, 142, 143 are laminated on the carryingface 130 a of thetransfer sheet 130 such that a thin film layer to be laminated at a position closer to theactive face 120 a of thewafer 120, is formed as an upper thin film layer. - The uppermost
thin film layer 141 on the carryingface 130 a of thetransfer sheet 130 comprises, in the same layer, insulatingfilm 141 a andmetallic wiring films 141 b. More specifically, themetallic wiring films 141 b are embedded in the insulatingfilm 141 a. The lowermostthin film layer 143 on the carryingface 130 a of thetransfer sheet 130 comprises, in the same layer, insulatingfilm 143 a andmetallic wiring films 143 b. The thin film layer 142 interposed between the thin film layers 141, 143 comprises, in the same layer, insulatingfilm 142 a andmetallic wiring films 142 b for connecting the upper and lowermetallic wiring films - From the state shown in
FIG. 7A , thewafer 120 and thetransfer sheet 130 are brought close to each other and then joined to each other as shown inFIG. 7B . In the state shown inFIG. 7B , when only thetransfer sheet 130 is separated from thethin film layer 143, the multi-layer wiring thin-film structure 140 is resultantly transferred to theactive face 120 a of thewafer 120 as shown inFIG. 7C . Thus, a plurality of thin film layers 141, 142, 143 comprising insulating films and metallic wiring films, are collectively transferred to thewafer 120. This remarkably improves the productivity as compared to a method in which each film layer of one type is transferred one by one onto the surface of thewafer 120 to form a multi-layer wiring thin-film structure 140 on thewafer 120. Further, the process is remarkably simplified. This accordingly reduces the semiconductor device production cost. -
FIG. 8 is a schematic view illustrating the arrangement of a transfer processing apparatus for transferring the plurality of thin film layers 141 to 143, which form the multi-layer wiring thin-film structure 140, from thetransfer sheet 130 to thewafer 120. The transfer processing apparatus has an arrangement similar to that of the transfer processing apparatus shown inFIG. 5 . InFIG. 8 , like parts are designated by like reference numerals used inFIG. 5 with the description of like parts omitted. - A
stationary stage 61 suctions and holds awafer 120 with anactive face 120 a faced downwardly. Amovable stage 62 suctions and holds atransfer sheet 130 with a multi-layer wiring thin-film structure 140 faced upwardly. Thestationary stage 61 and themovable stage 62 respectively have holding faces 61 a, 62 a for respectively suctioning and holding thewafer 120 and thetransfer sheet 130. The stationary andmovable stages - With the
wafer 120 suctioned and held by thestationary stage 61 and with thetransfer sheet 130 having the multi-layer wiring thin-film structure 140 on the carryingface 130 a suctioned and held by themovable stage 62, themovable stage 62 is moved up and brought close to thestationary stage 61. This causes thewafer 120 and thetransfer sheet 130 to be joined to each other, thus providing the state shown inFIG. 7B . - Thereafter, a
motor 68 is inversely rotated, causing themovable stage 62 to be separated from thestationary stage 61. This enables the multi-layer wiring thin-film structure 140 to be transferred from thetransfer sheet 130 to thewafer 120 side. -
FIG. 9A toFIG. 9C are schematic section views illustrating a thin film forming method according to still another embodiment of the present invention. According to this embodiment, a singlethin film layer 171 is formed on a carryingface 130 a of atransfer sheet 130 as shown inFIG. 9A . Thisthin film layer 171 is a flat thin film having insulatingfilm 171 a andmetallic wiring films 171 b embedded therein. Thetransfer sheet 130 having such athin film layer 171 formed thereon is joined to awafer 120, thus providing the state inFIG. 9B . Then, when only thetransfer sheet 130 is separated, thethin film layer 171 is transferred to thewafer 120 as shown inFIG. 9C . Thus, with a single transfer processing, the insulatingfilm 171 a and themetallic wiring films 171 b embedded therein are formed on the surface of thewafer 120. -
FIG. 10 is a schematic section view of a chip-size-package(CSP)-type semiconductor device, illustrating a still further embodiment of the present invention. Asemiconductor chip 181 is bonded, throughexternal connection terminals 182 such as solder balls or the like disposed on the active faces thereof, to aninterposer 183 serving as an insulating substrate. Theinterposer 183 is provided on onesurface 183 a thereof with amulti-layer wiring structure 184 comprising a plurality of thin films, and on theother surface 183 b thereof withexternal connection terminals 185 such as solder balls or the like. - The
external connection terminals 182 disposed at the underside of thesemiconductor chip 181, are arranged for example in one row along the periphery of thesemiconductor chip 181. On the other hand, theexternal connection terminals 185 formed on thesurface 183 b of theinterposer 183 are arranged in a two-dimensional manner. Themulti-layer wiring structure 184 incorporates three-dimensional wirings for re-wiring theexternal connection terminals 182 of thesemiconductor chip 181 to theexternal connection terminals 185 of theinterposer 183. - The thin film forming method of the present invention can be applied for forming the
multi-layer wiring structure 184 on onesurface 183 a of theinterposer 183. More specifically, themulti-layer wiring structure 184 may wholly or partially previously be formed on a transfer sheet, and themulti-layer wiring structure 184 may wholly or partially be transferred from this transfer sheet to thesurface 183 a of theinterposer 183. - In the embodiment above-mentioned, a combination of insulating films and wiring metallic films is taken as an example of a plurality of thin films to be transferred from a transfer sheet to a wafer. However, provision may be made such that insulating films of two or more different types (for example, silicon nitride films and SOG films) are formed in lamination on a transfer sheet, and that these insulating films of two or more different types are collectively transferred to the
wafer 120. - In the embodiment above-mentioned, a semiconductor wafer is taken as an example of the substrate. A similar process can also be applied for forming a plurality of thin films on any of a variety of substrates to be processed, such as a glass substrate for a liquid-crystal-display-panel, a glass substrate for a plasma-display-panel, a print-circuit board and the like.
- Examples of the metal which forms the metallic wiring film in the embodiments above-mentioned, include copper, aluminum, titan, tungsten and a mixture thereof.
- Examples of the material of the insulating film include an organic insulating film, a low dielectric interlayer insulating film, SOD, SOG and the like.
- In the transfer processing apparatus in
FIG. 8 , thewafer 120 is held by thestationary stage 61 and thetransfer sheet 130 is held by themovable stage 62. However, provision may be made such that thetransfer sheet 130 is held by thestationary stage 61 and thewafer 120 is held by themovable stage 62. - In the transfer processing apparatus in
FIG. 8 , thestationary stage 61 is disposed above themovable stage 62. However, the stationary stage may be disposed under the movable stage. - Provision may be made such that the both stages respectively holding the
wafer 120 and thetransfer member 130, are movable, and that these movable stages are moved toward or away from each other to transfer a plurality of thin films on thetransfer sheet 130 to thewafer 120. - The two stages respectively holding the
wafer 120 and thetransfer sheet 130, are not necessarily disposed opposite to each other in a vertical direction, but may be disposed opposite to each other in a horizontal direction. - Embodiments of the present invention have been discussed in detail, but these embodiments are mere specific examples for clarifying the technical features of the present invention. Therefore, the present invention should not be construed as limited to these specific examples. The spirit and scope of the present invention are limited only by the appended claims.
- This Application corresponds to Japanese Patent Application Serial No. 2001-290719 filed on Sep. 25, 2001 with Japanese Patent Office, and to Japanese Patent Application Serial No. 2001-296037 filed on Sep. 27, 2001 with Japanese Patent Office, the disclosures of which are incorporated herein by reference.
Claims (20)
1-7. (canceled)
8. A method of forming a thin film pattern on a surface of a substrate, comprising the steps of:
forming a thin film pattern on a thin film carrying surface of a transfer member; and
joining the transfer member to a substrate having a film formed on a surface thereof, so as to transfer the thin film pattern from the thin film carrying surface to the substrate,
wherein the thin film pattern is transferred to the substrate so as to embed the thin film pattern in the film formed on the surface of the substrate.
9. (canceled)
10. A method according to claim 8 , wherein the substrate is a substrate on which a wiring pattern or device is formed, and wherein the thin film pattern is a wiring film pattern.
11. (canceled)
12. A method according to claim 8 , further comprising the step of forming a gelatinous film as the film formed on the surface of the substrate, and wherein the thin film pattern is transferred to the substrate so that the thin film pattern is embedded in the gelatinous film formed thereon.
13. A method according to claim 8 , further comprising the steps of forming, on a surface of the transfer member, a recess portion and a projecting portion, and wherein the thin film carrying surface is formed on the projecting portion.
14. A method according to claim 8 , wherein the transfer member has a flat surface and the thin film pattern is formed on a predetermined area of the flat surface.
15. A method according to claim 8 , wherein the thin film pattern is formed by plating.
16-18. (canceled)
19. A thin film forming method of forming a plurality of thin films on a substrate, comprising the steps of:
forming a plurality of thin films on a surface of a transfer member; and
joining, to the substrate, the transfer member having the plurality of thin films formed thereon for collectively transferring the plurality of thin films to the substrate.
20. A method according to claim 19 , wherein there are formed, on the surface of the transfer member, thin films of different types, and said joining step transfers said films to a same layer on the substrate.
21. A method according to claim 19 , wherein there are formed, on the surface of the transfer member, a plurality of thin films, and said joining step transfers said films to different layers on the substrate.
22. A method according to claim 19 , wherein the substrate is a semiconductor substrate.
23. A method according to claim 19 , wherein the substrate is an insulating substrate.
24-28. (canceled)
29. A method according to claim 20 , wherein the thin films of different types include an insulating film and a metal wiring film.
30. A method according to claim 29 , wherein the thin films of different types are comprised in a multi-layer thin film wiring structure which is transferred onto the substrate in the joining step.
31. A method according to claim 21 , wherein the plurality of thin films include insulating films of two or more different types.
32. A method according to claim 21 , wherein the plurality of thin films includes an insulating film and a metal wiring film, comprised in a multi-layer thin film wiring structure which is transferred onto the substrate in the joining step.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/127,381 US20050230035A1 (en) | 2001-09-25 | 2005-05-12 | Thin film forming apparatus and thin film forming method |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001-290719 | 2001-09-25 | ||
JP2001290719A JP2003100664A (en) | 2001-09-25 | 2001-09-25 | Apparatus and method for formation of thin film |
JP2001296037A JP4043010B2 (en) | 2001-09-27 | 2001-09-27 | Thin film forming apparatus and thin film forming method |
JP2001-296037 | 2001-09-27 | ||
US10/216,002 US6926057B2 (en) | 2001-09-25 | 2002-08-08 | Thin film forming apparatus and thin film forming method |
US11/127,381 US20050230035A1 (en) | 2001-09-25 | 2005-05-12 | Thin film forming apparatus and thin film forming method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/216,002 Division US6926057B2 (en) | 2001-09-25 | 2002-08-08 | Thin film forming apparatus and thin film forming method |
Publications (1)
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US20050230035A1 true US20050230035A1 (en) | 2005-10-20 |
Family
ID=26622776
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US10/216,002 Expired - Lifetime US6926057B2 (en) | 2001-09-25 | 2002-08-08 | Thin film forming apparatus and thin film forming method |
US11/127,381 Abandoned US20050230035A1 (en) | 2001-09-25 | 2005-05-12 | Thin film forming apparatus and thin film forming method |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US10/216,002 Expired - Lifetime US6926057B2 (en) | 2001-09-25 | 2002-08-08 | Thin film forming apparatus and thin film forming method |
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US (2) | US6926057B2 (en) |
KR (1) | KR100491244B1 (en) |
TW (1) | TW561549B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102194654A (en) * | 2010-03-03 | 2011-09-21 | 美商豪威科技股份有限公司 | Device and method for forming protective film on mini-camera chip |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004351272A (en) * | 2003-05-27 | 2004-12-16 | Seiko Epson Corp | Method of forming thin film pattern, and method of producing device, optoelectronic device, and electronic component |
JP4813035B2 (en) * | 2004-10-01 | 2011-11-09 | 新光電気工業株式会社 | Manufacturing method of substrate with through electrode |
US7576426B2 (en) * | 2005-04-01 | 2009-08-18 | Skyworks Solutions, Inc. | Wafer level package including a device wafer integrated with a passive component |
JP5443070B2 (en) * | 2009-06-19 | 2014-03-19 | 東京エレクトロン株式会社 | Imprint system |
JP5060517B2 (en) * | 2009-06-24 | 2012-10-31 | 東京エレクトロン株式会社 | Imprint system |
JP2011009362A (en) * | 2009-06-24 | 2011-01-13 | Tokyo Electron Ltd | Imprint system, imprinting method, program, and computer storage medium |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4869767A (en) * | 1985-05-03 | 1989-09-26 | Hallmark Cards, Incorporated | Process for placing single or multiple patterned layers of conductive material on a substrate |
US5013397A (en) * | 1988-03-10 | 1991-05-07 | Yamaha Hatsudoki Kabushiki Kaisha | Printed circuit board and method of preparing same |
US5017255A (en) * | 1989-01-23 | 1991-05-21 | Clyde D. Calhoun | Method of transferring an inorganic image |
US5259926A (en) * | 1991-09-24 | 1993-11-09 | Hitachi, Ltd. | Method of manufacturing a thin-film pattern on a substrate |
US5321210A (en) * | 1991-01-09 | 1994-06-14 | Nec Corporation | Polyimide multilayer wiring board and method of producing same |
US20010044013A1 (en) * | 1994-03-04 | 2001-11-22 | Mcdonough Neil | Thin film transferrable electric components |
US20010051264A1 (en) * | 1993-10-29 | 2001-12-13 | Mieczyslaw H. Mazurek | Pressure-sensitive adhesives having microstructured surfaces |
US20030159644A1 (en) * | 1998-12-04 | 2003-08-28 | Takao Yonehara | Method of manufacturing semiconductor wafer method of using and utilizing the same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US1234567A (en) * | 1915-09-14 | 1917-07-24 | Edward J Quigley | Soft collar. |
US2988487A (en) * | 1957-08-29 | 1961-06-13 | Rutgers Res And Educational Fo | Process of treating keratinaceous material and a keratinase produced thereby |
US5171682A (en) * | 1988-03-31 | 1992-12-15 | North Carolina State University | Purified Bacillus licheniformis PWD-1 keratinase |
US5772905A (en) * | 1995-11-15 | 1998-06-30 | Regents Of The University Of Minnesota | Nanoimprint lithography |
US5687491A (en) * | 1996-01-26 | 1997-11-18 | Atlas Snow-Shoe Company | Snowshoe with contoured footbed |
KR100335070B1 (en) * | 1999-04-21 | 2002-05-03 | 백승준 | Method for forming micro pattern on substrate by using compression patterning technique |
EP1072954A3 (en) | 1999-07-28 | 2002-05-22 | Lucent Technologies Inc. | Lithographic process for device fabrication |
US6517995B1 (en) * | 1999-09-14 | 2003-02-11 | Massachusetts Institute Of Technology | Fabrication of finely featured devices by liquid embossing |
JP3558936B2 (en) | 1999-11-10 | 2004-08-25 | 日本電信電話株式会社 | Thin film forming equipment |
KR100407602B1 (en) * | 2001-04-17 | 2003-12-01 | 주식회사 미뉴타텍 | Method for forming a micro-pattern by using a dewetting phenomenon |
-
2002
- 2002-08-08 US US10/216,002 patent/US6926057B2/en not_active Expired - Lifetime
- 2002-08-17 KR KR10-2002-0048651A patent/KR100491244B1/en active IP Right Grant
- 2002-09-03 TW TW091120023A patent/TW561549B/en not_active IP Right Cessation
-
2005
- 2005-05-12 US US11/127,381 patent/US20050230035A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4869767A (en) * | 1985-05-03 | 1989-09-26 | Hallmark Cards, Incorporated | Process for placing single or multiple patterned layers of conductive material on a substrate |
US5013397A (en) * | 1988-03-10 | 1991-05-07 | Yamaha Hatsudoki Kabushiki Kaisha | Printed circuit board and method of preparing same |
US5017255A (en) * | 1989-01-23 | 1991-05-21 | Clyde D. Calhoun | Method of transferring an inorganic image |
US5321210A (en) * | 1991-01-09 | 1994-06-14 | Nec Corporation | Polyimide multilayer wiring board and method of producing same |
US5426849A (en) * | 1991-01-09 | 1995-06-27 | Nec Corporation | Method of producing a polyimide multilayer wiring board |
US5259926A (en) * | 1991-09-24 | 1993-11-09 | Hitachi, Ltd. | Method of manufacturing a thin-film pattern on a substrate |
US20010051264A1 (en) * | 1993-10-29 | 2001-12-13 | Mieczyslaw H. Mazurek | Pressure-sensitive adhesives having microstructured surfaces |
US20010044013A1 (en) * | 1994-03-04 | 2001-11-22 | Mcdonough Neil | Thin film transferrable electric components |
US20030159644A1 (en) * | 1998-12-04 | 2003-08-28 | Takao Yonehara | Method of manufacturing semiconductor wafer method of using and utilizing the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102194654A (en) * | 2010-03-03 | 2011-09-21 | 美商豪威科技股份有限公司 | Device and method for forming protective film on mini-camera chip |
Also Published As
Publication number | Publication date |
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KR100491244B1 (en) | 2005-05-24 |
KR20030026213A (en) | 2003-03-31 |
TW561549B (en) | 2003-11-11 |
US6926057B2 (en) | 2005-08-09 |
US20030056890A1 (en) | 2003-03-27 |
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