US20050221619A1 - System and method for etching a mask - Google Patents

System and method for etching a mask Download PDF

Info

Publication number
US20050221619A1
US20050221619A1 US11/103,604 US10360405A US2005221619A1 US 20050221619 A1 US20050221619 A1 US 20050221619A1 US 10360405 A US10360405 A US 10360405A US 2005221619 A1 US2005221619 A1 US 2005221619A1
Authority
US
United States
Prior art keywords
etching system
gas
variable parameter
layer
process gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/103,604
Inventor
Hongyu Yue
Asao Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to US11/103,604 priority Critical patent/US20050221619A1/en
Assigned to TOKYO ELECTRON LIMITED reassignment TOKYO ELECTRON LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAMASHITA, ASAO, YUE, HONGYU
Publication of US20050221619A1 publication Critical patent/US20050221619A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes

Definitions

  • the present invention relates to a system and method for etching a mask and, in particular, to a system and method for transferring a pattern from an overlying layer into the mask layer while laterally trimming the pattern in the mask by means of etching.
  • a (dry) plasma etch process can be utilized to remove or etch material along fine lines or within vias or contacts patterned on a silicon substrate.
  • the plasma etch process generally involves positioning a semiconductor substrate with an overlying patterned, protective layer, for example a photoresist layer, in a processing chamber. Once the substrate is positioned within the chamber, an ionizable, dissociative gas mixture is introduced within the chamber at a pre-specified flow rate, while a vacuum pump is throttled to achieve an ambient process pressure.
  • a plasma is formed when a fraction of the gas species present are ionized by electrons heated via the transfer of radio frequency (RF) power either inductively or capacitively, or microwave power using, for example, electron cyclotron resonance (ECR).
  • RF radio frequency
  • ECR electron cyclotron resonance
  • the heated electrons serve to dissociate some species of the ambient gas species and create reactant specie(s) suitable for the exposed surface etch chemistry.
  • substrates are etched by the plasma.
  • the process is adjusted to achieve appropriate conditions, including an appropriate concentration of desirable reactant and ion populations to etch various features (e.g., trenches, vias, contacts, gates, etc.) in the selected regions of the substrate.
  • substrate materials where etching is required include silicon dioxide (SiO 2 ), low-k dielectric materials, poly-silicon, and silicon nitride.
  • etching such features generally comprises the transfer of a pattern formed within an overlying layer to the underlying layer within which the respective features are formed.
  • the overlying layer can, for example, comprise a light-sensitive material such as (negative or positive) photo-resist.
  • a method for performing a one-step mask open process comprises: forming a first layer on a substrate; forming a second layer on the first layer; forming a pattern in the second layer, wherein the pattern includes a feature in the second layer having a first critical dimension; setting a target trim amount for reducing the first critical dimension to a second critical dimension; determining a variable parameter for a process recipe using the target trim amount and a process model relating trim amount data to the variable parameter; and transferring the pattern from the second layer to the first layer using the process recipe, while achieving the second critical dimension of the feature in the first layer.
  • a method of preparing a process model comprises: defining a nominal process recipe for transferring a pattern having a first feature size from an overlying layer to an underlying layer on a substrate, wherein the nominal process recipe comprises a variable process parameter and at least one constant process parameter; accumulating trim amount data as a function of the variable parameter by measuring the trim amount for one or more values of the variable parameter; and curve-fitting the trim amount data as a function of the variable parameter.
  • an etching system comprises: a process chamber; a substrate holder coupled to the process chamber, and configured to support a substrate; a plasma source coupled to the process chamber, and configured to form plasma in the process chamber; a gas injection system coupled to the process chamber, and configured to introduce a process gas to the process chamber; and a controller coupled to at least one of the process chamber, the substrate holder, the plasma source, and the gas injection system, and configured to execute a process recipe in order to transfer a pattern having a feature with a first critical dimension in an overlying layer to an underlying layer on the substrate, while reducing the first critical dimension to a second critical dimension by a target trim amount set by a process model.
  • FIGS. 1A and 1B illustrate a schematic representation of a film stack
  • FIG. 2 shows a simplified schematic diagram of a plasma processing system according to an embodiment of the invention
  • FIG. 3 shows a schematic diagram of a plasma processing system according to another embodiment of the invention.
  • FIG. 4 shows a schematic diagram of a plasma processing system according to another embodiment of the invention.
  • FIG. 5 shows a schematic diagram of a plasma processing system according to another embodiment of the invention.
  • FIG. 6 shows a schematic diagram of a plasma processing system according to another embodiment of the invention.
  • FIG. 7 shows etch rate data as a function of a gas ratio
  • FIG. 8 shows additional etch rate data as a function of the gas ratio
  • FIG. 9 shows a ratio of the etch rate data presented in FIGS. 7 and 8 as a function of the gas ratio
  • FIG. 10 presents the ratio of etch rate and two process models as a function of the gas ratio
  • FIG. 11 presents trim amount data as a function of the gas ratio
  • FIG. 12 presents a process model for relating the trim amount data to the gas ratio
  • FIG. 13 compares the process model of FIG. 12 with a second order polynomial fit and a third order polynomial fit of the trim amount data
  • FIG. 14 illustrates a method of performing a one-step mask open process according to an embodiment of the invention.
  • FIG. 15 illustrates a method of preparing a process model according to an embodiment of the invention.
  • pattern etching comprises the application of a thin layer of light-sensitive material, such as photoresist, to an upper surface of a substrate, that is subsequently patterned in order to provide a mask for transferring this pattern to the underlying thin film during etching.
  • the patterning of the light-sensitive material generally involves exposure by a radiation source through a reticle (and associated optics) of the light-sensitive material using, for example, a micro-lithography system, followed by the removal of the irradiated regions of the light-sensitive material (as in the case of positive photoresist), or non-irradiated regions (as in the case of negative resist) using a developing solvent.
  • multi-layer masks can be implemented for etching features in a thin film.
  • the mask pattern in the overlying mask layer such as the layer of light-sensitive material
  • the underlying mask layer can include an organic thin film, such as an organic anti-reflective coating (ARC, or bottom ARC (BARC)), an inorganic thin film, or a hybrid organic-inorganic thin film.
  • ARC organic anti-reflective coating
  • BARC bottom ARC
  • FIG. 1A illustrates a film stack 11 comprising a substrate 10 having a thin film 12 deposited thereon.
  • the film stack 11 further includes a first layer 14 formed on the thin film 12 , followed by a second layer 16 formed on the first layer 14 .
  • the first layer 14 and the second layer 16 can be formed using spin-on deposition (SOD) techniques, and/or vapor deposition techniques, such as chemical vapor deposition (CVD). Both techniques are well known to those skilled in the art of material deposition.
  • the second layer 16 can include a layer of light-sensitive material, such as photoresist.
  • the second layer 16 can be formed using a track system.
  • the track system can be configured for processing 248 nm resists, 193 nm resists, 157 nm resists, EUV resists, (top/bottom) anti-reflective coatings (TARC/BARC), and top coats.
  • the track system can comprise a Clean Track ACT 8, or ACT 12 resist coating and developing system commercially available from Tokyo Electron Limited (TEL).
  • TEL Tokyo Electron Limited
  • Other systems and methods for forming a photoresist film on a substrate are well known to those skilled in the art of spin-on resist technology.
  • the pattern 20 is transferred to the first layer 14 by etching, such as dry plasma etching.
  • etching such as dry plasma etching.
  • longitudinal etching (as indicated by reference numeral 24 ) completes the pattern transfer
  • lateral etching (as indicated by reference numeral 26 ) trims the feature 21 in the lateral dimension such that the first critical dimension 22 becomes a second critical dimension 28 .
  • the etch process for performing both the longitudinal and lateral etching comprises a one-step process.
  • the process chemistry for the one-step chemistry includes a C x F y containing gas (wherein x, y are integers greater than or equal to unity), and an oxygen containing gas.
  • the C x F y containing gas can include CF 4 , C 2 F 6 , C 3 F 6 , C 4 F 6 , C 4 F 8 , or C 5 F 8 or any combination of two or more thereof.
  • the oxygen containing gas can include O 2 , CO, CO 2 , NO, NO 2 , or N 2 O, or any combination of two or more thereof.
  • the one-step process chemistry can further include an inert gas, such as a Noble gas (e.g., He, Ar, Kr, Xe, or Ne, or any combination of two or more thereof), and/or N 2 .
  • a plasma processing system 1 for performing the one-step etch process is depicted in FIG. 2 comprising a plasma processing chamber 10 , a diagnostic system 12 coupled to the plasma processing chamber 10 , and a controller 14 coupled to the diagnostic system 12 and the plasma processing chamber 10 .
  • the controller 14 is configured to execute a process recipe comprising at least one of the above-identified chemistries (i.e. C x F y containing gas, and oxygen containing gas, etc.) to etch the first mask layer.
  • controller 14 is configured to receive at least one endpoint signal from the diagnostic system 12 and to post-process the at least one endpoint signal in order to accurately determine an endpoint for the process.
  • plasma processing system 1 depicted in FIG. 2 , utilizes a plasma for material processing.
  • Plasma processing system 1 includes an etch chamber.
  • plasma processing system 1 a can comprise plasma processing chamber 10 , substrate holder 20 , upon which a substrate 25 to be processed is affixed, and vacuum pumping system 30 .
  • Substrate 25 can be, for example, a semiconductor substrate, a wafer or a liquid crystal display.
  • Plasma processing chamber 10 can be, for example, configured to facilitate the generation of plasma in processing region 15 adjacent a surface of substrate 25 .
  • An ionizable gas or mixture of gases is introduced via a gas injection system (not shown) and the process pressure is adjusted.
  • a control mechanism (not shown) can be used to throttle the vacuum pumping system 30 .
  • Plasma can be utilized to create materials specific to a pre-determined materials process, and/or to aid the removal of material from the exposed surfaces of substrate 25 .
  • the plasma processing system 1 a can be configured to process 200 mm substrates, 300 mm substrates, or substrates of any size.
  • Substrate 25 can be, for example, affixed to the substrate holder 20 via an electrostatic clamping system.
  • substrate holder 20 can, for example, further include a cooling system including a re-circulating coolant flow that receives heat from substrate holder 20 and transfers heat to a heat exchanger system (not shown), or when heating, transfers heat from the heat exchanger system.
  • gas can, for example, be delivered to the back-side of substrate 25 via a backside gas system to improve the gas-gap thermal conductance between substrate 25 and substrate holder 20 .
  • a backside gas system can be utilized when temperature control of the substrate is required at elevated or reduced temperatures.
  • the backside gas system can comprise a two-zone gas distribution system, wherein the helium gas gap pressure can be independently varied between the center and the edge of substrate 25 .
  • heating/cooling elements such as resistive heating elements, or thermoelectric heaters/coolers can be included in the substrate holder 20 , as well as the chamber wall of the plasma processing chamber 10 and any other component within the plasma processing system 1 a.
  • substrate holder 20 can comprise an electrode through which RF power is coupled to the processing plasma in process space 15 .
  • substrate holder 20 can be electrically biased at a RF voltage via the transmission of RF power from a RF generator 40 through an impedance match network 50 to substrate holder 20 .
  • the RF bias can serve to heat electrons to form and maintain plasma.
  • the system can operate as a reactive ion etch (RIE) reactor, wherein the chamber and an upper gas injection electrode serve as ground surfaces.
  • RIE reactive ion etch
  • a frequency for the RF bias can range from about 0.1 MHz to about 100 MHz.
  • RF systems for plasma processing are well known to those skilled in the art.
  • RF power is applied to the substrate holder electrode at multiple frequencies.
  • impedance match network 50 serves to improve the transfer of RF power to plasma in plasma processing chamber 10 by reducing the reflected power.
  • Match network topologies e.g. L-type, ⁇ -type, T-type, etc.
  • automatic control methods are well known to those skilled in the art.
  • Vacuum pump system 30 can, for example, include a turbo-molecular vacuum pump (TMP) capable of a pumping speed up to about 5000 liters per second (and greater) and a gate valve for throttling the chamber pressure.
  • TMP turbo-molecular vacuum pump
  • a gate valve for throttling the chamber pressure In conventional plasma processing devices utilized for dry plasma etch, about 1000 to about 3000 liter per second TMP is generally employed. TMPs are useful for low pressure processing, typically less than about 50 mTorr. For high pressure processing (i.e., greater than about 100 mTorr), a mechanical booster pump and dry roughing pump can be used.
  • a device for monitoring chamber pressure (not shown) can be coupled to the plasma processing chamber 10 .
  • the pressure measuring device can be, for example, a Type 628B Baratron absolute capacitance manometer commercially available from MKS Instruments, Inc. (Andover, Mass.).
  • Controller 14 comprises a microprocessor, memory, and a digital I/O port capable of generating control voltages sufficient to communicate and activate inputs to plasma processing system 1 a as well as monitor outputs from plasma processing system 1 a .
  • controller 14 can be coupled to and can exchange information with RF generator 40 , impedance match network 50 , the gas injection system (not shown), vacuum pump system 30 , as well as the backside gas delivery system (not shown), the substrate/substrate holder temperature measurement system (not shown), and/or the electrostatic clamping system (not shown).
  • a program stored in the memory can be utilized to activate the inputs to the aforementioned components of plasma processing system 1 a according to a process recipe in order to perform the method of etching a mask layer.
  • controller 14 is a DELL PRECISION WORKSTATION610TM, available from Dell Corporation, Austin, Tex.
  • the diagnostic system 12 can include an optical diagnostic subsystem (not shown).
  • the optical diagnostic subsystem can comprise a detector such as a (silicon) photodiode or a photomultiplier tube (PMT) for measuring the light intensity emitted from the plasma.
  • the diagnostic system 12 can further include an optical filter such as a narrow-band interference filter.
  • the diagnostic system 12 can include at least one of a line CCD (charge coupled device), a CID (charge injection device) array, and a light dispersing device such as a grating or a prism.
  • diagnostic system 12 can include a monochromator (e.g., grating/detector system) for measuring light at a given wavelength, or a spectrometer (e.g., with a rotating grating) for measuring the light spectrum such as, for example, the device described in U.S. Pat. No. 5,888,337.
  • a monochromator e.g., grating/detector system
  • a spectrometer e.g., with a rotating grating
  • the diagnostic system 12 can include a high resolution Optical Emission Spectroscopy (OES) sensor such as from Peak Sensor Systems, or Verity Instruments, Inc.
  • OES Optical Emission Spectroscopy
  • Such an OES sensor has a broad spectrum that spans the ultraviolet (UV), visible (VIS), and near infrared (NIR) light spectrums. The resolution is approximately 1.4 Angstroms, that is, the sensor is capable of collecting 5550 wavelengths from 240 to 1000 nm.
  • the OES sensor can be equipped with high sensitivity miniature fiber optic UV-VIS-NIR spectrometers which are, in turn, integrated with 2048 pixel linear CCD arrays.
  • the spectrometers receive light transmitted through single and bundled optical fibers, where the light output from the optical fibers is dispersed across the line CCD array using a fixed grating. Similar to the configuration described above, light emitting through an optical vacuum window is focused onto the input end of the optical fibers via a convex spherical lens.
  • the plasma processing system 1 b can, for example, be similar to the embodiment of FIG. 2 or 3 and further comprise either a stationary, or mechanically or electrically rotating magnetic field system 60 , in order to potentially increase plasma density and/or improve plasma processing uniformity, in addition to those components described with reference to FIG. 2 and FIG. 3 .
  • controller 14 can be coupled to magnetic field system 60 in order to regulate the speed of rotation and field strength.
  • the design and implementation of a rotating magnetic field is well known to those skilled in the art.
  • the plasma processing system 1 c can, for example, be similar to the embodiment of FIG. 2 or FIG. 3 , and can further comprise an upper electrode 70 to which RF power can be coupled from RF generator 72 through impedance match network 74 .
  • a frequency for the application of RF power to the upper electrode can range from about 0.1 MHz to about 200 MHz.
  • a frequency for the application of power to the lower electrode can range from about 0.1 MHz to about 100 MHz.
  • controller 14 is coupled to RF generator 72 and impedance match network 74 in order to control the application of RF power to upper electrode 70 .
  • the design and implementation of an upper electrode is well known to those skilled in the art.
  • the plasma processing system 1 d can, for example, be similar to the embodiments of FIGS. 2 and 3 , and can further comprise an inductive coil 80 to which RF power is coupled via RF generator 82 through impedance match network 84 .
  • RF power is inductively coupled from inductive coil 80 through dielectric window (not shown) to plasma processing region 45 .
  • a frequency for the application of RF power to the inductive coil 80 can range from about 10 MHz to about 100 MHz.
  • a frequency for the application of power to the chuck electrode can range from about 0.1 MHz to about 100 MHz.
  • a slotted Faraday shield (not shown) can be employed to reduce capacitive coupling between the inductive coil 80 and plasma.
  • controller 14 is coupled to RF generator 82 and impedance match network 84 in order to control the application of power to inductive coil 80 .
  • inductive coil 80 can be a “spiral” coil or “pancake” coil in communication with the plasma processing region 15 from above as in a transformer coupled plasma (TCP) reactor.
  • ICP inductively coupled plasma
  • TCP transformer coupled plasma
  • the plasma can be formed using electron cyclotron resonance (ECR).
  • ECR electron cyclotron resonance
  • the plasma is formed from the launching of a Helicon wave.
  • the plasma is formed from a propagating surface wave.
  • a one-step etch process is performed, whereby longitudinal etching completes the transfer of a pattern from a second layer to a first layer, and lateral etching achieves a target critical dimension (CD) for the feature formed following the etch process.
  • the plasma processing device can comprise various elements, such as described in any of FIGS. 2 through 6 , or combinations thereof.
  • the method of etching comprises a process chemistry having a C x F y containing gas, and an oxygen containing gas.
  • the process chemistry can include CF 4 and O 2 .
  • the process parameter space can comprise a chamber pressure of about 1 to about 1000 mTorr, a CF 4 process gas flow rate ranging from about 5 to about 1000 sccm, an O 2 process gas flow rate ranging from about 5 to about 1000 sccm, an upper electrode (e.g., element 70 in FIG. 5 ) RF bias ranging from about 200 to about 2500 W, and a lower electrode (e.g., element 20 in FIG. 5 ) RF bias ranging from about 10 to about 2500 W.
  • the upper electrode bias frequency can range from about 0.1 MHz to about 200 MHz, e.g., 60 MHz.
  • the lower electrode bias frequency can range from about 0.1 MHz to about 100 MHz, e.g., 2 MHz.
  • a process model is prepared in order to form a relationship between a trim amount (e.g., the difference between the first CD 22 and the second CD 28 ; see FIGS. 1A and 1B ), and an amount of gas.
  • a process recipe is defined, whereby the total process gas flow rate (i.e., CF 4 and O 2 ), the chamber pressure, the RF bias on the upper electrode, the RF bias on the lower electrode, the temperature of the substrate holder, and the temperature of the chamber is maintained constant while the O 2 ratio is varied.
  • the O 2 ratio is the ratio of the amount of O 2 (e.g., molar flow rate of O 2 ), to the total amount of process gas (e.g., molar flow rate of O 2 and molar flow rate of CF 4 ).
  • FIG. 7 presents the longitudinal (or vertical) etch rate as a function of the O 2 ratio.
  • the longitudinal etch rate can be determined by taking the ratio of the known thickness of the first layer 14 , and the time to reach endpoint when etching the first layer 14 .
  • the asterisks (*) represent the data
  • the solid line represents a curve fit (such as a polynomial fit, a power law fit, or an exponential fit) of the data
  • the dashed lines indicate the predicted 95% confidence limits.
  • FIG. 8 presents the lateral etch rate as a function of the O 2 ratio.
  • the longitudinal etch rate can be determined by taking the ratio of the measured trim amount, and the time to reach endpoint when etching the first layer 14 .
  • the asterisks (*) represent the data
  • the solid line represent a curve fit (such as a polynomial fit, a power law fit, or an exponential fit) of the data
  • the dashed lines indicate the predicted 95% confidence limits.
  • FIG. 9 presents a ratio of the lateral etch rate to the longitudinal etch rate.
  • the asterisks (*) represent the data (i.e., from raw data), the solid line represents a curve fit (such as a polynomial fit, a power law fit, or an exponential fit) of the data, and the dashed lines indicate the predicted 95% confidence limits.
  • the expression for the etch rate ratio from the curve fit of the longitudinal etch rate data ( FIG. 7 ), and the lateral etch rate data ( FIG. 8 ) is (x+0.044)/(2.699 x+0.791) (i.e., ERR ⁇ ER2/ER1).
  • FIG. 10 presents the data of FIG. 9 , including the raw data, the curve fit of the etch rate ratio (i.e., data model), and the ratio of the longitudinal and lateral etch rate curve fits (i.e., ER model).
  • trim amount (TA) during the one-step etch process i.e., the difference between the first CD 22 and the second CD 28
  • TA 2OE ER lateral ( ⁇ / ER longitudinal ), (1)
  • the ER-based model compares well with the third order polynomial expression; however, it does not exhibit over-fitting as exhibited by the third order polynomial expression.
  • FIG. 14 illustrates the method for performing a one-step etch process using a flow chart 100 .
  • Flow chart 100 begins in 110 with forming a first layer on a substrate.
  • the first layer can, for example, include an organic layer.
  • a second layer is formed on the first layer.
  • the second layer can, for example, include a layer of light-sensitive material.
  • a pattern is formed in the second layer, wherein the pattern includes a feature in the second layer having a first critical dimension.
  • the pattern can, for example, be formed using micro-lithography.
  • a target trim amount is set for trimming the first critical dimension to a second critical dimension.
  • a variable parameter for a process recipe is determined using the target trim amount and a process model relating trim amount data with the variable parameter.
  • the variable parameter can include an amount of process gas, a chamber pressure, a RF power, a temperature, etc.
  • the amount of gas can include a mass, a number of moles, a mass flow rate, a molar flow rate, a mass fraction, a mole fraction, a partial pressure, or a concentration.
  • the process model can relate the trim amount with a mole fraction, as shown in FIGS. 11 through 13 .
  • the pattern is transferred from the second layer (or overlying layer) into the first layer (or underlying layer) using an etch process according to the process recipe. While transferring the pattern into and through the first layer, the first critical dimension of the feature formed in the second layer is reduced to the second critical dimension as the feature is formed in the first layer.
  • the method includes a flow chart 200 beginning in 210 with defining a nominal process recipe for transferring a pattern having a first feature size from an overlying layer to an underlying layer on a substrate, wherein the nominal process recipe comprises at least one variable parameter and at least one constant parameter.
  • trim amount data is accumulated as a function of the at least one variable parameter by measuring the trim amount for one or more values of the variable parameter.
  • the trim amount data as a function of the variable parameter is curve-fit.

Abstract

A system and method for transferring a pattern from an overlying layer into an underlying layer, while laterally trimming a feature present within the pattern is described. The pattern transfer is performed using an etch process according to a process recipe, wherein at least one variable parameter within the process recipe is adjusted given a target trim amount. The adjustment of the variable parameter is achieved using a process model established for relating trim amount data with the variable parameter.

Description

  • This is a continuation of U.S. patent application Ser. No. 10/813,520, filed Mar. 31, 2004, Issue Fee Paid, which is incorporated herein by reference in its entirety.
  • FIELD OF THE INVENTION
  • The present invention relates to a system and method for etching a mask and, in particular, to a system and method for transferring a pattern from an overlying layer into the mask layer while laterally trimming the pattern in the mask by means of etching.
  • BACKGROUND OF THE INVENTION
  • During semiconductor processing, a (dry) plasma etch process can be utilized to remove or etch material along fine lines or within vias or contacts patterned on a silicon substrate. The plasma etch process generally involves positioning a semiconductor substrate with an overlying patterned, protective layer, for example a photoresist layer, in a processing chamber. Once the substrate is positioned within the chamber, an ionizable, dissociative gas mixture is introduced within the chamber at a pre-specified flow rate, while a vacuum pump is throttled to achieve an ambient process pressure. Thereafter, a plasma is formed when a fraction of the gas species present are ionized by electrons heated via the transfer of radio frequency (RF) power either inductively or capacitively, or microwave power using, for example, electron cyclotron resonance (ECR). Moreover, the heated electrons serve to dissociate some species of the ambient gas species and create reactant specie(s) suitable for the exposed surface etch chemistry.
  • Once the plasma is formed, selected surfaces of the substrate are etched by the plasma. The process is adjusted to achieve appropriate conditions, including an appropriate concentration of desirable reactant and ion populations to etch various features (e.g., trenches, vias, contacts, gates, etc.) in the selected regions of the substrate. Such substrate materials where etching is required include silicon dioxide (SiO2), low-k dielectric materials, poly-silicon, and silicon nitride.
  • During material processing, etching such features generally comprises the transfer of a pattern formed within an overlying layer to the underlying layer within which the respective features are formed. The overlying layer can, for example, comprise a light-sensitive material such as (negative or positive) photo-resist. Once the pattern is transferred from the overlying layer into the underlying layer, the underlying, either by itself or with the overlying layer, can serve as a mask for etching underlying films.
  • SUMMARY OF THE INVENTION
  • In one aspect of the invention, a method for performing a one-step mask open process comprises: forming a first layer on a substrate; forming a second layer on the first layer; forming a pattern in the second layer, wherein the pattern includes a feature in the second layer having a first critical dimension; setting a target trim amount for reducing the first critical dimension to a second critical dimension; determining a variable parameter for a process recipe using the target trim amount and a process model relating trim amount data to the variable parameter; and transferring the pattern from the second layer to the first layer using the process recipe, while achieving the second critical dimension of the feature in the first layer.
  • In another aspect of the invention, a method of preparing a process model comprises: defining a nominal process recipe for transferring a pattern having a first feature size from an overlying layer to an underlying layer on a substrate, wherein the nominal process recipe comprises a variable process parameter and at least one constant process parameter; accumulating trim amount data as a function of the variable parameter by measuring the trim amount for one or more values of the variable parameter; and curve-fitting the trim amount data as a function of the variable parameter.
  • In yet another aspect of the invention, an etching system comprises: a process chamber; a substrate holder coupled to the process chamber, and configured to support a substrate; a plasma source coupled to the process chamber, and configured to form plasma in the process chamber; a gas injection system coupled to the process chamber, and configured to introduce a process gas to the process chamber; and a controller coupled to at least one of the process chamber, the substrate holder, the plasma source, and the gas injection system, and configured to execute a process recipe in order to transfer a pattern having a feature with a first critical dimension in an overlying layer to an underlying layer on the substrate, while reducing the first critical dimension to a second critical dimension by a target trim amount set by a process model.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • In the accompanying drawings:
  • FIGS. 1A and 1B illustrate a schematic representation of a film stack;
  • FIG. 2 shows a simplified schematic diagram of a plasma processing system according to an embodiment of the invention;
  • FIG. 3 shows a schematic diagram of a plasma processing system according to another embodiment of the invention;
  • FIG. 4 shows a schematic diagram of a plasma processing system according to another embodiment of the invention;
  • FIG. 5 shows a schematic diagram of a plasma processing system according to another embodiment of the invention;
  • FIG. 6 shows a schematic diagram of a plasma processing system according to another embodiment of the invention;
  • FIG. 7 shows etch rate data as a function of a gas ratio;
  • FIG. 8 shows additional etch rate data as a function of the gas ratio;
  • FIG. 9 shows a ratio of the etch rate data presented in FIGS. 7 and 8 as a function of the gas ratio;
  • FIG. 10 presents the ratio of etch rate and two process models as a function of the gas ratio;
  • FIG. 11 presents trim amount data as a function of the gas ratio;
  • FIG. 12 presents a process model for relating the trim amount data to the gas ratio;
  • FIG. 13 compares the process model of FIG. 12 with a second order polynomial fit and a third order polynomial fit of the trim amount data;
  • FIG. 14 illustrates a method of performing a one-step mask open process according to an embodiment of the invention; and
  • FIG. 15 illustrates a method of preparing a process model according to an embodiment of the invention.
  • DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS
  • In material processing methodologies, pattern etching comprises the application of a thin layer of light-sensitive material, such as photoresist, to an upper surface of a substrate, that is subsequently patterned in order to provide a mask for transferring this pattern to the underlying thin film during etching. The patterning of the light-sensitive material generally involves exposure by a radiation source through a reticle (and associated optics) of the light-sensitive material using, for example, a micro-lithography system, followed by the removal of the irradiated regions of the light-sensitive material (as in the case of positive photoresist), or non-irradiated regions (as in the case of negative resist) using a developing solvent.
  • Additionally, multi-layer masks can be implemented for etching features in a thin film. For example, when etching features in a thin film using a bilayer mask, the mask pattern in the overlying mask layer, such as the layer of light-sensitive material, is transferred to the underlying mask layer using a separate etch step preceding the main etch step for the thin film. For example, the underlying mask layer can include an organic thin film, such as an organic anti-reflective coating (ARC, or bottom ARC (BARC)), an inorganic thin film, or a hybrid organic-inorganic thin film.
  • In order to reduce the feature size formed in the thin film, the underlying mask layer can be trimmed laterally, while the mask pattern formed in the overlying mask layer is transferred into the underlying mask layer. For instance, FIG. 1A illustrates a film stack 11 comprising a substrate 10 having a thin film 12 deposited thereon. The film stack 11 further includes a first layer 14 formed on the thin film 12, followed by a second layer 16 formed on the first layer 14. The first layer 14 and the second layer 16 can be formed using spin-on deposition (SOD) techniques, and/or vapor deposition techniques, such as chemical vapor deposition (CVD). Both techniques are well known to those skilled in the art of material deposition.
  • The second layer 16 can include a layer of light-sensitive material, such as photoresist. The second layer 16 can be formed using a track system. The track system can be configured for processing 248 nm resists, 193 nm resists, 157 nm resists, EUV resists, (top/bottom) anti-reflective coatings (TARC/BARC), and top coats. For example, the track system can comprise a Clean Track ACT 8, or ACT 12 resist coating and developing system commercially available from Tokyo Electron Limited (TEL). Other systems and methods for forming a photoresist film on a substrate are well known to those skilled in the art of spin-on resist technology. Once the second layer 16 is formed, a pattern 20 can be formed in the second layer 16 using micro-lithography. After developing the irradiated (exposed) second layer 16, a feature 21 remains having a first critical dimension (CD) 22, as indicated in FIG. 1A.
  • Referring now to FIG. 1B, the pattern 20 is transferred to the first layer 14 by etching, such as dry plasma etching. During the etching process, longitudinal etching (as indicated by reference numeral 24) completes the pattern transfer, and lateral etching (as indicated by reference numeral 26) trims the feature 21 in the lateral dimension such that the first critical dimension 22 becomes a second critical dimension 28.
  • The etch process for performing both the longitudinal and lateral etching comprises a one-step process. The process chemistry for the one-step chemistry includes a CxFy containing gas (wherein x, y are integers greater than or equal to unity), and an oxygen containing gas. For example, the CxFy containing gas can include CF4, C2F6, C3F6, C4F6, C4F8, or C5F8 or any combination of two or more thereof. Additionally, for example, the oxygen containing gas can include O2, CO, CO2, NO, NO2, or N2O, or any combination of two or more thereof. Optionally, the one-step process chemistry can further include an inert gas, such as a Noble gas (e.g., He, Ar, Kr, Xe, or Ne, or any combination of two or more thereof), and/or N2.
  • According to one embodiment, a plasma processing system 1 for performing the one-step etch process is depicted in FIG. 2 comprising a plasma processing chamber 10, a diagnostic system 12 coupled to the plasma processing chamber 10, and a controller 14 coupled to the diagnostic system 12 and the plasma processing chamber 10. The controller 14 is configured to execute a process recipe comprising at least one of the above-identified chemistries (i.e. CxFy containing gas, and oxygen containing gas, etc.) to etch the first mask layer. Additionally, controller 14 is configured to receive at least one endpoint signal from the diagnostic system 12 and to post-process the at least one endpoint signal in order to accurately determine an endpoint for the process. In the illustrated embodiment, plasma processing system 1, depicted in FIG. 2, utilizes a plasma for material processing. Plasma processing system 1 includes an etch chamber.
  • According to the embodiment depicted in FIG. 3, plasma processing system 1 a can comprise plasma processing chamber 10, substrate holder 20, upon which a substrate 25 to be processed is affixed, and vacuum pumping system 30. Substrate 25 can be, for example, a semiconductor substrate, a wafer or a liquid crystal display. Plasma processing chamber 10 can be, for example, configured to facilitate the generation of plasma in processing region 15 adjacent a surface of substrate 25. An ionizable gas or mixture of gases is introduced via a gas injection system (not shown) and the process pressure is adjusted. For example, a control mechanism (not shown) can be used to throttle the vacuum pumping system 30. Plasma can be utilized to create materials specific to a pre-determined materials process, and/or to aid the removal of material from the exposed surfaces of substrate 25. The plasma processing system 1 a can be configured to process 200 mm substrates, 300 mm substrates, or substrates of any size.
  • Substrate 25 can be, for example, affixed to the substrate holder 20 via an electrostatic clamping system. Furthermore, substrate holder 20 can, for example, further include a cooling system including a re-circulating coolant flow that receives heat from substrate holder 20 and transfers heat to a heat exchanger system (not shown), or when heating, transfers heat from the heat exchanger system. Moreover, gas can, for example, be delivered to the back-side of substrate 25 via a backside gas system to improve the gas-gap thermal conductance between substrate 25 and substrate holder 20. Such a system can be utilized when temperature control of the substrate is required at elevated or reduced temperatures. For example, the backside gas system can comprise a two-zone gas distribution system, wherein the helium gas gap pressure can be independently varied between the center and the edge of substrate 25. In other embodiments, heating/cooling elements, such as resistive heating elements, or thermoelectric heaters/coolers can be included in the substrate holder 20, as well as the chamber wall of the plasma processing chamber 10 and any other component within the plasma processing system 1 a.
  • In the embodiment shown in FIG. 3, substrate holder 20 can comprise an electrode through which RF power is coupled to the processing plasma in process space 15. For example, substrate holder 20 can be electrically biased at a RF voltage via the transmission of RF power from a RF generator 40 through an impedance match network 50 to substrate holder 20. The RF bias can serve to heat electrons to form and maintain plasma. In this configuration, the system can operate as a reactive ion etch (RIE) reactor, wherein the chamber and an upper gas injection electrode serve as ground surfaces. A frequency for the RF bias can range from about 0.1 MHz to about 100 MHz. RF systems for plasma processing are well known to those skilled in the art.
  • Alternately, RF power is applied to the substrate holder electrode at multiple frequencies. Furthermore, impedance match network 50 serves to improve the transfer of RF power to plasma in plasma processing chamber 10 by reducing the reflected power. Match network topologies (e.g. L-type, π-type, T-type, etc.) and automatic control methods are well known to those skilled in the art.
  • Vacuum pump system 30 can, for example, include a turbo-molecular vacuum pump (TMP) capable of a pumping speed up to about 5000 liters per second (and greater) and a gate valve for throttling the chamber pressure. In conventional plasma processing devices utilized for dry plasma etch, about 1000 to about 3000 liter per second TMP is generally employed. TMPs are useful for low pressure processing, typically less than about 50 mTorr. For high pressure processing (i.e., greater than about 100 mTorr), a mechanical booster pump and dry roughing pump can be used. Furthermore, a device for monitoring chamber pressure (not shown) can be coupled to the plasma processing chamber 10. The pressure measuring device can be, for example, a Type 628B Baratron absolute capacitance manometer commercially available from MKS Instruments, Inc. (Andover, Mass.).
  • Controller 14 comprises a microprocessor, memory, and a digital I/O port capable of generating control voltages sufficient to communicate and activate inputs to plasma processing system 1 a as well as monitor outputs from plasma processing system 1 a. Moreover, controller 14 can be coupled to and can exchange information with RF generator 40, impedance match network 50, the gas injection system (not shown), vacuum pump system 30, as well as the backside gas delivery system (not shown), the substrate/substrate holder temperature measurement system (not shown), and/or the electrostatic clamping system (not shown). For example, a program stored in the memory can be utilized to activate the inputs to the aforementioned components of plasma processing system 1 a according to a process recipe in order to perform the method of etching a mask layer. One example of controller 14 is a DELL PRECISION WORKSTATION610™, available from Dell Corporation, Austin, Tex.
  • The diagnostic system 12 can include an optical diagnostic subsystem (not shown). The optical diagnostic subsystem can comprise a detector such as a (silicon) photodiode or a photomultiplier tube (PMT) for measuring the light intensity emitted from the plasma. The diagnostic system 12 can further include an optical filter such as a narrow-band interference filter. In an alternate embodiment, the diagnostic system 12 can include at least one of a line CCD (charge coupled device), a CID (charge injection device) array, and a light dispersing device such as a grating or a prism. Additionally, diagnostic system 12 can include a monochromator (e.g., grating/detector system) for measuring light at a given wavelength, or a spectrometer (e.g., with a rotating grating) for measuring the light spectrum such as, for example, the device described in U.S. Pat. No. 5,888,337.
  • The diagnostic system 12 can include a high resolution Optical Emission Spectroscopy (OES) sensor such as from Peak Sensor Systems, or Verity Instruments, Inc. Such an OES sensor has a broad spectrum that spans the ultraviolet (UV), visible (VIS), and near infrared (NIR) light spectrums. The resolution is approximately 1.4 Angstroms, that is, the sensor is capable of collecting 5550 wavelengths from 240 to 1000 nm. For example, the OES sensor can be equipped with high sensitivity miniature fiber optic UV-VIS-NIR spectrometers which are, in turn, integrated with 2048 pixel linear CCD arrays.
  • The spectrometers receive light transmitted through single and bundled optical fibers, where the light output from the optical fibers is dispersed across the line CCD array using a fixed grating. Similar to the configuration described above, light emitting through an optical vacuum window is focused onto the input end of the optical fibers via a convex spherical lens. Three spectrometers, each specifically tuned for a given spectral range (UV, VIS and NI R), form a sensor for a process chamber. Each spectrometer includes an independent A/D converter. And lastly, depending upon the sensor utilization, a full emission spectrum can be recorded every 0.1 to 1.0 seconds.
  • In the embodiment shown in FIG. 4, the plasma processing system 1 b can, for example, be similar to the embodiment of FIG. 2 or 3 and further comprise either a stationary, or mechanically or electrically rotating magnetic field system 60, in order to potentially increase plasma density and/or improve plasma processing uniformity, in addition to those components described with reference to FIG. 2 and FIG. 3. Moreover, controller 14 can be coupled to magnetic field system 60 in order to regulate the speed of rotation and field strength. The design and implementation of a rotating magnetic field is well known to those skilled in the art.
  • In the embodiment shown in FIG. 5, the plasma processing system 1 c can, for example, be similar to the embodiment of FIG. 2 or FIG. 3, and can further comprise an upper electrode 70 to which RF power can be coupled from RF generator 72 through impedance match network 74. A frequency for the application of RF power to the upper electrode can range from about 0.1 MHz to about 200 MHz. Additionally, a frequency for the application of power to the lower electrode can range from about 0.1 MHz to about 100 MHz. Moreover, controller 14 is coupled to RF generator 72 and impedance match network 74 in order to control the application of RF power to upper electrode 70. The design and implementation of an upper electrode is well known to those skilled in the art.
  • In the embodiment shown in FIG. 6, the plasma processing system 1 d can, for example, be similar to the embodiments of FIGS. 2 and 3, and can further comprise an inductive coil 80 to which RF power is coupled via RF generator 82 through impedance match network 84. RF power is inductively coupled from inductive coil 80 through dielectric window (not shown) to plasma processing region 45. A frequency for the application of RF power to the inductive coil 80 can range from about 10 MHz to about 100 MHz. Similarly, a frequency for the application of power to the chuck electrode can range from about 0.1 MHz to about 100 MHz. In addition, a slotted Faraday shield (not shown) can be employed to reduce capacitive coupling between the inductive coil 80 and plasma. Moreover, controller 14 is coupled to RF generator 82 and impedance match network 84 in order to control the application of power to inductive coil 80. In an alternate embodiment, inductive coil 80 can be a “spiral” coil or “pancake” coil in communication with the plasma processing region 15 from above as in a transformer coupled plasma (TCP) reactor. The design and implementation of an inductively coupled plasma (ICP) source, or transformer coupled plasma (TCP) source, is well known to those skilled in the art.
  • Alternately, the plasma can be formed using electron cyclotron resonance (ECR). In yet another embodiment, the plasma is formed from the launching of a Helicon wave. In yet another embodiment, the plasma is formed from a propagating surface wave. Each plasma source described above is well known to those skilled in the art.
  • In one embodiment, a one-step etch process is performed, whereby longitudinal etching completes the transfer of a pattern from a second layer to a first layer, and lateral etching achieves a target critical dimension (CD) for the feature formed following the etch process. For example, the plasma processing device can comprise various elements, such as described in any of FIGS. 2 through 6, or combinations thereof.
  • In the one embodiment, the method of etching comprises a process chemistry having a CxFy containing gas, and an oxygen containing gas. For example, the process chemistry can include CF4 and O2. The process parameter space can comprise a chamber pressure of about 1 to about 1000 mTorr, a CF4 process gas flow rate ranging from about 5 to about 1000 sccm, an O2 process gas flow rate ranging from about 5 to about 1000 sccm, an upper electrode (e.g., element 70 in FIG. 5) RF bias ranging from about 200 to about 2500 W, and a lower electrode (e.g., element 20 in FIG. 5) RF bias ranging from about 10 to about 2500 W. Also, the upper electrode bias frequency can range from about 0.1 MHz to about 200 MHz, e.g., 60 MHz. In addition, the lower electrode bias frequency can range from about 0.1 MHz to about 100 MHz, e.g., 2 MHz.
  • In a first example, a process model is prepared in order to form a relationship between a trim amount (e.g., the difference between the first CD 22 and the second CD 28; see FIGS. 1A and 1B), and an amount of gas. For instance, a process recipe is defined, whereby the total process gas flow rate (i.e., CF4 and O2), the chamber pressure, the RF bias on the upper electrode, the RF bias on the lower electrode, the temperature of the substrate holder, and the temperature of the chamber is maintained constant while the O2 ratio is varied. The O2 ratio is the ratio of the amount of O2 (e.g., molar flow rate of O2), to the total amount of process gas (e.g., molar flow rate of O2 and molar flow rate of CF4).
  • FIG. 7 presents the longitudinal (or vertical) etch rate as a function of the O2 ratio. The longitudinal etch rate can be determined by taking the ratio of the known thickness of the first layer 14, and the time to reach endpoint when etching the first layer 14. The asterisks (*) represent the data, the solid line represents a curve fit (such as a polynomial fit, a power law fit, or an exponential fit) of the data, and the dashed lines indicate the predicted 95% confidence limits. The curve fit for the data of FIG. 7 is given by ER1 (etch rate)=3.328 x+0.976 (where x represents the abscissa data).
  • FIG. 8 presents the lateral etch rate as a function of the O2 ratio. The longitudinal etch rate can be determined by taking the ratio of the measured trim amount, and the time to reach endpoint when etching the first layer 14. The asterisks (*) represent the data, the solid line represent a curve fit (such as a polynomial fit, a power law fit, or an exponential fit) of the data, and the dashed lines indicate the predicted 95% confidence limits. The curve fit for the data of FIG. 8 is given by ER2 (etch rate)=1.233x+0.056.
  • FIG. 9 presents a ratio of the lateral etch rate to the longitudinal etch rate. The asterisks (*) represent the data (i.e., from raw data), the solid line represents a curve fit (such as a polynomial fit, a power law fit, or an exponential fit) of the data, and the dashed lines indicate the predicted 95% confidence limits. The curve fit for the data of FIG. 9 is given by ERR (etch rate ratio)=(x+0.035)/(2.999 x+0.685). The expression for the etch rate ratio from the curve fit of the longitudinal etch rate data (FIG. 7), and the lateral etch rate data (FIG. 8) is (x+0.044)/(2.699 x+0.791) (i.e., ERR˜ER2/ER1).
  • FIG. 10 presents the data of FIG. 9, including the raw data, the curve fit of the etch rate ratio (i.e., data model), and the ratio of the longitudinal and lateral etch rate curve fits (i.e., ER model).
  • The trim amount (TA) during the one-step etch process (i.e., the difference between the first CD 22 and the second CD 28) can be given by the following expression
    TA=2OE ERlateral(τ/ER longitudinal),  (1)
      • where OE represents the amount of overetch (e.g., OE=1.1 for a 10% overetch), ERlateral represents the lateral etch rate, ERlongitudinal represents the longitudinal etch rate, and τ represents the thickness of the first layer 14. By inspection of equation (1), the trim amount (TA) is directly proportional to the etch rate ratio (ERR). Now referring to FIG. 11, the trim amount data is presented as a function of the O2 ratio. The asterisks (*) represent the data (i.e., from raw data), the solid line represents a curve fit of the data, and the dashed lines indicate the predicted 95% confidence limits. The curve fit is of the form
        TA=(x+a)/(bx+c),  (2)
      • where a, b, and c are constants. As shown in FIG. 12, extrapolation of the process model outside of the original bounds of the model (e.g., 0.25<O2 ratio<0.4) exhibits an improvement over polynomial fitting, for example. For instance, Table 1 illustrates the curve-fitting statistics for a second order polynomial expression, a third order polynomial expression, and an expression of the form in equation (2) (i.e., ER-based model). The curve-fitting statistics include the prediction R2, the root mean square of the error (RSME), the maximum predicted error, the average predicted error, and the predicted RMSE.
  • As depicted in Table 1 and FIG. 13, the ER-based model compares well with the third order polynomial expression; however, it does not exhibit over-fitting as exhibited by the third order polynomial expression.
  • FIG. 14 illustrates the method for performing a one-step etch process using a flow chart 100. Flow chart 100 begins in 110 with forming a first layer on a substrate. The first layer can, for example, include an organic layer.
    TABLE 1
    Second- Third-order ER-based
    order model model model
    R2 0.9802 0.9953 0.9888
    RMSE 1.1641 0.6331 0.8752
    Max Pred. Err 1.0988 0.7455 0.8987
    Avg. Pred. Err 0.4972 0.4439 0.4023
    Pred. RMSE 0.3812 0.2468 0.2369
  • In 120, a second layer is formed on the first layer. The second layer can, for example, include a layer of light-sensitive material. In 130, a pattern is formed in the second layer, wherein the pattern includes a feature in the second layer having a first critical dimension. The pattern can, for example, be formed using micro-lithography.
  • In 140, a target trim amount is set for trimming the first critical dimension to a second critical dimension. In 150, a variable parameter for a process recipe is determined using the target trim amount and a process model relating trim amount data with the variable parameter. For example, the variable parameter can include an amount of process gas, a chamber pressure, a RF power, a temperature, etc. Additionally, for example, the amount of gas can include a mass, a number of moles, a mass flow rate, a molar flow rate, a mass fraction, a mole fraction, a partial pressure, or a concentration. Additionally, for example, the process model can relate the trim amount with a mole fraction, as shown in FIGS. 11 through 13.
  • In 160, the pattern is transferred from the second layer (or overlying layer) into the first layer (or underlying layer) using an etch process according to the process recipe. While transferring the pattern into and through the first layer, the first critical dimension of the feature formed in the second layer is reduced to the second critical dimension as the feature is formed in the first layer.
  • In an alternate embodiment, following the transfer of the pattern into the first layer, the second critical dimension is measured, and a difference between the first critical dimension and the second critical dimension is determined. The difference is compared with the target trim amount, and an offset (or error) is determined from this comparison. Thereafter, when selecting a new target trim amount for another substrate, following the previously executed substrate, the new target trim amount is adjusted using the offset. For instance, the adjustment can utilize a filter, such as
    x new,a=(1−λ)x new +λy,  (3)
      • where xnew,a is the adjusted new target trim amount, xnew is the new target trim amount, y is the offset, and λ is the filter constant (0<λ<1).
  • Now referring to FIG. 15, a method for preparing a process model is described. The method includes a flow chart 200 beginning in 210 with defining a nominal process recipe for transferring a pattern having a first feature size from an overlying layer to an underlying layer on a substrate, wherein the nominal process recipe comprises at least one variable parameter and at least one constant parameter.
  • In 220, trim amount data is accumulated as a function of the at least one variable parameter by measuring the trim amount for one or more values of the variable parameter. In 230, the trim amount data as a function of the variable parameter is curve-fit. For example, the curve-fit can include an expression of the form y=(x+a)/(bx+c), where a, b, and c are constants, x is the at least one variable parameter and y is the trim amount.
  • Although only certain embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention.

Claims (20)

1. A method of preparing a process model comprising:
defining a nominal process recipe for transferring a pattern having a first feature size from an overlying layer to an underlying layer on a substrate, wherein said nominal process recipe comprises at least one variable parameter and at least one constant parameter;
accumulating trim amount data as a function of said at least one variable parameter by measuring the trim amount for one or more values of said at least one variable parameter; and
curve-fitting said trim amount data as a function of said at least one variable parameter.
2. The method of claim 1, wherein said curve-fitting includes fitting said trim amount data as a function of said variable parameter with an expression of the form y=(x+a)/(bx+c), where a, b, and c are constants, and where x is the at least one variable parameter and y is the trim amount.
3. An etching system comprising:
a process chamber;
a substrate holder coupled to said process chamber, and configured to support a substrate;
a plasma source coupled to said process chamber, and configured to form plasma in said process chamber;
a gas injection system coupled to said process chamber, and configured to introduce a process gas to said process chamber; and
a controller coupled to said process chamber, said substrate holder, said plasma source, or said gas injection system, or any combination of two or more thereof, and configured to execute a process recipe in order to transfer a pattern having a feature with a first critical dimension in an overlying layer to an underlying layer on said substrate, while reducing said first critical dimension to a second critical dimension by a target trim amount set by a process model.
4. The etching system of claim 3, wherein said target trim amount is set by determining a difference between said first critical dimension and said second critical dimension.
5. The etching system of claim 3, wherein said process model relates said target trim amount to a variable parameter in a process recipe.
6. The etching system of claim 5, wherein said variable parameter includes a flow rate of CF4, a flow rate of O2, a chamber pressure, a RF power to an upper electrode, or a RF power to a lower electrode, or any combination of two or more thereof.
7. The etching system of claim 5, wherein said process gas comprises a first process gas and a second process gas, and said variable parameter includes an amount of said first process gas, an amount of said second process gas, a total amount of said first process gas and said second process gas, a chamber pressure, or at least one RF power, or any combination of two or more thereof.
8. The etching system of claim 7, wherein determining said variable parameter includes determining said amount of said first process gas from said process model, and determining said amount of said second process gas from said amount of said first process gas and said total amount of said first process gas and said second process gas.
9. The etching system of claim 3, wherein said process model relates said target trim amount (y) to a variable parameter (x) in a process recipe according to a relationship of the form y=(x+a)/(bx+c), where a, b, and c are constants.
10. The etching system of claim 3, wherein said underlying layer includes a film formed by spin-on deposition and/or vapor deposition.
11. The etching system of claim 3, wherein said underlying layer includes an organic layer.
12. The etching system of claim 3, wherein said overlying layer includes a film formed by spin-on deposition and/or vapor deposition.
13. The etching system of claim 3, wherein said overlying layer includes a layer of light-sensitive material.
14. The etching system of claim 3, wherein said pattern in said overlying layer is formed by micro-lithography.
15. The etching system of claim 3, wherein said substrate holder comprises an electrostatic clamping system.
16. The etching system of claim 3, wherein said plasma source comprises an electrode configured to capacitively couple power to said process gas.
17. The etching system of claim 3, wherein said plasma source comprises a coil configured to inductively couple power to said process gas.
18. The etching system of claim 3, wherein said substrate holder is configured to control a temperature of said substrate.
19. The etching system of claim 3, wherein said process gas comprises a CxFy containing gas (wherein x, y are integers greater than or equal to unity), and an oxygen containing gas.
20. The etching system of claim 19, wherein said CxFy containing gas includes CF4, C2F6, C3F6, C4F6, C4F8, or C5F8 or any combination of two or more thereof, and said oxygen containing gas includes O2, CO, CO2, NO, NO2, or N2O, or any combination of two or more thereof.
US11/103,604 2004-03-31 2005-04-12 System and method for etching a mask Abandoned US20050221619A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/103,604 US20050221619A1 (en) 2004-03-31 2005-04-12 System and method for etching a mask

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/813,570 US6893975B1 (en) 2004-03-31 2004-03-31 System and method for etching a mask
US11/103,604 US20050221619A1 (en) 2004-03-31 2005-04-12 System and method for etching a mask

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/813,570 Continuation US6893975B1 (en) 2004-03-31 2004-03-31 System and method for etching a mask

Publications (1)

Publication Number Publication Date
US20050221619A1 true US20050221619A1 (en) 2005-10-06

Family

ID=34574882

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/813,570 Expired - Lifetime US6893975B1 (en) 2004-03-31 2004-03-31 System and method for etching a mask
US11/103,604 Abandoned US20050221619A1 (en) 2004-03-31 2005-04-12 System and method for etching a mask

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/813,570 Expired - Lifetime US6893975B1 (en) 2004-03-31 2004-03-31 System and method for etching a mask

Country Status (7)

Country Link
US (2) US6893975B1 (en)
EP (1) EP1730769B1 (en)
JP (1) JP2007531054A (en)
KR (1) KR101142709B1 (en)
CN (1) CN100511621C (en)
TW (1) TWI270121B (en)
WO (1) WO2005104217A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060255010A1 (en) * 2005-05-10 2006-11-16 International Business Machines Corporation Method and system for line-dimension control of an etch process
US9779952B2 (en) 2013-08-27 2017-10-03 Tokyo Electron Limited Method for laterally trimming a hardmask
US11675274B2 (en) * 2017-02-24 2023-06-13 Asml Netherlands B.V. Etch bias characterization and method of using the same
DE102014118843B4 (en) 2013-12-26 2024-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method for correcting line break and photoresist edge problems when patterning a three-layer photoresist

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7323417B2 (en) * 2004-09-21 2008-01-29 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US8075732B2 (en) * 2004-11-01 2011-12-13 Cymer, Inc. EUV collector debris management
US7292906B2 (en) * 2004-07-14 2007-11-06 Tokyo Electron Limited Formula-based run-to-run control
US7547504B2 (en) * 2004-09-21 2009-06-16 Molecular Imprints, Inc. Pattern reversal employing thick residual layers
US7205244B2 (en) * 2004-09-21 2007-04-17 Molecular Imprints Patterning substrates employing multi-film layers defining etch-differential interfaces
US7259102B2 (en) * 2005-09-30 2007-08-21 Molecular Imprints, Inc. Etching technique to planarize a multi-layer structure
US7932181B2 (en) * 2006-06-20 2011-04-26 Lam Research Corporation Edge gas injection for critical dimension uniformity improvement
CN101296554B (en) * 2008-06-19 2011-01-26 友达光电股份有限公司 Plasma processing device and electric pole plate thereof
US8039399B2 (en) * 2008-10-09 2011-10-18 Micron Technology, Inc. Methods of forming patterns utilizing lithography and spacers
US8236700B2 (en) * 2009-08-17 2012-08-07 Tokyo Electron Limited Method for patterning an ARC layer using SF6 and a hydrocarbon gas
US8334083B2 (en) 2011-03-22 2012-12-18 Tokyo Electron Limited Etch process for controlling pattern CD and integrity in multi-layer masks
CN105609415B (en) * 2015-12-25 2018-04-03 中国科学院微电子研究所 A kind of lithographic method
KR102576706B1 (en) * 2016-04-15 2023-09-08 삼성전자주식회사 Method of manufacturing semiconductor device
CN109950140B (en) * 2019-04-18 2021-11-05 上海华力微电子有限公司 Method for forming self-aligned double-layer pattern

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926690A (en) * 1997-05-28 1999-07-20 Advanced Micro Devices, Inc. Run-to-run control process for controlling critical dimensions
US20020063110A1 (en) * 2000-11-30 2002-05-30 Cantell Marc W. Etching of hard masks
US20030092281A1 (en) * 2001-11-13 2003-05-15 Chartered Semiconductors Manufactured Limited Method for organic barc and photoresist trimming process
US20030165755A1 (en) * 2002-03-01 2003-09-04 Applied Materials, Inc. Methodology for repeatable post etch CD in a production tool
US20030230551A1 (en) * 2002-06-14 2003-12-18 Akira Kagoshima Etching system and etching method
US6849151B2 (en) * 2002-08-07 2005-02-01 Michael S. Barnes Monitoring substrate processing by detecting reflectively diffracted light
US20050081781A1 (en) * 2003-10-17 2005-04-21 Taiwan Semiconductor Manufacturing Co. Fully dry, Si recess free process for removing high k dielectric layer
US20050085090A1 (en) * 2003-10-21 2005-04-21 Applied Materials, Inc. Method for controlling accuracy and repeatability of an etch process

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0394597A1 (en) * 1989-04-28 1990-10-31 International Business Machines Corporation Follow-up System for Monitoring the Etching Process in an RIE Equipment and its Application to Producing High-resolution and Reproducible Patterns
JP3388986B2 (en) * 1996-03-08 2003-03-24 株式会社東芝 Exposure mask and method of manufacturing the same
KR100881472B1 (en) * 1999-02-04 2009-02-05 어플라이드 머티어리얼스, 인코포레이티드 A method for depositing built-up structures upon a patterned mask surface resting on a predetermined substrate
US6235609B1 (en) * 2000-04-03 2001-05-22 Philips Electronics North America Corp. Method for forming isolation areas with improved isolation oxide
JP3406302B2 (en) * 2001-01-16 2003-05-12 株式会社半導体先端テクノロジーズ Method of forming fine pattern, method of manufacturing semiconductor device, and semiconductor device
US6716570B2 (en) * 2002-05-23 2004-04-06 Institute Of Microelectronics Low temperature resist trimming process

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926690A (en) * 1997-05-28 1999-07-20 Advanced Micro Devices, Inc. Run-to-run control process for controlling critical dimensions
US20020063110A1 (en) * 2000-11-30 2002-05-30 Cantell Marc W. Etching of hard masks
US20030092281A1 (en) * 2001-11-13 2003-05-15 Chartered Semiconductors Manufactured Limited Method for organic barc and photoresist trimming process
US20030165755A1 (en) * 2002-03-01 2003-09-04 Applied Materials, Inc. Methodology for repeatable post etch CD in a production tool
US20030230551A1 (en) * 2002-06-14 2003-12-18 Akira Kagoshima Etching system and etching method
US6849151B2 (en) * 2002-08-07 2005-02-01 Michael S. Barnes Monitoring substrate processing by detecting reflectively diffracted light
US20050081781A1 (en) * 2003-10-17 2005-04-21 Taiwan Semiconductor Manufacturing Co. Fully dry, Si recess free process for removing high k dielectric layer
US20050085090A1 (en) * 2003-10-21 2005-04-21 Applied Materials, Inc. Method for controlling accuracy and repeatability of an etch process

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060255010A1 (en) * 2005-05-10 2006-11-16 International Business Machines Corporation Method and system for line-dimension control of an etch process
WO2006121563A2 (en) * 2005-05-10 2006-11-16 International Business Machines Corporation Method and system for line-dimension control of an etch process
WO2006121563A3 (en) * 2005-05-10 2007-08-23 Ibm Method and system for line-dimension control of an etch process
US7291285B2 (en) * 2005-05-10 2007-11-06 International Business Machines Corporation Method and system for line-dimension control of an etch process
US20080032428A1 (en) * 2005-05-10 2008-02-07 Behm Gary W Method and system for line-dimension control of an etch process
US7700378B2 (en) 2005-05-10 2010-04-20 International Business Machines Corporation Method and system for line-dimension control of an etch process
US9779952B2 (en) 2013-08-27 2017-10-03 Tokyo Electron Limited Method for laterally trimming a hardmask
DE102014118843B4 (en) 2013-12-26 2024-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method for correcting line break and photoresist edge problems when patterning a three-layer photoresist
US11675274B2 (en) * 2017-02-24 2023-06-13 Asml Netherlands B.V. Etch bias characterization and method of using the same

Also Published As

Publication number Publication date
US6893975B1 (en) 2005-05-17
KR20070005921A (en) 2007-01-10
WO2005104217A2 (en) 2005-11-03
WO2005104217A3 (en) 2005-12-29
KR101142709B1 (en) 2012-05-03
JP2007531054A (en) 2007-11-01
CN1906747A (en) 2007-01-31
EP1730769B1 (en) 2016-07-06
CN100511621C (en) 2009-07-08
EP1730769A2 (en) 2006-12-13
TW200537598A (en) 2005-11-16
TWI270121B (en) 2007-01-01

Similar Documents

Publication Publication Date Title
US20050221619A1 (en) System and method for etching a mask
US7279427B2 (en) Damage-free ashing process and system for post low-k etch
US7846645B2 (en) Method and system for reducing line edge roughness during pattern etching
US7531461B2 (en) Process and system for etching doped silicon using SF6-based chemistry
JP4861987B2 (en) Method and system for etching a film stack
WO2005091796A2 (en) Method and system for treating a hard mask to improve etch characteristics
US7465673B2 (en) Method and apparatus for bilayer photoresist dry development
KR100989107B1 (en) Method and apparatus for multilayer photoresist dry development
WO2006025944A1 (en) Method and system for etching a gate stack
US7344991B2 (en) Method and apparatus for multilayer photoresist dry development
US20050136681A1 (en) Method and apparatus for removing photoresist from a substrate
US8048325B2 (en) Method and apparatus for multilayer photoresist dry development
US7767926B2 (en) Method and system for dry development of a multi-layer mask using sidewall passivation and mask passivation
US20050136666A1 (en) Method and apparatus for etching an organic layer
US20070056927A1 (en) Process and system for etching doped silicon

Legal Events

Date Code Title Description
AS Assignment

Owner name: TOKYO ELECTRON LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YUE, HONGYU;YAMASHITA, ASAO;REEL/FRAME:016467/0006;SIGNING DATES FROM 20040414 TO 20040420

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION