US20050218457A1 - MOSFET for an open-drain circuit and semiconductor integrated circuit device employing it - Google Patents
MOSFET for an open-drain circuit and semiconductor integrated circuit device employing it Download PDFInfo
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- US20050218457A1 US20050218457A1 US11/135,672 US13567205A US2005218457A1 US 20050218457 A1 US20050218457 A1 US 20050218457A1 US 13567205 A US13567205 A US 13567205A US 2005218457 A1 US2005218457 A1 US 2005218457A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims abstract description 47
- 239000012535 impurity Substances 0.000 claims abstract description 42
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 27
- 230000003068 static effect Effects 0.000 abstract description 18
- 239000000758 substrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
- H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
Definitions
- the present invention relates to the structure of a MOSFET (metal-oxide semiconductor field-effect transistor) for an open-drain circuit, and to a semiconductor integrated circuit device employing such a MOSFET. More particularly, the present invention relates to an improvement on the withstand voltage of a MOSFET for an open-drain circuit.
- MOSFET metal-oxide semiconductor field-effect transistor
- an open-drain output circuit as shown in FIG. 4 has been widely used as the output circuit of a semiconductor integrated circuit device.
- An input terminal 101 is connected to the gate of an N-channel MOSFET (hereinafter referred to as the “NMOS”) for an open-drain circuit.
- the drain of the NMOS 102 is connected to an output terminal 103 , and the source of the NMOS 102 is connected to ground.
- To the input terminal 101 of the output circuit is fed, for example, a signal output from a CMOS (complementary metal-oxide semiconductor) logic circuit provided in the semiconductor integrated circuit device.
- CMOS complementary metal-oxide semiconductor
- the NMOS 102 when a high-level signal is fed to the input terminal 101 , the NMOS 102 turns on, turning the output terminal 103 to a low level. On the other hand, when a low-level signal is fed to the input terminal 101 , the NMOS 102 turns off, bringing the output terminal 103 into an electrically floating state (a high-impedance state). At the drain, a parasitic diode Di is formed.
- an abnormal static electric charge may be applied to the output terminal 103 for some reason or other.
- a negative static electric charge is readily discharged by way of the parasitic diode Di, there is no route by way of which to discharge a positive static electric charge.
- the NMOS 102 is liable to be destroyed between its drain and gate or between its drain and source.
- FIG. 5 is a sectional view schematically showing the conventional NMOS structure used as the NMOS 102 .
- the conventional NMOS structure is formed in a device-forming region between field oxide films (LOCOS) 2 a and 2 b on a P-type semiconductor substrate 1 such as a silicon substrate.
- LOC field oxide films
- high-concentration N-type impurity diffusion regions (source regions 3 a and 3 b and a drain region 4 ) are formed. Between the field oxide films 2 a and 2 b and the source regions 3 a and 3 b , high-concentration P-type impurity diffusion regions 5 a and 5 b are formed.
- low-concentration N-type impurity diffusion regions 6 a and 6 b are formed, with a LOCOS 7 a formed on top of the low-concentration N-type impurity diffusion region 6 a and a LOCOS 7 b formed on the low-concentration N-type impurity diffusion region 6 b .
- gate insulating films 8 a and 8 b are formed, with polysilicon films formed as gate electrodes 9 a and 9 b on top of the gate insulating films 8 a and 8 b .
- the drain region 4 is connected to a drain lead electrode D.
- the gate electrodes 9 a and 9 b are connected to a gate lead electrode G.
- the source regions 3 a and 3 b are connected to a source lead electrode S.
- the high-concentration P-type impurity diffusion regions 5 a and 5 b are connected to a backgate lead electrode BG.
- parasitic resistance components R 1 ′ and R 2 ′ are formed respectively.
- Parasitic resistance components are formed also in the high-concentration regions constituting the drain and source, but these are not illustrated, because their resistances are low as compared with that of the parasitic resistance component R 1 ′.
- FIG. 6 shows the equivalent circuit of a conventionally structured MOSFET in its state in which the source lead electrode S and the backgate lead electrode BG are kept at an equal potential.
- the drain lead electrode D is connected through the parasitic resistor R 1 ′ to the drain of the MOSFET 16 and to the collector of an NPN-type parasitic transistor Q 1 .
- the base of the parasitic transistor Q 1 is connected to one end of the parasitic resistor R 2 ′.
- the source of the MOSFET 16 , the emitter of the parasitic transistor Q 1 , and the other end of the parasitic resistor R 2 ′ are connected to the source lead electrode S and to the backgate lead electrode BG.
- Japanese Patent Registered No. 3204168 discloses an invention relating to a semiconductor integrated circuit that can alleviate the lowering of the on-state withstand voltage of a transistor.
- this publication discloses nothing about the static withstand voltage of a MOSFET for an open-drain circuit.
- An object of the present invention is to provide an N-channel MOSFET for an open-drain circuit which has a high static withstand voltage, and to provide a semiconductor integrated circuit device employing such a MOSFET.
- an open-drain N-channel MOSFET is provided with a drain region formed of an N-type semiconductor layer, a P-type impurity diffusion layer formed within the drain region, two high-concentration N-type impurity diffusion layers formed within the drain region so as to sandwich the P-type impurity diffusion layer, and a drain electrode connected to the P-type impurity diffusion layer and to the two high-concentration N-type impurity diffusion layers.
- a semiconductor integrated circuit device is provided with an output circuit incorporating an open-drain N-channel MOSFET structured as described above, with the drain of the MOSFET connected to the output terminal of the output circuit.
- the peripheral portion of the drain region and the peripheral portion of the source region may each be given, as seen in a plan view, a substantially circular shape or a substantially regular-polygonal shape with four or more sides, with the gates formed in a net-like pattern.
- FIG. 1 is a diagram showing the structure of an open-drain N-channel MOSFET according to the invention
- FIG. 2 is a diagram showing the equivalent circuit of the open-drain N-channel MOSFET of the invention shown in FIG. 1 ;
- FIG. 3A is a diagram showing a layout with low area efficiency for an open-drain N-channel MOSFET
- FIG. 3B is a diagram showing a layout with high area efficiency for an open-drain N-channel MOSFET
- FIG. 4 is a diagram showing the configuration of an open-drain output circuit
- FIG. 5 is a sectional view schematically showing the structure of a conventional MOSFET.
- FIG. 6 is a diagram showing the equivalent circuit of the conventionally structured MOSFET shown in FIG. 5 .
- FIG. 1 shows the structure of an N-channel MOSFET for an open-drain circuit according to the invention.
- FIG. 1 such circuit elements as are found in FIG. 5 are identified with the same reference symbols.
- the open-drain N-channel MOSFET according to the invention is formed in a device-forming region between field oxide films 2 a and 2 b on a P-type semiconductor substrate 1 such as a silicon substrate.
- the P-type semiconductor substrate 1 may be replaced with a P well.
- an N-type well 11 is formed, and high-concentration N-type impurity diffusion regions are formed as source regions 3 a and 3 b . Between the field oxide films 2 a and 2 b and the source regions 3 a and 3 b , high-concentration P-type impurity diffusion regions 5 a and 5 b are formed.
- a high-concentration P-type impurity diffusion region 12 is formed, and two high-concentration N-type impurity diffusion regions 13 and 14 are formed so as to sandwich the high-concentration P-type impurity diffusion region 12 .
- a drain electrode 15 is formed on top of a region covering the high-concentration P-type impurity diffusion region 12 and parts of the high-concentration N-type impurity diffusion regions 13 and 14 . Contiguous with the high-concentration N-type impurity diffusion regions 13 and 14 formed in the N well 11 , low-concentration N-type impurity diffusion regions 6 a and 6 b are formed so as to bridge from the N well 11 to the P-sub region. A LOCOS 7 a is formed on top of the low-concentration N-type impurity diffusion region 6 a , and a LOCOS 7 b is formed on the low-concentration N-type impurity diffusion region 6 b .
- gate insulating films 8 a and 8 b are formed, with polysilicon or aluminum films formed as gate electrodes 9 a and 9 b on top of the gate insulating films 8 a and 8 b .
- the drain electrode 14 is connected to a drain lead electrode D.
- the gate electrodes 9 a and 9 b are connected to a gate lead electrode G.
- the source regions 3 a and 3 b are connected to a source lead electrode S.
- the high-concentration P-type impurity diffusion regions 5 a and 5 b are connected to a backgate lead electrode BG.
- parasitic resistance components R 1 and R 2 are formed respectively.
- FIG. 2 shows the equivalent circuit of the open-drain N-channel MOSFET of the invention in its state in which the source lead electrode S and the backgate lead electrode BG are kept at an equal potential.
- FIG. 2 such circuit elements as are found in FIG. 6 are identified with the same reference symbols.
- the drain lead electrode D is connected through the parasitic resistor R 1 to the drain of the MOSFET 16 , to the collector of an NPN-type parasitic transistor Q 1 , and to the base of a PNP-type parasitic transistor Q 2 .
- the node between the drain lead electrode D and the parasitic resistor R 1 is connected to the emitter of the parasitic transistor Q 2 .
- the base of the parasitic transistor Q 1 is connected to one end of the parasitic resistor R 2 .
- the node between the base of the parasitic transistor Q 1 and the parasitic resistor R 2 is connected to the collector of the parasitic transistor Q 2 .
- the source of the MOSFET 16 , the emitter of the parasitic transistor Q 1 , and the other end of the parasitic resistor R 2 are connected to the source lead electrode S and to the backgate lead electrode BG.
- the open-drain N-channel MOSFET of the invention shown in FIG. 1 only when a positive static electric charge is applied to the drain lead electrode D and thus the potential difference between the drain lead electrode D and the source lead electrode S is great, the parasitic transistor Q 2 turns on and a current flows through it, forming a route by way of which the static electric charge is discharged.
- the open-drain N-channel MOSFET of the invention has a satisfactorily high static withstand voltage, specifically as high as ⁇ 4000 V as measured under the HBM condition, or ⁇ 400 V as measured under the MM condition.
- open-drain N-channel MOSFET shown in FIG. 1 it is advisable to use in a semiconductor integrated circuit device incorporating an open-drain output circuit (for example, the output circuit shown in FIG. 4 ). This helps improve the static withstand voltage of the open-drain MOSFET, and thus helps enhance the reliability of the semiconductor integrated circuit device.
- the open-drain N-channel MOSFET shown in FIG. 1 requires a large drain area. Therefore, in a semiconductor integrated circuit device incorporating a plurality of open-drain output circuits employing the open-drain N-channel MOSFET shown in FIG. 1 , it is preferable to adopt, as the layout of the open-drain N-channel MOSFET, a layout with high area efficiency as shown in a schematic plan view in FIG. 3B rather than a layout with low area efficiency as shown in a schematic plan view in FIG. 3A . Adopting the layout with high area efficiency shown in a schematic plan view in FIG. 3B helps reduce the size and cost of the semiconductor integrated circuit device. In FIGS.
- the distance from the gate to the drain is made greater than that from the source contact to the gate.
- high-concentration P-type diffusion regions and high-concentration N-type diffusion regions are arranged alternately as the drain.
- FIG. 3A the layout shown in FIG.
- the backgate is located in an outermost portion of the MOSFET.
- the drain and source are each arranged in a pattern like the teeth of a comb.
- the drain and source are given different shapes (whereas the former is substantially square, the latter is substantially regular hexagonal). Giving the drain and source different shapes in this way helps further increase the area efficiency.
- the backgate is located uniformly within the transistor.
- the gates are laid in a net-like pattern (with the drain and source located at the eyes of the net).
Abstract
In a conventional N-channel MOSFET for an open-drain circuit, when a positive static electric charge is applied to its drain, there is no route by way of which to discharge the static electric charge, resulting in a rather low static withstand voltage. To overcome this, according to the invention, an open-drain N-channel MOSFET has a drain region formed of an N-type semiconductor layer, a P-type impurity diffusion layer formed within the drain region, two high-concentration N-type impurity diffusion layers formed within the drain region so as to sandwich the P-type impurity diffusion layer, and a drain electrode connected to the P-type impurity diffusion layer and to the two high-concentration N-type impurity diffusion layers. When a positive static electric charge is applied to the drain, a parasitic transistor appears that forms a route by way of which the static electric charge is discharged.
Description
- This application is based on Japanese Patent Application No. 2002-370525 filed on Dec. 20, 2002, the contents of which are hereby incorporated by reference.
- 1. Field of the Invention
- The present invention relates to the structure of a MOSFET (metal-oxide semiconductor field-effect transistor) for an open-drain circuit, and to a semiconductor integrated circuit device employing such a MOSFET. More particularly, the present invention relates to an improvement on the withstand voltage of a MOSFET for an open-drain circuit.
- 2. Description of the Prior Art
- Conventionally, an open-drain output circuit as shown in
FIG. 4 has been widely used as the output circuit of a semiconductor integrated circuit device. Aninput terminal 101 is connected to the gate of an N-channel MOSFET (hereinafter referred to as the “NMOS”) for an open-drain circuit. The drain of theNMOS 102 is connected to anoutput terminal 103, and the source of theNMOS 102 is connected to ground. To theinput terminal 101 of the output circuit is fed, for example, a signal output from a CMOS (complementary metal-oxide semiconductor) logic circuit provided in the semiconductor integrated circuit device. - In the open-drain output circuit shown in
FIG. 4 , when a high-level signal is fed to theinput terminal 101, theNMOS 102 turns on, turning theoutput terminal 103 to a low level. On the other hand, when a low-level signal is fed to theinput terminal 101, the NMOS 102 turns off, bringing theoutput terminal 103 into an electrically floating state (a high-impedance state). At the drain, a parasitic diode Di is formed. - In a non-operating state, (i.e., when the
NMOS 102 is off), an abnormal static electric charge may be applied to theoutput terminal 103 for some reason or other. In the open-drain output circuit shown inFIG. 4 , while a negative static electric charge is readily discharged by way of the parasitic diode Di, there is no route by way of which to discharge a positive static electric charge. As a result, when a static electric charge higher than the gate withstand voltage or drain-source withstand voltage of theNMOS 102 is applied to theoutput terminal 103, theNMOS 102 is liable to be destroyed between its drain and gate or between its drain and source. -
FIG. 5 is a sectional view schematically showing the conventional NMOS structure used as theNMOS 102. The conventional NMOS structure is formed in a device-forming region between field oxide films (LOCOS) 2 a and 2 b on a P-type semiconductor substrate 1 such as a silicon substrate. - On the P-
type semiconductor substrate 1, high-concentration N-type impurity diffusion regions (source regions field oxide films source regions impurity diffusion regions source regions drain region 4, contiguous with thedrain region 4, low-concentration N-typeimpurity diffusion regions LOCOS 7 a formed on top of the low-concentration N-typeimpurity diffusion region 6 a and aLOCOS 7 b formed on the low-concentration N-typeimpurity diffusion region 6 b. On top of the channel regions between thesource regions impurity diffusion regions gate insulating films gate electrodes gate insulating films drain region 4 is connected to a drain lead electrode D. Thegate electrodes source regions impurity diffusion regions -
FIG. 6 shows the equivalent circuit of a conventionally structured MOSFET in its state in which the source lead electrode S and the backgate lead electrode BG are kept at an equal potential. InFIG. 6 , such circuit elements as are found inFIG. 5 are identified with the same reference symbols. The drain lead electrode D is connected through the parasitic resistor R1′ to the drain of theMOSFET 16 and to the collector of an NPN-type parasitic transistor Q1. The base of the parasitic transistor Q1 is connected to one end of the parasitic resistor R2′. The source of theMOSFET 16, the emitter of the parasitic transistor Q1, and the other end of the parasitic resistor R2′ are connected to the source lead electrode S and to the backgate lead electrode BG. - In the conventionally structured NMOS shown in
FIG. 5 , when a positive static electric charge is applied to the drain lead electrode D, theNMOS 16 and the parasitic transistor Q1 both remain off (seeFIG. 6 ), and therefore there is no route by way of which to discharge the static electric charge. This makes the static withstand voltage of the conventionally structured NMOS rather low, specifically as low as +300 V to +600 V as measured under the HBM (human body model) condition, or +150 V to +250 V as measured under the MM (machine model) condition. - Incidentally, Japanese Patent Registered No. 3204168 discloses an invention relating to a semiconductor integrated circuit that can alleviate the lowering of the on-state withstand voltage of a transistor. However, this publication discloses nothing about the static withstand voltage of a MOSFET for an open-drain circuit.
- An object of the present invention is to provide an N-channel MOSFET for an open-drain circuit which has a high static withstand voltage, and to provide a semiconductor integrated circuit device employing such a MOSFET.
- To achieve the above object, according to one aspect of the present invention, an open-drain N-channel MOSFET is provided with a drain region formed of an N-type semiconductor layer, a P-type impurity diffusion layer formed within the drain region, two high-concentration N-type impurity diffusion layers formed within the drain region so as to sandwich the P-type impurity diffusion layer, and a drain electrode connected to the P-type impurity diffusion layer and to the two high-concentration N-type impurity diffusion layers.
- According to another aspect of the present invention, a semiconductor integrated circuit device is provided with an output circuit incorporating an open-drain N-channel MOSFET structured as described above, with the drain of the MOSFET connected to the output terminal of the output circuit. In a case where the semiconductor integrated circuit device incorporates a plurality of such output circuits, in the open-drain N-channel MOSFET structured as described above, the peripheral portion of the drain region and the peripheral portion of the source region may each be given, as seen in a plan view, a substantially circular shape or a substantially regular-polygonal shape with four or more sides, with the gates formed in a net-like pattern.
- This and other objects and features of the present invention will become clear from the following description, taken in conjunction with the preferred embodiments with reference to the accompanying drawings in which:
-
FIG. 1 is a diagram showing the structure of an open-drain N-channel MOSFET according to the invention; -
FIG. 2 is a diagram showing the equivalent circuit of the open-drain N-channel MOSFET of the invention shown inFIG. 1 ; -
FIG. 3A is a diagram showing a layout with low area efficiency for an open-drain N-channel MOSFET; -
FIG. 3B is a diagram showing a layout with high area efficiency for an open-drain N-channel MOSFET; -
FIG. 4 is a diagram showing the configuration of an open-drain output circuit; -
FIG. 5 is a sectional view schematically showing the structure of a conventional MOSFET; and -
FIG. 6 is a diagram showing the equivalent circuit of the conventionally structured MOSFET shown inFIG. 5 . -
FIG. 1 shows the structure of an N-channel MOSFET for an open-drain circuit according to the invention. InFIG. 1 , such circuit elements as are found inFIG. 5 are identified with the same reference symbols. - The open-drain N-channel MOSFET according to the invention is formed in a device-forming region between
field oxide films type semiconductor substrate 1 such as a silicon substrate. The P-type semiconductor substrate 1 may be replaced with a P well. - On the P-
type semiconductor substrate 1, an N-type well 11 is formed, and high-concentration N-type impurity diffusion regions are formed assource regions field oxide films source regions impurity diffusion regions N well 11, a high-concentration P-typeimpurity diffusion region 12 is formed, and two high-concentration N-typeimpurity diffusion regions 13 and 14 are formed so as to sandwich the high-concentration P-typeimpurity diffusion region 12. On top of a region covering the high-concentration P-typeimpurity diffusion region 12 and parts of the high-concentration N-typeimpurity diffusion regions 13 and 14, adrain electrode 15 is formed. Contiguous with the high-concentration N-typeimpurity diffusion regions 13 and 14 formed in the N well 11, low-concentration N-typeimpurity diffusion regions LOCOS 7 a is formed on top of the low-concentration N-typeimpurity diffusion region 6 a, and aLOCOS 7 b is formed on the low-concentration N-typeimpurity diffusion region 6 b. On top of the channel regions between thesource regions impurity diffusion regions gate insulating films gate electrodes gate insulating films gate electrodes source regions impurity diffusion regions -
FIG. 2 shows the equivalent circuit of the open-drain N-channel MOSFET of the invention in its state in which the source lead electrode S and the backgate lead electrode BG are kept at an equal potential. InFIG. 2 , such circuit elements as are found inFIG. 6 are identified with the same reference symbols. The drain lead electrode D is connected through the parasitic resistor R1 to the drain of theMOSFET 16, to the collector of an NPN-type parasitic transistor Q1, and to the base of a PNP-type parasitic transistor Q2. The node between the drain lead electrode D and the parasitic resistor R1 is connected to the emitter of the parasitic transistor Q2. The base of the parasitic transistor Q1 is connected to one end of the parasitic resistor R2. The node between the base of the parasitic transistor Q1 and the parasitic resistor R2 is connected to the collector of the parasitic transistor Q2. The source of theMOSFET 16, the emitter of the parasitic transistor Q1, and the other end of the parasitic resistor R2 are connected to the source lead electrode S and to the backgate lead electrode BG. - In the open-drain N-channel MOSFET of the invention shown in
FIG. 1 , only when a positive static electric charge is applied to the drain lead electrode D and thus the potential difference between the drain lead electrode D and the source lead electrode S is great, the parasitic transistor Q2 turns on and a current flows through it, forming a route by way of which the static electric charge is discharged. As a result, as compared with the conventionally structured MOSFET shown inFIG. 5 , the open-drain N-channel MOSFET of the invention has a satisfactorily high static withstand voltage, specifically as high as ±4000 V as measured under the HBM condition, or ±400 V as measured under the MM condition. - It is advisable to use the open-drain N-channel MOSFET shown in
FIG. 1 in a semiconductor integrated circuit device incorporating an open-drain output circuit (for example, the output circuit shown inFIG. 4 ). This helps improve the static withstand voltage of the open-drain MOSFET, and thus helps enhance the reliability of the semiconductor integrated circuit device. - The open-drain N-channel MOSFET shown in
FIG. 1 requires a large drain area. Therefore, in a semiconductor integrated circuit device incorporating a plurality of open-drain output circuits employing the open-drain N-channel MOSFET shown inFIG. 1 , it is preferable to adopt, as the layout of the open-drain N-channel MOSFET, a layout with high area efficiency as shown in a schematic plan view inFIG. 3B rather than a layout with low area efficiency as shown in a schematic plan view inFIG. 3A . Adopting the layout with high area efficiency shown in a schematic plan view inFIG. 3B helps reduce the size and cost of the semiconductor integrated circuit device. InFIGS. 3A and 3B , the following reference numerals are used: 20 represents a drain conductor; 21 represents a locos; 22 represents a drain; 23 represents a contact; 24 represents a high-concentration P-type diffusion region; 25 represents a high-concentration N-type diffusion region; 26 represents a high-concentration P-type diffusion region; 27 represents a source/backgate conductor; and 28 represents a gate conductor. In the layout shown inFIG. 3A , the distance from the gate to the drain is made greater than that from the source contact to the gate. Moreover, in the layout shown inFIG. 3A , high-concentration P-type diffusion regions and high-concentration N-type diffusion regions are arranged alternately as the drain. Moreover, in the layout shown inFIG. 3A , the backgate is located in an outermost portion of the MOSFET. By contrast, in the layout shown inFIG. 3B , the drain and source are each arranged in a pattern like the teeth of a comb. Moreover, in the layout shown inFIG. 3B , the drain and source are given different shapes (whereas the former is substantially square, the latter is substantially regular hexagonal). Giving the drain and source different shapes in this way helps further increase the area efficiency. Moreover, in the layout shown inFIG. 3B , the backgate is located uniformly within the transistor. Moreover, in the layout shown inFIG. 3B , the gates are laid in a net-like pattern (with the drain and source located at the eyes of the net).
Claims (4)
1-4. (canceled)
5. A semiconductor integrated circuit device, comprising:
an output circuit,
wherein the output circuit comprises:
an open-drain N-channel MOSFET; and
an output terminal connected to a drain of the open-drain N-channel MOSFET,
wherein the open-drain N-channel MOSFET comprises:
a drain region formed of an N-type semiconductor layer;
a P-type impurity diffusion layer formed within the drain region;
two high-concentration N-type impurity diffusion layers formed within the drain region so as to sandwich the P-type impurity diffusion layer;
a low-concentration N-type impurity diffusion region formed in contact with the drain region; and
a drain electrode connected to the P-type impurity diffusion layer and to the two high-concentration N-type impurity diffusion layers,
wherein there are provided a plurality of the output circuit,
wherein the drain region and a source region of the open-drain N-channel MOSFET are formed in a pattern like teeth of a comb
wherein the source region and a backgate region are arranged on both sides of the drain region
wherein the output circuit includes a circuit that outputs a signal to the gate of the open drain N-channel MOSFET.
6. A semiconductor integrated circuit device, comprising:
an output circuit,
wherein the output circuit comprises:
an open-drain N-channel MOSFET; and
an output terminal connected to a drain of the open-drain N-channel MOSFET,
wherein the open-drain N-channel MOSFET comprises:
a drain region formed of an N-type semiconductor layer;
a P-type impurity diffusion layer formed within the drain region;
two high-concentration N-type impurity diffusion layers formed within the drain region so as to sandwich the P-type impurity diffusion layer;
a low-concentration N-type impurity diffusion region formed in contact with the drain region; and
a drain electrode connected to the P-type impurity diffusion layer and to the two high-concentration N-type impurity diffusion layers,
wherein there are provided a plurality of the output circuit,
wherein a peripheral portion of the drain region of the open-drain N-channel MOSFET and a peripheral portion of a source region of the open-drain N-channel MOSFET have, as seen in a plan view, different shapes
wherein the output circuit includes a circuit that outputs a signal to the gate of the open drain N-channel MOSFET.
7. (canceled)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/135,672 US20050218457A1 (en) | 2002-12-20 | 2005-05-24 | MOSFET for an open-drain circuit and semiconductor integrated circuit device employing it |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002-370525 | 2002-12-20 | ||
JP2002370525A JP3753692B2 (en) | 2002-12-20 | 2002-12-20 | Open drain MOSFET and semiconductor integrated circuit device using the same |
US10/730,995 US6953969B2 (en) | 2002-12-20 | 2003-12-10 | MOSFET for an open-drain circuit and semiconductor integrated circuit device employing it |
US11/135,672 US20050218457A1 (en) | 2002-12-20 | 2005-05-24 | MOSFET for an open-drain circuit and semiconductor integrated circuit device employing it |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/730,995 Continuation US6953969B2 (en) | 2002-12-20 | 2003-12-10 | MOSFET for an open-drain circuit and semiconductor integrated circuit device employing it |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050218457A1 true US20050218457A1 (en) | 2005-10-06 |
Family
ID=32588400
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/730,995 Expired - Fee Related US6953969B2 (en) | 2002-12-20 | 2003-12-10 | MOSFET for an open-drain circuit and semiconductor integrated circuit device employing it |
US11/135,672 Abandoned US20050218457A1 (en) | 2002-12-20 | 2005-05-24 | MOSFET for an open-drain circuit and semiconductor integrated circuit device employing it |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/730,995 Expired - Fee Related US6953969B2 (en) | 2002-12-20 | 2003-12-10 | MOSFET for an open-drain circuit and semiconductor integrated circuit device employing it |
Country Status (5)
Country | Link |
---|---|
US (2) | US6953969B2 (en) |
JP (1) | JP3753692B2 (en) |
KR (1) | KR101033724B1 (en) |
CN (1) | CN1280921C (en) |
TW (1) | TW200419806A (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4312451B2 (en) * | 2002-12-24 | 2009-08-12 | Necエレクトロニクス株式会社 | Electrostatic protection element and semiconductor device |
JP4197660B2 (en) * | 2004-04-30 | 2008-12-17 | ローム株式会社 | MOS transistor and semiconductor integrated circuit device having the same |
JP4321444B2 (en) * | 2004-11-19 | 2009-08-26 | パナソニック株式会社 | Motor drive device with MOS FET, MOS FET, and motor with MOS FET |
TW200814320A (en) * | 2006-09-15 | 2008-03-16 | Sanyo Electric Co | Semiconductor device and method for making same |
JP5386916B2 (en) * | 2008-09-30 | 2014-01-15 | ソニー株式会社 | Transistor-type protection device, semiconductor integrated circuit, and manufacturing method thereof |
KR102164721B1 (en) * | 2014-11-19 | 2020-10-13 | 삼성전자 주식회사 | Semiconductor device |
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-
2002
- 2002-12-20 JP JP2002370525A patent/JP3753692B2/en not_active Expired - Fee Related
-
2003
- 2003-12-05 KR KR1020030087900A patent/KR101033724B1/en not_active IP Right Cessation
- 2003-12-08 TW TW092134519A patent/TW200419806A/en unknown
- 2003-12-10 US US10/730,995 patent/US6953969B2/en not_active Expired - Fee Related
- 2003-12-11 CN CNB200310120414XA patent/CN1280921C/en not_active Expired - Fee Related
-
2005
- 2005-05-24 US US11/135,672 patent/US20050218457A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
---|---|
JP2004200601A (en) | 2004-07-15 |
TW200419806A (en) | 2004-10-01 |
US20040119120A1 (en) | 2004-06-24 |
JP3753692B2 (en) | 2006-03-08 |
US6953969B2 (en) | 2005-10-11 |
KR20040055581A (en) | 2004-06-26 |
CN1280921C (en) | 2006-10-18 |
CN1510759A (en) | 2004-07-07 |
KR101033724B1 (en) | 2011-05-09 |
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Legal Events
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Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |