US20050176213A1 - Hemi-spherical grain silicon enhancement - Google Patents
Hemi-spherical grain silicon enhancement Download PDFInfo
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- US20050176213A1 US20050176213A1 US11/097,857 US9785705A US2005176213A1 US 20050176213 A1 US20050176213 A1 US 20050176213A1 US 9785705 A US9785705 A US 9785705A US 2005176213 A1 US2005176213 A1 US 2005176213A1
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- spherical grain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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Abstract
Hemi-spherical grain silicon enhancement with epitaxial silicon for semiconductor assemblies is described. Epitaxial silicon is used to enhance hemi-spherical grain silicon on semiconductor structures, such as storage node capacitor plates for a semiconductor assembly. Methods described include forming an optional amorphous silicon layer as a base to form hemi-spherical grain silicon thereon. The rough texture of the hemi-spherical grain silicon enhances the overall textured surface of the capacitor plate by the addition of epitaxial silicon.
Description
- This application is a continuation to U.S. patent application Ser. No. 10/643,520, filed Aug. 18, 2003.
- This invention relates to semiconductor fabrication processing and, more particularly, to a method for forming epitaxial silicon enhanced hemi-spherical grain silicon for semiconductor devices, such as dynamic random access memories (DRAMs).
- The continuing trend of scaling down integrated circuits has motivated the semiconductor industry to consider new techniques for fabricating precise components at sub-micron levels. Along with the need for smaller components, there has been a growing demand for devices consuming less power. In the manufacture of memory devices, these trends have led the industry to refine approaches to achieve thinner capacitor cell dielectric and surface enhanced storage capacitor electrodes.
- In dynamic random access memory (DRAM) devices it is essential that storage node capacitor cell plates be large enough to exhibit sufficient capacitance in order to retain an adequate charge in spite of parasitic capacitance and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate.
- The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices. The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
- One area of manufacturing technology that has emerged has been in the development of Hemi-Spherical Grain (HSG) silicon. HSG silicon enhances storage capacitance when used to form the storage node electrode without increasing the area required for the cell or the storage electrode height. The available methods known to those skilled in the art include use of Low Pressure Chemical Vapor Deposition (LPCVD) to deposit thin silicon films (conductively doped and non-doped silicon films) to form a rough surface. One method adds the silicon seeding and anneal steps in-situ and another method performs the silicon seeding and anneal in separate LPCVD systems. Methods to form HSG silicon, known to those skilled in the art, are utilized in conjunction with the several embodiments of the present invention that enhance the roughness of HSG silicon.
- Embodiments of the present invention describe structures and the formation thereof which utilize hemi-spherical grain silicon material, the size and shape of which is enhanced by the use of epitaxial silicon, to be used in semiconductor structures for semiconductor assemblies, which will become apparent to those skilled in the art from the following disclosure.
- Exemplary implementations of the present invention include hemi-spherical grain enhancement with epitaxial silicon for semiconductor assemblies, such as storage node capacitor plates for a semiconductor assembly and methods of forming thereof, comprising an optional amorphous silicon layer directly connecting to an underlying conductive material, such as a conductive polysilicon plug, a hemi-spherical grain silicon laying directly on the amorphous silicon layer and an epitaxial silicon laying directly on the hemi-spherical grain silicon.
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FIG. 1 is a cross-sectional view of a semiconductor substrate section showing an example of a completed storage cell having a container capacitor structure of an embodiment of the present invention. -
FIG. 2 is a cross-sectional view of a semiconductor substrate section depicting storage cell access transistors with an overlying planarized isolation material having a hole etched therein that is filled with a polysilicon plug which in turn connects to an underlying source/drain region of an access transistor. -
FIG. 3 is a subsequent cross-sectional view taken fromFIG. 2 following the formation of a borophosphosilicate glass (BPSG) material (or any kind of insulating materials) and the subsequent patterning and etching of an opening to provide access to the underlying polysilicon plug. -
FIG. 4 is a subsequent cross-sectional view taken fromFIG. 3 following the formation and planarization of the amorphous silicon layer, after which the amorphous silicon layer is etched back below the upper level of the BPSG. -
FIG. 5 is a cross-sectional view taken fromFIG. 4 following the formation of a hemi-spherical grain silicon on the amorphous silicon layer and the formation of epitaxial silicon on the hemi-spherical grain silicon, the combination of which is shown in an accompanying expanded view. -
FIG. 6 is an enlarged cross-sectional view taken from a region outlined inFIG. 5 . -
FIG. 7 is a cross-sectional view taken fromFIG. 5 following the formation of a conformal storage cell dielectric layer and the formation of a top storage cell electrode. -
FIG. 8 is a subsequent cross-sectional view taken fromFIG. 3 following the formation of hemi-spherical grain silicon along the upper surface and sidewalls of the BPSG material and on the exposed polysilicon plug, as well as the formation of epitaxial silicon on the hemi-spherical grain silicon. -
FIG. 9 is an enlarged cross-sectional view taken from a region outlined inFIG. 8 . -
FIG. 10 is a cross-sectional view taken fromFIG. 8 following the removal of the epitaxial hemi-spherical grain silicon that overlies the isolation region laying outside the desired storage node plate area followed by the formation of a conformal storage cell dielectric layer and the formation of a top storage cell electrode. -
FIG. 11 is an overhead plan view ofFIG. 10 showing a completed memory cell depicting an embodiment of the present invention. -
FIG. 12 is a simplified block diagram of a semiconductor system comprising a processor and memory device to which the present invention may be applied. - Exemplary implementations of the present invention are directed to processes for forming epitaxial enhanced HSG silicon and structures utilizing the epitaxial enhanced HSG silicon in a semiconductor device as depicted in the embodiment of
FIGS. 2-7 and the embodiment ofFIGS. 2-3 and 8-10. - In the following description, the terms “wafer” and “substrate” are to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, silicon-on-insulator, silicon-on-saphire, germanium, or gallium arsenide, among others.
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FIG. 1 depicts a representation of a completed storage cell incorporating an embodiment of the present invention. Seen inFIG. 1 issubstrate 20 on which has been formed field effect transistors (FETs), comprising source/drain region 22,transistor gate oxide 23,conductive transistor gates 24 isolated bymaterials Source drain region 22 of a field effect transistor is isolated from a neighboring source/drain region of an adjacent field effect transistor (not shown) by field oxide ortrench isolation material 21. As explained below,isolation material 30 is planarized and a hole provided therein to allow conductive plug 29 to connect to source/drain region 22. A capacitor storage node plate 29, having a roughened surface, sits atop and connects toconductive plug 28. A conformal storage cell dielectric 101 covers capacitor storage node plate 29 and the bordering exposedisolation material 30. Finally, a storagecapacitor top plate 102 overlies cell dielectric 101 to complete the storage cell structure. Fabrication methods to form the storage cell structure ofFIG. 1 are described below. - Referring to
FIG. 2 ,substrate 20 is prepared for the processing steps of the present embodiment.Substrate 20 may be a silicon material, such as a conductively doped silicon wafer. Processing steps known by one skilled in the art are used to form field effect transistors (FETs), comprising source/drain regions 22,transistor gate oxide 23 andconductive transistor gates 24 isolated bymaterials trench isolation material 21 andisolation material 27, such as borophosphosilicate glass (BPSG), is formed over the FETs, planarized and a hole etched therein to expose the underlying source/drain region 22. Next, a conductive polysilicon (poly) material is deposited and planarized to formpoly plug 28. - Referring now to
FIG. 3 , asecond isolation material 30, such as BPSG, is formed on the surface ofisolation material 27 andpoly plug 28.Isolation material 30 now incorporatesisolation material 27 seen inFIG. 2 .Isolation material 30 is patterned and etched to form anopening 31 therein and to provide access topoly plug 28. A following poly etchrecesses poly plug 28 somewhat to ensure all overlying isolation material (i.e., oxide) is removed from the poly plug. - Referring now to
FIG. 4 , a conformal layer ofamorphous silicon 40 is formed on the exposed surface ofisolation material 30, intoopening 31 along the sidewalls ofisolation material 30, on any exposed portion ofisolation materials poly plug 28. An amorphous silicon layer having a preferred thickness of about 200-500 Angstroms may be formed by decomposing SiH4 at approximately 500° C. -
Amorphous silicon 40 may be a conductively doped material, a non-conductively doped material, or a combination of doped and non-conductively doped amorphous silicon layers.Amorphous silicon 40 will serve as a silicon-seeding site for subsequent formation of Hemi-Spherical Grain (HSG) silicon.Amorphous silicon layer 40 is stripped from the upper surface ofisolation material 30, by a method such as planarization. Then the amorphous silicon is etched back so that it is recessed below the top surface of opening 31 inisolation material 30 to ensure the subsequently formed storage node cell plate is physically isolated from any neighboring storage node cell plate in a memory array. The remainingamorphous silicon 40, defines a future storage node cell plate region that will reside in opening 31. - Referring now to
FIG. 5 , Hemi-Spherical Grain (HSG)silicon 51 is formed onamorphous silicon 40 by methods known to those skilled in the art. Typically, the formation of HSG silicon does not result in uniform silicon spheres and may instead be non-uniform silicon hemispheres with varying grain size and grain spacing. For example, as demonstrated inFIG. 5 , asilicon seed 50 is deposited onamorphous silicon 40, using the amorphous silicon as a silicon-seeding site. As deposition continues,HSG silicon 51 develops into non-uniform silicon hemispheres with varying grain size and grain spacing. - Next, to further enhance the roughness of
HSG silicon 51,epitaxial silicon 52 is grown on the HSG silicon to extend the size and shape of the silicon grain. For example, to enhance the roughness of the HSG silicon material, the epitaxial silicon is grown on the HSG silicon by decomposing DCS (Si2H2Cl2) in an H2/HCl environment at about 550 to 1000° C. A preferred epitaxial silicon thickness is approximately 100 Angstroms. - During epitaxial silicon deposition, the epitaxial silicon growth is promoted on the HSG silicon, but is inhibited from growing on
isolation material 30. However, a small amount ofepitaxial silicon 53 does in fact form on the exposed portions ofisolation material 30, creating an unwanted epi-defect that could possibly provide an electrical path to a neighboring capacitor storage node plate. To ensure this defect is eliminated, first a hydrofluoric acid wet clean is used to remove any oxide that may have formed on the epitaxial silicon. Following the hydrofluoric acid wet clean (if needed), a chlorine etch is used to remove the epi-defect, but in doing so the epitaxial growth on the HSG silicon is somewhat reduced. However, the reduction of HSG silicon is minimal due to the small amount of epi-defect requiring removal. Thus, the chlorine etch has the added advantage of being able to control the epitaxial enhanced, HSG silicon grain size to obtain a desired overall rough surface for the storage node plate. - For example, the preferred epitaxial silicon deposition process (incorporating a chlorine etch) is conducted in a deposition chamber for a total of 5 cycles, with each cycle performed at a temperature of approximately 750-900° C. as follows. First, flow approximately 5-50 sccm of Si2H6 (flow for approximately 5-20 seconds), and then evacuate the chamber. Second, flow approximately 1-20 sccm of Cl2 (flow for approximately 5-20 seconds), and then evacuate the chamber. Third, flow approximately 10-100 sccm of H2 (flow for approximately 5-20 seconds), and then evacuate the chamber. The chamber may be evacuated by such methods as vacuum.
- Referring now to
FIG. 6 , an enlarged view ofregion 54 inFIG. 5 , demonstrates a major advantage gained by the addition ofepitaxial silicon 52. The non-uniform silicon hemispheres with varying grain size and grain spacing of HSG silicon 41 show how the HSG silicon may form any shape of silicon grains from smaller grains, such as HSG silicon 51 a, to larger grains, such as HSG silicon 51 b, which may form both uniform or non-uniform hemi-spherical shapes. While the HSG silicon provides for a rough surface, a desirable characteristic for a storage plate of a capacitor due to increased storage plate surface area, the addition ofepitaxial silicon 52 further increases the roughness (or overall textured surface) of the final storage plate. - However, the growth pattern of
epitaxial silicon 52 varies according to the size and shape of the underlying hemi-spherical silicon due to the effects of a bonding energy that changes according to grain size. As seen in enlarged view ofregion 54, on the smaller hemi-spherical silicon grain, such as HSG silicon 51 a, the epitaxial silicon 52 a grows in a more vertical direction and grows less in a horizontal direction to form a somewhat oblong silicon shape from the center point silicon seed 50 a. This result may be due to the bond energy being greater along the upper surface of the smaller HSG silicon grain, thus causing a greater growth of epitaxial silicon 52 a in vertical direction away from the silicon seed 50 a that graduates down to less growth of epitaxial silicon 52 a in the horizontal direction. - In varying contrast, on a larger hemi-spherical silicon grain, such as HSG silicon 51 b, the epitaxial silicon 52 b growth is more uniform along the entire surface of HSG silicon 51 b to form a rounded, more uniform silicon shape from the center point silicon seed 50 b. This result may be due to the bond energy being substantially equal along the surface of the larger HSG silicon grain, thus causing an even growth of epitaxial silicon 52 b on the surface of HSG silicon 51 b and the growth being somewhat equidistant away from the silicon seed 50 b.
- The enlarged view of
region 54 demonstrates in a visual respect how the overall surface area of theoriginal HSG silicon 51 has been significantly increased by the addition ofepitaxial silicon 52, which is a desired feature of the present invention when this process is utilized in semiconductor fabrication processes, such as formation of Dynamic Random Access Memory (DRAM) storage capacitors or other semiconductor devices that may benefit from enhanced electric charge storage capabilities. - Referring now to
FIG. 7 , a conformalstorage cell dielectric 71, such as nitride, is formed over, preferably directly on, the epitaxial silicon covered HSG siliconstorage node plate 70 and the exposed regions of borderingisolation material 30. Next, a storage nodecapacitor top plate 72, such as conductively doped polysilicon, is formed on the cell dielectric to complete the formation of a storage cell. The semiconductor assembly is then completed using fabrication methods know to those skilled in the art. - A second exemplary embodiment of the present invention is depicted in
FIGS. 2-3 and 8-10. A semiconductor assembly is prepared as depicted inFIGS. 2 and 3 as anopening 31 is etched intoisolation material 30 to expose anunderlying polysilicon plug 28, as previously describe in the first exemplary implementation of the present invention. The second implementation of the present invention continues withFIGS. 8-10 . - Referring now to
FIG. 8 , a layer of deposited Hemi-Spherical Grain (HSG) silicon 81 is deposited on the exposed surfaces ofisolation material 30 and the exposed surface of recessedpolysilicon plug 28, by methods know to those skilled in the art. As discussed previously, typically the formation of HSG silicon does not result in uniform silicon spheres and may instead be non-uniform silicon hemispheres with varying grain size and grain spacing. As seen inFIG. 8 , asilicon seed 80 is deposited on the exposed surfaces comprisingisolation material 30, gate isolation material 26 (if exposed) andpolysilicon plug 28. As deposition continues, HSG silicon 81 develops into non-uniform silicon hemispheres with varying grain size and grain spacing. - Next, to further enhance the roughness of HSG silicon 81,
epitaxial silicon 82 is grown on the HSG silicon to extend the size and shape of the silicon grain. For example, to enhance the roughness of the HSG silicon material, the epitaxial silicon is grown on the HSG silicon by decomposing DCS (Si2H2Cl2) in an H2 and HCl environment at about 550 to 1000° C. A preferred epitaxial silicon thickness is approximately 100 Angstroms. - Referring now to
FIG. 9 , an enlarged view ofregion 83, shown inFIG. 7 , demonstrates a major advantage gained by the addition ofepitaxial silicon 82. The non-uniform silicon hemispheres with varying grain size and grain spacing of HSG silicon 81 show how the HSG silicon may form any shape of silicon grains from smaller grains, such as HSG silicon 81 a, to larger grains, such as HSG silicon 81 b, which may form both uniform or non-uniform hemi-spherical shapes. While the HSG silicon provides for a rough surface, a desirable characteristic for a storage plate of a capacitor due to increased storage plate surface area, the addition ofepitaxial silicon 82 further increase the roughness of the final storage plate, as evidenced by the epitaxial silicon growth of 82 a and 82 b. The different growth pattern of epitaxial silicon 82 a and 82 b is similar to the discussion of the epitaxial silicon growth described in the first exemplary implementation of the present invention and therefore not repeated. - The enlarged view of
region 83 demonstrates, in a visual respect, how the overall surface area of the original HSG silicon 81 has been significantly increased by the addition ofepitaxial silicon 82, which is a desired feature of the present invention when this process is utilized in semiconductor fabrication processes, such as formation of Dynamic Random Access Memory (DRAM) storage capacitors or other semiconductor devices that may benefit from enhanced electric charge storage capabilities. - Referring now to
FIG. 10 , a conformalstorage cell dielectric 101, such as nitride, is formed over, preferably directly on, the epitaxial silicon covered HSG siliconstorage node plate 100 and the exposed regions of borderingisolation material 30. Next, a storage nodecapacitor top plate 102, such as conductively doped polysilicon, is formed on the cell dielectric to complete the formation of a storage cell. The semiconductor assembly is then completed using fabrication methods know to those skilled in the art. -
FIG. 11 is an overhead plan view ofFIG. 10 showing a completed memory cell depicting an embodiment of the present invention. InFIG. 11 the source/drain region 22 of a FET is imbedded insubstrate 20. The FET gates (not seen) underlieisolation regions drain region 22 and overlying container storage node plate 100 (the epitaxial silicon covered HSG silicon storage node plate in fact covers the bottom of the plate).Isolation region 30, seen inFIG. 10 , is not shown to allow for a basic overhead view of the regions of the underlying FET. If the isolation region was shown, it would surroundstorage node plate 100 and cover the underlying regions of the FETs. - The present invention may be applied to a semiconductor system, such as the one depicted in
FIG. 12 , the general operation of which is known to one skilled in the art.FIG. 12 represents a general block diagram of a semiconductor system comprising aprocessor 120 and amemory device 121 showing the basic sections of a memory integrated circuit, such as row and column address buffers, 123 and 124, row and column decoders, 125 and 126,sense amplifiers 127,memory array 128 and data input/output 129, which are manipulated by control/timing signals from the processor throughcontrol 122. - It is to be understood that although the present invention has been described with reference to several preferred embodiments, various modifications, known to those skilled in the art, such as utilizing the disclosed methods to form DRAM storage capacitors or other semiconductor devices, may be made to the process steps presented herein without departing from the invention as recited in the several claims appended hereto.
- U.S. Pat. No. 5,407,534, U.S. Pat. No. 5,418,180, U.S. Pat. No. 5,658,381, U.S. Pat. No. 5,721,171 and U.S. Pat. No. 6,448,129 contain disclosure concerning HSG silicon formation and are hereby incorporated by reference as if set forth in their entirety.
Claims (12)
1. A method of forming a semiconductor assembly having a textured surfaced structure comprising:
forming hemi-spherical grain silicon over a supporting substrate; and
forming epitaxial silicon directly on the hemi-spherical grain silicon, wherein the epitaxial silicon has a non-uniform thickness across the outer surface of the hemi-spherical grain silicon;
wherein the non-uniform thickness across the outer surface of the hemi-spherical grain silicon forms an oblong outer surface of the epitaxial silicon.
2. The method of claim 1 , wherein the epitaxial silicon thickness varies in thickness up to approximately 100 Angstroms.
3. The method of claim 1 , wherein the textured surfaced structure is a capacitor structure.
4. A method of forming a semiconductor assembly having textured surfaced structure comprising:
forming hemi-spherical grain silicon directly connecting to an underlying conductive material;
forming epitaxial silicon directly on an outer surface of the hemi-spherical grain silicon, wherein a thickness of the epitaxial silicon varies across the surface of the hemi-spherical grain silicon such that the epitaxial silicon has a greatest thickness at an apex of the hemi-spherical grain silicon;
wherein the non-uniform thickness across the outer surface of the hemi-spherical grain silicon forms an oblong outer surface of the epitaxial silicon.
5. The method of claim 4 , wherein the textured surfaced structure is a capacitor structure.
6. The method of claim 4 , wherein the epitaxial silicon thickness varies in thickness up to approximately 10 Angstroms.
7. A semiconductor assembly having a textured surfaced structure comprising:
a hemi-spherical grain silicon over a supporting substrate; and
an epitaxial silicon directly on the hemi-spherical grain silicon, wherein the epitaxial silicon has a non-uniform thickness across the outer surface of the hemi-spherical grain silicon;
wherein an outer surface of the epitaxial silicon is oblong shaped.
8. The semiconductor assembly of claim 7 , wherein the epitaxial silicon thickness varies in thickness up to approximately 100 Angstroms.
9. The semiconductor assembly of claim 7 , wherein the textured surfaced structure is a capacitor structure.
10. A semiconductor assembly having textured surfaced structure comprising:
a hemi-spherical grain silicon directly connecting to an underlying conductive material; and
an epitaxial silicon directly on an outer surface of the hemi-spherical grain silicon, wherein a thickness of the epitaxial silicon varies across the surface of the hemi-spherical grain silicon such that the epitaxial silicon has a greatest thickness at an apex of the hemi-spherical grain silicon;
wherein an outer surface of the epitaxial silicon is oblong shaped.
11. The semiconductor assembly of claim 10 , wherein the textured surfaced structure is a capacitor structure.
12. The semiconductor assembly of claim 10 , wherein the epitaxial silicon thickness varies in thickness up to approximately 100 Angstroms.
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US11/097,857 US20050176213A1 (en) | 2003-08-18 | 2005-03-31 | Hemi-spherical grain silicon enhancement |
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US10/643,520 US6902973B2 (en) | 2003-08-18 | 2003-08-18 | Hemi-spherical grain silicon enhancement |
US11/097,857 US20050176213A1 (en) | 2003-08-18 | 2005-03-31 | Hemi-spherical grain silicon enhancement |
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US20070059888A1 (en) * | 2005-09-15 | 2007-03-15 | Elpida Memory, Inc. | Semiconductor integrated circuit device and manufacturing method thereof |
US20110189828A1 (en) * | 2009-12-21 | 2011-08-04 | Elpida Memory, Inc. | Method for forming silicon layer and method for manufacturing semiconductor device |
US20120012812A1 (en) * | 2010-07-16 | 2012-01-19 | Micron Technology, Inc. | Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing |
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US6902973B2 (en) * | 2003-08-18 | 2005-06-07 | Micron Technology, Inc. | Hemi-spherical grain silicon enhancement |
TWI284318B (en) * | 2005-12-09 | 2007-07-21 | Ind Tech Res Inst | DRAM cylindrical capacitor and method of manufacturing the same |
US7601215B1 (en) | 2006-11-17 | 2009-10-13 | Alliance For Sustainable Energy, Llc | Method for rapid, controllable growth and thickness, of epitaxial silicon films |
US20100273307A1 (en) * | 2009-04-27 | 2010-10-28 | Infineon Technologies Ag | Method of making a device including a capacitive structure |
US8236645B1 (en) * | 2011-02-07 | 2012-08-07 | GlobalFoundries, Inc. | Integrated circuits having place-efficient capacitors and methods for fabricating the same |
US9988260B2 (en) * | 2016-04-29 | 2018-06-05 | Nxp Usa, Inc. | Rough MEMS surface |
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