US20050176168A1 - Package structure of optical device and method for manufacturing the same - Google Patents

Package structure of optical device and method for manufacturing the same Download PDF

Info

Publication number
US20050176168A1
US20050176168A1 US10/906,095 US90609505A US2005176168A1 US 20050176168 A1 US20050176168 A1 US 20050176168A1 US 90609505 A US90609505 A US 90609505A US 2005176168 A1 US2005176168 A1 US 2005176168A1
Authority
US
United States
Prior art keywords
optical device
wafer
package structure
cover
connection pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/906,095
Inventor
Kuo-Chung Yee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC. reassignment ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YEE, KUO-CHUNG
Publication of US20050176168A1 publication Critical patent/US20050176168A1/en
Priority to US12/471,455 priority Critical patent/US8003426B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Light Receiving Elements (AREA)

Abstract

A package structure of optical device has a chip, a sealant, a cover, a substrate, a plurality of bonding wires, and a transparent encapsulant. The chip has an optical device and a plurality of chip connection pads. The sealant is disposed around the optical elements. The cover is disposed on the sealant. The substrate supports the chip and has a plurality of connection pads. The bonding wires are used for electrically connecting the chip connection pads of the chip to the connection pads of the substrate. The transparent encapsulant is formed over the substrate and the cover, and encapsulates the bonding wires.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority benefit of Taiwan application serial no. 93102847, filed on Feb. 6, 2004.
    • BACKGROUND OF THE INVENTION
  • 1. Field of Invention
  • The present invention relates to a package structure of optical semiconductor integrated circuit device. More particularly, the invention relates to a package structure of optical semiconductor integrated circuit device having a cover and a transparent encapsulant.
  • 2. Description of Related Art
  • In the general photoelectric applications, in order to protect the optical device in the form of integrated circuit chip, such as image sensor chip, from being physical damage and environmental contamination, the image sensor chip in practical situation is disposed in a package structure. The package structure has an opening, which is sealed by a transparent cover, so that the image sensor chip can sense the optical signals.
  • For example, the image sensor chip usually is implemented on a ceramic substrate with protruding pins by using a molding layer. The molding layer usually needs the curing process, so as to firmly implement the image sensing device on the ceramic substrate. After bonding wire and window sealing, the pins are cut to have a proper length. The final structure is achieved and the package process is accomplished.
  • In the fabrication process about sealing the window, typically, it uses a work process by distributing or molding, so that the molding compound encloses the image sensing device, which is then implemented on the substrate. After then, a transparent cover is disposed over the molding compound, so as to seal the image sensing device between the substrate and the cover. For example, the U.S. Pat. No. 5,811,799 issued to Wu on Sep. 22, 1998 by a title “Image Sensor Package Having A Wall with A Sealed Cover” has disclosed a package structure of image sensor, in which a pre-molded wall is used to package an image sensor chip on a ceramic substrate. The foregoing package structure of the optical device is easily warped, and therefore it needs the ceramic substrate that is rather expansive.
  • Therefore, it is necessary for the manufacturers in packaging the optical device to provide a package structure of the optical device, so as to reduce the fabrication cost.
    • SUMMARY OF THE INVENTION
  • The invention provides a package structure of optical semiconductor integrated circuit device, so as to reduce the fabrication cost.
  • The invention provides a package structure of optical device, including a chip, a sealant, a cover, a substrate, multiple bonding wires, and a transparent encapsulant. The chip has an optical device and multiple chip connection pads. The sealant is disposed to enclose the optical device. The cover is disposed on the sealant. The substrate supports the chips and has multiple connection pads. The bonding wires are used to electrically connect the chip connection pads of the chip to the connection pads of the substrate. The transparent encapsulant is formed over the substrate and the cover, and enclosing the bonding wires.
  • According to the present invention, the package structure of optical device has a cover, which covers over the optical device of the chip, so that it is helpful to prevent from the moisture and reduce the warpage. The package structure of optical device can use a usual substrate in completion without need of the expensive ceramic or bisma-leimide triazine resin as the substrate. As a result, the fabrication cost is greatly reduced.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIG. 1 is a cross-sectional view, schematically illustrating a package structure of optical device, according to preferred embodiment of the invention.
  • FIG. 2 is a top view, schematically illustrating a package structure of optical device of FIG. 1, according to preferred embodiment of the invention.
  • FIGS. 3-9 are drawings, schematically illustrating the fabrication processes for the package structure of optical device, according to the invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Referring to FIG. 1, it is a cross-sectional view, schematically illustrating a package structure of optical device 100, according to preferred embodiment of the invention. The package structure of optical device 100 includes a chip 110, having an active surface 112 and back surface 114 in opposites side. The active surface 112 of the chip 110 has an active zone 116, having multiple optical devices, such as the optical sensor, used for conversion between the optical signals and the electrical signals.
  • A sealant 122 encloses the optical devices 100 and is disposed on the active surface 112 of the chip 110. A cover 120 is disposed on the sealant 122, and is firmly adhered to the chip 110 by the sealant 122. The sealant 122 is mixed with spacers (not shown in figure), so as to allow the cover 120 to have a fixed gap from the chip 110. Moreover, the cover 120 can be a simple transparent cover, or a cover 120 that can also provide some optical properties, such as filtering or focusing. In other words, the cover 120 can be a filter plate or a lens.
  • The chip 110 can be firmly adhered to a substrate 150 by an adhering layer 142. Multiple chip connection pads 118 are additionally disposed on the active surface 112 of the chip 110, so as to electrically connect to the first connection pads 156 on the upper surface of the substrate 150 by multiple bonding wires 140. The substrate 150 also has multiple circuit line 152, so as to electrically connect the first connection pads 156 to the second connection pads 154 on the lower surface of the substrate 150. A transparent encapsulant 130 encloses the chip 110, the cover 120, the bonding wires 140 and the upper surface of the substrate 150. The second connection pad 154 can be electrically connected and firmly mounted on an external printed circuit board (not shown) by a surface mounting technology. In other words, the package structure of optical device 100 has the package structure of land grid array. The ordinary skilled artisans can understand that the second connection pad 154 can be easily changed with solder balls or connection pins, so as to form the structures of the ball grid array or pin grid array.
  • Referring to FIGS. 3-9, they are the drawings schematically illustrating the fabrication processes for the package structure of optical device 100, according to an embodiment of the invention. In FIG. 3, according to the fabrication process of the invention, a wafer 160 is provided. The wafer 160 has multiple chips 110 and multiple first cutting lines 162, so as to define the chips 110. Each chip 110 has an active zone 116 and multiple chip connection pads 118, which are disposed around the active zone 116. Then, a sealant 122 is dispensed to each chip 110 by a dispenser (not shown), so as to enclose the active zone 116. The chip connection pads 118 are located at outside of the sealant 122, as shown in FIG. 4 in detail.
  • Referring to FIG. 5, a cover substrate 170 is disposed over the wafer 160. The cover substrate 170 has multiple covers 120 and multiple second cutting lines 172, so as to define the covers 120. As previously described, the cover substrate 170 can be a transparent plate, an optical filtering plate, or can have multiple lenses. The sealant 122 can be ultraviolet cure adhesive, mixed with spacers (not shown). After the cover substrate 170 is aligned with the wafer 160 and is disposed over the wafer 160, the sealant 122 can be cured by the ultraviolet light. As a result, the cover 120 can be adhered onto the chips 110 by a substantially uniform spacing, and a cavity with uniform spacing is formed above the active zone 116.
  • Referring to FIG. 6, the cutting devices 180 and 182 cut the wafer 160 and the cover substrate 170 along the first and second cutting lines 162 and 172 respectively on the wafer 160 and the cover substrate 170. Thereby, by the cutting process, the wafer 160 and the cover substrate 170 are cut into several singulated pieces, and then the multiple package structures 190 are formed. Preferably, the wafer 160 and the cover substrate 170 are processed to form multiple grooves 184, 186. Then, in the subsequent process, the wafer 160 and the cover substrate 170 are broken at the grooves 184, 186 by a breaking process, and then the package structures 190 are formed as shown in FIG. 7.
  • In FIG. 8, according to the fabrication process of the invention, a substrate strip 192 is provided, in which multiple substrates 150 are included, and are arranged by an array manner. The package structures 190 can be respectively adhered to the substrates 150 of the substrate strip 192 by multiple adhering layers 142. The bonding wires 140 are used to electrically connect the chip connection pads 118 of the chip 110 to the first connection pads 156 of the substrates 150.
  • In FIG. 9, the transparent encapsulant 130 is formed by a transparent molding compound to mold onto the substrate strip 192, so as to encapsulate the package structure 190, the bonding wires 140, and the upper surface of the substrate 150. After then, the substrate strip 192 is cut and the package structure of optical device 100 is formed.
  • As the foregoing descriptions, according to the invention, the package structure of optical device is a land grid array structure. However, the ordinary skilled artisans can understand that the second connection pads 154 can be easily changed with solder balls or connection pins, so as to form the structures of the ball grid array or pin grid array.
  • According to the invention, the package structure of optical device has a cover, covering over the optical device of the chip, whereby it is helpful to avoid the moisture and reduce warpage. The package structure of optical device can use a usual substrate without need of expensive ceramic or bisma-leimide triasine resin as the substrate. As a result, the fabrication cost can be greatly reduced. Moreover, since the package structure has no the outer pins, the signal transmitting path is shorter and thereby it has better electric properties.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.

Claims (28)

1. A package structure of optical device, comprising:
a chip, having an optical device and a plurality of chip connection pads;
a sealant, disposed around the optical device;
a cover, disposed on the sealant;
a substrate, supporting the chip and having a plurality of first connection pads;
a plurality of bonding wires, electrically connecting the chip connection pads of the chip to the first connection pads of the substrate; and
a transparent encapsulant, formed over the substrate and the cover, and packaging the bonding wires.
2. The package structure of optical device of claim 1, wherein the substrate further comprises a plurality of second connection pads, electrically connected to the first connection pads for connecting to an external circuit apparatus.
3. The package structure of optical device of claim 2, wherein the substrate further comprises a plurality of circuit lines, used to electrically connect the first connection pads to the second connection pads.
4. The package structure of optical device of claim 1, wherein the cover is an optical filtering plate.
5. The package structure of optical device of claim 1, wherein the cover is a lens.
6. The package structure of optical device of claim 1, wherein the sealant includes a plurality of spacers, so as to maintain the cover to have a uniform spacing to the chip.
7. A fabrication method for a package structure of optical device, comprising:
providing a wafer, having a plurality of chips, and each of the chips having an optical device and a plurality of chip connection pads, and a plurality of first cutting lines for separating the chips;
dispensing a sealant to each of the chips on the wafer, and enclosing the optical device;
providing a cover substrate, having a plurality of covers, each of the covers is corresponding to the optical device of the chips and a plurality of second cutting lines, used for separating the covers;
aligning the cover substrate with the wafer, and disposing the cover substrate on the wafer;
curing the sealant;
cutting the wafer and the cover substrate along the first scribe lines and the second scribe lines, so as to form a plurality of pre-package structures;
providing a substrate strip, having a plurality of substrates, wherein each of the substrates has a plurality of first connection pads;
affixing the pre-package structures to the substrates;
electrically connecting the chip connection pads of the chips to the substrates by a plurality of bonding wires;
molding an encapsulant over the substrates, so as to package the bonding wires; and
cutting the substrates and the encapsulant, for forming the package structure of optical device.
8. The fabrication method of claim 7, wherein each of the substrates further includes a plurality of second connection pads, electrically connected to the first connection pads, so as to be connected to an external circuit apparatus.
9. The fabrication method of claim 8, wherein each of the substrates further includes a plurality of circuit lines, so as to electrically connect the first connection pads to the second connection pads.
10. The fabrication method of claim 7, wherein the cover is an optical filtering plate.
11. The fabrication method of claim 7, wherein each of the covers is a lens.
12. The fabrication method of claim 7, wherein the sealant provides a plurality of spacers, so as to maintain a uniform spacing between the covers and the chips.
13. The fabrication method of claim 7, wherein in the step of respectively cutting the wafer and the cover substrate to form the pre-package structures, the wafer and the cover substrate are cut along the first cutting lines and the second cutting lines but not cut through.
14. The fabrication method of claim 13, wherein the step of respectively cutting the wafer and the cover substrate for forming the pre-package structures further comprises a breaking process to form the pre-package structures.
15. The fabrication method of claim 7, wherein in the step of respectively cutting the wafer and the cover substrate to form the pre-package structures, the wafer and the cover substrate are cut along the first cutting lines and the second cutting lines to form a plurality of grooves thereon.
16. The fabrication method of claim 15, wherein the step of respectively cutting the wafer and the cover substrate for forming the pre-package structures further comprises a breaking process to form the pre-package structures.
17. A package structure of optical device, comprising:
a chip, having an optical device and a plurality of connection pads;
a sealant, disposed around the optical device; and
a cover, disposed over the sealant.
18. The package structure of claim 16, wherein the cover is an optical filtering plate.
19. The package structure of claim 16, wherein the cover is a lens.
20. The package structure of claim 16, wherein the sealant provides a plurality of spacers, so as to maintain a uniform spacing between the covers and the chips.
21. A fabrication method for a package structure of optical device, comprising the steps of:
providing a wafer, having a plurality of chips, each of the chips having an optical device and a plurality of chip connection pads, and a plurality of first cutting lines for separating the chips;
dispensing a sealant on the chips of the wafer around the optical device;
providing a cover substrate, having a plurality of covers, wherein each of the covers is corresponding to the optical device, and a plurality of second cutting lines for separating the covers;
aligning the cover substrate with the wafer, and disposing the cover substrate over the wafer;
curing the sealant;
cutting the wafer and the cover substrate along the first cutting lines and the second cutting lines, for forming the package structure of optical device.
22. The fabrication method of claim 20, wherein each of the covers is an optical filtering plate.
23. The fabrication method of claim 20, wherein each of the covers is a lens.
24. The fabrication method of claim 20, wherein the sealant provides a plurality of spacers, so as to maintain a uniform spacing between the covers and the chips.
25. The fabrication method of claim 20, wherein in the step of cutting the wafer and the cover substrate along the first cutting lines and the second cutting lines for forming the package structure of optical device, the wafer and the cover substrate are not cut through.
26. The fabrication method of claim 25, wherein the step of cutting the wafer and the cover substrate for forming the package structure of optical device further comprises a breaking process to form the package structures.
27. The fabrication method of claim 20, wherein in the step of cutting the wafer and the cover substrate along the first cutting lines and the second cutting lines for forming the package structure of optical device, the wafer and the cover substrate are cut to form a plurality of grooves thereon.
28. The fabrication method of claim 27, wherein the step of cutting the wafer and the cover substrate for forming the package structure of optical device further comprises a breaking process to form the package structures.
US10/906,095 2004-02-06 2005-02-03 Package structure of optical device and method for manufacturing the same Abandoned US20050176168A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/471,455 US8003426B2 (en) 2004-02-06 2009-05-25 Method for manufacturing package structure of optical device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW093102847A TWI324829B (en) 2004-02-06 2004-02-06 Optical semiconductor package and method for manufacturing the same
TW93102847 2004-02-06

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/471,455 Division US8003426B2 (en) 2004-02-06 2009-05-25 Method for manufacturing package structure of optical device

Publications (1)

Publication Number Publication Date
US20050176168A1 true US20050176168A1 (en) 2005-08-11

Family

ID=34825391

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/906,095 Abandoned US20050176168A1 (en) 2004-02-06 2005-02-03 Package structure of optical device and method for manufacturing the same
US12/471,455 Active 2025-07-08 US8003426B2 (en) 2004-02-06 2009-05-25 Method for manufacturing package structure of optical device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/471,455 Active 2025-07-08 US8003426B2 (en) 2004-02-06 2009-05-25 Method for manufacturing package structure of optical device

Country Status (3)

Country Link
US (2) US20050176168A1 (en)
JP (1) JP4166759B2 (en)
TW (1) TWI324829B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040161871A1 (en) * 2002-11-27 2004-08-19 Seiko Epson Corporation Semiconductor device, method of manufacturing the same, circuit substrate and electronic equipment
US20080102552A1 (en) * 2006-10-30 2008-05-01 Warren Farnworth Wafer level method of locating focal plane of imager devices
US20080254558A1 (en) * 2005-06-01 2008-10-16 Samsung Electro-Mechanics Co., Ltd. Side-emitting LED package and method of manufacturing the same
CN102194714A (en) * 2010-03-05 2011-09-21 铜陵三佳科技股份有限公司 Semiconductor packaging device with resin material loading photoelectric detection device
US20130203200A1 (en) * 2010-01-20 2013-08-08 Siliconware Precision Industries Co., Ltd. Fabrication method of package structure having mems element
US20220037206A1 (en) * 2020-07-28 2022-02-03 Socionext Inc. Method for producing semiconductor device, semiconductor package, and method for producing semiconductor package

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9488779B2 (en) 2013-11-11 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method of forming laser chip package with waveguide for light coupling
JP6748501B2 (en) * 2016-07-14 2020-09-02 ローム株式会社 Electronic component and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729437A (en) * 1994-06-22 1998-03-17 Seiko Epson Corporation Electronic part including a thin body of molding resin
US5811799A (en) * 1997-07-31 1998-09-22 Wu; Liang-Chung Image sensor package having a wall with a sealed cover
US7273765B2 (en) * 2003-04-28 2007-09-25 Matsushita Electric Industrial Co., Ltd. Solid-state imaging device and method for producing the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0724287B2 (en) * 1987-02-12 1995-03-15 三菱電機株式会社 Semiconductor device having light transmitting window and method of manufacturing the same
JP2656336B2 (en) * 1989-01-18 1997-09-24 日東電工株式会社 Optical semiconductor device and epoxy resin composition for encapsulating optical semiconductor used therein
EP0678904A1 (en) * 1994-04-12 1995-10-25 Lsi Logic Corporation Multicut wafer saw process
US5904548A (en) * 1996-11-21 1999-05-18 Texas Instruments Incorporated Trench scribe line for decreased chip spacing
US6271102B1 (en) * 1998-02-27 2001-08-07 International Business Machines Corporation Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
JP3139462B2 (en) * 1998-07-17 2001-02-26 日本電気株式会社 Manufacturing method of organic thin film EL device
JP2000216413A (en) * 1999-01-26 2000-08-04 Apic Yamada Corp Bga type transparent plastic semiconductor package
JP2001185657A (en) * 1999-12-10 2001-07-06 Amkor Technology Korea Inc Semiconductor package and manufacturing method therefor
JP2001308349A (en) * 2000-04-14 2001-11-02 Hiroaki Hayashi Photosensor chip assembly and method of manufacturing the same
US6518079B2 (en) * 2000-12-20 2003-02-11 Lumileds Lighting, U.S., Llc Separation method for gallium nitride devices on lattice-mismatched substrates
JP3881888B2 (en) * 2001-12-27 2007-02-14 セイコーエプソン株式会社 Optical device manufacturing method
US6818532B2 (en) * 2002-04-09 2004-11-16 Oriol, Inc. Method of etching substrates
US7002241B1 (en) * 2003-02-12 2006-02-21 National Semiconductor Corporation Packaging of semiconductor device with a non-opaque cover

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729437A (en) * 1994-06-22 1998-03-17 Seiko Epson Corporation Electronic part including a thin body of molding resin
US5811799A (en) * 1997-07-31 1998-09-22 Wu; Liang-Chung Image sensor package having a wall with a sealed cover
US7273765B2 (en) * 2003-04-28 2007-09-25 Matsushita Electric Industrial Co., Ltd. Solid-state imaging device and method for producing the same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040161871A1 (en) * 2002-11-27 2004-08-19 Seiko Epson Corporation Semiconductor device, method of manufacturing the same, circuit substrate and electronic equipment
US20080254558A1 (en) * 2005-06-01 2008-10-16 Samsung Electro-Mechanics Co., Ltd. Side-emitting LED package and method of manufacturing the same
US7833811B2 (en) * 2005-06-01 2010-11-16 Samsung Led Co., Ltd. Side-emitting LED package and method of manufacturing the same
US20080102552A1 (en) * 2006-10-30 2008-05-01 Warren Farnworth Wafer level method of locating focal plane of imager devices
US7785915B2 (en) * 2006-10-30 2010-08-31 Aptina Imaging Corporation Wafer level method of locating focal plane of imager devices
US20130203200A1 (en) * 2010-01-20 2013-08-08 Siliconware Precision Industries Co., Ltd. Fabrication method of package structure having mems element
US8716070B2 (en) * 2010-01-20 2014-05-06 Siliconware Precision Industries Co. Ltd. Fabrication method of package structure having MEMS element
CN102194714A (en) * 2010-03-05 2011-09-21 铜陵三佳科技股份有限公司 Semiconductor packaging device with resin material loading photoelectric detection device
US20220037206A1 (en) * 2020-07-28 2022-02-03 Socionext Inc. Method for producing semiconductor device, semiconductor package, and method for producing semiconductor package
US11621193B2 (en) * 2020-07-28 2023-04-04 Socionext Inc. Method for producing semiconductor device, semiconductor package, and method for producing semiconductor package

Also Published As

Publication number Publication date
TW200527690A (en) 2005-08-16
US20090239329A1 (en) 2009-09-24
US8003426B2 (en) 2011-08-23
JP4166759B2 (en) 2008-10-15
TWI324829B (en) 2010-05-11
JP2005328028A (en) 2005-11-24

Similar Documents

Publication Publication Date Title
US8624371B2 (en) Methods of fabrication of package assemblies for optically interactive electronic devices and package assemblies therefor
US8003426B2 (en) Method for manufacturing package structure of optical device
US7723146B2 (en) Integrated circuit package system with image sensor system
KR100604190B1 (en) Solid state imaging device, semiconductor wafer, optical device module, method of solid state imaging device fabrication, and method of optical device module fabrication
US7227236B1 (en) Image sensor package and its manufacturing method
US7405100B1 (en) Packaging of a semiconductor device with a non-opaque cover
US20170110416A1 (en) Chip package having a protection piece compliantly attached on a chip sensing surface
US20090256222A1 (en) Packaging method of image sensing device
JPH07221278A (en) Solid-state image pickup element and its preparation
KR101579623B1 (en) Semiconductor package for image sensor and fabricatingmethod thereof
US20090026593A1 (en) Thin semiconductor die packages and associated systems and methods
JP2002329850A (en) Chip size package and its manufacturing method
US20070164386A1 (en) Semiconductor device and fabrication method thereof
JP2010050406A (en) Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus
US20050212129A1 (en) Semiconductor package with build-up structure and method for fabricating the same
JP4925832B2 (en) Method for mounting an optical sensor
US20090166831A1 (en) Sensor semiconductor package and method for fabricating the same
US20090215216A1 (en) Packaging method of image sensing device
CN111900181A (en) Wafer level packaging method for image sensing chip
US20070004087A1 (en) Chip packaging process
US20090179290A1 (en) Encapsulated imager packaging
TW202141098A (en) Lens packaging module and method for manufacturing the same
US7696008B2 (en) Wafer-level chip packaging process and chip package structure
KR20050100114A (en) Manufacturing method for semiconductor chip package using uv cure type encapsulant
KR20090043949A (en) Method of fabricating semiconductor package

Legal Events

Date Code Title Description
AS Assignment

Owner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YEE, KUO-CHUNG;REEL/FRAME:015638/0450

Effective date: 20040719

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION