US20050161727A1 - Integrated circuit devices having a metal-insulator-metal (MIM) capacitor - Google Patents
Integrated circuit devices having a metal-insulator-metal (MIM) capacitor Download PDFInfo
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- US20050161727A1 US20050161727A1 US11/083,874 US8387405A US2005161727A1 US 20050161727 A1 US20050161727 A1 US 20050161727A1 US 8387405 A US8387405 A US 8387405A US 2005161727 A1 US2005161727 A1 US 2005161727A1
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- integrated circuit
- circuit device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Definitions
- the present invention relates generally to integrated circuit devices, and, more particularly, to integrated circuit capacitors and methods of forming same.
- MIS capacitors may have relatively low dielectrics so that they may not provide desired capacitance values.
- MIM capacitors may be used to replace MIS capacitors.
- FIG. 1 is a cross-sectional view of a conventional integrated circuit device that comprises a MIM capacitor.
- a contact plug 15 is formed in an interlevel-insulating layer 13 on a substrate 11 , e.g., a silicon substrate.
- the contact plug 15 may comprise a TiN layer and may be used as a barrier layer.
- a MIM capacitor 23 is formed on the contact plug 15 .
- the contact plug 15 may connect the MIM capacitor 23 to a driving transistor (not shown) allowing charges to accumulate on the MIM capacitor 23 or be discharged from the MIM capacitor 23 .
- the MIM capacitor 23 comprises a lower electrode 17 , a dielectric layer 19 , and an upper electrode 21 .
- the lower electrode 17 and the upper electrode 21 may comprise a metal, such as Pt or Ru, and the dielectric layer 19 may comprise Ta 2 O 5 .
- CMP chemical mechanical polishing
- an integrated circuit device comprises a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate.
- a unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole.
- a dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. Because the lower electrode and the contact plug comprise a unitary body, cracks in the interlevel-insulating layer may be reduced and a seam may not be created in the contact plug.
- a barrier layer is disposed between the contact portion of the lower electrode and both the substrate and sidewalls of the interlevel-insulating layer.
- the barrier layer may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 ⁇ to about 300 ⁇ .
- the lower electrode of the capacitor is cylindrical and the barrier layer has a thickness in a range of about 30 ⁇ to about 300 ⁇ .
- a mold layer which may comprise silicon oxide, is on the interlevel-insulating layer that has an opening therein through which the lower electrode of the capacitor is received.
- An etch stop layer may also be on the mold layer and have an opening therein through which the lower electrode of the capacitor is received.
- the etch stop layer may comprise silicon oxide and/or tantalum oxide.
- the dielectric layer may comprise may comprise Al 2 O 3 , Ta 2 O 5 , TiO, (Ba, Sr)TiO 3 , Pb(Zr, Ti)O 3 , (Pb, La)(Zr, Ti)O 3 , and/or alloys thereof and the upper and lower electrodes of the capacitor may comprise one or more platinum group metals, such as Pt, Ru, and Ir.
- an integrated circuit device comprises a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate.
- a barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer.
- a contact plug is disposed in the hole on the barrier layer.
- a lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween.
- a dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.
- the barrier layer may increase adhesion with the contact plug and may also reduce contact resistance.
- the barrier layer may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 ⁇ to about 300 ⁇ .
- the present invention may also be embodied as methods of forming integrated circuit devices.
- FIG. 1 is a cross-sectional view of a conventional integrated circuit device that includes a metal-insulator-metal (MIM) capacitor; and
- FIGS. 2-9 are cross sectional views that illustrate integrated circuit devices that comprise a MIM capacitor and methods of forming same in accordance with various embodiments of the present invention.
- FIG. 2 is a cross-sectional view that illustrates integrated circuit devices having a MIM capacitor according to some embodiments of the present invention.
- an interlevel-insulating layer 103 is disposed on, for example, a silicon substrate 101 and has a contact hole 105 formed therein that exposes a portion of the substrate 101 .
- the interlevel-insulating layer 103 may comprise silicon oxide.
- a barrier layer 107 is formed along the sidewalls and bottom of the contact hole 105 to fill a portion thereof.
- the barrier layer 107 may be used to increase adhesion between the barrier layer 107 and a contact plug 119 a , which will be subsequently formed, and to lower contact resistance.
- the barrier layer 107 may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 ⁇ to about 300 ⁇ .
- a contact plug 119 a comprising a metal is disposed in the contact hole 105 .
- a lower electrode 119 b extends from the contact plug 119 a and the contact hole 105 .
- the contact plug 119 a and the lower electrode 119 b comprise a unitary body.
- the contact plug 119 a and the lower electrode 119 b may comprise one or more platinum group metals, such as Pt, Ru, and/or Ir.
- the lower electrode 119 b may be viewed as a stack type electrode.
- the contact plug 119 a filling the contact hole 105 comprises the same metal as the lower electrode 119 b , instead of, for example, TiN. As a result, cracks in the interlevel-insulating layer 103 may be reduced, and a seam may not be created in the contact plug 119 a.
- a lower mold layer pattern 111 a and a wet etch stop pattern 113 a are formed on the interlevel-insulating layer 103 and at both sides of the lower electrode 119 b .
- the lower mold layer pattern 111 a may provide enhanced stability in forming the lower electrode 119 b .
- the wet etch stop pattern 113 a may protect the lower mold layer pattern 111 a and/or the interlevel-insulating layer 103 during manufacturing processing of the capacitor.
- a dielectric layer 121 is formed on the lower electrode 119 b .
- the dielectric layer 121 may comprise Al 2 O 3 , Ta 2 O 5 , TiO, (Ba, Sr)TiO 3 , Pb(Zr, Ti)O 3 , (Pb, La)(Zr, Ti)O 3 , and/or alloys thereof.
- An upper electrode 123 is formed on the dielectric layer 121 .
- the upper electrode 123 may comprise one or more platinum group metals, such as Pt, Ru, and/or Ir.
- a MIM capacitor comprises the lower electrode 119 b , the dielectric layer 121 , and the upper electrode 123 .
- the contact plug 119 a may connect the MIM capacitor to a driving transistor (not shown) allowing charges to accumulate on the MIM capacitor or be discharged from the MIM capacitor.
- FIG. 3 is a cross-sectional view that illustrates integrated circuit devices having a MIM capacitor according to further embodiments of the present invention.
- Embodiments of integrated circuit devices illustrated in FIG. 3 are similar to the integrated circuit device embodiments discussed above with respect to FIG. 2 , with the exception that a barrier layer 207 , which is formed along the sidewalls and the bottom of the contact hole 105 , is thicker than the barrier layer 107 of FIG. 2 , and a lower electrode 219 b of a capacitor is cylindrical.
- the barrier layer 207 may comprise TiN, TiSiN, TIAIN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 ⁇ to about 300 ⁇ .
- a contact plug 219 a may fill the contact hole 105 .
- a lower electrode 219 b extends from the contact plug 219 a and the contact hole 105 . Because the lower electrode 219 b of the MIM capacitor is cylindrical, the capacitance may be increased.
- FIG. 4 is a cross-sectional view that illustrates integrated circuit devices having a MIM capacitor according to further embodiments of the present invention.
- Embodiments of integrated circuit devices illustrated in FIG. 3 are similar to integrated circuit device embodiments discussed above with respect to FIG. 2 , with the exception that the barrier layer 207 , which is formed along the sidewalls and the bottom of the contact hole 105 , is thicker than the barrier layer 107 of FIG. 2 , and a contact plug 319 a and a lower electrode 319 b do not comprise a unitary body.
- the barrier layer 207 may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 ⁇ to about 300 ⁇ .
- FIG. 5 is a cross-sectional view that illustrates integrated circuit devices having a MIM capacitor according to further embodiments of the present invention.
- Embodiments of integrated circuit devices illustrated in FIG. 5 are similar to integrated circuit device embodiments discussed above with respect to FIG. 4 , with the exception that a lower electrode 419 a of the MIM capacitor is cylindrical.
- FIGS. 6A through 6H are cross-sectional views that illustrate operations in fabricating integrated circuit devices having a MIM capacitor according to some embodiments of the present invention described above with reference to FIG. 2 .
- an interlevel-insulating layer 103 is formed on a substrate 101 , which may comprise silicon.
- the interlevel-insulating layer 103 may comprise silicon oxide.
- the interlevel-insulating layer 103 is patterned by photolithography to form a first contact hole 105 .
- a barrier layer 107 is formed on the surface of the semiconductor substrate 101 .
- a barrier layer 107 is formed along the sidewalls and bottom of the first contact hole 105 and on the interlevel-insulating layer 103 without filling the first contact hole 105 .
- the barrier layer 107 may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 ⁇ to about 300 ⁇ .
- a first sacrificial layer 109 is formed on the surface of the substrate 101 to fill the first contact hole 105 .
- the first sacrificial layer 109 fills the first contact hole 105 and is formed on the interlevel-insulating layer 103 .
- the first sacrificial layer 109 may be a flowable oxide layer.
- the first sacrificial layer 109 is planarized using the upper surface of the interlevel-insulating layer 103 as an etch stop, leaving the first sacrificial layer 109 in the first contact hole 105 .
- the planarization of the first sacrificial layer 109 may be performed by CMP (Chemical Mechanical Polishing).
- the barrier layer 107 on the interlevel-insulating layer 103 may also etched during planarization of the first sacrificial layer 109 . In other words, the barrier layer 107 may remain only along the sidewalls and bottom of the first contact hole 105 . Thus, a barrier layer in one cell may be separated from a barrier layer in another cell.
- a lower mold layer 111 is formed on the first sacrificial layer 109 and the interlevel-insulating layer 103 .
- the lower mold layer 111 may comprise silicon oxide.
- the lower mold layer 111 may allow a lower electrode of the MIM capacitor to be formed with improved stability subsequently.
- a wet etch stop layer 113 is formed on the lower mold layer 111 .
- the wet etch stop layer 113 may protect the lower mold layer 111 and/or the interlevel-insulating layer 103 from manufacturing processes.
- the wet etch stop layer 113 may comprise silicon oxide, tantalum oxide, and/or combinations thereof.
- An upper mold layer 115 is formed on the wet etch stop layer 113 .
- the upper mold layer 115 may comprise silicon oxide.
- the upper mold layer 115 , the wet etch stop layer 113 , and the lower mold layer 111 are patterned to form a second contact hole 117 exposing an upper surface of the first sacrificial layer 109 .
- an upper mold layer pattern 115 a , a wet etch stop layer pattern 113 a , and a lower mold layer pattern 111 a are formed on the interlevel-insulating layer 103 .
- the first sacrificial layer 109 in the first contact hole 105 is removed by wet etching. Because the first sacrificial layer 109 in the first contact hole 105 is a flowable oxide layer, it may be etched faster than the interlevel-insulating layer 103 and the lower and upper mold layers 111 and 115 . Thus, the first sacrificial layer 109 in the first contact hole 105 may be removed with minimal damage to the interlevel-insulating layer 103 and/or the lower and upper mold layers 111 and 115 . As a result, the barrier layer 107 in the first contact hole 105 is exposed.
- a metal layer is formed on the substrate in the first and second contact holes 105 and 117 and then the metal layer is reflowed using a high thermal treatment to form a contact plug 119 a , which fills the first contact hole 105 .
- the formation and reflow of the metal layer using a thermal treatment may inhibit a seam from occurring in the metal layer due to poor step coverage when the metal layer is formed.
- the contact plug 119 a may comprise a platinum group metal, such as Pt, Ru, and/or Ir.
- the second contact hole 117 is filled with the same metal filling the first contact hole 105 to form a lower electrode 119 b of a stack type capacitor.
- the lower electrode 119 b may comprise a platinum group metal, such as Pt, Ru, and/or Ir.
- the contact plug 119 a and the lower electrode 119 b comprise a unitary body and fill the first and second contact holes 105 and 117 .
- the upper mold layer pattern 115 a is removed by wet etching using the wet etch stop pattern 113 a as an etch stop.
- the wet etching of the upper mold layer pattern 115 may be performed for a few tens to hundreds of seconds using an oxide etchant, e.g., a buffered oxide etchant.
- a dielectric layer 121 is formed on the surface of the semiconductor substrate 101 .
- the dielectric layer 121 may comprise Al 2 O 3 , Ta 2 O 5 , TiO, (Ba, Sr)TiO 3 , Pb(Zr, Ti)O 3 , and/or (Pb, La)(Zr, Ti)O 3 .
- An upper electrode 123 comprising a metal is formed on the dielectric layer 121 to complete an integrated circuit device having a MIM capacitor.
- the upper electrode 123 may comprise a platinum group metal, such as Pt, Ru, and/or Ir.
- FIGS. 7A through 7C are cross-sectional views that illustrate operations in fabricating integrated circuit devices having a MIM capacitor according to some embodiments of the present invention described above with reference to FIG. 3 .
- Methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated in FIG. 3 are similar to methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated in FIG. 2 , with the exception that a barrier layer 207 , which is formed along the sidewalls and the bottom of the contact hole 105 , is thicker than the barrier layer 107 of FIG. 2 , and a lower electrode 219 b of a capacitor is cylindrical.
- the barrier layer 207 may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 ⁇ to about 300 ⁇ .
- a metal layer 219 is formed on the substrate 101 on which the barrier layer 207 is formed along the sidewalls and bottom of the first contact hole 105 to fill the first contact hole 105 .
- the metal layer 219 is used as a contact plug and a lower electrode.
- the metal layer 219 is formed along the sidewalls and bottom of the second contact hole 117 and on the surface of the upper mold layer pattern 115 a to fill the first contact hole 105 , but not the second contact hole 117 .
- a second sacrificial layer 223 is formed on the substrate 101 on which the metal layer 219 is formed to fill the second contact hole 117 .
- the second sacrificial layer 223 may comprise a flowable oxide.
- the second sacrificial layer 223 is patterned using the upper mold layer pattern 115 a as an etch stop to leave the second sacrificial layer 223 only in the second contact hole 117 .
- the metal layer 219 on the upper mold layer pattern 115 a is etched and the second sacrificial layer 223 is planarized using CMP.
- a contact plug 219 a is formed that fills the first contact hole 105
- a lower electrode 219 b of a capacitor having a cylindrical shape is formed along the sidewalls and bottom of the second contact hole 117 .
- the second sacrificial layer 223 left in the second contact hole 117 is removed.
- the upper mold layer pattern 115 is removed using the wet etch stop pattern 111 a as an etch stop. Because the second sacrificial layer 223 left in the second contact hole 117 comprises a flowable oxide, the upper mold layer pattern 115 a and the second sacrificial layer 223 may be simultaneously etched.
- a dielectric layer 121 and an upper electrode 123 are formed on the substrate 101 on which the lower electrode 219 b is formed, thereby completing a semiconductor device having a MIM capacitor.
- FIGS. 8A through 8F are cross-sectional views that illustrate operations in fabricating integrated circuit devices having a MIM capacitor according to some embodiments of the present invention described above with reference to FIG. 4 .
- Methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated in FIG. 4 are similar to methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated in FIG. 2 , with the exception that the barrier layer 207 , which is formed along the sidewalls and the bottom of the contact hole 105 , is thicker than the barrier layer 107 of FIG. 2 , and a contact plug 319 a and a lower electrode 319 b do not comprise a unitary body.
- an interlevel-insulating layer 103 is formed on a semiconductor substrate 101 , which may comprise silicon.
- the interlevel-insulating layer 103 may comprise silicon oxide.
- the interlevel-insulating layer 103 is patterned by photolithography to form a first contact hole 105 .
- a barrier layer 207 is formed on the semiconductor substrate 101 in which the first contact hole 105 is formed.
- the barrier layer 207 which is thicker than the barrier layer 107 shown in FIG. 6A , is formed along the sidewalls and bottom of the first contact hole 105 and on the interlevel-insulating layer 103 without filling the first contact hole 105 .
- the barrier layer 207 may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 ⁇ to about 300 ⁇ .
- a metal layer 319 for a contact plug is formed on the surface of the semiconductor substrate to fill the first contact hole 105 .
- the metal layer 319 for a contact plug may comprise a platinum group metal, such as Pt, Ru, and/or Ir.
- the metal layer 0 . 319 for a contact plug and the barrier layer 207 are planarized using the interlevel-insulating layer 103 as an etch stop.
- the planarization of the metal layer 319 for a contact plug and the barrier layer 207 may be performed using CMP.
- the barrier layer 207 remains along the sidewalls and bottom of the first contact hole 105 .
- a contact plug 319 a is formed in the first contact hole 105 on the barrier layer 207 .
- a lower mold layer 111 , a wet etch stop layer 113 , and an upper mold layer 115 are formed on the contact plug 319 a , the barrier layer 207 , and the interlevel-insulating layer 103 .
- the lower mold layer 111 , the wet etch stop layer 113 , and the upper mold layer 115 may comprise the same materials and perform the same functions as described above with reference to FIG. 6D .
- the upper mold layer 115 , the wet etch stop layer 113 , and the lower mold layer 111 are patterned to form a second contact hole 117 that exposes the upper surface of the contact plug 319 a and the barrier layer 207 .
- an upper mold layer pattern 115 a , a wet etch stop pattern 113 a , and a lower mold layer pattern 111 a are formed on the interlevel-insulating layer 103 .
- the second contact plug 117 is filled with the same metal as the contact plug 319 a to form a lower electrode 319 b of a stack type capacitor.
- the metal used to form the lower electrode 319 b may comprise a platinum group metal, such as Pt, Ru, and/or Ir.
- the contact plug 319 a and the lower electrode 319 b fill the first and second contact holes 105 and 117 .
- the upper mold layer pattern 115 a is removed by wet etching using the wet etch stop pattern 113 a as an etch stop as shown in FIG. 6H .
- a dielectric layer 121 and an upper electrode 123 are formed on the semiconductor substrate 101 on which the lower electrode 319 b is formed, thereby completing a semiconductor device having a MIM capacitor.
- FIGS. 9A through 9C are cross-sectional views that illustrate operations in fabricating integrated circuit devices having a MIM capacitor according to some embodiments of the present invention described above with reference to FIG. 5 .
- Methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated in FIG. 5 are similar to methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated in FIG. 4 , with the exception that a lower electrode 419 a of the MIM capacitor is cylindrical.
- a metal layer 419 for a lower electrode is formed on the substrate 101 on which a second contact hole 117 is formed to expose upper surfaces of a contact plug 319 a and a barrier layer 207 .
- the metal layer 419 is formed along the sidewalls and bottom of the second contact hole 117 and on an upper mold layer pattern 115 a , but does not fill the second contact hole 117 .
- a sacrificial layer 421 is formed on the surface of the substrate 101 to fill the second contact hole 117 .
- the sacrificial layer 421 may comprise a flowable oxide.
- the sacrificial layer 421 is planarized using the upper mold layer pattern 115 a as an etch stop so that the sacrificial layer 421 remains only in the second contact hole 117 .
- the metal layer 419 on the upper mold layer pattern 115 a is etched and the sacrificial layer 421 is planarized using CMP. As a result, a lower electrode 419 a is formed along the sidewalls and bottom of the second contact hole 117 .
- the sacrificial layer 421 remaining in the second contact hole 117 is removed.
- the upper mold layer pattern 115 a is removed using the wet etch stop pattern 113 a as an etch stop. Because the sacrificial layer 421 remaining in the second contact hole 117 is flowable oxide, the upper mold layer pattern 115 a and the sacrificial layer 421 may be simultaneously etched. As shown in FIG. 5 , a dielectric layer 121 and an upper electrode 123 are formed on the substrate 101 on which the lower electrode 419 a is formed, thereby completing a semiconductor device having a MIM capacitor.
- a contact plug filling a contact hole may comprise a metal as a lower electrode instead of TiN.
- a barrier layer may be formed along the sidewalls and bottom of the contact hole to increase adhesion between the barrier layer and the contact plug and to reduce contact resistance.
Abstract
In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.
Description
- This application claims the benefit of Korean Patent Application No. 2001-0030529, filed May 31, 2001, the disclosure of which is hereby incorporated herein by reference.
- The present invention relates generally to integrated circuit devices, and, more particularly, to integrated circuit capacitors and methods of forming same.
- In general, as the integration density of integrated circuit devices increases, conventional metal-insulator-semiconductor (MIS) capacitors may have relatively low dielectrics so that they may not provide desired capacitance values. As a result, metal-insulator-metal (MIM) capacitors may be used to replace MIS capacitors.
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FIG. 1 is a cross-sectional view of a conventional integrated circuit device that comprises a MIM capacitor. As shown inFIG. 1 , acontact plug 15 is formed in an interlevel-insulating layer 13 on asubstrate 11, e.g., a silicon substrate. Thecontact plug 15 may comprise a TiN layer and may be used as a barrier layer. AMIM capacitor 23 is formed on thecontact plug 15. Thecontact plug 15 may connect theMIM capacitor 23 to a driving transistor (not shown) allowing charges to accumulate on theMIM capacitor 23 or be discharged from theMIM capacitor 23. TheMIM capacitor 23 comprises alower electrode 17, adielectric layer 19, and anupper electrode 21. Thelower electrode 17 and theupper electrode 21 may comprise a metal, such as Pt or Ru, and thedielectric layer 19 may comprise Ta2O5. - Unfortunately, cracks may occur in the interlevel-insulating layer 13 due to stress generated during the deposition of the TiN layer, i.e., the
contact plug 15. Also, due to generally poor step coverage of the TiN layer, a seam may occur in the TiN layer if the TiN layer is deposited and then planarized by chemical mechanical polishing (CMP). - According to some embodiments of the present invention, an integrated circuit device comprises a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. Because the lower electrode and the contact plug comprise a unitary body, cracks in the interlevel-insulating layer may be reduced and a seam may not be created in the contact plug.
- In other embodiments of the present invention, a barrier layer is disposed between the contact portion of the lower electrode and both the substrate and sidewalls of the interlevel-insulating layer. The barrier layer may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 Å to about 300 Å.
- In still other embodiments, the lower electrode of the capacitor is cylindrical and the barrier layer has a thickness in a range of about 30 Å to about 300 Å.
- In further embodiments of the present invention, a mold layer, which may comprise silicon oxide, is on the interlevel-insulating layer that has an opening therein through which the lower electrode of the capacitor is received. An etch stop layer may also be on the mold layer and have an opening therein through which the lower electrode of the capacitor is received. The etch stop layer may comprise silicon oxide and/or tantalum oxide.
- In still further embodiments, the dielectric layer may comprise may comprise Al2O3, Ta2O5, TiO, (Ba, Sr)TiO3, Pb(Zr, Ti)O3, (Pb, La)(Zr, Ti)O3, and/or alloys thereof and the upper and lower electrodes of the capacitor may comprise one or more platinum group metals, such as Pt, Ru, and Ir.
- In other embodiments of the present invention, an integrated circuit device comprises a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. Advantageously, the barrier layer may increase adhesion with the contact plug and may also reduce contact resistance. In particular embodiments, the barrier layer may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 Å to about 300 Å.
- Although described above primarily with respect to device embodiments, the present invention may also be embodied as methods of forming integrated circuit devices.
- Other features of the present invention will be more readily understood from the following detailed description of specific embodiments thereof when read in conjunction with the accompanying drawings, in which:
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FIG. 1 is a cross-sectional view of a conventional integrated circuit device that includes a metal-insulator-metal (MIM) capacitor; and -
FIGS. 2-9 are cross sectional views that illustrate integrated circuit devices that comprise a MIM capacitor and methods of forming same in accordance with various embodiments of the present invention. - While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Like numbers refer to like elements throughout the description of the figures. In the figures, the dimensions of layers and regions are exaggerated for clarity. It will also be understood that when an element, such as a layer, region, or substrate, is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element, such as a layer, region, or substrate, is referred to as being “directly on” another element, there are no intervening elements present.
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FIG. 2 is a cross-sectional view that illustrates integrated circuit devices having a MIM capacitor according to some embodiments of the present invention. As shown inFIG. 2 , an interlevel-insulatinglayer 103 is disposed on, for example, asilicon substrate 101 and has acontact hole 105 formed therein that exposes a portion of thesubstrate 101. The interlevel-insulating layer 103 may comprise silicon oxide. Abarrier layer 107 is formed along the sidewalls and bottom of thecontact hole 105 to fill a portion thereof. Thebarrier layer 107 may be used to increase adhesion between thebarrier layer 107 and acontact plug 119 a, which will be subsequently formed, and to lower contact resistance. Thebarrier layer 107 may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 Å to about 300 Å. - A
contact plug 119 a comprising a metal is disposed in thecontact hole 105. Moreover, alower electrode 119 b extends from thecontact plug 119 a and thecontact hole 105. Thus, thecontact plug 119 a and thelower electrode 119 b comprise a unitary body. Thecontact plug 119 a and thelower electrode 119 b may comprise one or more platinum group metals, such as Pt, Ru, and/or Ir. Thelower electrode 119 b may be viewed as a stack type electrode. Advantageously, thecontact plug 119 a filling thecontact hole 105 comprises the same metal as thelower electrode 119 b, instead of, for example, TiN. As a result, cracks in the interlevel-insulatinglayer 103 may be reduced, and a seam may not be created in thecontact plug 119 a. - A lower
mold layer pattern 111 a and a wetetch stop pattern 113 a are formed on the interlevel-insulatinglayer 103 and at both sides of thelower electrode 119 b. The lowermold layer pattern 111 a may provide enhanced stability in forming thelower electrode 119 b. The wetetch stop pattern 113 a may protect the lowermold layer pattern 111 a and/or the interlevel-insulatinglayer 103 during manufacturing processing of the capacitor. - A
dielectric layer 121 is formed on thelower electrode 119 b. Thedielectric layer 121 may comprise Al2O3, Ta2O5, TiO, (Ba, Sr)TiO3, Pb(Zr, Ti)O3, (Pb, La)(Zr, Ti)O3, and/or alloys thereof. Anupper electrode 123 is formed on thedielectric layer 121. Theupper electrode 123 may comprise one or more platinum group metals, such as Pt, Ru, and/or Ir. Thus, a MIM capacitor, according to some embodiments of the present invention, comprises thelower electrode 119 b, thedielectric layer 121, and theupper electrode 123. Thecontact plug 119 a may connect the MIM capacitor to a driving transistor (not shown) allowing charges to accumulate on the MIM capacitor or be discharged from the MIM capacitor. -
FIG. 3 is a cross-sectional view that illustrates integrated circuit devices having a MIM capacitor according to further embodiments of the present invention. Embodiments of integrated circuit devices illustrated inFIG. 3 are similar to the integrated circuit device embodiments discussed above with respect toFIG. 2 , with the exception that abarrier layer 207, which is formed along the sidewalls and the bottom of thecontact hole 105, is thicker than thebarrier layer 107 ofFIG. 2 , and alower electrode 219 b of a capacitor is cylindrical. Thebarrier layer 207 may comprise TiN, TiSiN, TIAIN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 Å to about 300 Å. Similar to the description above with respect toFIG. 2 , acontact plug 219 a may fill thecontact hole 105. Alower electrode 219 b extends from the contact plug 219 a and thecontact hole 105. Because thelower electrode 219 b of the MIM capacitor is cylindrical, the capacitance may be increased. -
FIG. 4 is a cross-sectional view that illustrates integrated circuit devices having a MIM capacitor according to further embodiments of the present invention. Embodiments of integrated circuit devices illustrated inFIG. 3 are similar to integrated circuit device embodiments discussed above with respect toFIG. 2 , with the exception that thebarrier layer 207, which is formed along the sidewalls and the bottom of thecontact hole 105, is thicker than thebarrier layer 107 ofFIG. 2 , and acontact plug 319 a and alower electrode 319 b do not comprise a unitary body. Thebarrier layer 207 may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 Å to about 300 Å. -
FIG. 5 is a cross-sectional view that illustrates integrated circuit devices having a MIM capacitor according to further embodiments of the present invention. Embodiments of integrated circuit devices illustrated inFIG. 5 are similar to integrated circuit device embodiments discussed above with respect toFIG. 4 , with the exception that alower electrode 419 a of the MIM capacitor is cylindrical. - Methods of fabricating integrated circuit devices having a MIM capacitor, in accordance with various embodiments of the present invention, will now be described.
FIGS. 6A through 6H are cross-sectional views that illustrate operations in fabricating integrated circuit devices having a MIM capacitor according to some embodiments of the present invention described above with reference toFIG. 2 . Referring now toFIG. 6A , an interlevel-insulatinglayer 103 is formed on asubstrate 101, which may comprise silicon. The interlevel-insulatinglayer 103 may comprise silicon oxide. The interlevel-insulatinglayer 103 is patterned by photolithography to form afirst contact hole 105. Abarrier layer 107 is formed on the surface of thesemiconductor substrate 101. Abarrier layer 107 is formed along the sidewalls and bottom of thefirst contact hole 105 and on the interlevel-insulatinglayer 103 without filling thefirst contact hole 105. Thebarrier layer 107 may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 Å to about 300 Å. - Referring now to
FIGS. 6B and 6C , a firstsacrificial layer 109 is formed on the surface of thesubstrate 101 to fill thefirst contact hole 105. In other words, the firstsacrificial layer 109 fills thefirst contact hole 105 and is formed on the interlevel-insulatinglayer 103. The firstsacrificial layer 109 may be a flowable oxide layer. - The first
sacrificial layer 109 is planarized using the upper surface of the interlevel-insulatinglayer 103 as an etch stop, leaving the firstsacrificial layer 109 in thefirst contact hole 105. The planarization of the firstsacrificial layer 109 may be performed by CMP (Chemical Mechanical Polishing). Thebarrier layer 107 on the interlevel-insulatinglayer 103 may also etched during planarization of the firstsacrificial layer 109. In other words, thebarrier layer 107 may remain only along the sidewalls and bottom of thefirst contact hole 105. Thus, a barrier layer in one cell may be separated from a barrier layer in another cell. - Referring to
FIG. 6D , alower mold layer 111 is formed on the firstsacrificial layer 109 and the interlevel-insulatinglayer 103. Thelower mold layer 111 may comprise silicon oxide. Thelower mold layer 111 may allow a lower electrode of the MIM capacitor to be formed with improved stability subsequently. - A wet
etch stop layer 113 is formed on thelower mold layer 111. The wetetch stop layer 113 may protect thelower mold layer 111 and/or the interlevel-insulatinglayer 103 from manufacturing processes. The wetetch stop layer 113 may comprise silicon oxide, tantalum oxide, and/or combinations thereof. Anupper mold layer 115 is formed on the wetetch stop layer 113. Theupper mold layer 115 may comprise silicon oxide. - Referring now to
FIG. 6E , theupper mold layer 115, the wetetch stop layer 113, and thelower mold layer 111 are patterned to form asecond contact hole 117 exposing an upper surface of the firstsacrificial layer 109. Thus, an uppermold layer pattern 115 a, a wet etchstop layer pattern 113 a, and a lowermold layer pattern 111 a are formed on the interlevel-insulatinglayer 103. - The first
sacrificial layer 109 in thefirst contact hole 105 is removed by wet etching. Because the firstsacrificial layer 109 in thefirst contact hole 105 is a flowable oxide layer, it may be etched faster than the interlevel-insulatinglayer 103 and the lower and upper mold layers 111 and 115. Thus, the firstsacrificial layer 109 in thefirst contact hole 105 may be removed with minimal damage to the interlevel-insulatinglayer 103 and/or the lower and upper mold layers 111 and 115. As a result, thebarrier layer 107 in thefirst contact hole 105 is exposed. - Referring now to
FIG. 6F , a metal layer is formed on the substrate in the first and second contact holes 105 and 117 and then the metal layer is reflowed using a high thermal treatment to form acontact plug 119 a, which fills thefirst contact hole 105. The formation and reflow of the metal layer using a thermal treatment may inhibit a seam from occurring in the metal layer due to poor step coverage when the metal layer is formed. Thecontact plug 119 a may comprise a platinum group metal, such as Pt, Ru, and/or Ir. - Referring now to
FIG. 6G , thesecond contact hole 117 is filled with the same metal filling thefirst contact hole 105 to form alower electrode 119 b of a stack type capacitor. Thelower electrode 119 b may comprise a platinum group metal, such as Pt, Ru, and/or Ir. As a result, the contact plug 119 a and thelower electrode 119 b comprise a unitary body and fill the first and second contact holes 105 and 117. - Referring to
FIG. 6H , the uppermold layer pattern 115 a is removed by wet etching using the wetetch stop pattern 113 a as an etch stop. The wet etching of the uppermold layer pattern 115 may be performed for a few tens to hundreds of seconds using an oxide etchant, e.g., a buffered oxide etchant. - Next, as shown in
FIG. 2 , adielectric layer 121 is formed on the surface of thesemiconductor substrate 101. Thedielectric layer 121 may comprise Al2O3, Ta2O5, TiO, (Ba, Sr)TiO3, Pb(Zr, Ti)O3, and/or (Pb, La)(Zr, Ti)O3. Anupper electrode 123 comprising a metal is formed on thedielectric layer 121 to complete an integrated circuit device having a MIM capacitor. Theupper electrode 123 may comprise a platinum group metal, such as Pt, Ru, and/or Ir. -
FIGS. 7A through 7C are cross-sectional views that illustrate operations in fabricating integrated circuit devices having a MIM capacitor according to some embodiments of the present invention described above with reference toFIG. 3 . Methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated inFIG. 3 are similar to methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated inFIG. 2 , with the exception that abarrier layer 207, which is formed along the sidewalls and the bottom of thecontact hole 105, is thicker than thebarrier layer 107 ofFIG. 2 , and alower electrode 219 b of a capacitor is cylindrical. Thebarrier layer 207 may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 Å to about 300 Å. - First, the operations described above with reference to
FIGS. 6A through 6E are performed. Referring now toFIG. 7A , ametal layer 219 is formed on thesubstrate 101 on which thebarrier layer 207 is formed along the sidewalls and bottom of thefirst contact hole 105 to fill thefirst contact hole 105. Themetal layer 219 is used as a contact plug and a lower electrode. Themetal layer 219 is formed along the sidewalls and bottom of thesecond contact hole 117 and on the surface of the uppermold layer pattern 115 a to fill thefirst contact hole 105, but not thesecond contact hole 117. A secondsacrificial layer 223 is formed on thesubstrate 101 on which themetal layer 219 is formed to fill thesecond contact hole 117. The secondsacrificial layer 223 may comprise a flowable oxide. - Referning now to
FIG. 7B , the secondsacrificial layer 223 is patterned using the uppermold layer pattern 115 a as an etch stop to leave the secondsacrificial layer 223 only in thesecond contact hole 117. Themetal layer 219 on the uppermold layer pattern 115 a is etched and the secondsacrificial layer 223 is planarized using CMP. As a result, acontact plug 219 a is formed that fills thefirst contact hole 105, and alower electrode 219 b of a capacitor having a cylindrical shape is formed along the sidewalls and bottom of thesecond contact hole 117. - Referring now to
FIG. 7C , the secondsacrificial layer 223 left in thesecond contact hole 117 is removed. The uppermold layer pattern 115 is removed using the wetetch stop pattern 111 a as an etch stop. Because the secondsacrificial layer 223 left in thesecond contact hole 117 comprises a flowable oxide, the uppermold layer pattern 115 a and the secondsacrificial layer 223 may be simultaneously etched. - As shown in
FIG. 3 , adielectric layer 121 and anupper electrode 123 are formed on thesubstrate 101 on which thelower electrode 219 b is formed, thereby completing a semiconductor device having a MIM capacitor. -
FIGS. 8A through 8F are cross-sectional views that illustrate operations in fabricating integrated circuit devices having a MIM capacitor according to some embodiments of the present invention described above with reference toFIG. 4 . Methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated inFIG. 4 are similar to methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated inFIG. 2 , with the exception that thebarrier layer 207, which is formed along the sidewalls and the bottom of thecontact hole 105, is thicker than thebarrier layer 107 ofFIG. 2 , and acontact plug 319 a and alower electrode 319 b do not comprise a unitary body. - Referring now to
FIG. 8A , an interlevel-insulatinglayer 103 is formed on asemiconductor substrate 101, which may comprise silicon. The interlevel-insulatinglayer 103 may comprise silicon oxide. The interlevel-insulatinglayer 103 is patterned by photolithography to form afirst contact hole 105. - A
barrier layer 207 is formed on thesemiconductor substrate 101 in which thefirst contact hole 105 is formed. Thebarrier layer 207, which is thicker than thebarrier layer 107 shown inFIG. 6A , is formed along the sidewalls and bottom of thefirst contact hole 105 and on the interlevel-insulatinglayer 103 without filling thefirst contact hole 105. Thebarrier layer 207 may comprise TiN, TiSiN, TiAlN, TaN, TaSiN, TaAlN, and/or alloys thereof, and may have a thickness in a range of about 30 Å to about 300 Å. Ametal layer 319 for a contact plug is formed on the surface of the semiconductor substrate to fill thefirst contact hole 105. Themetal layer 319 for a contact plug may comprise a platinum group metal, such as Pt, Ru, and/or Ir. - Referring now to
FIG. 8B , the metal layer 0.319 for a contact plug and thebarrier layer 207 are planarized using the interlevel-insulatinglayer 103 as an etch stop. The planarization of themetal layer 319 for a contact plug and thebarrier layer 207 may be performed using CMP. Thebarrier layer 207 remains along the sidewalls and bottom of thefirst contact hole 105. Acontact plug 319 a is formed in thefirst contact hole 105 on thebarrier layer 207. Thus, a barrier layer and a contact plug in one cell are separated from a barrier layer and a contact plug in another cell. - Referring now to
FIG. 8C , alower mold layer 111, a wetetch stop layer 113, and anupper mold layer 115 are formed on the contact plug 319 a, thebarrier layer 207, and the interlevel-insulatinglayer 103. Thelower mold layer 111, the wetetch stop layer 113, and theupper mold layer 115 may comprise the same materials and perform the same functions as described above with reference toFIG. 6D . - Referring now to
FIG. 8D , theupper mold layer 115, the wetetch stop layer 113, and thelower mold layer 111 are patterned to form asecond contact hole 117 that exposes the upper surface of the contact plug 319 a and thebarrier layer 207. Thus, an uppermold layer pattern 115 a, a wetetch stop pattern 113 a, and a lowermold layer pattern 111 a are formed on the interlevel-insulatinglayer 103. - Referring now to
FIG. 8E , thesecond contact plug 117 is filled with the same metal as the contact plug 319 a to form alower electrode 319 b of a stack type capacitor. The metal used to form thelower electrode 319 b may comprise a platinum group metal, such as Pt, Ru, and/or Ir. As a result, the contact plug 319 a and thelower electrode 319 b fill the first and second contact holes 105 and 117. - Referring now to
FIG. 8F , the uppermold layer pattern 115 a is removed by wet etching using the wetetch stop pattern 113 a as an etch stop as shown inFIG. 6H . As shown inFIG. 4 , adielectric layer 121 and anupper electrode 123 are formed on thesemiconductor substrate 101 on which thelower electrode 319 b is formed, thereby completing a semiconductor device having a MIM capacitor. -
FIGS. 9A through 9C are cross-sectional views that illustrate operations in fabricating integrated circuit devices having a MIM capacitor according to some embodiments of the present invention described above with reference toFIG. 5 . Methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated inFIG. 5 are similar to methods of fabricating an integrated circuit device according to embodiments of the present invention illustrated inFIG. 4 , with the exception that alower electrode 419 a of the MIM capacitor is cylindrical. - First, the operations described above with reference to
FIGS. 8A through 8D are performed. Referring now toFIG. 9A , ametal layer 419 for a lower electrode is formed on thesubstrate 101 on which asecond contact hole 117 is formed to expose upper surfaces of acontact plug 319 a and abarrier layer 207. Themetal layer 419 is formed along the sidewalls and bottom of thesecond contact hole 117 and on an uppermold layer pattern 115 a, but does not fill thesecond contact hole 117. Asacrificial layer 421 is formed on the surface of thesubstrate 101 to fill thesecond contact hole 117. Thesacrificial layer 421 may comprise a flowable oxide. - Referring now to
FIG. 9B , thesacrificial layer 421 is planarized using the uppermold layer pattern 115 a as an etch stop so that thesacrificial layer 421 remains only in thesecond contact hole 117. Themetal layer 419 on the uppermold layer pattern 115 a is etched and thesacrificial layer 421 is planarized using CMP. As a result, alower electrode 419 a is formed along the sidewalls and bottom of thesecond contact hole 117. - Referring now to
FIG. 9C , thesacrificial layer 421 remaining in thesecond contact hole 117 is removed. The uppermold layer pattern 115 a is removed using the wetetch stop pattern 113 a as an etch stop. Because thesacrificial layer 421 remaining in thesecond contact hole 117 is flowable oxide, the uppermold layer pattern 115 a and thesacrificial layer 421 may be simultaneously etched. As shown inFIG. 5 , adielectric layer 121 and anupper electrode 123 are formed on thesubstrate 101 on which thelower electrode 419 a is formed, thereby completing a semiconductor device having a MIM capacitor. - As described above, in integrated circuit devices according to embodiments of the present invention, a contact plug filling a contact hole may comprise a metal as a lower electrode instead of TiN. As a result, cracks in an interlevel-insulating layer may be reduced and a seam in the contact plug may be avoided. Moreover, a barrier layer may be formed along the sidewalls and bottom of the contact hole to increase adhesion between the barrier layer and the contact plug and to reduce contact resistance.
- In concluding the detailed description, it should be noted that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims.
Claims (24)
1. An integrated circuit device, comprising:
a substrate;
an interlevel-insulating layer on the substrate having a hole therein that exposes the substrate;
a unitary lower electrode of a capacitor disposed on the substrate that has a contact plug portion thereof that is disposed in the hole;
a dielectric layer on the lower electrode of the capacitor; and
an upper electrode of the capacitor on the dielectric layer.
2. The integrated circuit device of claim 1 , further comprising:
a barrier layer between the contact plug portion of the lower electrode of the capacitor and both the substrate and sidewalls of the interlevel-insulating layer.
3. The integrated circuit device of claim 2 , wherein the barrier layer has a thickness in a range of about 30 Å to about 300 Å.
4. The integrated circuit device of claim 2 , wherein the barrier layer comprises a material that is selected from the group of materials consisting of TiN, TiSiN, TiAlN, TaN, TaSiN, and TaAlN.
5. The integrated circuit device of claim 2 , wherein the lower electrode of the capacitor is cylindrical.
6. The integrated circuit device of claim 5 , wherein the barrier layer has a thickness in a range of about 30 Å to about 300 Å.
7. The integrated circuit device of claim 1 , further comprising:
a mold layer on the interlevel-insulating layer that has an opening therein through which the lower electrode of the capacitor is received.
8. The integrated circuit device of claim 7 , wherein the mold layer comprises silicon oxide.
9. The integrated circuit device of claim 7 , further comprising:
an etch stop layer on the mold layer that has an opening therein through which the lower electrode of the capacitor is received.
10. The integrated circuit device of claim 9 , wherein the etch stop layer comprises a material selected from the group of materials consisting of silicon oxide, and tantalum oxide.
11. The integrated circuit device of claim 1 , wherein the dielectric layer comprises a material selected from the group of materials consisting of Al2O3, Ta2O5, TiO, (Ba, Sr)TiO3, Pb(Zr, Ti)O3, and (Pb, La)(Zr, Ti)O3.
12. The integrated circuit device of claim 1 , wherein the upper and lower electrodes of the capacitor comprise a material selected from the group of materials consisting of Pt, Ru, and Ir.
13. An integrated circuit device, comprising:
a substrate;
an interlevel-insulating layer on the substrate having a hole therein that exposes the substrate;
a barrier layer on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer;
a contact plug disposed in the hole on the barrier layer;
a lower electrode of a capacitor disposed on the contact plug and that engages the contact plug at a boundary therebetween;
a dielectric layer on the lower electrode of the capacitor; and
an upper electrode of the capacitor on the dielectric layer.
14. The integrated circuit device of claim 13 , wherein the barrier layer has a thickness in a range of about 30 Å to about 300 Å.
15. The integrated circuit device of claim 13 , wherein the barrier layer comprises a material that is selected from the group of materials consisting of TiN, TiSiN, TiAlN, TaN, TaSiN, and TaAlN.
16. The integrated circuit device of claim 13 , wherein the lower electrode of the capacitor is cylindrical.
17. The integrated circuit device of claim 16 , wherein the barrier layer has a thickness in a range of about 30 Å to about 300 Å.
18. The integrated circuit device of claim 13 , further comprising:
a mold layer on the interlevel-insulating layer that has an opening therein through which the lower electrode of the capacitor is received.
19. The integrated circuit device of claim 18 , wherein the mold layer comprises silicon oxide.
20. The integrated circuit device of claim 18 , further comprising:
an etch stop layer on the mold layer that has an opening therein through which the lower electrode of the capacitor is received.
21. The integrated circuit device of claim 20 , wherein the etch stop layer comprises a material selected from the group of materials consisting of silicon oxide, and tantalum oxide.
22. The integrated circuit device of claim 13 , wherein the dielectric layer comprises a material selected from the group of materials consisting of Al2O3, Ta2O5, TiO, (Ba, Sr)TiO3, Pb(Zr, Ti)O3, and (Pb, La)(Zr, Ti)O3.
23. The integrated circuit device of claim 13 , wherein the upper and lower electrodes of the capacitor and the contact plug comprise a material selected from the group of materials consisting of Pt, Ru, and Ir.
24-38. (canceled)
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US12/270,286 US7781819B2 (en) | 2001-05-31 | 2008-11-13 | Semiconductor devices having a contact plug and fabrication methods thereof |
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KR2001-0030529 | 2001-05-31 | ||
KR10-2001-0030529A KR100408410B1 (en) | 2001-05-31 | 2001-05-31 | Semiconductor device having MIM capacitor and fabrication method thereof |
US10/160,646 US6884673B2 (en) | 2001-05-31 | 2002-05-31 | Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor |
US11/083,874 US20050161727A1 (en) | 2001-05-31 | 2005-03-18 | Integrated circuit devices having a metal-insulator-metal (MIM) capacitor |
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US12/270,286 Continuation-In-Part US7781819B2 (en) | 2001-05-31 | 2008-11-13 | Semiconductor devices having a contact plug and fabrication methods thereof |
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US11/083,874 Abandoned US20050161727A1 (en) | 2001-05-31 | 2005-03-18 | Integrated circuit devices having a metal-insulator-metal (MIM) capacitor |
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US20090072350A1 (en) * | 2001-05-31 | 2009-03-19 | Samsung Electronics Co., Ltd. | Semiconductor devices having a contact plug and fabrication methods thereof |
US9153499B2 (en) | 2011-05-24 | 2015-10-06 | Samsung Electronics Co., Ltd. | Semiconductor device having metal plug and method of forming the same |
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KR100881728B1 (en) | 2007-05-04 | 2009-02-06 | 주식회사 하이닉스반도체 | Semiconductor device with ruthenium electrode and method for fabricating the same |
CN102473674B (en) * | 2009-07-09 | 2015-08-12 | 株式会社村田制作所 | Antifuse element |
US8748309B2 (en) * | 2012-09-14 | 2014-06-10 | GlobalFoundries, Inc. | Integrated circuits with improved gate uniformity and methods for fabricating same |
KR102542758B1 (en) * | 2015-06-05 | 2023-06-12 | 도쿄엘렉트론가부시키가이샤 | Ruthenium metal feature filling for interconnects |
US10903308B2 (en) | 2016-07-13 | 2021-01-26 | Samsung Electronics Co., Ltd. | Semiconductor device |
KR20180007543A (en) * | 2016-07-13 | 2018-01-23 | 삼성전자주식회사 | Semiconductor device |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20090072350A1 (en) * | 2001-05-31 | 2009-03-19 | Samsung Electronics Co., Ltd. | Semiconductor devices having a contact plug and fabrication methods thereof |
US7781819B2 (en) * | 2001-05-31 | 2010-08-24 | Samsung Electronics Co., Ltd. | Semiconductor devices having a contact plug and fabrication methods thereof |
US9153499B2 (en) | 2011-05-24 | 2015-10-06 | Samsung Electronics Co., Ltd. | Semiconductor device having metal plug and method of forming the same |
Also Published As
Publication number | Publication date |
---|---|
KR20020091663A (en) | 2002-12-06 |
US6884673B2 (en) | 2005-04-26 |
KR100408410B1 (en) | 2003-12-06 |
US20020179954A1 (en) | 2002-12-05 |
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