US20050130448A1 - Method of forming a silicon oxynitride layer - Google Patents

Method of forming a silicon oxynitride layer Download PDF

Info

Publication number
US20050130448A1
US20050130448A1 US10/736,061 US73606103A US2005130448A1 US 20050130448 A1 US20050130448 A1 US 20050130448A1 US 73606103 A US73606103 A US 73606103A US 2005130448 A1 US2005130448 A1 US 2005130448A1
Authority
US
United States
Prior art keywords
sio
gate dielectric
oxide film
processing system
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/736,061
Inventor
Christopher Olsen
Faran Nouri
Thai Chua
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to US10/736,061 priority Critical patent/US20050130448A1/en
Assigned to APPLIES MATERIALS, INC. reassignment APPLIES MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OLSEN, CHRISTOPHER, CHUA, THAI CHENG, NOURI, FARAN
Priority to JP2006545639A priority patent/JP2007515078A/en
Priority to KR1020067013590A priority patent/KR20060130089A/en
Priority to EP04810597A priority patent/EP1700330A2/en
Priority to PCT/US2004/037346 priority patent/WO2005062345A2/en
Priority to CNA2004800372954A priority patent/CN1894778A/en
Publication of US20050130448A1 publication Critical patent/US20050130448A1/en
Priority to US11/612,276 priority patent/US7569502B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith

Definitions

  • Embodiments of the present invention generally relate to a method of forming a gate dielectric. More particularly, embodiments of the invention relate to a method of forming a silicon oxynitride (SiO x N y ) gate dielectric.
  • Integrated circuits are composed of many, e.g., millions, of devices such as transistors, capacitors, and resistors.
  • Transistors such as field effect transistors, typically include a source, a drain, and a gate stack.
  • the gate stack typically includes a substrate, such as a silicon substrate, a gate dielectric, such as silicon dioxide, SiO 2 , on the substrate, and a gate electrode, such as polycrystalline silicon, on the gate dielectric.
  • the gate drive current required to increase the speed of the transistor has increased. Because the drive current increases as the gate capacitance increases, and capacitance is inversely proportional to the gate dielectric thickness, decreasing the dielectric thickness is one method of increasing the drive current.
  • SiO 2 gate dielectrics below 20 ⁇ .
  • boron from a boron doped gate electrode can penetrate through a thin SiO 2 gate dielectric into the underlying silicon substrate.
  • gate leakage i.e., tunneling
  • Thin SiO 2 gate dielectrics may be susceptible to hot carrier damage, in which high energy carriers traveling across the dielectric can damage or destroy the gate.
  • Thin SiO 2 gate dielectrics may also be susceptible to negative bias temperature instability (NBTI), wherein the threshold voltage or drive current drifts with operation of the gate.
  • NBTI negative bias temperature instability
  • One method that has been used to address the problems with thin SiO 2 gate dielectrics is to incorporate nitrogen into the SiO 2 layer to form a SiO x N y gate dielectric. Incorporating nitrogen into the SiO 2 layer blocks boron penetration into the underlying silicon substrate and raises the dielectric constant of the gate dielectric, allowing the use of a thicker dielectric layer.
  • Heating a silicon oxide layer in the presence of ammonia (NH 3 ) has been used to convert a SiO 2 layer to a SiO x N y layer.
  • NH 3 ammonia
  • the conventional methods of heating a silicon oxide layer in the presence of NH 3 in a furnace have typically resulted in non-uniform incorporation of nitrogen across the SiO 2 layer in different parts of the furnace due to air flow when the furnace is opened or closed. Additionally, oxygen or water vapor contamination of the SiO 2 layer may block incorporation of nitrogen into the SiO 2 layer.
  • Plasma nitriding has also been used to convert a SiO 2 layer to a SiO x N y layer. Gate stacks with a high PMOS drive current and a low gate leakage have been formed using plasma nitriding. However, attempts to form gate stacks with a high N-channel metal-oxide semiconductor (NMOS) drive current and a low gate leakage using plasma nitriding have been unsuccessful at less than 12 ⁇ EOT (equivalent oxide thickness). For example, FIG.
  • NMOS N-channel metal-oxide semiconductor
  • FIG. 1 shows that heating a silicon oxide layer in the presence of NH 3 results in a higher NMOS drive current at a normalized voltage of the threshold voltage +0.75 V (Idsat(Vt+0.75V)) relative to NMOS gate leakage at a normalized voltage of the threshold voltage +1 V (Jg(Vt+1)) than plasma nitriding the silicon oxide layer.
  • FIG. 2 shows that plasma nitriding a silicon oxide layer results in a higher P-channel metal-oxide semiconductor (PMOS) drive current at a normalized voltage of the threshold voltage +0.75 V (Idsat(Vt+0.75V)) relative to NMOS gate leakage at a normalized voltage of the threshold voltage +1 V (Jg(Vt+1)) than heating the silicon oxide layer in the presence of NH 3 .
  • PMOS P-channel metal-oxide semiconductor
  • CMOS circuits typically contain both NMOS and PMOS devices.
  • CMOS circuits typically contain both NMOS and PMOS devices.
  • a method of depositing a SiO x N y gate dielectric that has a high drive current and low leakage current for both PMOS and NMOS devices.
  • Embodiments of the present invention generally provide a method of forming a SiO x N y gate dielectric, comprising heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH 3 to incorporate nitrogen into the silicon oxide film, and then exposing the structure to a plasma comprising a nitrogen source to form a SiO x N y gate dielectric on the substrate.
  • the structure is annealed after the structure is exposed to a plasma comprising a nitrogen source.
  • Embodiments of the invention also provide a method of forming a SiO x N y gate dielectric in an integrated processing system, comprising heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH 3 in a first processing chamber of the integrated processing system to incorporate nitrogen into the silicon oxide film, transferring the structure to a second processing chamber of the integrated processing system, and then exposing the structure to a plasma comprising a nitrogen source in the second processing chamber to form a SiO x N y gate dielectric on the substrate.
  • the silicon oxide film is formed on the substrate in the integrated processing system, and the structure is not removed from the integrated processing system until after the SiO x N y gate dielectric is formed.
  • a SiO x N y gate dielectric formed by a method comprising heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH 3 to incorporate nitrogen into the silicon oxide film, and then exposing the structure to a plasma comprising a nitrogen source to form a SiO x N y gate dielectric on the substrate, is provided.
  • FIG. 1 is a graph showing NMOS drive current relative to NMOS gate leakage for gate stacks comprising SiO x N y gate dielectrics.
  • FIG. 2 is a graph showing PMOS drive current relative to NMOS gate leakage for gate stacks comprising SiO x N y gate dielectrics.
  • FIG. 3 is a top schematic view of an integrated processing system.
  • FIG. 4 is a flow chart depicting an embodiment of the invention.
  • FIG. 5 is a top schematic view of an integrated processing system.
  • FIG. 6 is a graph showing NMOS drive current relative to NMOS gate leakage for gate stacks comprising SiO x N y gate dielectrics.
  • FIG. 7 is a graph showing PMOS drive current relative to NMOS gate leakage for gate stacks comprising SiO x N y gate dielectrics.
  • Embodiments of the invention include a method for depositing a SiO x N y gate dielectric. Gate stacks including the SiO x N y gate dielectric exhibit desirable electrical properties in both NMOS and PMOS devices.
  • a SiO x N y gate dielectric is formed by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH 3 .
  • a silicon substrate includes single layer silicon substrates, such as silicon wafers, or structures that include a silicon layer on one or more other layers.
  • the silicon oxide film on the silicon substrate may be formed by exposing the silicon substrate to an atmosphere comprising oxygen to oxidize the top surface of the substrate.
  • the atmosphere comprising oxygen may be an ambient of oxygen (O 2 ), hydrogen (H 2 ) and O 2 , H 2 and nitrous oxide (N 2 O), O 2 and an inert gas, or combinations thereof.
  • the silicon oxide film may have a thickness of about 4 ⁇ to about 16 ⁇ , for example.
  • the silicon substrate may be exposed to an atmosphere comprising oxygen at a substrate temperature between about 700° C. and about 1100° C. and at a pressure between about 0.1 Torr and about 800 Torr for a time of between about 1 second and about 120 seconds.
  • the temperature is between about 750° C. and about 1000° C.
  • the pressure is between about 0.5 Torr and about 50 Torr.
  • Heating the structure comprising a silicon oxide film in an atmosphere comprising NH 3 incorporates nitrogen into the silicon oxide film such that the top surface of the silicon oxide film is nitrogen-doped.
  • the structure may be heated to a temperature of at least about 700° C. at a pressure of less than about 100 Torr, such as a pressure between about 0.1 Torr and about 100 Torr.
  • the structure is heated to a temperature between about 700° C. and about 1100° C., such as about 1050° C., at an NH 3 partial pressure of about 1 Torr.
  • the structure may be heated for a time of between about 1 second and about 120 seconds or for a period of time sufficient to nitrogen dope the top surface of the silicon oxide film.
  • substantially no oxygen is incorporated into the structure while heating the structure in an atmosphere comprising NH 3 .
  • the structure is exposed to a plasma comprising a nitrogen source to incorporate more nitrogen into the silicon oxide film, thereby forming the SiO x N y gate dielectric.
  • the nitrogen source may be nitrogen (N 2 ), NH 3 , or combinations thereof.
  • the plasma may further comprise an inert gas, such as helium, argon, or combinations thereof.
  • the pressure during the plasma exposure of the substrate may be between about 1 mTorr and about 30 mTorr, such as between about 1 mTorr and about 10 mTorr.
  • the SiO x N y gate dielectric described herein comprises at least 5 atomic percent nitrogen.
  • the SiO x N y gate dielectric comprises between about 5 atomic percent nitrogen and about 15 atomic percent nitrogen.
  • the structure is annealed after exposure to the plasma.
  • the structure is annealed in an atmosphere comprising O 2 .
  • the partial pressure of O 2 during the anneal may be less than 50 Torr, such as between about 10 mTorr and about 50 Torr.
  • the structure may be annealed at a temperature of between about 700° C. and about 1100° C., such as at a temperature between about 950° C. and about 1100° C.
  • the structure is annealed in an inert or reducing atmosphere and then annealed in an atmosphere comprising O 2 as described above.
  • the structure may be annealed in the inert or reducing atmosphere at a temperature of between about 700° C.
  • the structure may be annealed at a temperature of about 1000° C. in an atmosphere comprising N 2 at an N 2 partial pressure of between about 1 Torr and about 760 Torr.
  • a gate electrode such as a polysilicon layer, may be deposited on the SiO x N y gate dielectric to complete a gate stack.
  • a SiO x N y gate dielectric may be formed on a substrate in an integrated processing system, such as an integrated semiconductor processing system, in a method in which the substrate is not removed from the integrated processing system until after the SiO x N y gate dielectric is formed.
  • an integrated processing system 100 that may be used is the Gate Stack Centura® system, available from Applied Materials, Inc. of Santa Clara, Calif., which is shown in FIG. 3 .
  • the integrated processing system 100 may include a central transfer chamber 102 , transfer robot 103 , load locks 104 , 106 , a cool down chamber 108 , a thermal processing chamber 110 , a plasma processing chamber 114 , a rapid thermal processing (RTP) chamber 116 , and a CVD processing chamber 118 .
  • CVD processing chamber 118 may be a low pressure chemical vapor deposition chamber (LPCVD), such as a POLYgen chamber, available from Applied Materials.
  • LPCVD low pressure chemical vapor deposition chamber
  • the processing conditions for embodiments in which the SiO x N y gate dielectric is formed in an integrated processing system may be the same as the processing conditions described above for the formation of the silicon oxide film and the SiO x N y gate dielectric.
  • a structure comprising a silicon dioxide film on a silicon substrate may be heated in an atmosphere comprising NH 3 in a first processing chamber of the integrated processing system to incorporate nitrogen into the silicon oxide film. Because the substrate is exposed to an atmosphere comprising NH 3 within an enclosed integrated processing system, contaminating oxygen is typically not incorporated into the structure during the heating in an atmosphere comprising NH 3 .
  • the structure may then be transferred to a second processing chamber of the integrated processing system and exposed to a plasma comprising a nitrogen source in the second processing chamber.
  • the structure may be transferred to a third processing chamber of the integrated processing system and annealed in the third processing chamber.
  • a substrate is introduced into an integrated processing system and a silicon oxide film, a SiO x N y gate dielectric, and a gate electrode are deposited on the substrate without removing the substrate from the integrated processing system. This embodiment will be described below with respect to FIGS. 3 and 4 .
  • a silicon substrate may be introduced into the integrated processing system 100 via a load lock 102 or 104 and placed in RTP chamber 116 , where a silicon oxide film may be formed on the silicon substrate, as shown in steps 200 and 202 of FIG. 4 .
  • the structure, including the substrate and the silicon oxide film, may then be transferred to thermal processing chamber 110 , where it is heated in an atmosphere comprising NH 3 to incorporate nitrogen into the silicon oxide film, as shown in steps 204 and 206 .
  • the structure may then be transferred to cool down chamber 108 and cooled, for example, to less than about 100° C. in about 1 to about 2 minutes, as shown in step 208 .
  • the structure may then be transferred to plasma processing chamber 114 , where it is exposed to a plasma comprising a nitrogen source to incorporate more nitrogen into the silicon oxide film and form the SiO x N y gate dielectric, as shown in steps 210 and 212 .
  • the structure may be transferred to RTP chamber 116 where the structure may be annealed, as shown in steps 214 and 216 .
  • the structure may then be transferred to CVD processing chamber 118 , as shown in step 218 , and a gate electrode, such as a polysilicon layer or an amorphous silicon layer may be deposited on the structure, as shown in step 220 .
  • the structure may then be removed from the integrated processing system 100 via a load lock 102 or 104 .
  • the silicon oxide film is formed on the substrate in RTP chamber 116 in one step and the structure is annealed in the same RTP chamber 116 in another step.
  • a second RTP chamber is configured on an integrated processing system 300 , as shown in FIG. 5 , and the silicon oxide film is formed in one RTP chamber in one step and the structure is annealed in a different RTP chamber in another step.
  • the integrated processing system 300 may include a central transfer chamber 302 , transfer robot 303 , load locks 304 , 306 , a cool down chamber 308 , a thermal processing chamber 310 , a plasma processing chamber 314 , a rapid thermal processing (RTP) chamber 316 , and a RTP chamber 318 .
  • a central transfer chamber 302 transfer robot 303 , load locks 304 , 306 , a cool down chamber 308 , a thermal processing chamber 310 , a plasma processing chamber 314 , a rapid thermal processing (RTP) chamber 316 , and a RTP chamber 318 .
  • RTP rapid thermal processing
  • a silicon substrate may be introduced into the integrated processing system 300 via a load lock 302 or 304 and placed in RTP chamber 316 , where a silicon oxide film may be formed on the silicon substrate.
  • the structure, including the substrate and the silicon oxide film, may then be transferred to thermal processing chamber 310 , where it is heated in an atmosphere comprising NH 3 to incorporate nitrogen into the silicon oxide film.
  • the structure may then be transferred to cool down chamber 308 and cooled, for example, to less than about 100° C. in about 1 to about 2 minutes.
  • the structure may then be transferred to plasma processing chamber 314 , where it is exposed to a plasma comprising a nitrogen source to incorporate more nitrogen into the silicon oxide film and form the SiO x N y gate dielectric.
  • the structure may then be transferred to RTP chamber 318 where the structure may be annealed.
  • the structure may be transferred out of the integrated processing system 300 via load lock 302 or 304 to a processing chamber (not shown) external to the integrated processing system such as a low pressure chemical vapor deposition chamber (LPCVD), for depositing a gate electrode, such as a polysilicon layer or an amorphous silicon layer.
  • LPCVD low pressure chemical vapor deposition chamber
  • FIGS. 6 and 7 respectively show the NMOS drive current versus NMOS gate leakage and PMOS drive current versus NMOS gate leakage for gate stacks including a structure comprising a SiO x N y gate dielectric formed according to embodiments of the invention as well as for gate stacks formed according to other methods. The following process sequences were compared in FIGS.
  • a silicon substrate was oxidized to form a 10 ⁇ silicon oxide layer on the substrate (10 ⁇ oxide), plasma treated in nitrogen atmosphere (decoupled plasma nitridation, DPN), and then annealed (post nitridation anneal, PNA); 10 ⁇ oxide, heated in an atmosphere comprising NH 3 (NH 3 ), and then PNA; 10 ⁇ oxide, DPN, heated in an atmosphere comprising N 2 (N 2 ) and then NH 3 , and then PNA; 10 ⁇ oxide, DPN, heated in an atmosphere comprising NH 3 , heated in an atmosphere comprising N 2 , and then PNA; and 10 ⁇ oxide, NH 3 , DPN, and then PNA, according to an embodiment of the invention.
  • the PNA was performed at 1000° C. for 15 seconds in atmosphere with an O 2 partial pressure of 60 mTorr.
  • FIG. 6 illustrates that while a process sequence in which a structure is heated in an atmosphere comprising NH 3 and then annealed provides low NMOS gate leakage at a high NMOS drive current, a process sequence in which a structure is heated in an atmosphere comprising NH 3 , treated with a plasma comprising nitrogen, and then annealed, as described in embodiments of the invention, also provides desirable NMOS performance.
  • FIG. 7 illustrates that a process in which a structure is heated in an atmosphere comprising NH 3 , treated with a plasma comprising nitrogen, and then annealed, as described in embodiments of the invention, provides less NMOS gate leakage at a higher PMOS drive current than the other processes tested.
  • a process in which a structure is heated in an atmosphere comprising NH 3 , treated with a plasma comprising nitrogen, and then annealed can provide gate stacks that have desirable low gate leakage relative to both NMOS drive currents and PMOS drive currents. Furthermore, a process in which a structure is treated with a plasma comprising nitrogen, heated in an atmosphere comprising NH 3 , and then annealed provides structures that have significantly higher NMOS gate leakages for comparable NMOS and PMOS drive currents.
  • heating the structure in an atmosphere comprising NH 3 prior to treating the structure with a plasma comprising nitrogen smoothens the interface between the gate dielectric and the underlying silicon substrate, resulting in enhanced device performance and reliability. It is also believed that the formation of a slightly thicker oxide film by heating the structure first in an atmosphere comprising NH 3 prior to plasma treating the structure enhances the performance characteristics of a PMOS device.

Abstract

A SiOxNy gate dielectric and a method for forming a SiOxNy gate dielectric by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 and then exposing the structure to a plasma comprising a nitrogen source are provided. In one aspect, the structure is annealed after it is exposed to a plasma comprising a nitrogen source. In another aspect, a SiOxNy gate dielectric is formed in an integrated processing system by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 in one chamber of the integrated processing system and then exposing the structure to a plasma comprising a nitrogen source in another chamber of the integrated processing system.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • Embodiments of the present invention generally relate to a method of forming a gate dielectric. More particularly, embodiments of the invention relate to a method of forming a silicon oxynitride (SiOxNy) gate dielectric.
  • 2. Description of the Related Art
  • Integrated circuits are composed of many, e.g., millions, of devices such as transistors, capacitors, and resistors. Transistors, such as field effect transistors, typically include a source, a drain, and a gate stack. The gate stack typically includes a substrate, such as a silicon substrate, a gate dielectric, such as silicon dioxide, SiO2, on the substrate, and a gate electrode, such as polycrystalline silicon, on the gate dielectric.
  • As integrated circuit sizes and the sizes of the transistors thereon decrease, the gate drive current required to increase the speed of the transistor has increased. Because the drive current increases as the gate capacitance increases, and capacitance is inversely proportional to the gate dielectric thickness, decreasing the dielectric thickness is one method of increasing the drive current.
  • Attempts have been made to reduce the thickness of SiO2 gate dielectrics below 20 Å. However, it has been found that the use of thin SiO2 gate dielectrics below 20 Å often results in undesirable effects on gate performance and durability. For example, boron from a boron doped gate electrode can penetrate through a thin SiO2 gate dielectric into the underlying silicon substrate. Also, there is typically an increase in gate leakage, i.e., tunneling, with thin dielectrics that increases the amount of power consumed by the gate. Thin SiO2 gate dielectrics may be susceptible to hot carrier damage, in which high energy carriers traveling across the dielectric can damage or destroy the gate. Thin SiO2 gate dielectrics may also be susceptible to negative bias temperature instability (NBTI), wherein the threshold voltage or drive current drifts with operation of the gate.
  • One method that has been used to address the problems with thin SiO2 gate dielectrics is to incorporate nitrogen into the SiO2 layer to form a SiOxNy gate dielectric. Incorporating nitrogen into the SiO2 layer blocks boron penetration into the underlying silicon substrate and raises the dielectric constant of the gate dielectric, allowing the use of a thicker dielectric layer.
  • Heating a silicon oxide layer in the presence of ammonia (NH3) has been used to convert a SiO2 layer to a SiOxNy layer. However, the conventional methods of heating a silicon oxide layer in the presence of NH3 in a furnace have typically resulted in non-uniform incorporation of nitrogen across the SiO2 layer in different parts of the furnace due to air flow when the furnace is opened or closed. Additionally, oxygen or water vapor contamination of the SiO2 layer may block incorporation of nitrogen into the SiO2 layer.
  • Plasma nitriding (DPN) has also been used to convert a SiO2 layer to a SiOxNy layer. Gate stacks with a high PMOS drive current and a low gate leakage have been formed using plasma nitriding. However, attempts to form gate stacks with a high N-channel metal-oxide semiconductor (NMOS) drive current and a low gate leakage using plasma nitriding have been unsuccessful at less than 12 Å EOT (equivalent oxide thickness). For example, FIG. 1 shows that heating a silicon oxide layer in the presence of NH3 results in a higher NMOS drive current at a normalized voltage of the threshold voltage +0.75 V (Idsat(Vt+0.75V)) relative to NMOS gate leakage at a normalized voltage of the threshold voltage +1 V (Jg(Vt+1)) than plasma nitriding the silicon oxide layer. Additionally, FIG. 2 shows that plasma nitriding a silicon oxide layer results in a higher P-channel metal-oxide semiconductor (PMOS) drive current at a normalized voltage of the threshold voltage +0.75 V (Idsat(Vt+0.75V)) relative to NMOS gate leakage at a normalized voltage of the threshold voltage +1 V (Jg(Vt+1)) than heating the silicon oxide layer in the presence of NH3.
  • CMOS circuits typically contain both NMOS and PMOS devices. Thus, there remains a need for a method of depositing a SiOxNy gate dielectric that has a high drive current and low leakage current for both PMOS and NMOS devices.
    • SUMMARY OF THE INVENTION
  • Embodiments of the present invention generally provide a method of forming a SiOxNy gate dielectric, comprising heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 to incorporate nitrogen into the silicon oxide film, and then exposing the structure to a plasma comprising a nitrogen source to form a SiOxNy gate dielectric on the substrate. In one embodiment, the structure is annealed after the structure is exposed to a plasma comprising a nitrogen source.
  • Embodiments of the invention also provide a method of forming a SiOxNy gate dielectric in an integrated processing system, comprising heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 in a first processing chamber of the integrated processing system to incorporate nitrogen into the silicon oxide film, transferring the structure to a second processing chamber of the integrated processing system, and then exposing the structure to a plasma comprising a nitrogen source in the second processing chamber to form a SiOxNy gate dielectric on the substrate. In one embodiment, the silicon oxide film is formed on the substrate in the integrated processing system, and the structure is not removed from the integrated processing system until after the SiOxNy gate dielectric is formed.
  • In another embodiment, a SiOxNy gate dielectric, formed by a method comprising heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 to incorporate nitrogen into the silicon oxide film, and then exposing the structure to a plasma comprising a nitrogen source to form a SiOxNy gate dielectric on the substrate, is provided.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
  • FIG. 1 is a graph showing NMOS drive current relative to NMOS gate leakage for gate stacks comprising SiOxNy gate dielectrics.
  • FIG. 2 is a graph showing PMOS drive current relative to NMOS gate leakage for gate stacks comprising SiOxNy gate dielectrics.
  • FIG. 3 is a top schematic view of an integrated processing system.
  • FIG. 4 is a flow chart depicting an embodiment of the invention.
  • FIG. 5 is a top schematic view of an integrated processing system.
  • FIG. 6 is a graph showing NMOS drive current relative to NMOS gate leakage for gate stacks comprising SiOxNy gate dielectrics.
  • FIG. 7 is a graph showing PMOS drive current relative to NMOS gate leakage for gate stacks comprising SiOxNy gate dielectrics.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Embodiments of the invention include a method for depositing a SiOxNy gate dielectric. Gate stacks including the SiOxNy gate dielectric exhibit desirable electrical properties in both NMOS and PMOS devices.
  • In one embodiment, a SiOxNy gate dielectric is formed by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3. As defined herein, a silicon substrate includes single layer silicon substrates, such as silicon wafers, or structures that include a silicon layer on one or more other layers. The silicon oxide film on the silicon substrate may be formed by exposing the silicon substrate to an atmosphere comprising oxygen to oxidize the top surface of the substrate. The atmosphere comprising oxygen may be an ambient of oxygen (O2), hydrogen (H2) and O2, H2 and nitrous oxide (N2O), O2 and an inert gas, or combinations thereof. The silicon oxide film may have a thickness of about 4 Å to about 16 Å, for example. In one embodiment, the silicon substrate may be exposed to an atmosphere comprising oxygen at a substrate temperature between about 700° C. and about 1100° C. and at a pressure between about 0.1 Torr and about 800 Torr for a time of between about 1 second and about 120 seconds. Preferably, the temperature is between about 750° C. and about 1000° C., and the pressure is between about 0.5 Torr and about 50 Torr.
  • Heating the structure comprising a silicon oxide film in an atmosphere comprising NH3 incorporates nitrogen into the silicon oxide film such that the top surface of the silicon oxide film is nitrogen-doped. The structure may be heated to a temperature of at least about 700° C. at a pressure of less than about 100 Torr, such as a pressure between about 0.1 Torr and about 100 Torr. Preferably, the structure is heated to a temperature between about 700° C. and about 1100° C., such as about 1050° C., at an NH3 partial pressure of about 1 Torr. The structure may be heated for a time of between about 1 second and about 120 seconds or for a period of time sufficient to nitrogen dope the top surface of the silicon oxide film. Preferably, substantially no oxygen is incorporated into the structure while heating the structure in an atmosphere comprising NH3.
  • After the structure is heated in an atmosphere comprising NH3, the structure is exposed to a plasma comprising a nitrogen source to incorporate more nitrogen into the silicon oxide film, thereby forming the SiOxNy gate dielectric. The nitrogen source may be nitrogen (N2), NH3, or combinations thereof. The plasma may further comprise an inert gas, such as helium, argon, or combinations thereof. The pressure during the plasma exposure of the substrate may be between about 1 mTorr and about 30 mTorr, such as between about 1 mTorr and about 10 mTorr.
  • Preferably, the SiOxNy gate dielectric described herein comprises at least 5 atomic percent nitrogen. In one embodiment, the SiOxNy gate dielectric comprises between about 5 atomic percent nitrogen and about 15 atomic percent nitrogen.
  • Optionally, the structure is annealed after exposure to the plasma. In one embodiment, the structure is annealed in an atmosphere comprising O2. The partial pressure of O2 during the anneal may be less than 50 Torr, such as between about 10 mTorr and about 50 Torr. The structure may be annealed at a temperature of between about 700° C. and about 1100° C., such as at a temperature between about 950° C. and about 1100° C. In another embodiment, the structure is annealed in an inert or reducing atmosphere and then annealed in an atmosphere comprising O2 as described above. The structure may be annealed in the inert or reducing atmosphere at a temperature of between about 700° C. and about 1100° C., such as at a temperature between about 950° C. and about 1100° C. For example, the structure may be annealed at a temperature of about 1000° C. in an atmosphere comprising N2 at an N2 partial pressure of between about 1 Torr and about 760 Torr.
  • After the structure is exposed to the plasma and optionally annealed, a gate electrode, such as a polysilicon layer, may be deposited on the SiOxNy gate dielectric to complete a gate stack.
  • Integrated Processing Sequence
  • In a further embodiment, a SiOxNy gate dielectric may be formed on a substrate in an integrated processing system, such as an integrated semiconductor processing system, in a method in which the substrate is not removed from the integrated processing system until after the SiOxNy gate dielectric is formed. An example of an integrated processing system 100 that may be used is the Gate Stack Centura® system, available from Applied Materials, Inc. of Santa Clara, Calif., which is shown in FIG. 3. The integrated processing system 100 may include a central transfer chamber 102, transfer robot 103, load locks 104, 106, a cool down chamber 108, a thermal processing chamber 110, a plasma processing chamber 114, a rapid thermal processing (RTP) chamber 116, and a CVD processing chamber 118. CVD processing chamber 118 may be a low pressure chemical vapor deposition chamber (LPCVD), such as a POLYgen chamber, available from Applied Materials.
  • The processing conditions for embodiments in which the SiOxNy gate dielectric is formed in an integrated processing system may be the same as the processing conditions described above for the formation of the silicon oxide film and the SiOxNy gate dielectric. For example, in one embodiment a structure comprising a silicon dioxide film on a silicon substrate may be heated in an atmosphere comprising NH3 in a first processing chamber of the integrated processing system to incorporate nitrogen into the silicon oxide film. Because the substrate is exposed to an atmosphere comprising NH3 within an enclosed integrated processing system, contaminating oxygen is typically not incorporated into the structure during the heating in an atmosphere comprising NH3. The structure may then be transferred to a second processing chamber of the integrated processing system and exposed to a plasma comprising a nitrogen source in the second processing chamber. Optionally, after exposing the structure to the plasma, the structure may be transferred to a third processing chamber of the integrated processing system and annealed in the third processing chamber.
  • In another embodiment, a substrate is introduced into an integrated processing system and a silicon oxide film, a SiOxNy gate dielectric, and a gate electrode are deposited on the substrate without removing the substrate from the integrated processing system. This embodiment will be described below with respect to FIGS. 3 and 4.
  • A silicon substrate may be introduced into the integrated processing system 100 via a load lock 102 or 104 and placed in RTP chamber 116, where a silicon oxide film may be formed on the silicon substrate, as shown in steps 200 and 202 of FIG. 4. The structure, including the substrate and the silicon oxide film, may then be transferred to thermal processing chamber 110, where it is heated in an atmosphere comprising NH3 to incorporate nitrogen into the silicon oxide film, as shown in steps 204 and 206. The structure may then be transferred to cool down chamber 108 and cooled, for example, to less than about 100° C. in about 1 to about 2 minutes, as shown in step 208. The structure may then be transferred to plasma processing chamber 114, where it is exposed to a plasma comprising a nitrogen source to incorporate more nitrogen into the silicon oxide film and form the SiOxNy gate dielectric, as shown in steps 210 and 212. Optionally, the structure may be transferred to RTP chamber 116 where the structure may be annealed, as shown in steps 214 and 216. The structure may then be transferred to CVD processing chamber 118, as shown in step 218, and a gate electrode, such as a polysilicon layer or an amorphous silicon layer may be deposited on the structure, as shown in step 220. The structure may then be removed from the integrated processing system 100 via a load lock 102 or 104.
  • In the embodiment described above with respect to FIGS. 3 and 4, the silicon oxide film is formed on the substrate in RTP chamber 116 in one step and the structure is annealed in the same RTP chamber 116 in another step. In an alternative embodiment, a second RTP chamber is configured on an integrated processing system 300, as shown in FIG. 5, and the silicon oxide film is formed in one RTP chamber in one step and the structure is annealed in a different RTP chamber in another step. The integrated processing system 300 may include a central transfer chamber 302, transfer robot 303, load locks 304, 306, a cool down chamber 308, a thermal processing chamber 310, a plasma processing chamber 314, a rapid thermal processing (RTP) chamber 316, and a RTP chamber 318.
  • A silicon substrate may be introduced into the integrated processing system 300 via a load lock 302 or 304 and placed in RTP chamber 316, where a silicon oxide film may be formed on the silicon substrate. The structure, including the substrate and the silicon oxide film, may then be transferred to thermal processing chamber 310, where it is heated in an atmosphere comprising NH3 to incorporate nitrogen into the silicon oxide film. The structure may then be transferred to cool down chamber 308 and cooled, for example, to less than about 100° C. in about 1 to about 2 minutes. The structure may then be transferred to plasma processing chamber 314, where it is exposed to a plasma comprising a nitrogen source to incorporate more nitrogen into the silicon oxide film and form the SiOxNy gate dielectric. Optionally, the structure may then be transferred to RTP chamber 318 where the structure may be annealed. After the structure is annealed, the structure may be transferred out of the integrated processing system 300 via load lock 302 or 304 to a processing chamber (not shown) external to the integrated processing system such as a low pressure chemical vapor deposition chamber (LPCVD), for depositing a gate electrode, such as a polysilicon layer or an amorphous silicon layer.
  • While the above embodiments are described with respect to FIGS. 3 and 5, it is recognized that other integrated processing systems may be used with the embodiments described herein.
  • Performance of SiOxNy Gate Dielectrics in NMOS and PMOS Devices
  • FIGS. 6 and 7 respectively show the NMOS drive current versus NMOS gate leakage and PMOS drive current versus NMOS gate leakage for gate stacks including a structure comprising a SiOxNy gate dielectric formed according to embodiments of the invention as well as for gate stacks formed according to other methods. The following process sequences were compared in FIGS. 6 and 7: a silicon substrate was oxidized to form a 10 Å silicon oxide layer on the substrate (10 Å oxide), plasma treated in nitrogen atmosphere (decoupled plasma nitridation, DPN), and then annealed (post nitridation anneal, PNA); 10 Å oxide, heated in an atmosphere comprising NH3 (NH3), and then PNA; 10 Å oxide, DPN, heated in an atmosphere comprising N2 (N2) and then NH3, and then PNA; 10 Å oxide, DPN, heated in an atmosphere comprising NH3, heated in an atmosphere comprising N2, and then PNA; and 10 Å oxide, NH3, DPN, and then PNA, according to an embodiment of the invention. The PNA was performed at 1000° C. for 15 seconds in atmosphere with an O2 partial pressure of 60 mTorr.
  • FIG. 6 illustrates that while a process sequence in which a structure is heated in an atmosphere comprising NH3 and then annealed provides low NMOS gate leakage at a high NMOS drive current, a process sequence in which a structure is heated in an atmosphere comprising NH3, treated with a plasma comprising nitrogen, and then annealed, as described in embodiments of the invention, also provides desirable NMOS performance.
  • FIG. 7 illustrates that a process in which a structure is heated in an atmosphere comprising NH3, treated with a plasma comprising nitrogen, and then annealed, as described in embodiments of the invention, provides less NMOS gate leakage at a higher PMOS drive current than the other processes tested.
  • Thus, a process in which a structure is heated in an atmosphere comprising NH3, treated with a plasma comprising nitrogen, and then annealed, as described in embodiments of the invention, can provide gate stacks that have desirable low gate leakage relative to both NMOS drive currents and PMOS drive currents. Furthermore, a process in which a structure is treated with a plasma comprising nitrogen, heated in an atmosphere comprising NH3, and then annealed provides structures that have significantly higher NMOS gate leakages for comparable NMOS and PMOS drive currents.
  • It is believed that heating the structure in an atmosphere comprising NH3 prior to treating the structure with a plasma comprising nitrogen smoothens the interface between the gate dielectric and the underlying silicon substrate, resulting in enhanced device performance and reliability. It is also believed that the formation of a slightly thicker oxide film by heating the structure first in an atmosphere comprising NH3 prior to plasma treating the structure enhances the performance characteristics of a PMOS device.
  • While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (26)

1. A method of forming a SiOxNy gate dielectric, comprising:
providing a structure comprising a silicon oxide film formed on a silicon substrate;
heating the structure in an atmosphere comprising NH3 to incorporate nitrogen into the silicon oxide film; and then
exposing the structure to a plasma comprising a nitrogen source to form a SiOxNy gate dielectric on the substrate.
2. The method of claim 1, further comprising annealing the structure after the exposing the structure to the plasma.
3. The method of claim 2, wherein the annealing is performed in an atmosphere comprising O2.
4. The method of claim 3, wherein the annealing further comprises annealing the structure in an inert or reducing atmosphere before the annealing in an atmosphere comprising O2.
5. The method of claim 1, wherein the nitrogen source is selected from the group consisting of N2, NH3, and combinations thereof.
6. The method of claim 1, wherein heating the structure comprises heating the structure to a temperature of at least about 700° C. at a pressure of less than about 100 Torr.
7. The method of claim 1, wherein exposing the structure to a plasma is performed at a pressure of between about 1 mTorr and about 30 mTorr.
8. The method of claim 1, further comprising forming the silicon oxide film by oxidizing a top surface of the silicon substrate.
9. The method of claim 1, wherein substantially no oxygen is incorporated into the structure while heating the structure in an atmosphere comprising NH3.
10. A method of forming a SiOxNy gate dielectric in an integrated processing system, comprising:
heating a structure comprising a silicon oxide film formed on a silicon substrate in an atmosphere comprising NH3 in a first processing chamber of the integrated processing system to incorporate nitrogen into the silicon oxide film;
transferring the structure to a second processing chamber of the integrated processing system; and then
exposing the structure to a plasma comprising a nitrogen source in the second processing chamber to form a SiOxNy gate dielectric on the substrate.
11. The method of claim 10, further comprising:
transferring the structure to a third processing chamber of the integrated processing system; and
annealing the substrate in the third processing chamber.
12. The method of claim 11, further comprising:
introducing the silicon substrate into the integrated processing system; and
forming the silicon oxide film on the substrate in the third processing chamber of the integrated processing system to form the structure comprising a silicon oxide film on a silicon substrate.
13. The method of claim 12, further comprising:
transferring the structure to a fourth processing chamber of the integrated processing system after the annealing the substrate; and
depositing a polysilicon layer on the SiOxNy gate dielectric in the fifth processing chamber.
14. The method of claim 11, further comprising:
introducing the silicon substrate into the integrated processing system; and
forming the silicon oxide film on the substrate in a fourth processing chamber of the integrated processing system to form the structure comprising a silicon oxide film on a silicon substrate.
15. The method of claim 14, further comprising:
transferring the structure to a fifth processing chamber external to the integrated processing system after the exposing the structure to the plasma; and
depositing a polysilicon layer on the SiOxNy gate dielectric in the fifth processing chamber.
16. The method of claim 11, wherein the annealing is performed in an atmosphere comprising O2.
17. The method of claim 16, wherein the annealing further comprises annealing the structure in an inert or reducing atmosphere before the annealing in an atmosphere comprising O2.
18. The method of claim 10, further comprising transferring the structure to a cool down chamber after the heating and before the transferring the structure to a second processing chamber.
19. A SiOxNy gate dielectric, formed by a method comprising:
heating a structure comprising a silicon oxide film formed on a silicon substrate in an atmosphere comprising NH3 to incorporate nitrogen into the silicon oxide film; and then
exposing the structure to a plasma comprising a nitrogen source to form a SiOxNy gate dielectric on the substrate.
20. The SiOxNy gate dielectric of claim 19, wherein the gate dielectric comprises at least 5% nitrogen.
21. The SiOxNy gate dielectric of claim 19, wherein the method further comprises annealing the structure after the exposing the structure to a plasma.
22. The SiOxNy gate dielectric of claim 19, wherein substantially no oxygen is incorporated into the structure while heating the structure in an atmosphere comprising NH3.
23. The SiOxNy gate dielectric of claim 19, wherein the nitrogen source is selected from the group consisting of N2, NH3, and combinations thereof.
24. The SiOxNy gate dielectric of claim 19, wherein the method further comprises forming the silicon oxide film by oxidizing a top surface of the silicon substrate.
25. The SiOxNy gate dielectric of claim 19, wherein the method further comprises placing the silicon substrate in an integrated processing system and not removing the structure from the integrated processing system until after the gate dielectric is formed.
26. The SiOxNy gate dielectric of claim 25, wherein the method further comprises depositing a polysilicon layer on the substrate, wherein the structure is not removed from the integrated processing system until after the polysilicon layer is deposited.
US10/736,061 2003-12-15 2003-12-15 Method of forming a silicon oxynitride layer Abandoned US20050130448A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US10/736,061 US20050130448A1 (en) 2003-12-15 2003-12-15 Method of forming a silicon oxynitride layer
JP2006545639A JP2007515078A (en) 2003-12-15 2004-11-09 Method for forming a silicon oxynitride layer
KR1020067013590A KR20060130089A (en) 2003-12-15 2004-11-09 A method of forming a silicon oxynitride layer
EP04810597A EP1700330A2 (en) 2003-12-15 2004-11-09 A method of forming a silicon oxynitride layer
PCT/US2004/037346 WO2005062345A2 (en) 2003-12-15 2004-11-09 A method of forming a silicon oxynitride layer
CNA2004800372954A CN1894778A (en) 2003-12-15 2004-11-09 A method of forming a silicon oxynitride layer
US11/612,276 US7569502B2 (en) 2003-12-15 2006-12-18 Method of forming a silicon oxynitride layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/736,061 US20050130448A1 (en) 2003-12-15 2003-12-15 Method of forming a silicon oxynitride layer

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/612,276 Continuation US7569502B2 (en) 2003-12-15 2006-12-18 Method of forming a silicon oxynitride layer

Publications (1)

Publication Number Publication Date
US20050130448A1 true US20050130448A1 (en) 2005-06-16

Family

ID=34653770

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/736,061 Abandoned US20050130448A1 (en) 2003-12-15 2003-12-15 Method of forming a silicon oxynitride layer
US11/612,276 Active 2024-05-17 US7569502B2 (en) 2003-12-15 2006-12-18 Method of forming a silicon oxynitride layer

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/612,276 Active 2024-05-17 US7569502B2 (en) 2003-12-15 2006-12-18 Method of forming a silicon oxynitride layer

Country Status (6)

Country Link
US (2) US20050130448A1 (en)
EP (1) EP1700330A2 (en)
JP (1) JP2007515078A (en)
KR (1) KR20060130089A (en)
CN (1) CN1894778A (en)
WO (1) WO2005062345A2 (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040251495A1 (en) * 2003-03-26 2004-12-16 Tetsuya Ikuta Semiconductor device and manufacturing method of the same
US20060178018A1 (en) * 2003-03-07 2006-08-10 Applied Materials, Inc. Silicon oxynitride gate dielectric formation using multiple annealing steps
US20060292844A1 (en) * 2005-06-27 2006-12-28 Applied Materials, Inc. Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric
US20070010103A1 (en) * 2005-07-11 2007-01-11 Applied Materials, Inc. Nitric oxide reoxidation for improved gate leakage reduction of sion gate dielectrics
WO2007011666A2 (en) * 2005-07-19 2007-01-25 Applied Materials, Inc. Method and apparatus for semiconductor processing
US20080026553A1 (en) * 2006-07-31 2008-01-31 Thai Cheng Chua Method for fabricating an integrated gate dielectric layer for field effect transistors
US20080119057A1 (en) * 2006-11-20 2008-05-22 Applied Materials,Inc. Method of clustering sequential processing for a gate stack structure
US20080200000A1 (en) * 2007-02-19 2008-08-21 Fujitsu Limited Method for manufacturing semiconductor device
US20090181548A1 (en) * 2006-04-05 2009-07-16 Toshiki Takahashi Vertical plasma processing apparatus and method for semiconductor process
US7645710B2 (en) 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7678710B2 (en) 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US20100230655A1 (en) * 2007-12-06 2010-09-16 Fujitsu Limited Variable resistance device, method for manufacturing variable resistance device, and semiconductor storage device using variable resistance device
US7837838B2 (en) 2006-03-09 2010-11-23 Applied Materials, Inc. Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
US7902018B2 (en) 2006-09-26 2011-03-08 Applied Materials, Inc. Fluorine plasma treatment of high-k gate stack for defect passivation
US20110124172A1 (en) * 2009-11-24 2011-05-26 Samsung Electronics Co., Ltd. Method of forming insulating layer and method of manufacturing transistor using the same
US7964514B2 (en) 2006-03-02 2011-06-21 Applied Materials, Inc. Multiple nitrogen plasma treatments for thin SiON dielectrics
US8119210B2 (en) 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material
WO2023069187A1 (en) * 2021-10-22 2023-04-27 Applied Materials, Inc. . methods, systems, and apparatus for conducting a radical treatment operation prior to conducting an annealing operation

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5070702B2 (en) * 2006-01-19 2012-11-14 富士通セミコンダクター株式会社 Semiconductor device manufacturing method and manufacturing apparatus
JP2010021378A (en) * 2008-07-11 2010-01-28 Tokyo Electron Ltd Forming method and forming device for silicon oxynitride film
RU2498445C2 (en) * 2011-12-19 2013-11-10 Учреждение Российской академии наук Институт физики полупроводников им. А.В. Ржанова Сибирского отделения РАН (ИФП СО РАН) Method of dielectric layer manufacturing
US8889523B2 (en) 2012-01-02 2014-11-18 United Microelectronics Corp. Semiconductor process
CN107305842B (en) * 2016-04-25 2021-08-17 联华电子股份有限公司 Method for manufacturing gate dielectric layer
RU2719622C1 (en) * 2019-08-13 2020-04-21 Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" Semiconductor device manufacturing method
CN110634803B (en) * 2019-09-06 2022-11-29 上海华力集成电路制造有限公司 Method for repairing gate dielectric layer interface state defect in CMOS device and gate dielectric layer

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5591494A (en) * 1993-09-24 1997-01-07 Applied Materials, Inc. Deposition of silicon nitrides by plasma-enhanced chemical vapor deposition
US5780115A (en) * 1996-02-29 1998-07-14 Samsung Electronics Co., Ltd. Methods for fabricating electrode structures including oxygen and nitrogen plasma treatments
US5939131A (en) * 1996-07-23 1999-08-17 Samsung Electronics Co., Ltd. Methods for forming capacitors including rapid thermal oxidation
US6268267B1 (en) * 2000-01-24 2001-07-31 Taiwan Semiconductor Manufacturing Company Silicon-oxynitride-oxide (SXO) continuity film pad to recessed bird's beak of LOCOS
US20010049186A1 (en) * 1999-12-07 2001-12-06 Effiong Ibok Method for establishing ultra-thin gate insulator using anneal in ammonia
US20020197880A1 (en) * 2001-06-20 2002-12-26 Hiroaki Niimi Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates
US20020197884A1 (en) * 2001-06-20 2002-12-26 Hiroaki Niimi Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
US20020197882A1 (en) * 2001-06-20 2002-12-26 Hiroaki Niimi Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates
US20020197883A1 (en) * 2001-06-20 2002-12-26 Hiroaki Niimi Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
US6509604B1 (en) * 2000-01-26 2003-01-21 Advanced Micro Devices, Inc. Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation
US6548368B1 (en) * 2000-08-23 2003-04-15 Applied Materials, Inc. Method of forming a MIS capacitor
US20030109146A1 (en) * 2001-12-12 2003-06-12 Luigi Colombo Oxynitride device and method using non-stoichiometric silicon oxide
US20030111678A1 (en) * 2001-12-14 2003-06-19 Luigi Colombo CVD deposition of M-SION gate dielectrics
US6599807B2 (en) * 2001-08-14 2003-07-29 Samsung Electronics, Co., Ltd Method for manufacturing capacitor of semiconductor device having improved leakage current characteristics
US6649538B1 (en) * 2002-10-09 2003-11-18 Taiwan Semiconductor Manufacturing Co. Ltd. Method for plasma treating and plasma nitriding gate oxides
US20040053472A1 (en) * 2000-09-18 2004-03-18 Hideki Kiryu Method for film formation of gate insulator, apparatus for film formation of gate insulator, and cluster tool
US6780720B2 (en) * 2002-07-01 2004-08-24 International Business Machines Corporation Method for fabricating a nitrided silicon-oxide gate dielectric

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06140392A (en) * 1992-10-27 1994-05-20 Fujitsu Ltd Manufacture of semiconductor device
JPH10284488A (en) * 1997-04-03 1998-10-23 Hitachi Ltd Method and apparatus for manufacturing semiconductor integrated circuit
US6245616B1 (en) * 1999-01-06 2001-06-12 International Business Machines Corporation Method of forming oxynitride gate dielectric
JP2002270596A (en) * 2001-03-12 2002-09-20 Matsushita Electric Ind Co Ltd Apparatus for fabricating semiconductor device
JP2002305196A (en) * 2001-04-09 2002-10-18 Toshiba Corp Method for manufacturing semiconductor device

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5591494A (en) * 1993-09-24 1997-01-07 Applied Materials, Inc. Deposition of silicon nitrides by plasma-enhanced chemical vapor deposition
US5780115A (en) * 1996-02-29 1998-07-14 Samsung Electronics Co., Ltd. Methods for fabricating electrode structures including oxygen and nitrogen plasma treatments
US5939131A (en) * 1996-07-23 1999-08-17 Samsung Electronics Co., Ltd. Methods for forming capacitors including rapid thermal oxidation
US20010049186A1 (en) * 1999-12-07 2001-12-06 Effiong Ibok Method for establishing ultra-thin gate insulator using anneal in ammonia
US6268267B1 (en) * 2000-01-24 2001-07-31 Taiwan Semiconductor Manufacturing Company Silicon-oxynitride-oxide (SXO) continuity film pad to recessed bird's beak of LOCOS
US6509604B1 (en) * 2000-01-26 2003-01-21 Advanced Micro Devices, Inc. Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation
US6605511B2 (en) * 2000-01-26 2003-08-12 Advanced Micro Devices, Inc. Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation
US6548368B1 (en) * 2000-08-23 2003-04-15 Applied Materials, Inc. Method of forming a MIS capacitor
US20040053472A1 (en) * 2000-09-18 2004-03-18 Hideki Kiryu Method for film formation of gate insulator, apparatus for film formation of gate insulator, and cluster tool
US20020197880A1 (en) * 2001-06-20 2002-12-26 Hiroaki Niimi Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates
US6548366B2 (en) * 2001-06-20 2003-04-15 Texas Instruments Incorporated Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
US20020197883A1 (en) * 2001-06-20 2002-12-26 Hiroaki Niimi Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
US20020197882A1 (en) * 2001-06-20 2002-12-26 Hiroaki Niimi Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates
US6610614B2 (en) * 2001-06-20 2003-08-26 Texas Instruments Incorporated Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates
US20020197884A1 (en) * 2001-06-20 2002-12-26 Hiroaki Niimi Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
US6599807B2 (en) * 2001-08-14 2003-07-29 Samsung Electronics, Co., Ltd Method for manufacturing capacitor of semiconductor device having improved leakage current characteristics
US20030109146A1 (en) * 2001-12-12 2003-06-12 Luigi Colombo Oxynitride device and method using non-stoichiometric silicon oxide
US20030111678A1 (en) * 2001-12-14 2003-06-19 Luigi Colombo CVD deposition of M-SION gate dielectrics
US6780720B2 (en) * 2002-07-01 2004-08-24 International Business Machines Corporation Method for fabricating a nitrided silicon-oxide gate dielectric
US6649538B1 (en) * 2002-10-09 2003-11-18 Taiwan Semiconductor Manufacturing Co. Ltd. Method for plasma treating and plasma nitriding gate oxides

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060178018A1 (en) * 2003-03-07 2006-08-10 Applied Materials, Inc. Silicon oxynitride gate dielectric formation using multiple annealing steps
US7429540B2 (en) 2003-03-07 2008-09-30 Applied Materials, Inc. Silicon oxynitride gate dielectric formation using multiple annealing steps
US20040251495A1 (en) * 2003-03-26 2004-12-16 Tetsuya Ikuta Semiconductor device and manufacturing method of the same
US8119210B2 (en) 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material
US20060292844A1 (en) * 2005-06-27 2006-12-28 Applied Materials, Inc. Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric
US7429538B2 (en) 2005-06-27 2008-09-30 Applied Materials, Inc. Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric
US20070010103A1 (en) * 2005-07-11 2007-01-11 Applied Materials, Inc. Nitric oxide reoxidation for improved gate leakage reduction of sion gate dielectrics
WO2007011666A3 (en) * 2005-07-19 2008-07-03 Applied Materials Inc Method and apparatus for semiconductor processing
WO2007011666A2 (en) * 2005-07-19 2007-01-25 Applied Materials, Inc. Method and apparatus for semiconductor processing
US7964514B2 (en) 2006-03-02 2011-06-21 Applied Materials, Inc. Multiple nitrogen plasma treatments for thin SiON dielectrics
US7837838B2 (en) 2006-03-09 2010-11-23 Applied Materials, Inc. Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
US7645710B2 (en) 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7678710B2 (en) 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7825039B2 (en) * 2006-04-05 2010-11-02 Tokyo Electron Limited Vertical plasma processing method for forming silicon containing film
US20090181548A1 (en) * 2006-04-05 2009-07-16 Toshiki Takahashi Vertical plasma processing apparatus and method for semiconductor process
WO2008016769A1 (en) * 2006-07-31 2008-02-07 Applied Materials, Inc. Method for fabricating an integrated gate dielectric layer for field effect transistors
US20080026553A1 (en) * 2006-07-31 2008-01-31 Thai Cheng Chua Method for fabricating an integrated gate dielectric layer for field effect transistors
US7902018B2 (en) 2006-09-26 2011-03-08 Applied Materials, Inc. Fluorine plasma treatment of high-k gate stack for defect passivation
US20080119057A1 (en) * 2006-11-20 2008-05-22 Applied Materials,Inc. Method of clustering sequential processing for a gate stack structure
US20080200000A1 (en) * 2007-02-19 2008-08-21 Fujitsu Limited Method for manufacturing semiconductor device
US20100230655A1 (en) * 2007-12-06 2010-09-16 Fujitsu Limited Variable resistance device, method for manufacturing variable resistance device, and semiconductor storage device using variable resistance device
US8350244B2 (en) * 2007-12-06 2013-01-08 Fujitsu Limited Variable resistance device, method for manufacturing variable resistance device, and semiconductor storage device using variable resistance device
US20110124172A1 (en) * 2009-11-24 2011-05-26 Samsung Electronics Co., Ltd. Method of forming insulating layer and method of manufacturing transistor using the same
US8183136B2 (en) * 2009-11-24 2012-05-22 Samsung Electronics Co., Ltd. Method of forming insulating layer and method of manufacturing transistor using the same
WO2023069187A1 (en) * 2021-10-22 2023-04-27 Applied Materials, Inc. . methods, systems, and apparatus for conducting a radical treatment operation prior to conducting an annealing operation
US11901195B2 (en) 2021-10-22 2024-02-13 Applied Materials, Inc. Methods, systems, and apparatus for conducting a radical treatment operation prior to conducting an annealing operation

Also Published As

Publication number Publication date
EP1700330A2 (en) 2006-09-13
WO2005062345A2 (en) 2005-07-07
WO2005062345A3 (en) 2005-11-24
KR20060130089A (en) 2006-12-18
CN1894778A (en) 2007-01-10
US20070087583A1 (en) 2007-04-19
US7569502B2 (en) 2009-08-04
JP2007515078A (en) 2007-06-07

Similar Documents

Publication Publication Date Title
US7569502B2 (en) Method of forming a silicon oxynitride layer
US7429540B2 (en) Silicon oxynitride gate dielectric formation using multiple annealing steps
US7429538B2 (en) Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric
US9337046B1 (en) System and method for mitigating oxide growth in a gate dielectric
US20040175961A1 (en) Two-step post nitridation annealing for lower EOT plasma nitrided gate dielectrics
US5861651A (en) Field effect devices and capacitors with improved thin film dielectrics and method for making same
US6444592B1 (en) Interfacial oxidation process for high-k gate dielectric process integration
US5891809A (en) Manufacturable dielectric formed using multiple oxidation and anneal steps
US7560792B2 (en) Reliable high voltage gate dielectric layers using a dual nitridation process
US5393683A (en) Method of making semiconductor devices having two-layer gate structure
JP2007194431A (en) Manufacturing method and manufacturing equipment of semiconductor device
JP2004048001A (en) Forming method of silicon nitride oxide/gate insulation film
WO2012018975A2 (en) Mos transistors including sion gate dielectric with enhanced nitrogen concentration at its sidewalls
US7306985B2 (en) Method for manufacturing semiconductor device including heat treating with a flash lamp
JP3593340B2 (en) Manufacturing method of integrated circuit device
US7192887B2 (en) Semiconductor device with nitrogen in oxide film on semiconductor substrate and method of manufacturing the same
US20070010103A1 (en) Nitric oxide reoxidation for improved gate leakage reduction of sion gate dielectrics
CN1762045A (en) Two-step post nitridation annealing for lower EOT plasma nitrided gate dielectrics

Legal Events

Date Code Title Description
AS Assignment

Owner name: APPLIES MATERIALS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OLSEN, CHRISTOPHER;NOURI, FARAN;CHUA, THAI CHENG;REEL/FRAME:014809/0028;SIGNING DATES FROM 20031205 TO 20031208

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION