US20050087517A1 - Adhesion between carbon doped oxide and etch stop layers - Google Patents

Adhesion between carbon doped oxide and etch stop layers Download PDF

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Publication number
US20050087517A1
US20050087517A1 US10/683,759 US68375903A US2005087517A1 US 20050087517 A1 US20050087517 A1 US 20050087517A1 US 68375903 A US68375903 A US 68375903A US 2005087517 A1 US2005087517 A1 US 2005087517A1
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substrate
top surface
carbon doped
doped oxide
range
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Andrew Ott
Ajay Jain
Ying Zhou
Jessica Xu
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Intel Corp
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Intel Corp
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Publication of US20050087517A1 publication Critical patent/US20050087517A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to layers in microelectronic circuits, and more particularly to adhesion strength between layers of microelectronic circuits.
  • FIG. 1 is a side cross sectional view of a mircroelectronic circuit package assembly 100 .
  • a die 102 is connected to a package 110 by connectors 112 , such as solder balls.
  • the die 102 may include multiple layers, such as an etch stop layer 104 and a substrate layer 106 .
  • Such an interface may be between an etch stop layer 104 and a carbon doped oxide layer that is located at the upper surface of the substrate layer 106 .
  • the package 110 and die 102 may be raised to an elevated temperature. Subsequently, as the temperature decreases, the package 110 and die 102 may have different coefficients of thermal expansion and/or may cool at different rates. This may cause stresses to occur between the package 110 and the die 102 and/or within the die 102 , such as at the interface 108 between the etch stop layer 104 and the substrate layer 106 .
  • the connectors 112 may be solder balls that comprise a lead-tin alloy. Such connectors 112 are relatively soft. Stresses generated by differing coefficients of thermal expansion and/or cooling rates between the package 110 and the die 102 may cause such soft solder ball connectors 112 to deform. This deformation may act to reduce stresses acting on the interface 108 between layers 104 , 106 in the die 102 .
  • FIG. 1 is a side cross sectional view of a microelectronic circuit package assembly.
  • FIG. 2 is a side cross sectional view of a package assembly with a strengthened interface between an etch stop layer and a substrate.
  • FIGS. 3 a through 3 d are cross sectional side views that illustrate how a die may be fabricated with a stronger interface between a substrate and etch stop layer.
  • FIG. 4 is a chart that illustrates how methyl groups may be removed by the hydrogen plasma treatment.
  • FIG. 5 is a chart that illustrates how the interface may be strengthened by applying the hydrogen plasma treatment to the substrate.
  • FIG. 2 is a side cross sectional view of a package assembly 200 with a strengthened interface 208 between an etch stop layer 206 and a substrate 204 according to one embodiment of the present invention.
  • the package assembly 200 may include a die 202 connected to a package 214 by connectors 216 .
  • the connectors 216 may comprise a stiff material such as copper that deforms relatively little in comparison with lead-containing solder balls. These stiffer connectors 216 may include substantially no lead. Such stiffer connectors 216 may therefore subject the die 202 to more stress during heating and cooling, due to differing coefficients of thermal expansion and/or cooling rates of the package 214 and die 202 , than softer connectors that deform to reduce the stress to which the die 202 is subjected.
  • the die 202 may include a substrate 204 .
  • the substrate 204 may include carbon doped oxide (“CDO”) material at a top surface. This CDO material may act as a dielectric with a low dielectric constant (a low “k”).
  • CDO carbon doped oxide
  • Above the substrate 204 may be an etch stop layer 206 .
  • the etch stop layer 206 may be a diffusion barrier layer 206 .
  • the term “etch stop layer” will therefore refer to both an etch stop layer and a diffusion barrier layer.
  • the etch stop layer 206 may comprise a material such as SiN or SiC. There may be an interface 208 between the etch stop layer 206 and the substrate 204 .
  • Stiff connectors 216 such as copper connectors 216 , may cause relatively high stresses to act on the interface 208 .
  • the interface 208 may be strengthened so that it may withstand increased stress resulting to that the etch stop layer 206 remains adhered to the substrate 204 .
  • Such a strengthening may be achieved through modifying a portion of the substrate 204 to increase adhesion between the substrate 204 and the etch stop layer 206 .
  • the ILD layer 210 may comprise a material with a low k, such as SiO2, SiOF, CDO, polymer-containing dielectrics, or other dielectric materials.
  • Extending through the ILD layer 210 and the etch stop layer 206 may be a via or interconnect 216 .
  • the via 216 may comprise a conductive material such as aluminum, copper, or other conductive materials. This via 216 may electrically connect a conductor on the top surface of the substrate 204 to a connector 216 . This connector 216 may then electrically connect the conductor on the top surface of the substrate to a conductor in the package 214 .
  • FIGS. 3 a through 3 d are cross sectional side views that illustrate how a die 202 may be fabricated with a stronger interface 208 between a substrate 204 and etch stop layer 206 , according to one embodiment. This may be done by use of a plasma enhanced chemical vapor deposition (“PECVD”) treatment, where hydrogen plasma is used to modify carbon doped oxide (“CDO”) material in the substrate 204 .
  • PECVD plasma enhanced chemical vapor deposition
  • CDO carbon doped oxide
  • FIG. 3 a is a cross sectional side view that illustrates the substrate 204 according to one embodiment.
  • the substrate 204 may be any layer generated when making an integrated circuit.
  • the substrate 204 thus may comprise, for example, active and passive devices that are formed on a silicon wafer, such as transistors, capacitors, resistors, diffused junctions, gate electrodes, local interconnects, or other structures.
  • the substrate 204 may also comprise insulating materials (e.g., silicon dioxide, either undoped or doped with phosphorus or boron and phosphorus; silicon nitride; silicon oxynitride; or a polymer), and may comprise other formed materials.
  • the substrate 204 may include CDO material at a top surface, along with patterned conductors.
  • FIG. 3 b is a cross sectional side view that illustrates the substrate 204 after it has been modified to increase the strength of the interface 208 according to one embodiment.
  • the substrate 204 may be modified by a plasma treatment.
  • the substrate 204 may be modified by a PECVD treatment.
  • the substrate 204 may be placed in a plasma chamber for modification as part of a wafer that comprises a number of substrates 204 , prior to singulation of the wafer.
  • several wafers, each with multiple substrates 204 may be placed in the plasma chamber for modification.
  • four wafers may be placed in the plasma chamber for modification.
  • the wafers may have a diameter of 300 millimeters.
  • the substrate 204 may be brought to a temperature in a range from about 200 degrees Celsius to about 450 degrees Celsius. In an embodiment, the substrate 204 may be brought to a temperature of about 400 degrees Celsius.
  • a flow of hydrogen may be introduced into the plasma chamber. In some embodiments, the flow of hydrogen into the plasma chamber may have a flow rate in a range of about 0.1 liter per minute to about 10 liters per minute. In an embodiment, the flow of hydrogen into the plasma chamber may have a flow rate of about 1 liter per minute.
  • a flow of helium, ammonia, and/or nitrogen or another reducing or inert gas may also be introduced into the plasma chamber. In some embodiments, the chamber may have a pressure in a range from about 1 Torr to about 10 Torr.
  • the chamber may have a pressure in a range from about 2 Torr to about 5 Torr. In an embodiment, the chamber may have a pressure of about 2.5 Torr. In an embodiment, the plasma chamber may be ramped up to the pressure from a lower starting pressure.
  • a radio frequency (“RF”) power source may apply RF power to the plasma chamber to strike a plasma. In some embodiments with a 300 mm wafer, the radio frequency power source may apply a power in a range from about 200 Watts to about 1000 Watts. In some embodiments, the radio frequency power source may apply a power in a range from about 400 Watts to about 600 Watts. In an embodiment, the radio frequency power source may apply a power of about 500 Watts.
  • the power may be applied for a time in a range from about 4 seconds to about 30 seconds. In some embodiments, the power may be applied for a time in a range from about 10 seconds to about 15 seconds. In an embodiment, the power may be applied for about 12 seconds.
  • FIG. 4 is a chart 400 that illustrates how methyl groups may be removed by the hydrogen plasma treatment according to one embodiment. As shown in the chart 400 , in an embodiment, the longer the hydrogen plasma is applied to the substrate 204 , the fewer methyl groups remain in CDO material at the surface of the substrate 204 . Removal of these methyl groups may result in a stronger interface 208 between the substrate 204 and the etch stop layer 206 .
  • the PECVD modification of the substrate 204 may result in a graded modified region 302 of the substrate.
  • the graded modified region 302 may be a region where methyl groups formerly present in carbon doped oxide material of the substrate 204 have been removed by the hydrogen plasma treatment.
  • the graded region 302 may have a depth 304 .
  • the depth 304 is about 100 angstroms or less.
  • the depth 304 is about 50 angstroms or less.
  • the region 302 is graded since more methyl groups have been removed from the carbon doped oxide near the surface of the substrate 204 and fewer methyl groups have been removed from carbon doped oxide further from the surface of the substrate 204 .
  • Carbon doped oxide in an unmodified region 306 that begins beneath the graded modified region 302 at the depth 304 beneath the surface of the substrate 204 may remain substantially unchanged, with substantially the same amount of methyl groups as before the plasma modification.
  • the relatively small depth 304 of the modified graded region 302 may allow the substrate 204 to retain a low k value that is relatively unchanged by the modification.
  • FIG. 3 c is a cross sectional side view that illustrates the substrate 204 after an etch stop layer 206 has been deposited on the substrate 204 according to one embodiment.
  • the etch stop layer 206 may be deposited on the substrate 204 while the substrate 204 is in the same plasma chamber in which the graded modified region 302 was created, and the etch stop layer 206 may be deposited at the same temperature at which the substrate 204 was modified to create the graded modified layer 302 .
  • the etch stop layer 206 may comprise a material such as SiN or SiC.
  • There may be an interface 208 between the etch stop layer 206 and the substrate 204 . Modifying the substrate 204 to create the graded modified layer 302 may cause the interface between the etch stop layer 206 and the substrate 204 to be stronger than it would be otherwise, so that the etch stop layer 206 may be adhered more strongly to the substrate 204 .
  • FIG. 5 is a chart 500 that illustrates how the interface 208 may be strengthened by applying the hydrogen plasma treatment to the substrate 204 for various times according to one embodiment.
  • treating the substrate 204 by the hydrogen plasma may strengthen the interface 208 between the substrate 204 and the etch stop layer 206 .
  • the longer the substrate 204 is treated by the hydrogen plasma the stronger the interface 208 may be.
  • the gains achieved by exposing the substrate 204 to the hydrogen plasma for longer periods may slow so that only minor gains may be achieved by further exposure, after a certain amount of time. Excessive exposure length may even start to decrease the interface 208 strength as compared to shorter exposure times.
  • FIG. 3 d is a cross sectional side view that illustrates the die 202 after an ILD layer 210 and via 212 have been formed, according to one embodiment.
  • the ILD layer 210 , the via 212 , and/or other structures may be formed using known methods. While an ILD layer 210 and via 212 are shown in FIG. 3 d, other layers and structures may be formed in addition to, or in place of the ILD layer 210 and via 212 .
  • the layers and structures formed on the substrate 204 , and sections of the etch stop layer 206 removed during such formation of layers and structures will depend on the die being fabricated and the use to which it will be put.
  • the die 202 After the die 202 has been formed, it may be connected to a package 214 with a connector 216 , as shown in FIG. 2 .
  • CDO material in a layer, film, or other form may be treated by hydrogen plasma to remove methyl groups.
  • An etch stop or diffusion barrier layer such as ones that comprise SiN, SiON or SiC may be deposited on the modified CDO material.
  • the interface between the CDO and etch stop or diffusion barrier layer may be stronger than if the CDO material had not been modified.
  • ILD's with organic functional groups such as low k spin on dielectrics or porous CDO films can be modified in this manner to improve adhesion between the etch stop layer and ILD layer.
  • hydrogen plasma treatment may be used to remove the organic functional groups from a region near the surface of the material, which may result in a graded region with fewer organic functional group near the surface.
  • this technique could be used to improve the adhesion between ILD layers for integration schemes where an etch stop layer 206 is not needed.

Abstract

The invention forms a graded modified layer in a substrate by exposing the substrate to hydrogen plasma. Methyl groups may be removed from carbon doped oxide in the substrate by the hydrogen plasma treatment. This may result in a stronger interface between the substrate and an etch stop layer on the substrate.

Description

    BACKGROUND
  • 1. Field of the Invention
  • This invention relates to layers in microelectronic circuits, and more particularly to adhesion strength between layers of microelectronic circuits.
    • BACKGROUND OF THE INVENTION
  • FIG. 1 is a side cross sectional view of a mircroelectronic circuit package assembly 100. A die 102 is connected to a package 110 by connectors 112, such as solder balls. The die 102 may include multiple layers, such as an etch stop layer 104 and a substrate layer 106. There is an interface 108 between the two layers 104, 106 in the die 102. Such an interface may be between an etch stop layer 104 and a carbon doped oxide layer that is located at the upper surface of the substrate layer 106.
  • During fabrication of the package assembly 100, the package 110 and die 102 may be raised to an elevated temperature. Subsequently, as the temperature decreases, the package 110 and die 102 may have different coefficients of thermal expansion and/or may cool at different rates. This may cause stresses to occur between the package 110 and the die 102 and/or within the die 102, such as at the interface 108 between the etch stop layer 104 and the substrate layer 106.
  • In conventional package assemblies 100, the connectors 112 may be solder balls that comprise a lead-tin alloy. Such connectors 112 are relatively soft. Stresses generated by differing coefficients of thermal expansion and/or cooling rates between the package 110 and the die 102 may cause such soft solder ball connectors 112 to deform. This deformation may act to reduce stresses acting on the interface 108 between layers 104, 106 in the die 102.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention is illustrated by way of example and is not limited in the figures of the accompanying drawings, in which like references indicate similar elements. Features shown in the drawings are not intended to be drawn to scale, nor are they intended to be shown in precise positional relationship.
  • FIG. 1 is a side cross sectional view of a microelectronic circuit package assembly.
  • FIG. 2 is a side cross sectional view of a package assembly with a strengthened interface between an etch stop layer and a substrate.
  • FIGS. 3 a through 3 d are cross sectional side views that illustrate how a die may be fabricated with a stronger interface between a substrate and etch stop layer.
  • FIG. 4 is a chart that illustrates how methyl groups may be removed by the hydrogen plasma treatment.
  • FIG. 5 is a chart that illustrates how the interface may be strengthened by applying the hydrogen plasma treatment to the substrate.
    • DETAILED DESCRIPTION
  • In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings in which like references indicate similar elements. The illustrative embodiments described herein are disclosed in sufficient detail to enable those skilled in the art to practice the invention. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the invention is defined only by the appended claims.
  • FIG. 2 is a side cross sectional view of a package assembly 200 with a strengthened interface 208 between an etch stop layer 206 and a substrate 204 according to one embodiment of the present invention. The package assembly 200 may include a die 202 connected to a package 214 by connectors 216. The connectors 216 may comprise a stiff material such as copper that deforms relatively little in comparison with lead-containing solder balls. These stiffer connectors 216 may include substantially no lead. Such stiffer connectors 216 may therefore subject the die 202 to more stress during heating and cooling, due to differing coefficients of thermal expansion and/or cooling rates of the package 214 and die 202, than softer connectors that deform to reduce the stress to which the die 202 is subjected.
  • The die 202 may include a substrate 204. In an embodiment, the substrate 204 may include carbon doped oxide (“CDO”) material at a top surface. This CDO material may act as a dielectric with a low dielectric constant (a low “k”). Above the substrate 204 may be an etch stop layer 206. Alternatively, the etch stop layer 206 may be a diffusion barrier layer 206. The term “etch stop layer” will therefore refer to both an etch stop layer and a diffusion barrier layer. In some embodiments, the etch stop layer 206 may comprise a material such as SiN or SiC. There may be an interface 208 between the etch stop layer 206 and the substrate 204. Stiff connectors 216, such as copper connectors 216, may cause relatively high stresses to act on the interface 208. The interface 208 may be strengthened so that it may withstand increased stress resulting to that the etch stop layer 206 remains adhered to the substrate 204. Such a strengthening may be achieved through modifying a portion of the substrate 204 to increase adhesion between the substrate 204 and the etch stop layer 206.
  • There may also be an interlayer dielectric (“ILD”) layer 210 above the etch stop layer 206. The ILD layer 210 may comprise a material with a low k, such as SiO2, SiOF, CDO, polymer-containing dielectrics, or other dielectric materials. Extending through the ILD layer 210 and the etch stop layer 206 may be a via or interconnect 216. The via 216 may comprise a conductive material such as aluminum, copper, or other conductive materials. This via 216 may electrically connect a conductor on the top surface of the substrate 204 to a connector 216. This connector 216 may then electrically connect the conductor on the top surface of the substrate to a conductor in the package 214.
  • FIGS. 3 a through 3 d are cross sectional side views that illustrate how a die 202 may be fabricated with a stronger interface 208 between a substrate 204 and etch stop layer 206, according to one embodiment. This may be done by use of a plasma enhanced chemical vapor deposition (“PECVD”) treatment, where hydrogen plasma is used to modify carbon doped oxide (“CDO”) material in the substrate 204.
  • FIG. 3 a is a cross sectional side view that illustrates the substrate 204 according to one embodiment. The substrate 204 may be any layer generated when making an integrated circuit. The substrate 204 thus may comprise, for example, active and passive devices that are formed on a silicon wafer, such as transistors, capacitors, resistors, diffused junctions, gate electrodes, local interconnects, or other structures. The substrate 204 may also comprise insulating materials (e.g., silicon dioxide, either undoped or doped with phosphorus or boron and phosphorus; silicon nitride; silicon oxynitride; or a polymer), and may comprise other formed materials. The substrate 204 may include CDO material at a top surface, along with patterned conductors.
  • FIG. 3 b is a cross sectional side view that illustrates the substrate 204 after it has been modified to increase the strength of the interface 208 according to one embodiment. The substrate 204 may be modified by a plasma treatment. In an embodiment, the substrate 204 may be modified by a PECVD treatment. The substrate 204 may be placed in a plasma chamber for modification as part of a wafer that comprises a number of substrates 204, prior to singulation of the wafer. In an embodiment, several wafers, each with multiple substrates 204 may be placed in the plasma chamber for modification. In an embodiment, four wafers may be placed in the plasma chamber for modification. In an embodiment, the wafers may have a diameter of 300 millimeters.
  • The substrate 204 may be brought to a temperature in a range from about 200 degrees Celsius to about 450 degrees Celsius. In an embodiment, the substrate 204 may be brought to a temperature of about 400 degrees Celsius. A flow of hydrogen may be introduced into the plasma chamber. In some embodiments, the flow of hydrogen into the plasma chamber may have a flow rate in a range of about 0.1 liter per minute to about 10 liters per minute. In an embodiment, the flow of hydrogen into the plasma chamber may have a flow rate of about 1 liter per minute. A flow of helium, ammonia, and/or nitrogen or another reducing or inert gas may also be introduced into the plasma chamber. In some embodiments, the chamber may have a pressure in a range from about 1 Torr to about 10 Torr. In some embodiments, the chamber may have a pressure in a range from about 2 Torr to about 5 Torr. In an embodiment, the chamber may have a pressure of about 2.5 Torr. In an embodiment, the plasma chamber may be ramped up to the pressure from a lower starting pressure. A radio frequency (“RF”) power source may apply RF power to the plasma chamber to strike a plasma. In some embodiments with a 300 mm wafer, the radio frequency power source may apply a power in a range from about 200 Watts to about 1000 Watts. In some embodiments, the radio frequency power source may apply a power in a range from about 400 Watts to about 600 Watts. In an embodiment, the radio frequency power source may apply a power of about 500 Watts. In some embodiments, the power may be applied for a time in a range from about 4 seconds to about 30 seconds. In some embodiments, the power may be applied for a time in a range from about 10 seconds to about 15 seconds. In an embodiment, the power may be applied for about 12 seconds.
  • This may result in a hydrogen plasma flowing over CDO material in the substrate. The hydrogen plasma may remove methyl groups from CDO within the substrate. In an embodiment, the longer the hydrogen plasma treatment, the fewer methyl groups remain. FIG. 4 is a chart 400 that illustrates how methyl groups may be removed by the hydrogen plasma treatment according to one embodiment. As shown in the chart 400, in an embodiment, the longer the hydrogen plasma is applied to the substrate 204, the fewer methyl groups remain in CDO material at the surface of the substrate 204. Removal of these methyl groups may result in a stronger interface 208 between the substrate 204 and the etch stop layer 206.
  • Returning to FIG. 3 b, the PECVD modification of the substrate 204 may result in a graded modified region 302 of the substrate. The graded modified region 302 may be a region where methyl groups formerly present in carbon doped oxide material of the substrate 204 have been removed by the hydrogen plasma treatment. The graded region 302 may have a depth 304. In an embodiment, the depth 304 is about 100 angstroms or less. In an embodiment, the depth 304 is about 50 angstroms or less. In an embodiment, the region 302 is graded since more methyl groups have been removed from the carbon doped oxide near the surface of the substrate 204 and fewer methyl groups have been removed from carbon doped oxide further from the surface of the substrate 204. Carbon doped oxide in an unmodified region 306 that begins beneath the graded modified region 302 at the depth 304 beneath the surface of the substrate 204 may remain substantially unchanged, with substantially the same amount of methyl groups as before the plasma modification. The relatively small depth 304 of the modified graded region 302 may allow the substrate 204 to retain a low k value that is relatively unchanged by the modification.
  • FIG. 3 c is a cross sectional side view that illustrates the substrate 204 after an etch stop layer 206 has been deposited on the substrate 204 according to one embodiment. In an embodiment, the etch stop layer 206 may be deposited on the substrate 204 while the substrate 204 is in the same plasma chamber in which the graded modified region 302 was created, and the etch stop layer 206 may be deposited at the same temperature at which the substrate 204 was modified to create the graded modified layer 302. The etch stop layer 206 may comprise a material such as SiN or SiC. There may be an interface 208 between the etch stop layer 206 and the substrate 204. Modifying the substrate 204 to create the graded modified layer 302 may cause the interface between the etch stop layer 206 and the substrate 204 to be stronger than it would be otherwise, so that the etch stop layer 206 may be adhered more strongly to the substrate 204.
  • FIG. 5 is a chart 500 that illustrates how the interface 208 may be strengthened by applying the hydrogen plasma treatment to the substrate 204 for various times according to one embodiment. As shown in the chart 500, in an embodiment, treating the substrate 204 by the hydrogen plasma may strengthen the interface 208 between the substrate 204 and the etch stop layer 206. In an embodiment, up to an inflection point, the longer the substrate 204 is treated by the hydrogen plasma, the stronger the interface 208 may be. The gains achieved by exposing the substrate 204 to the hydrogen plasma for longer periods may slow so that only minor gains may be achieved by further exposure, after a certain amount of time. Excessive exposure length may even start to decrease the interface 208 strength as compared to shorter exposure times.
  • FIG. 3 d is a cross sectional side view that illustrates the die 202 after an ILD layer 210 and via 212 have been formed, according to one embodiment. The ILD layer 210, the via 212, and/or other structures may be formed using known methods. While an ILD layer 210 and via 212 are shown in FIG. 3 d, other layers and structures may be formed in addition to, or in place of the ILD layer 210 and via 212. The layers and structures formed on the substrate 204, and sections of the etch stop layer 206 removed during such formation of layers and structures will depend on the die being fabricated and the use to which it will be put. After the die 202 has been formed, it may be connected to a package 214 with a connector 216, as shown in FIG. 2.
  • While the foregoing description discusses strengthening an interface 208 between a substrate 204 and an etch stop layer 206, other interfaces may also be strengthened. CDO material in a layer, film, or other form may be treated by hydrogen plasma to remove methyl groups. An etch stop or diffusion barrier layer, such as ones that comprise SiN, SiON or SiC may be deposited on the modified CDO material. The interface between the CDO and etch stop or diffusion barrier layer may be stronger than if the CDO material had not been modified. Alternatively, other ILD's with organic functional groups, such as low k spin on dielectrics or porous CDO films can be modified in this manner to improve adhesion between the etch stop layer and ILD layer. In such embodiments, hydrogen plasma treatment may be used to remove the organic functional groups from a region near the surface of the material, which may result in a graded region with fewer organic functional group near the surface. Finally, this technique could be used to improve the adhesion between ILD layers for integration schemes where an etch stop layer 206 is not needed.
  • The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims (26)

1. A method, comprising:
forming a substrate with a top surface;
exposing the top surface of the substrate to hydrogen plasma to remove methyl groups from the top surface; and
depositing an intermediate layer on the top surface of the substrate.
2. The method of claim 1, wherein the intermediate layer comprises at least one of an etch stop layer and a diffusion barrier layer.
3. The method of claim 2, wherein the intermediate layer comprises at ieast one of SiN, SiON and SiC.
4. The method of claim 2, wherein the substrate comprises at least one of carbon doped oxide, a spin on dielectric layer, and porous carbon doped oxide that includes the methyl groups.
5. The method of claim 4, wherein exposing the top surface of the substrate to hydrogen plasma to remove methyl groups comprises:
disposing the substrate within a plasma chamber;
exposing the substrate to a flow of hydrogen into the plasma chamber; and
applying a radio frequency power for a selected time.
6. The method of claim 5, wherein the substrate is part of a wafer with a diameter of about 300 mm, and wherein the radio frequency power has a range from about 200 Watts to about 1000 Watts.
7. The method of claim 5, wherein the substrate is part of a wafer with a diameter of about 300 mm, and wherein the radio frequency power has a range from about 400 Watts to about 600 Watts for a 300 mm wafer.
8. The method of claim 5, wherein the selected time is in a range from about 4 seconds to about 30 seconds.
9. The method of claim 5, wherein the selected time is in a range from about 10 seconds to about 15 seconds.
10. The method of claim 5, wherein the substrate is exposed to hydrogen plasma at a temperature in a range from about 200 degrees Celsius to about 450 degrees Celsius.
11. The method of claim 5, wherein the flow of hydrogen into the plasma chamber has a flow rate in a range of about 0.1 liter per minute to about 10 liters per minute.
12. The method of claim 5, wherein the substrate is exposed to hydrogen plasma at a pressure in a range from about 1 Torr to about 10 Torr.
13. The method of claim 5, wherein the substrate is exposed to hydrogen plasma at a pressure in a range from about 2 Torr to about 5 Torr.
14. The method of claim 1, wherein exposing the top surface of the substrate to hydrogen plasma results in a graded modified region of reduced methyl groups with fewer methyl groups at the top surface of the substrate.
15. The method of claim 14, wherein the graded modified region extends less than about 100 angstroms below the top surface of the substrate.
16. The method of claim 14, wherein the graded modified region extends less than about 50 angstroms below the top surface of the substrate.
17. A device, comprising:
a substrate with a top surface;
a graded region of the substrate starting at the top surface of the substrate and extending a distance into the substrate, the graded region having fewer methyl groups at the top surface of the substrate and more methyl groups further into the substrate; and
an intermediate layer on the top surface of the substrate.
18. The device of claim 17, wherein the graded region extends less than about 100 angstroms below the top surface of the substrate.
19. The device of claim 17, wherein the graded region extends less than about 50 angstroms below the top surface of the substrate.
20. The device of claim 17, wherein the intermediate layer comprises at least one of an etch stop layer and a diffusion barrier layer.
21. The device of claim 20, wherein the intermediate layer comprises at least one of SiN, SiON and SiC.
22. The device of claim 21, wherein the substrate comprises at least one of carbon doped oxide, spin on dielectric, and porous carbon doped oxide that includes the methyl groups.
23. The device of claim 17, further comprising an interlayer dielectric layer.
24. The device of claim 17, further comprising:
an interlayer dielectric layer;
a via extending from the substrate through the intermediate layer and the interlayer dielectric layer;
a connector electrically connected to the via; and
a package electrically connected to the connector.
25. A method, comprising:
forming a first layer comprising carbon doped oxide;
exposing the carbon doped oxide to hydrogen plasma to remove methyl groups from the carbon doped oxide; and
depositing a second layer comprising at least one of SiN and SiC on the first layer.
26. The method of claim 25, wherein exposing the carbon doped oxide to hydrogen plasma comprises:
disposing the carbon doped oxide within a plasma chamber;
flowing hydrogen into the chamber at a rate of about 1 liter per minute;
heating the carbon doped oxide to a temperature in a range of about 200 degrees Celsius to about 450 degrees Celsius; and
applying a radio frequency power in a range from about 400 Watts to about 600 Watts for a time in a range from about 10 seconds to about 15 seconds.
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Cited By (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080116481A1 (en) * 2006-11-21 2008-05-22 Sharma Ajay K Selective deposition of a dielectric on a self-assembled monolayer-adsorbed metal
US20080157365A1 (en) * 2006-12-27 2008-07-03 Andrew Ott Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate, and method therefor
CN100442438C (en) * 2006-12-20 2008-12-10 南京大学 Manufacturing method of amorphous carbon-film semiconductor
CN106158729A (en) * 2015-04-08 2016-11-23 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US9978564B2 (en) 2012-09-21 2018-05-22 Applied Materials, Inc. Chemical control features in wafer process equipment
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10032606B2 (en) 2012-08-02 2018-07-24 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10062575B2 (en) * 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10062578B2 (en) 2011-03-14 2018-08-28 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US10062587B2 (en) 2012-07-18 2018-08-28 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10147620B2 (en) 2015-08-06 2018-12-04 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10186428B2 (en) 2016-11-11 2019-01-22 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10424463B2 (en) 2015-08-07 2019-09-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10465294B2 (en) 2014-05-28 2019-11-05 Applied Materials, Inc. Oxide and metal removal
US10468267B2 (en) 2017-05-31 2019-11-05 Applied Materials, Inc. Water-free etching methods
US10468285B2 (en) 2015-02-03 2019-11-05 Applied Materials, Inc. High temperature chuck for plasma processing systems
US10468276B2 (en) 2015-08-06 2019-11-05 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10593523B2 (en) 2014-10-14 2020-03-17 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10615047B2 (en) 2018-02-28 2020-04-07 Applied Materials, Inc. Systems and methods to form airgaps
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11239061B2 (en) 2014-11-26 2022-02-01 Applied Materials, Inc. Methods and systems to enhance process uniformity
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11594428B2 (en) 2015-02-03 2023-02-28 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6028015A (en) * 1999-03-29 2000-02-22 Lsi Logic Corporation Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption
US6156671A (en) * 1999-03-10 2000-12-05 United Microelectronics Corp. Method for improving characteristic of dielectric material
US6265303B1 (en) * 1997-05-28 2001-07-24 Texas Instruments Incorporated Integrated circuit dielectric and method
US6303192B1 (en) * 1998-07-22 2001-10-16 Philips Semiconductor Inc. Process to improve adhesion of PECVD cap layers in integrated circuits
US6423639B1 (en) * 1999-09-09 2002-07-23 Samsung Electronics Co., Ltd. Planarization method of insulating layer for semiconductor device
US6485815B1 (en) * 1999-05-24 2002-11-26 Samsung Electronics Co., Ltd. Multi-layered dielectric layer including insulating layer having Si-CH3 bond therein and method for fabricating the same
US6498112B1 (en) * 2001-07-13 2002-12-24 Advanced Micro Devices, Inc. Graded oxide caps on low dielectric constant (low K) chemical vapor deposition (CVD) films
US6528426B1 (en) * 1998-10-16 2003-03-04 Texas Instruments Incorporated Integrated circuit interconnect and method
US20030124870A1 (en) * 2001-11-16 2003-07-03 Macneil John Forming low k dielectric layers
US6605549B2 (en) * 2001-09-29 2003-08-12 Intel Corporation Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics
US20030155657A1 (en) * 2002-02-14 2003-08-21 Nec Electronics Corporation Manufacturing method of semiconductor device
US6759098B2 (en) * 2000-03-20 2004-07-06 Axcelis Technologies, Inc. Plasma curing of MSQ-based porous low-k film materials
US6821905B2 (en) * 2002-07-30 2004-11-23 Taiwan Semiconductor Manufacturing Co., Ltd Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6265303B1 (en) * 1997-05-28 2001-07-24 Texas Instruments Incorporated Integrated circuit dielectric and method
US6303192B1 (en) * 1998-07-22 2001-10-16 Philips Semiconductor Inc. Process to improve adhesion of PECVD cap layers in integrated circuits
US6528426B1 (en) * 1998-10-16 2003-03-04 Texas Instruments Incorporated Integrated circuit interconnect and method
US6156671A (en) * 1999-03-10 2000-12-05 United Microelectronics Corp. Method for improving characteristic of dielectric material
US6028015A (en) * 1999-03-29 2000-02-22 Lsi Logic Corporation Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption
US6485815B1 (en) * 1999-05-24 2002-11-26 Samsung Electronics Co., Ltd. Multi-layered dielectric layer including insulating layer having Si-CH3 bond therein and method for fabricating the same
US6423639B1 (en) * 1999-09-09 2002-07-23 Samsung Electronics Co., Ltd. Planarization method of insulating layer for semiconductor device
US6759098B2 (en) * 2000-03-20 2004-07-06 Axcelis Technologies, Inc. Plasma curing of MSQ-based porous low-k film materials
US6498112B1 (en) * 2001-07-13 2002-12-24 Advanced Micro Devices, Inc. Graded oxide caps on low dielectric constant (low K) chemical vapor deposition (CVD) films
US6605549B2 (en) * 2001-09-29 2003-08-12 Intel Corporation Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics
US20030124870A1 (en) * 2001-11-16 2003-07-03 Macneil John Forming low k dielectric layers
US20030155657A1 (en) * 2002-02-14 2003-08-21 Nec Electronics Corporation Manufacturing method of semiconductor device
US6821905B2 (en) * 2002-07-30 2004-11-23 Taiwan Semiconductor Manufacturing Co., Ltd Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer

Cited By (115)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7790631B2 (en) 2006-11-21 2010-09-07 Intel Corporation Selective deposition of a dielectric on a self-assembled monolayer-adsorbed metal
US20080116481A1 (en) * 2006-11-21 2008-05-22 Sharma Ajay K Selective deposition of a dielectric on a self-assembled monolayer-adsorbed metal
CN100442438C (en) * 2006-12-20 2008-12-10 南京大学 Manufacturing method of amorphous carbon-film semiconductor
US8120114B2 (en) 2006-12-27 2012-02-21 Intel Corporation Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate
US8399317B2 (en) 2006-12-27 2013-03-19 Intel Corporation Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate, and method therefor
US20080157365A1 (en) * 2006-12-27 2008-07-03 Andrew Ott Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate, and method therefor
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US10062578B2 (en) 2011-03-14 2018-08-28 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US10062587B2 (en) 2012-07-18 2018-08-28 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US10032606B2 (en) 2012-08-02 2018-07-24 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9978564B2 (en) 2012-09-21 2018-05-22 Applied Materials, Inc. Chemical control features in wafer process equipment
US11264213B2 (en) 2012-09-21 2022-03-01 Applied Materials, Inc. Chemical control features in wafer process equipment
US10354843B2 (en) 2012-09-21 2019-07-16 Applied Materials, Inc. Chemical control features in wafer process equipment
US11024486B2 (en) 2013-02-08 2021-06-01 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US10465294B2 (en) 2014-05-28 2019-11-05 Applied Materials, Inc. Oxide and metal removal
US10707061B2 (en) 2014-10-14 2020-07-07 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US10796922B2 (en) 2014-10-14 2020-10-06 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US10490418B2 (en) 2014-10-14 2019-11-26 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US10593523B2 (en) 2014-10-14 2020-03-17 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US11239061B2 (en) 2014-11-26 2022-02-01 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US10468285B2 (en) 2015-02-03 2019-11-05 Applied Materials, Inc. High temperature chuck for plasma processing systems
US11594428B2 (en) 2015-02-03 2023-02-28 Applied Materials, Inc. Low temperature chuck for plasma processing systems
CN106158729A (en) * 2015-04-08 2016-11-23 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
US10607867B2 (en) 2015-08-06 2020-03-31 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US10147620B2 (en) 2015-08-06 2018-12-04 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US11158527B2 (en) 2015-08-06 2021-10-26 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US10468276B2 (en) 2015-08-06 2019-11-05 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US10424464B2 (en) 2015-08-07 2019-09-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10424463B2 (en) 2015-08-07 2019-09-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US11476093B2 (en) 2015-08-27 2022-10-18 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US11735441B2 (en) 2016-05-19 2023-08-22 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10062575B2 (en) * 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US11049698B2 (en) 2016-10-04 2021-06-29 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10224180B2 (en) 2016-10-04 2019-03-05 Applied Materials, Inc. Chamber with flow-through source
US10541113B2 (en) 2016-10-04 2020-01-21 Applied Materials, Inc. Chamber with flow-through source
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US10319603B2 (en) 2016-10-07 2019-06-11 Applied Materials, Inc. Selective SiN lateral recess
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10770346B2 (en) 2016-11-11 2020-09-08 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10186428B2 (en) 2016-11-11 2019-01-22 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10600639B2 (en) 2016-11-14 2020-03-24 Applied Materials, Inc. SiN spacer profile patterning
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10903052B2 (en) 2017-02-03 2021-01-26 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10529737B2 (en) 2017-02-08 2020-01-07 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10325923B2 (en) 2017-02-08 2019-06-18 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11361939B2 (en) 2017-05-17 2022-06-14 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11915950B2 (en) 2017-05-17 2024-02-27 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10468267B2 (en) 2017-05-31 2019-11-05 Applied Materials, Inc. Water-free etching methods
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10593553B2 (en) 2017-08-04 2020-03-17 Applied Materials, Inc. Germanium etching systems and methods
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US11101136B2 (en) 2017-08-07 2021-08-24 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10861676B2 (en) 2018-01-08 2020-12-08 Applied Materials, Inc. Metal recess for semiconductor structures
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10699921B2 (en) 2018-02-15 2020-06-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10615047B2 (en) 2018-02-28 2020-04-07 Applied Materials, Inc. Systems and methods to form airgaps
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US11004689B2 (en) 2018-03-12 2021-05-11 Applied Materials, Inc. Thermal silicon etch
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes

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