US20050082583A1 - Self-aligned Vo-contact for cell size reduction - Google Patents

Self-aligned Vo-contact for cell size reduction Download PDF

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Publication number
US20050082583A1
US20050082583A1 US10/677,852 US67785203A US2005082583A1 US 20050082583 A1 US20050082583 A1 US 20050082583A1 US 67785203 A US67785203 A US 67785203A US 2005082583 A1 US2005082583 A1 US 2005082583A1
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Prior art keywords
contact
feram
bottom electrode
hole
mask
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US10/677,852
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US7061035B2 (en
Inventor
Jingyu Lian
Nicolas Nagel
Stefan Gernhardt
Rainer Bruchhaus
Andreas Hilliger
Uwe Wellhausen
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Polaris Innovations Ltd
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Infineon Technologies AG
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Priority to US10/677,852 priority Critical patent/US7061035B2/en
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GERNHARDT, STEFAN, BRUCHHAUS, RAINER, HILLIGER, ANDREAS, NAGEL, NICOLAS, WELLHAUSEN, UWE, LIAN, JINGYU
Priority to PCT/SG2004/000273 priority patent/WO2005031858A1/en
Publication of US20050082583A1 publication Critical patent/US20050082583A1/en
Priority to US11/373,080 priority patent/US7378700B2/en
Publication of US7061035B2 publication Critical patent/US7061035B2/en
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Assigned to QIMONDA AG reassignment QIMONDA AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INFINEON TECHNOLOGIES AG
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: QIMONDA AG
Assigned to POLARIS INNOVATIONS LIMITED reassignment POLARIS INNOVATIONS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INFINEON TECHNOLOGIES AG
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material

Definitions

  • the present invention relates to the self-alignment of a V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
  • V0-contacts are contact vias which are used as vertical interconnects between the source/drain of CMOS devices and the metal lines in multilevel interconnect schemes.
  • CMOS devices complementary metal-oxide-semiconductor devices
  • metal lines in multilevel interconnect schemes.
  • a huge space is designed in between the V0-contact and the capacitor side wall to avoid shorts and capacitor damage.
  • FIG. 1 shows a top view of a conventional layout of a V0-mask 101 , TW-mask 103 , TE-mask 105 and BE-mask 107 of a FeRAM memory chip mask 110 .
  • V0-mask 101 There is a huge space between the V0-mask 101 and the masks 103 , 105 , 107 .
  • FIG. 2 shows a cross-sectional view of the conventional layout of an FeRAM memory chip 200 .
  • a cover layer 201 (solid line) is over a BE-mask 107 (the cover layer can be A 1 2 O 3 , for example).
  • the TE 207 and a bottom electrode BE 209 sandwich a PZT ferroelectric layer 211 forming a ferroelectric capacitor 213 of a capacitor stack 223 of the FeRAM memory chip 200 .
  • An encapsulation layer 216 (solid line) is deposited onto the TE 207 prior to depositing the TE-mask 105 .
  • An encapsulation layer 215 (solid line) covers the ferroelectric capacitor 213 .
  • the cover layer 201 and encapsulation layers 215 , 216 help protect the ferroelectric capacitor 213 from damage.
  • a TW-contact 205 extends through the cover layer 201 , TF-mask 105 , and the encapsulation layers 215 , 216 , to provide an electrical connection to a top electrode TE 207 .
  • a CS-contact 223 provides a contact to the source/drain of a CMOS device.
  • a V0-contact 221 passes though a dielectric covering 222 and connects electrically to th CS-contact 223 .
  • th V0-contact 221 passes though a dielectric covering 222 and connects electrically to th CS-contact 223 .
  • th V0-contact 221 passes though a dielectric covering 222 and connects electrically to th CS-contact 223 .
  • the present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
  • An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode.
  • a V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode.
  • a liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact.
  • a is method is utilized to form a V0-contact in an FeRAM comprising.
  • An Fe capacitor of the FeRAM is encapsulated, a boftom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
  • FIG. 1 shows a top view of a conventional layout of a V0-mask, TW-mask, TE-mask and BE-mask of a FeRAM memory chip mask.
  • FIG. 2 shows a cross-sectional view of a conventional layout of an FeRAM memory chip.
  • FIG. 3 shows a top view of a layout of a V0-mask, TW-mask, TE-mask and BE-mask of an FeRAM memory chip mask of the present invention.
  • FIG. 4 shows a crossesectional view of the layout of an FeRAM memory chip of the present invention.
  • the present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
  • FIG. 3 shows a top view of a layout of a V0-mask 101 , TW-mask 103 , TE-mask 105 and BE-mask 107 of a FeRAM memory chip mask 301 of the present invention.
  • the huge space between the V0-mask 101 and the masks 103 , 105 , 107 has been eliminated.
  • FIG. 4 shows a cross-sectional view of the layout of an FeRAM memory chip 400 of the present invention.
  • a high quality single layer or multi-layer cover is used for an encapsulation layer 415 and a cover layer 403 illustrated in FIG. 4 .
  • a) Encapsulation of the capacitor 213 is performed as early and as is well as possible.
  • One encapsulation layer 216 (solid line) is deposited over the TE 207 before depositing the TE-mask so that it is under the TE-mask, and the encapsulation layer 415 is deposited before depositing the BE-mask 107 so that it is under the BE-mask 107 as is currently done.
  • the TE-mask can be made of TEOS, TiN or other metal, oxide or nitride materials, for example, and can be deposited using such methods as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
  • the BE-electrode 209 is then etched as steeply as possible and the cover layer 403 is deposited.
  • the dlelectric layer 222 is applied.
  • the cover layer 403 serves as both an etch stop liner and as a cover. A highly selective etch is used which stops on the cover layer 403 . Due to the effect of the spacer, the cover layer 403 remains intact on BE-sidewalls 407 .
  • the result is almost vertical BE sidewalls 407 , good step coverage for the ALD-deposition of Alumina inside the V0-contact hole 405 , highly selective etch of the hole for the V0-contact 405 , and no “noses” (no “noses” means that the sidewalls of the V0-contact hole 405 are smooth), thus providing a good Alumina spacer deposited on the walls of the V0-contact hole 405 .
  • a break-through etch is next used to clean the bottom of the V0-contact 405 and creates an electrical contact with the CS-contact 223 underneath.
  • This process can be used even when the TE 207 and BE 209 are etched together.
  • This process also works well with dry etching techniques.

Abstract

An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.

Description

    FIELD OF THE INVENTION
  • The present invention relates to the self-alignment of a V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
  • BACKGROUND OF THE INVENTION
  • V0-contacts are contact vias which are used as vertical interconnects between the source/drain of CMOS devices and the metal lines in multilevel interconnect schemes. In prior art FeRAM memories, in order to simplify process development, a huge space is designed in between the V0-contact and the capacitor side wall to avoid shorts and capacitor damage.
  • FIG. 1 shows a top view of a conventional layout of a V0-mask 101, TW-mask 103, TE-mask 105 and BE-mask 107 of a FeRAM memory chip mask 110. There is a huge space between the V0-mask 101 and the masks 103, 105, 107.
  • FIG. 2 shows a cross-sectional view of the conventional layout of an FeRAM memory chip 200. A cover layer 201 (solid line) is over a BE-mask 107 (the cover layer can be A1 2O3, for example). The TE 207 and a bottom electrode BE 209 sandwich a PZT ferroelectric layer 211 forming a ferroelectric capacitor 213 of a capacitor stack 223 of the FeRAM memory chip 200. An encapsulation layer 216 (solid line) is deposited onto the TE 207 prior to depositing the TE-mask 105. An encapsulation layer 215 (solid line) covers the ferroelectric capacitor 213. The cover layer 201 and encapsulation layers 215, 216 help protect the ferroelectric capacitor 213 from damage.
  • A TW-contact 205 extends through the cover layer 201, TF-mask 105, and the encapsulation layers 215, 216, to provide an electrical connection to a top electrode TE 207.
  • A CS-contact 223 provides a contact to the source/drain of a CMOS device. A V0-contact 221 passes though a dielectric covering 222 and connects electrically to th CS-contact 223. As can b s en, there is a huge space between th V0-contact 221 and a capacitor stack contact 223, making the memory chip 200 large. In the prior art, despite the cover and encapsulation layers, this huge space has been necessary to prevent short circuits and capacitor damage.
  • It would be desirable to reduce the size of the memory cell and overall FeRAM chip without the resulting short circuits or capacitor damage.
  • SUMMARY OF THE INVENTION
  • The present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
  • An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A is method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a boftom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
  • BRIEF DESCRIPTION OF THE FIGURES
  • Further preferred features of the invention will now be described for the sake of example only with reference to the following figures, in which:
  • FIG. 1 shows a top view of a conventional layout of a V0-mask, TW-mask, TE-mask and BE-mask of a FeRAM memory chip mask.
  • FIG. 2 shows a cross-sectional view of a conventional layout of an FeRAM memory chip.
  • FIG. 3 shows a top view of a layout of a V0-mask, TW-mask, TE-mask and BE-mask of an FeRAM memory chip mask of the present invention.
  • FIG. 4 shows a crossesectional view of the layout of an FeRAM memory chip of the present invention.
  • DETAILED DESCRIPTION OF THE EMBODIMENTS
  • The present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
  • FIG. 3 shows a top view of a layout of a V0-mask 101, TW-mask 103, TE-mask 105 and BE-mask 107 of a FeRAM memory chip mask 301 of the present invention. As can been seen, in the present invention the huge space between the V0-mask 101 and the masks 103, 105, 107 has been eliminated.
  • FIG. 4 shows a cross-sectional view of the layout of an FeRAM memory chip 400 of the present invention. To improve the protection for the ferroelectric capacitor 213, a high quality single layer or multi-layer cover is used for an encapsulation layer 415 and a cover layer 403 illustrated in FIG. 4.
  • The process flow is as follows:
  • a) Encapsulation of the capacitor 213 is performed as early and as is well as possible. One encapsulation layer 216 (solid line) is deposited over the TE 207 before depositing the TE-mask so that it is under the TE-mask, and the encapsulation layer 415 is deposited before depositing the BE-mask 107 so that it is under the BE-mask 107 as is currently done. The TE-mask can be made of TEOS, TiN or other metal, oxide or nitride materials, for example, and can be deposited using such methods as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
  • b) The BE-electrode 209 is then etched as steeply as possible and the cover layer 403 is deposited. Next the dlelectric layer 222 is applied. To protect the capacitor and bottom electrode during etching of the hole for a V0-contact 405 through the layer 222, the cover layer 403 serves as both an etch stop liner and as a cover. A highly selective etch is used which stops on the cover layer 403. Due to the effect of the spacer, the cover layer 403 remains intact on BE-sidewalls 407. The result is almost vertical BE sidewalls 407, good step coverage for the ALD-deposition of Alumina inside the V0-contact hole 405, highly selective etch of the hole for the V0-contact 405, and no “noses” (no “noses” means that the sidewalls of the V0-contact hole 405 are smooth), thus providing a good Alumina spacer deposited on the walls of the V0-contact hole 405.
  • c) A break-through etch is next used to clean the bottom of the V0-contact 405 and creates an electrical contact with the CS-contact 223 underneath.
  • This process can be used even when the TE 207 and BE 209 are etched together.
  • This process also works well with dry etching techniques.
  • Still other materials and method steps can be added or substituted for those above. Thus, although the invention has been described above using particular embodiments, many variations are possible within the scope of the claims, as will be clear to a skilled reader.

Claims (7)

1. An FeRAM comprising:
a ferroelectric material sandwiched between a top electrode and a bottom electrode; and
a V0-contact for providing an electrical connection with an underlying CS-contact, the V0-contact aligned by the bottom electrode.
2. The FeRAM of claim 1, further comprising a liner layer covering a sidewall of the bottom electrode for providing a stop to an etch of a hole in which the V0-contact is formed.
3. The FeRAM of claim 1 wherein the liner layer is between and in direct physical contact with both a sidewall of the bottom electrode and the V0-contact.
4. The FeRAM of claim 1, further comprising an Alumina spacer deposited on walls of the hole following etching of the hole.
5. A method for forming a V0-contact in an FeRAM comprising:
encapsulating an Fe capacitor of the FeRAM;
etching a bottom electrode;
depositing a liner layer covering a sidewall of the bottom electrod; and
etching a hole in which the VO-contact is formed until the etching is stopped by the liner layer.
6. The method of claim 5, further comprising the step of depositing an Alumina spacer on walls of the hole following etching of the hole.
7. The method of claim 5, further comprising the step of performing a break-through etch to clean the bottom of the V0-contact hole so that the V0 contact can electrically connect to an underlying CS-ontact.
US10/677,852 2003-10-01 2003-10-01 Self-aligned V0-contact for cell size reduction Expired - Fee Related US7061035B2 (en)

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US10/677,852 US7061035B2 (en) 2003-10-01 2003-10-01 Self-aligned V0-contact for cell size reduction
PCT/SG2004/000273 WO2005031858A1 (en) 2003-10-01 2004-08-31 Self-aligned v0-contact for cell size reduction of feram devices
US11/373,080 US7378700B2 (en) 2003-10-01 2006-03-09 Self-aligned V0-contact for cell size reduction

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Cited By (1)

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US11244733B2 (en) * 2017-08-04 2022-02-08 Micron Technology, Inc. Mitigating disturbances of memory cells

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JP2008205300A (en) * 2007-02-21 2008-09-04 Toshiba Corp Semiconductor device and manufacturing method of semiconductor device
US9786557B1 (en) 2016-04-12 2017-10-10 International Business Machines Corporation Two-dimensional self-aligned super via integration on self-aligned gate contact

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US7061035B2 (en) 2006-06-13
US20060151819A1 (en) 2006-07-13
US7378700B2 (en) 2008-05-27
WO2005031858A1 (en) 2005-04-07

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