US20050082583A1 - Self-aligned Vo-contact for cell size reduction - Google Patents
Self-aligned Vo-contact for cell size reduction Download PDFInfo
- Publication number
- US20050082583A1 US20050082583A1 US10/677,852 US67785203A US2005082583A1 US 20050082583 A1 US20050082583 A1 US 20050082583A1 US 67785203 A US67785203 A US 67785203A US 2005082583 A1 US2005082583 A1 US 2005082583A1
- Authority
- US
- United States
- Prior art keywords
- contact
- feram
- bottom electrode
- hole
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005549 size reduction Methods 0.000 title 1
- 239000003990 capacitor Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 24
- 238000005538 encapsulation Methods 0.000 description 9
- 230000015654 memory Effects 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 210000001331 nose Anatomy 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
Definitions
- the present invention relates to the self-alignment of a V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
- V0-contacts are contact vias which are used as vertical interconnects between the source/drain of CMOS devices and the metal lines in multilevel interconnect schemes.
- CMOS devices complementary metal-oxide-semiconductor devices
- metal lines in multilevel interconnect schemes.
- a huge space is designed in between the V0-contact and the capacitor side wall to avoid shorts and capacitor damage.
- FIG. 1 shows a top view of a conventional layout of a V0-mask 101 , TW-mask 103 , TE-mask 105 and BE-mask 107 of a FeRAM memory chip mask 110 .
- V0-mask 101 There is a huge space between the V0-mask 101 and the masks 103 , 105 , 107 .
- FIG. 2 shows a cross-sectional view of the conventional layout of an FeRAM memory chip 200 .
- a cover layer 201 (solid line) is over a BE-mask 107 (the cover layer can be A 1 2 O 3 , for example).
- the TE 207 and a bottom electrode BE 209 sandwich a PZT ferroelectric layer 211 forming a ferroelectric capacitor 213 of a capacitor stack 223 of the FeRAM memory chip 200 .
- An encapsulation layer 216 (solid line) is deposited onto the TE 207 prior to depositing the TE-mask 105 .
- An encapsulation layer 215 (solid line) covers the ferroelectric capacitor 213 .
- the cover layer 201 and encapsulation layers 215 , 216 help protect the ferroelectric capacitor 213 from damage.
- a TW-contact 205 extends through the cover layer 201 , TF-mask 105 , and the encapsulation layers 215 , 216 , to provide an electrical connection to a top electrode TE 207 .
- a CS-contact 223 provides a contact to the source/drain of a CMOS device.
- a V0-contact 221 passes though a dielectric covering 222 and connects electrically to th CS-contact 223 .
- th V0-contact 221 passes though a dielectric covering 222 and connects electrically to th CS-contact 223 .
- th V0-contact 221 passes though a dielectric covering 222 and connects electrically to th CS-contact 223 .
- the present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
- An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode.
- a V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode.
- a liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact.
- a is method is utilized to form a V0-contact in an FeRAM comprising.
- An Fe capacitor of the FeRAM is encapsulated, a boftom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
- FIG. 1 shows a top view of a conventional layout of a V0-mask, TW-mask, TE-mask and BE-mask of a FeRAM memory chip mask.
- FIG. 2 shows a cross-sectional view of a conventional layout of an FeRAM memory chip.
- FIG. 3 shows a top view of a layout of a V0-mask, TW-mask, TE-mask and BE-mask of an FeRAM memory chip mask of the present invention.
- FIG. 4 shows a crossesectional view of the layout of an FeRAM memory chip of the present invention.
- the present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
- FIG. 3 shows a top view of a layout of a V0-mask 101 , TW-mask 103 , TE-mask 105 and BE-mask 107 of a FeRAM memory chip mask 301 of the present invention.
- the huge space between the V0-mask 101 and the masks 103 , 105 , 107 has been eliminated.
- FIG. 4 shows a cross-sectional view of the layout of an FeRAM memory chip 400 of the present invention.
- a high quality single layer or multi-layer cover is used for an encapsulation layer 415 and a cover layer 403 illustrated in FIG. 4 .
- a) Encapsulation of the capacitor 213 is performed as early and as is well as possible.
- One encapsulation layer 216 (solid line) is deposited over the TE 207 before depositing the TE-mask so that it is under the TE-mask, and the encapsulation layer 415 is deposited before depositing the BE-mask 107 so that it is under the BE-mask 107 as is currently done.
- the TE-mask can be made of TEOS, TiN or other metal, oxide or nitride materials, for example, and can be deposited using such methods as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
- the BE-electrode 209 is then etched as steeply as possible and the cover layer 403 is deposited.
- the dlelectric layer 222 is applied.
- the cover layer 403 serves as both an etch stop liner and as a cover. A highly selective etch is used which stops on the cover layer 403 . Due to the effect of the spacer, the cover layer 403 remains intact on BE-sidewalls 407 .
- the result is almost vertical BE sidewalls 407 , good step coverage for the ALD-deposition of Alumina inside the V0-contact hole 405 , highly selective etch of the hole for the V0-contact 405 , and no “noses” (no “noses” means that the sidewalls of the V0-contact hole 405 are smooth), thus providing a good Alumina spacer deposited on the walls of the V0-contact hole 405 .
- a break-through etch is next used to clean the bottom of the V0-contact 405 and creates an electrical contact with the CS-contact 223 underneath.
- This process can be used even when the TE 207 and BE 209 are etched together.
- This process also works well with dry etching techniques.
Abstract
Description
- The present invention relates to the self-alignment of a V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
- V0-contacts are contact vias which are used as vertical interconnects between the source/drain of CMOS devices and the metal lines in multilevel interconnect schemes. In prior art FeRAM memories, in order to simplify process development, a huge space is designed in between the V0-contact and the capacitor side wall to avoid shorts and capacitor damage.
-
FIG. 1 shows a top view of a conventional layout of a V0-mask 101, TW-mask 103, TE-mask 105 and BE-mask 107 of a FeRAMmemory chip mask 110. There is a huge space between the V0-mask 101 and themasks -
FIG. 2 shows a cross-sectional view of the conventional layout of an FeRAMmemory chip 200. A cover layer 201 (solid line) is over a BE-mask 107 (the cover layer can be A1 2O3, for example). The TE 207 and abottom electrode BE 209 sandwich a PZTferroelectric layer 211 forming aferroelectric capacitor 213 of acapacitor stack 223 of the FeRAMmemory chip 200. An encapsulation layer 216 (solid line) is deposited onto the TE 207 prior to depositing the TE-mask 105. An encapsulation layer 215 (solid line) covers theferroelectric capacitor 213. Thecover layer 201 andencapsulation layers ferroelectric capacitor 213 from damage. - A TW-contact 205 extends through the
cover layer 201, TF-mask 105, and theencapsulation layers top electrode TE 207. - A CS-
contact 223 provides a contact to the source/drain of a CMOS device. A V0-contact 221 passes though a dielectric covering 222 and connects electrically to th CS-contact 223. As can b s en, there is a huge space between th V0-contact 221 and acapacitor stack contact 223, making thememory chip 200 large. In the prior art, despite the cover and encapsulation layers, this huge space has been necessary to prevent short circuits and capacitor damage. - It would be desirable to reduce the size of the memory cell and overall FeRAM chip without the resulting short circuits or capacitor damage.
- The present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
- An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A is method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a boftom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
- Further preferred features of the invention will now be described for the sake of example only with reference to the following figures, in which:
-
FIG. 1 shows a top view of a conventional layout of a V0-mask, TW-mask, TE-mask and BE-mask of a FeRAM memory chip mask. -
FIG. 2 shows a cross-sectional view of a conventional layout of an FeRAM memory chip. -
FIG. 3 shows a top view of a layout of a V0-mask, TW-mask, TE-mask and BE-mask of an FeRAM memory chip mask of the present invention. -
FIG. 4 shows a crossesectional view of the layout of an FeRAM memory chip of the present invention. - The present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
-
FIG. 3 shows a top view of a layout of a V0-mask 101, TW-mask 103, TE-mask 105 and BE-mask 107 of a FeRAMmemory chip mask 301 of the present invention. As can been seen, in the present invention the huge space between the V0-mask 101 and themasks -
FIG. 4 shows a cross-sectional view of the layout of an FeRAMmemory chip 400 of the present invention. To improve the protection for theferroelectric capacitor 213, a high quality single layer or multi-layer cover is used for anencapsulation layer 415 and acover layer 403 illustrated inFIG. 4 . - The process flow is as follows:
- a) Encapsulation of the
capacitor 213 is performed as early and as is well as possible. One encapsulation layer 216 (solid line) is deposited over theTE 207 before depositing the TE-mask so that it is under the TE-mask, and theencapsulation layer 415 is deposited before depositing theBE-mask 107 so that it is under theBE-mask 107 as is currently done. The TE-mask can be made of TEOS, TiN or other metal, oxide or nitride materials, for example, and can be deposited using such methods as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD). - b) The BE-electrode 209 is then etched as steeply as possible and the
cover layer 403 is deposited. Next thedlelectric layer 222 is applied. To protect the capacitor and bottom electrode during etching of the hole for a V0-contact 405 through thelayer 222, thecover layer 403 serves as both an etch stop liner and as a cover. A highly selective etch is used which stops on thecover layer 403. Due to the effect of the spacer, thecover layer 403 remains intact on BE-sidewalls 407. The result is almostvertical BE sidewalls 407, good step coverage for the ALD-deposition of Alumina inside the V0-contact hole 405, highly selective etch of the hole for the V0-contact 405, and no “noses” (no “noses” means that the sidewalls of the V0-contact hole 405 are smooth), thus providing a good Alumina spacer deposited on the walls of the V0-contact hole 405. - c) A break-through etch is next used to clean the bottom of the V0-
contact 405 and creates an electrical contact with the CS-contact 223 underneath. - This process can be used even when the TE 207 and BE 209 are etched together.
- This process also works well with dry etching techniques.
- Still other materials and method steps can be added or substituted for those above. Thus, although the invention has been described above using particular embodiments, many variations are possible within the scope of the claims, as will be clear to a skilled reader.
Claims (7)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/677,852 US7061035B2 (en) | 2003-10-01 | 2003-10-01 | Self-aligned V0-contact for cell size reduction |
PCT/SG2004/000273 WO2005031858A1 (en) | 2003-10-01 | 2004-08-31 | Self-aligned v0-contact for cell size reduction of feram devices |
US11/373,080 US7378700B2 (en) | 2003-10-01 | 2006-03-09 | Self-aligned V0-contact for cell size reduction |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/677,852 US7061035B2 (en) | 2003-10-01 | 2003-10-01 | Self-aligned V0-contact for cell size reduction |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/373,080 Division US7378700B2 (en) | 2003-10-01 | 2006-03-09 | Self-aligned V0-contact for cell size reduction |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050082583A1 true US20050082583A1 (en) | 2005-04-21 |
US7061035B2 US7061035B2 (en) | 2006-06-13 |
Family
ID=34393820
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/677,852 Expired - Fee Related US7061035B2 (en) | 2003-10-01 | 2003-10-01 | Self-aligned V0-contact for cell size reduction |
US11/373,080 Expired - Fee Related US7378700B2 (en) | 2003-10-01 | 2006-03-09 | Self-aligned V0-contact for cell size reduction |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/373,080 Expired - Fee Related US7378700B2 (en) | 2003-10-01 | 2006-03-09 | Self-aligned V0-contact for cell size reduction |
Country Status (2)
Country | Link |
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US (2) | US7061035B2 (en) |
WO (1) | WO2005031858A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11244733B2 (en) * | 2017-08-04 | 2022-02-08 | Micron Technology, Inc. | Mitigating disturbances of memory cells |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008205300A (en) * | 2007-02-21 | 2008-09-04 | Toshiba Corp | Semiconductor device and manufacturing method of semiconductor device |
US9786557B1 (en) | 2016-04-12 | 2017-10-10 | International Business Machines Corporation | Two-dimensional self-aligned super via integration on self-aligned gate contact |
Citations (11)
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US5543644A (en) * | 1992-02-18 | 1996-08-06 | National Semiconductor Corporation | High density electrical ceramic oxide capacitor |
US6051858A (en) * | 1996-07-26 | 2000-04-18 | Symetrix Corporation | Ferroelectric/high dielectric constant integrated circuit and method of fabricating same |
US6249014B1 (en) * | 1998-10-01 | 2001-06-19 | Ramtron International Corporation | Hydrogen barrier encapsulation techniques for the control of hydrogen induced degradation of ferroelectric capacitors in conjunction with multilevel metal processing for non-volatile integrated circuit memory devices |
US20010044205A1 (en) * | 1999-12-22 | 2001-11-22 | Gilbert Stephen R. | Method of planarizing a conductive plug situated under a ferroelectric capacitor |
US6423592B1 (en) * | 2001-06-26 | 2002-07-23 | Ramtron International Corporation | PZT layer as a temporary encapsulation and hard mask for a ferroelectric capacitor |
US20030124791A1 (en) * | 2001-12-31 | 2003-07-03 | Summerfelt Scott R. | Detection of AIOx ears for process control in FeRAM processing |
US20030146460A1 (en) * | 2001-12-28 | 2003-08-07 | Stmicroelectronics S.R.I | Capacitor for semiconductor integrated devices |
US20030155595A1 (en) * | 2002-02-15 | 2003-08-21 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
US6717197B2 (en) * | 2001-09-21 | 2004-04-06 | Samsung Electronics Co., Ltd. | Ferroelectric memory device and method of fabricating the same |
US6746878B2 (en) * | 2002-03-15 | 2004-06-08 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
US6809360B2 (en) * | 2002-03-20 | 2004-10-26 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6919168B2 (en) * | 1998-01-13 | 2005-07-19 | Applied Materials, Inc. | Masking methods and etching sequences for patterning electrodes of high density RAM capacitors |
-
2003
- 2003-10-01 US US10/677,852 patent/US7061035B2/en not_active Expired - Fee Related
-
2004
- 2004-08-31 WO PCT/SG2004/000273 patent/WO2005031858A1/en active Application Filing
-
2006
- 2006-03-09 US US11/373,080 patent/US7378700B2/en not_active Expired - Fee Related
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5543644A (en) * | 1992-02-18 | 1996-08-06 | National Semiconductor Corporation | High density electrical ceramic oxide capacitor |
US6051858A (en) * | 1996-07-26 | 2000-04-18 | Symetrix Corporation | Ferroelectric/high dielectric constant integrated circuit and method of fabricating same |
US6249014B1 (en) * | 1998-10-01 | 2001-06-19 | Ramtron International Corporation | Hydrogen barrier encapsulation techniques for the control of hydrogen induced degradation of ferroelectric capacitors in conjunction with multilevel metal processing for non-volatile integrated circuit memory devices |
US20030006439A1 (en) * | 1998-10-01 | 2003-01-09 | Bailey Richard A. | Hydrogen barrier encapsulation techniques for the control of hydrogen induced degradation of ferroelectric capacitors in conjunction with multilevel metal processing for non-volatile integrated circuit memory devices |
US20010044205A1 (en) * | 1999-12-22 | 2001-11-22 | Gilbert Stephen R. | Method of planarizing a conductive plug situated under a ferroelectric capacitor |
US6423592B1 (en) * | 2001-06-26 | 2002-07-23 | Ramtron International Corporation | PZT layer as a temporary encapsulation and hard mask for a ferroelectric capacitor |
US6717197B2 (en) * | 2001-09-21 | 2004-04-06 | Samsung Electronics Co., Ltd. | Ferroelectric memory device and method of fabricating the same |
US20030146460A1 (en) * | 2001-12-28 | 2003-08-07 | Stmicroelectronics S.R.I | Capacitor for semiconductor integrated devices |
US20030124791A1 (en) * | 2001-12-31 | 2003-07-03 | Summerfelt Scott R. | Detection of AIOx ears for process control in FeRAM processing |
US20030155595A1 (en) * | 2002-02-15 | 2003-08-21 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
US6720600B2 (en) * | 2002-02-15 | 2004-04-13 | Fujitsu Limited | FeRam semiconductor device with improved contact plug structure |
US6746878B2 (en) * | 2002-03-15 | 2004-06-08 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
US6809360B2 (en) * | 2002-03-20 | 2004-10-26 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11244733B2 (en) * | 2017-08-04 | 2022-02-08 | Micron Technology, Inc. | Mitigating disturbances of memory cells |
Also Published As
Publication number | Publication date |
---|---|
US7061035B2 (en) | 2006-06-13 |
US20060151819A1 (en) | 2006-07-13 |
US7378700B2 (en) | 2008-05-27 |
WO2005031858A1 (en) | 2005-04-07 |
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