US20050047432A1 - Integrated digital subscriber line transceiver - Google Patents
Integrated digital subscriber line transceiver Download PDFInfo
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- US20050047432A1 US20050047432A1 US10/641,702 US64170203A US2005047432A1 US 20050047432 A1 US20050047432 A1 US 20050047432A1 US 64170203 A US64170203 A US 64170203A US 2005047432 A1 US2005047432 A1 US 2005047432A1
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- subscriber line
- signal processing
- processing engine
- digital subscriber
- digital signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/005—Interface circuits for subscriber lines
- H04M3/007—Access interface units for simultaneous transmission of speech and data, e.g. digital subscriber line [DSL] access interface units
Definitions
- the following description relates to telecommunications in general and to digital subscriber line (DSL) devices in particular.
- DSL digital subscriber line
- DSL digital subscriber line
- a line unit located in a central office of a service provider communicates with a remote unit located at a remote site.
- the central office line unit communicates with the remote unit over a high bit-rate digital subscriber line 2 (HDSL2) communication link or a symmetric digital subscriber line communication link supporting the ITU G.991.2 standard (referred to here as “G.SHDSL”).
- HDSL2 or G.SHDSL link uses one twisted-pair telephone line.
- the central office line unit communicates with the remote unit over a high bit-rate DSL (HDSL or HDSL1) or a high bit-rate DSL 4 (HDSL4) communication link using two twisted-pair telephone lines.
- the line unit and the remote unit typically include various components such as a hybrid circuit, a line driver, an analog front end, a digital signal processing (DSP) engine, a T1/E1 framer, and a T1/E1 line interface unit along with a microprocessor and different types of memory.
- DSP digital signal processing
- T1/E1 framer, DSP engine, and microprocessor are physically embodied in separate components. This can lead to increased costs in constructing a line unit or remote unit from these components due to, for example, increased costs associated with procuring, integrating, and testing the different components.
- an integrated digital subscriber line transceiver includes a single integrated circuit having a digital signal processing engine adapted to couple the transceiver to at least one digital subscriber line communication link.
- the single integrated circuit also includes a time division multiplexing framer adapted to couple the transceiver to at least one time division multiplexing communication link.
- the single integrated circuit further includes a static random access memory and a microprocessor. The microprocessor is coupled to the digital signal processing engine, the time division multiplexing framer, and the static random access memory.
- a digital subscriber line unit in another embodiment, includes an analog interface adapted to couple the digital subscriber line unit to at least one digital subscriber line communication link.
- the digital subscriber line unit further includes a time division multiplexing line interface unit adapted to couple the digital subscriber line unit to at least one time division multiplexing communication link.
- the digital subscriber line unit further includes an integrated digital subscriber line transceiver.
- the integrated digital subscriber line transceiver includes a single integrated circuit having a digital signal processing engine coupled to the analog interface.
- the single integrated circuit further includes a time division multiplexing framer coupled to the time division multiplexing line interface unit.
- the single integrated circuit further includes a static random access memory and a microprocessor. The microprocessor is coupled to the digital signal processing engine, the time division multiplexing framer, and the static random access memory.
- an integrated digital subscriber line transceiver in another embodiment, includes a single integrated circuit having a digital signal processing engine adapted to couple the transceiver to at least one digital subscriber line communication link and to at least one time division multiplexing communication link.
- the single integrated circuit further includes a static random access memory and a microprocessor.
- the microprocessor is coupled to the digital signal processing engine and the static random access memory.
- a digital subscriber line unit in another embodiment, includes an analog interface adapted to couple the digital subscriber line unit to at least one digital subscriber line communication link.
- the digital subscriber line unit further includes a time division multiplexing line interface unit adapted to couple the digital subscriber line unit to at least one time division multiplexing communication link.
- the digital subscriber line unit further includes a time division multiplexing framer coupled to the time division multiplexing line interface unit and an integrated digital subscriber line transceiver.
- the integrated digital subscriber line transceiver includes a single integrated circuit having a digital signal processing engine coupled to the analog interface and the time division multiplexing framer.
- the single integrated circuit further includes a static random access memory and a microprocessor. The microprocessor is coupled to the digital signal processing engine, the time division multiplexing framer, and the static random access memory.
- FIG. 1 is a block diagram of one embodiment of a line unit having an integrated transceiver.
- FIG. 2 is a block diagram of another embodiment of a line unit having an integrated transceiver.
- FIG. 1 is a block diagram of one embodiment of a digital subscriber line (DSL) unit 100 .
- DSL unit 100 are suitable for use in, for example, a line unit housed within a central office of a service provider and/or a remote unit located at a remote site (for example, a remote unit housed within a remote terminal).
- the embodiment of the DSL unit 100 shown in FIG. 1 supports communicating over an HDSL2 or G.SHDSL communication link.
- other DSL communication links for example, HDSL and/or HDSL4 communication links
- HDSL2 and/or G.SHDSL communication links are supported in addition to, or instead of, HDSL2 and/or G.SHDSL communication links.
- DSL unit 100 is used to send and receive DS1 traffic over an HDSL2 or G.SHDSL communication link using one twisted-pair telephone line (also referred to here as a “local loop” or “loop”).
- Data received from the HDSL2 or G.SHDSL link is coupled to a time division multiplexing (TDM) link that is cross-connected to a TDM network.
- TDM time division multiplexing
- the TDM link is a T1 or El communication link.
- Digital subscriber line unit 100 includes an analog interface 104 , an integrated transceiver 106 , and a TDM line interface unit 108 .
- the analog interface 104 includes an analog front end (AFE) 110 .
- the analog front end 110 includes a transmit channel and a receive channel (not shown in FIG. 1 ).
- the AFE 110 receives a digital pulse amplitude modulated (PAM) data stream from the integrated transceiver 106 , converts the digital stream to an analog signal, and filters the analog signal to suppress out-of-band noise.
- the analog signal is output to a line driver 112 for amplification.
- the AFE 110 receives an analog signal from a hybrid circuit 114 , amplifies the received analog signal, and converts the amplified analog signal to a digital signal.
- the digital signal is output to the integrated transceiver 106 .
- the hybrid circuit 114 couples the analog interface 104 to a twisted-pair telephone line 116 .
- the hybrid circuit 114 couples one twisted-pair telephone line to the analog interface 104 .
- the hybrid circuit 114 couples the analog interface 104 to multiple twisted-pair telephone lines (for example, 2 telephone lines in the case of HDSL, HDSL4, or 2-pair G.SHDSL embodiments).
- a separate 2-line transmit path and a separate 2-line receive path for each twisted-pair telephone line is provided between the AFE 110 and the integrated transceiver 106 .
- the analog interface 104 is implemented as a single integrated circuit that includes the analog front end 110 , the line driver 112 , and the hybrid circuit 114 .
- the integrated transceiver 106 is a single integrated circuit that includes a digital signal processing (DSP) engine 118 , a time division multiplexing (TDM) framer 120 , a microprocessor 122 and a static random access memory 124 .
- DSP digital signal processing
- TDM time division multiplexing
- the DSP engine 118 supports G.SHDSL and HDSL2 communication links, in other embodiments other DSL communication links (such as HDSL or HDSL4 communication links) are supported in addition to, or instead of, HDSL2 and/or G.SHDSL communication links.
- the DSP engine 118 includes an HDSL2/G.SHDSL data pump 126 and an HDSL2/G.SHDSL framer 128 .
- the TDM framer 120 is a framer that supports T1 and/or E1 communication links.
- the TDM line interface unit 108 receives an analog DS1 signal from a TDM communication link 130 (such as a T1/E1 communication link) and converts the analog DS1 signal to a digital pulse code modulated (PCM) signal for the TDM framer 120 .
- the TDM framer 120 outputs a serial digital DS1 data stream that is encapsulated into a stream of HDSL2 or G.SHDSL frames by the HDSL2/G.SHDSL framer 128 .
- the output of the HDSL2/G.SHDSL framer 128 is encoded and bit-to-level mapped by the HDSL2/G.SHDSL data pump 126 and is output to the analog front end 110 .
- the HDSL2/G.SHDSL data pump 126 receives HDSL2 or G.SHDSL frames from the analog front end 110 , which are decoded and level-to-bit mapped.
- the HDSL2/G.SHDSL framer 128 outputs DS1 data to the TDM framer 120 , which encapsulates the DS1 data into appropriate TDM frames (for example, T1 or E1 frames) for transmission onto the TDM communication link 130 via the TDM line interface unit 108 .
- the TDM line interface unit 108 is embodied as a physically separate device and supports T1 and/or E1 communication links.
- the microprocessor 122 communicates with and controls the operation of the DSP engine 118 and the TDM framer 120 .
- the microprocessor 122 communicates with the DSP engine 118 and the TDM framer 120 over a 16-bit bus 132 .
- the microprocessor 122 is coupled to static random access memory (RAM) 124 over the 16-bit bus 132 .
- Program instructions executed by the microprocessor 120 along with data used by the microprocessor 122 and other components of the transceiver 106 are stored in and retrieved from the static RAM 124 .
- the static RAM 124 is a 128 kilobit by 8 bit static RAM.
- the integrated transceiver 106 also includes a dual universal asynchronous receiver-transmitter (UART) 134 .
- the dual UART 134 couples the microprocessor 122 to a RS-232 serial port 136 .
- a data terminal (not shown) can be connected to the RS-232 serial port 136 in order to communicate with a control program executing on the microprocessor 122 .
- the control program is used to view and/or modify various configuration and status parameters of the DSL unit 100 .
- the dual UART 134 also is used to couple the microprocessor 122 to a backplane (not shown) of a chassis in which the DSL unit 100 is housed. This allows a management program executing on a device external to the DSL unit 100 to communicate with the microprocessor 122 and the control program executing thereon over the backplane of the chassis.
- the integrated transceiver 106 also includes a clock generator 138 that provides a clock signal to the components of the transceiver 106 and the DSL unit 100 based on a signal from a clock oscillator 140 .
- the clock oscillator 140 is external to the transceiver 106 .
- the microprocessor 122 also communicates with a display 142 over a serial bus 144 .
- the TDM line interface unit 108 also communicates with the display 142 .
- Display 142 is used to display, for example, information about the DSL unit 100 and/or the TDM communication link 130 .
- display 142 includes a 4-character LED display mounted on a front panel of the DSL unit 100 .
- the DSL unit 100 also includes a flash memory 146 .
- the flash memory 146 is coupled to the microprocessor 122 via the 16-bit bus 132 .
- the flash memory 144 stores programs instructions that are executed on the microprocessor 122 and other components of the integrated transceiver 106 (such as the DSP engine 118 ). For example, in one embodiment, when the DSL unit 100 is powered on, any program instructions stored in the flash memory 144 are downloaded from the flash memory 144 to the microprocessor 122 and the other components for execution thereon.
- the flash memory 144 is a 512 kilobit by 8 bit flash memory.
- the DSL unit 100 also includes a non-volatile random access memory 148 that is coupled to the microprocessor 122 .
- Line interface settings and PRM data are stored in and retrieved from the non-volatile RAM 148 by the microprocessor 122 over the serial bus 144 .
- the non-volatile RAM 148 is a 16 kilobit by 8 bit non-volatile RAM.
- the DSL unit 100 also includes a power supply 150 that supplies power to the various components of the DSL unit 100 .
- the TDM line interface unit 108 receives a downstream analog DS1 signal from the TDM communication link 130 and converts the analog DS1 signal to a digital PCM signal for the TDM framer 120 .
- the TDM framer 120 outputs a serial digital DS1 data stream that is encapsulated into a stream of HDSL2 or G.SHDSL frames by the HDSL2/G.SHDSL framer 128 .
- the output of the HDSL2/G.SHDSL framer 128 is encoded and bit-to-level mapped by the HDSL2/G.SHDSL data pump 126 and is output to the analog front end 110 .
- the AFE 110 receives the digital PAM data stream from the integrated transceiver 106 , converts the digital stream to an analog signal, and filters the analog signal to suppress out-of-band noise.
- the analog signal is output to a line driver 112 for amplification and application to the twisted-pair telephone line 116 by the hybrid circuit 114 .
- the AFE 110 receives an HDSL2/G.SHDSL2 analog signal from the hybrid circuit 114 , amplifies the received analog signal, and converts the amplified analog signal to a digital signal.
- the digital signal is output to the HDSL2/G.SHDSL data pump 126 , which decodes and level-to-bit maps the received digital signal.
- the HDSL2/G.SHDSL framer 128 outputs digital DS1 data to the TDM framer 120 which encapsulates the DS1 data into appropriate T1/E1 frames for transmission onto the TDM communication link 130 via the TDM line interface unit 108 .
- Embodiments of the integrated transceiver 106 have an improved speed of operation because the microprocessor 122 is able to communicate with the DSP engine 118 , T1/E1 framer 120 , and static RAM 124 at a high clock rate over the internal 16-bit bus 132 . Also, the amount of power required for those components to communicate with one another is reduced by using embodiments of the integrated transceiver 106 . Moreover, the amount of board space that is needed to accommodate a DSP engine, T1/E1 framer, microprocessor, and static RAM is reduced by using embodiments of the integrated transceiver 106 . This allows greater flexibility in designing embodiments of the DSL unit 100 .
- embodiments of the integrated transceiver 106 can reduce the amount of testing and integration that is required to incorporate a DSP engine, T1/E1 framer, microprocessor, and the static random access memory into a line unit.
- the integrated transceiver 106 can be implemented as an all digital device that contains only digital components.
- FIG. 2 is a block diagram of an alternative embodiment of a digital subscriber line unit 200 .
- Embodiments of DSL unit 200 are suitable for use in, for example, a line unit housed within a central office of a service provider and/or a remote unit located at a remote site (for example, a remote unit housed within a remote terminal).
- the embodiment of the DSL unit 200 shown in FIG. 2 supports communicating over an HDSL2 or G.SHDSL communication link.
- other DSL communication links for example, HDSL and/or HDSL4 communication links
- Digital subscriber line unit 200 is used to send and receive DS1 traffic over an HDSL2 or G.SHDSL communication link using one twisted-pair telephone line.
- Data received from the HDSL2 or G.SHDSL link is coupled to a TDM link that is cross-connected to a TDM network.
- the TDM link is a T1 or E1 communication link.
- the embodiment of a DSL unit 200 shown in FIG. 2 is similar to the embodiment of the DSL unit 100 shown in FIG. 1 except that an integrated transceiver 206 of the DSL unit 200 does not include a TDM framer 220 . Instead, the TDM framer 220 and a TDM line interface unit 208 are external to the integrated transceiver 206 . For example, in one embodiment, the T1/E1 framer 220 and T1/E1 line interface unit 208 are physically embodied together in a single integrated circuit. Elements of the embodiment of DSL unit 200 shown in FIG. 2 corresponding to respective elements of the embodiment of the DSL unit 100 shown in FIG. 1 are numbered with like reference numbers that are incremented by 100.
- the methods and techniques described here may be implemented in digital electronic circuitry, or with a programmable processor (for example, a special-purpose processor or a general-purpose processor such as a computer) firmware, software, or in combinations of them.
- Apparatus embodying these techniques may include appropriate input and output devices, a programmable processor, and a storage medium tangibly embodying program instructions for execution by the programmable processor.
- a process embodying these techniques may be performed by a programmable processor executing a program of instructions to perform desired functions by operating on input data and generating appropriate output.
- the techniques may advantageously be implemented in one or more programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device.
- a processor will receive instructions and data from a read-only memory and/or a random access memory.
- Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and DVD disks. Any of the foregoing may be supplemented by, or incorporated in, specially-designed application-specific integrated circuits (ASICs).
- ASICs application-specific integrated circuits
Abstract
Description
- The following description relates to telecommunications in general and to digital subscriber line (DSL) devices in particular.
- One way in which telecommunication service providers provide high-speed digital communication services is by using digital subscriber line (DSL) technology. In one typical configuration, a line unit located in a central office of a service provider communicates with a remote unit located at a remote site. The central office line unit communicates with the remote unit over a high bit-rate digital subscriber line 2 (HDSL2) communication link or a symmetric digital subscriber line communication link supporting the ITU G.991.2 standard (referred to here as “G.SHDSL”). Such a HDSL2 or G.SHDSL link uses one twisted-pair telephone line. In other configurations, the central office line unit communicates with the remote unit over a high bit-rate DSL (HDSL or HDSL1) or a high bit-rate DSL 4 (HDSL4) communication link using two twisted-pair telephone lines.
- The line unit and the remote unit typically include various components such as a hybrid circuit, a line driver, an analog front end, a digital signal processing (DSP) engine, a T1/E1 framer, and a T1/E1 line interface unit along with a microprocessor and different types of memory. Typically the T1/E1 framer, DSP engine, and microprocessor are physically embodied in separate components. This can lead to increased costs in constructing a line unit or remote unit from these components due to, for example, increased costs associated with procuring, integrating, and testing the different components.
- In one embodiment, an integrated digital subscriber line transceiver includes a single integrated circuit having a digital signal processing engine adapted to couple the transceiver to at least one digital subscriber line communication link. The single integrated circuit also includes a time division multiplexing framer adapted to couple the transceiver to at least one time division multiplexing communication link. The single integrated circuit further includes a static random access memory and a microprocessor. The microprocessor is coupled to the digital signal processing engine, the time division multiplexing framer, and the static random access memory.
- In another embodiment, a digital subscriber line unit includes an analog interface adapted to couple the digital subscriber line unit to at least one digital subscriber line communication link. The digital subscriber line unit further includes a time division multiplexing line interface unit adapted to couple the digital subscriber line unit to at least one time division multiplexing communication link. The digital subscriber line unit further includes an integrated digital subscriber line transceiver. The integrated digital subscriber line transceiver includes a single integrated circuit having a digital signal processing engine coupled to the analog interface. The single integrated circuit further includes a time division multiplexing framer coupled to the time division multiplexing line interface unit. The single integrated circuit further includes a static random access memory and a microprocessor. The microprocessor is coupled to the digital signal processing engine, the time division multiplexing framer, and the static random access memory.
- In another embodiment, an integrated digital subscriber line transceiver includes a single integrated circuit having a digital signal processing engine adapted to couple the transceiver to at least one digital subscriber line communication link and to at least one time division multiplexing communication link. The single integrated circuit further includes a static random access memory and a microprocessor. The microprocessor is coupled to the digital signal processing engine and the static random access memory.
- In another embodiment, a digital subscriber line unit includes an analog interface adapted to couple the digital subscriber line unit to at least one digital subscriber line communication link. The digital subscriber line unit further includes a time division multiplexing line interface unit adapted to couple the digital subscriber line unit to at least one time division multiplexing communication link. The digital subscriber line unit further includes a time division multiplexing framer coupled to the time division multiplexing line interface unit and an integrated digital subscriber line transceiver. The integrated digital subscriber line transceiver includes a single integrated circuit having a digital signal processing engine coupled to the analog interface and the time division multiplexing framer. The single integrated circuit further includes a static random access memory and a microprocessor. The microprocessor is coupled to the digital signal processing engine, the time division multiplexing framer, and the static random access memory.
- The details of one or more embodiments of the claimed invention are set forth in the accompanying drawings and the description below. Other features and advantages will become apparent from the description, the drawings, and the claims.
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FIG. 1 is a block diagram of one embodiment of a line unit having an integrated transceiver. -
FIG. 2 is a block diagram of another embodiment of a line unit having an integrated transceiver. - Like reference numbers and designations in the various drawings indicate like elements.
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FIG. 1 is a block diagram of one embodiment of a digital subscriber line (DSL)unit 100. Embodiments ofDSL unit 100 are suitable for use in, for example, a line unit housed within a central office of a service provider and/or a remote unit located at a remote site (for example, a remote unit housed within a remote terminal). The embodiment of theDSL unit 100 shown inFIG. 1 supports communicating over an HDSL2 or G.SHDSL communication link. In other embodiments, other DSL communication links (for example, HDSL and/or HDSL4 communication links) are supported in addition to, or instead of, HDSL2 and/or G.SHDSL communication links.DSL unit 100 is used to send and receive DS1 traffic over an HDSL2 or G.SHDSL communication link using one twisted-pair telephone line (also referred to here as a “local loop” or “loop”). Data received from the HDSL2 or G.SHDSL link is coupled to a time division multiplexing (TDM) link that is cross-connected to a TDM network. In the embodiment shown inFIG. 1 , the TDM link is a T1 or El communication link. - Digital
subscriber line unit 100 includes ananalog interface 104, an integratedtransceiver 106, and a TDMline interface unit 108. Theanalog interface 104 includes an analog front end (AFE) 110. Theanalog front end 110 includes a transmit channel and a receive channel (not shown inFIG. 1 ). In the transmit channel, the AFE 110 receives a digital pulse amplitude modulated (PAM) data stream from the integratedtransceiver 106, converts the digital stream to an analog signal, and filters the analog signal to suppress out-of-band noise. The analog signal is output to aline driver 112 for amplification. In the receive channel, the AFE 110 receives an analog signal from ahybrid circuit 114, amplifies the received analog signal, and converts the amplified analog signal to a digital signal. The digital signal is output to the integratedtransceiver 106. - The
hybrid circuit 114 couples theanalog interface 104 to a twisted-pair telephone line 116. In embodiments ofDSL unit 100 that support an HDSL2 single pair communication link, thehybrid circuit 114 couples one twisted-pair telephone line to theanalog interface 104. In other embodiments, thehybrid circuit 114 couples theanalog interface 104 to multiple twisted-pair telephone lines (for example, 2 telephone lines in the case of HDSL, HDSL4, or 2-pair G.SHDSL embodiments). A separate 2-line transmit path and a separate 2-line receive path for each twisted-pair telephone line is provided between the AFE 110 and the integratedtransceiver 106. In one embodiment, theanalog interface 104 is implemented as a single integrated circuit that includes theanalog front end 110, theline driver 112, and thehybrid circuit 114. - The integrated
transceiver 106 is a single integrated circuit that includes a digital signal processing (DSP)engine 118, a time division multiplexing (TDM)framer 120, amicroprocessor 122 and a staticrandom access memory 124. In the embodiment shown inFIG. 1 , theDSP engine 118 supports G.SHDSL and HDSL2 communication links, in other embodiments other DSL communication links (such as HDSL or HDSL4 communication links) are supported in addition to, or instead of, HDSL2 and/or G.SHDSL communication links. TheDSP engine 118 includes an HDSL2/G.SHDSL data pump 126 and an HDSL2/G.SHDSL framer 128. In the embodiment shown inFIG. 1 , theTDM framer 120 is a framer that supports T1 and/or E1 communication links. - In the downstream, the TDM
line interface unit 108 receives an analog DS1 signal from a TDM communication link 130 (such as a T1/E1 communication link) and converts the analog DS1 signal to a digital pulse code modulated (PCM) signal for theTDM framer 120. The TDM framer 120 outputs a serial digital DS1 data stream that is encapsulated into a stream of HDSL2 or G.SHDSL frames by the HDSL2/G.SHDSL framer 128. The output of the HDSL2/G.SHDSL framer 128 is encoded and bit-to-level mapped by the HDSL2/G.SHDSL data pump 126 and is output to theanalog front end 110. - In the upstream, the HDSL2/G.SHDSL data pump 126 receives HDSL2 or G.SHDSL frames from the analog
front end 110, which are decoded and level-to-bit mapped. The HDSL2/G.SHDSL framer 128 outputs DS1 data to theTDM framer 120, which encapsulates the DS1 data into appropriate TDM frames (for example, T1 or E1 frames) for transmission onto the TDM communication link 130 via the TDMline interface unit 108. In the embodiment shown inFIG. 1 , the TDMline interface unit 108 is embodied as a physically separate device and supports T1 and/or E1 communication links. - The
microprocessor 122 communicates with and controls the operation of theDSP engine 118 and theTDM framer 120. In the embodiment shown inFIG. 1 , themicroprocessor 122 communicates with theDSP engine 118 and theTDM framer 120 over a 16-bit bus 132. Themicroprocessor 122 is coupled to static random access memory (RAM) 124 over the 16-bit bus 132. Program instructions executed by themicroprocessor 120 along with data used by themicroprocessor 122 and other components of thetransceiver 106 are stored in and retrieved from thestatic RAM 124. In one implementation, thestatic RAM 124 is a 128 kilobit by 8 bit static RAM. - The
integrated transceiver 106 also includes a dual universal asynchronous receiver-transmitter (UART) 134. Thedual UART 134 couples themicroprocessor 122 to a RS-232serial port 136. A data terminal (not shown) can be connected to the RS-232serial port 136 in order to communicate with a control program executing on themicroprocessor 122. In one embodiment, the control program is used to view and/or modify various configuration and status parameters of theDSL unit 100. Thedual UART 134 also is used to couple themicroprocessor 122 to a backplane (not shown) of a chassis in which theDSL unit 100 is housed. This allows a management program executing on a device external to theDSL unit 100 to communicate with themicroprocessor 122 and the control program executing thereon over the backplane of the chassis. - The
integrated transceiver 106 also includes a clock generator 138 that provides a clock signal to the components of thetransceiver 106 and theDSL unit 100 based on a signal from aclock oscillator 140. In the embodiment shown inFIG. 1 , theclock oscillator 140 is external to thetransceiver 106. Themicroprocessor 122 also communicates with adisplay 142 over aserial bus 144. In the embodiment shown inFIG. 1 , the TDMline interface unit 108 also communicates with thedisplay 142.Display 142 is used to display, for example, information about theDSL unit 100 and/or theTDM communication link 130. In one embodiment,display 142 includes a 4-character LED display mounted on a front panel of theDSL unit 100. - The
DSL unit 100 also includes aflash memory 146. Theflash memory 146 is coupled to themicroprocessor 122 via the 16-bit bus 132. Theflash memory 144 stores programs instructions that are executed on themicroprocessor 122 and other components of the integrated transceiver 106 (such as the DSP engine 118). For example, in one embodiment, when theDSL unit 100 is powered on, any program instructions stored in theflash memory 144 are downloaded from theflash memory 144 to themicroprocessor 122 and the other components for execution thereon. In one implementation, theflash memory 144 is a 512 kilobit by 8 bit flash memory. - The
DSL unit 100 also includes a non-volatilerandom access memory 148 that is coupled to themicroprocessor 122. Line interface settings and PRM data are stored in and retrieved from thenon-volatile RAM 148 by themicroprocessor 122 over theserial bus 144. In one implementation, thenon-volatile RAM 148 is a 16 kilobit by 8 bit non-volatile RAM. TheDSL unit 100 also includes apower supply 150 that supplies power to the various components of theDSL unit 100. - In operation, the TDM
line interface unit 108 receives a downstream analog DS1 signal from theTDM communication link 130 and converts the analog DS1 signal to a digital PCM signal for theTDM framer 120. TheTDM framer 120 outputs a serial digital DS1 data stream that is encapsulated into a stream of HDSL2 or G.SHDSL frames by the HDSL2/G.SHDSL framer 128. The output of the HDSL2/G.SHDSL framer 128 is encoded and bit-to-level mapped by the HDSL2/G.SHDSL data pump 126 and is output to the analogfront end 110. TheAFE 110 receives the digital PAM data stream from theintegrated transceiver 106, converts the digital stream to an analog signal, and filters the analog signal to suppress out-of-band noise. The analog signal is output to aline driver 112 for amplification and application to the twisted-pair telephone line 116 by thehybrid circuit 114. - In the upstream direction, the
AFE 110 receives an HDSL2/G.SHDSL2 analog signal from thehybrid circuit 114, amplifies the received analog signal, and converts the amplified analog signal to a digital signal. The digital signal is output to the HDSL2/G.SHDSL data pump 126, which decodes and level-to-bit maps the received digital signal. The HDSL2/G.SHDSL framer 128 outputs digital DS1 data to theTDM framer 120 which encapsulates the DS1 data into appropriate T1/E1 frames for transmission onto the TDM communication link 130 via the TDMline interface unit 108. - Embodiments of the
integrated transceiver 106 have an improved speed of operation because themicroprocessor 122 is able to communicate with theDSP engine 118, T1/E1 framer 120, andstatic RAM 124 at a high clock rate over the internal 16-bit bus 132. Also, the amount of power required for those components to communicate with one another is reduced by using embodiments of theintegrated transceiver 106. Moreover, the amount of board space that is needed to accommodate a DSP engine, T1/E1 framer, microprocessor, and static RAM is reduced by using embodiments of theintegrated transceiver 106. This allows greater flexibility in designing embodiments of theDSL unit 100. Furthermore, embodiments of theintegrated transceiver 106 can reduce the amount of testing and integration that is required to incorporate a DSP engine, T1/E1 framer, microprocessor, and the static random access memory into a line unit. In addition, theintegrated transceiver 106 can be implemented as an all digital device that contains only digital components. -
FIG. 2 is a block diagram of an alternative embodiment of a digital subscriber line unit 200. Embodiments of DSL unit 200 are suitable for use in, for example, a line unit housed within a central office of a service provider and/or a remote unit located at a remote site (for example, a remote unit housed within a remote terminal). The embodiment of the DSL unit 200 shown inFIG. 2 supports communicating over an HDSL2 or G.SHDSL communication link. In other embodiments, other DSL communication links (for example, HDSL and/or HDSL4 communication links) are supported in addition to, or instead of, HDSL2 and/or G.SHDSL communication links. Digital subscriber line unit 200 is used to send and receive DS1 traffic over an HDSL2 or G.SHDSL communication link using one twisted-pair telephone line. Data received from the HDSL2 or G.SHDSL link is coupled to a TDM link that is cross-connected to a TDM network. In the embodiment shown inFIG. 2 , the TDM link is a T1 or E1 communication link. - The embodiment of a DSL unit 200 shown in
FIG. 2 is similar to the embodiment of theDSL unit 100 shown inFIG. 1 except that an integrated transceiver 206 of the DSL unit 200 does not include aTDM framer 220. Instead, theTDM framer 220 and a TDM line interface unit 208 are external to the integrated transceiver 206. For example, in one embodiment, the T1/E1 framer 220 and T1/E1 line interface unit 208 are physically embodied together in a single integrated circuit. Elements of the embodiment of DSL unit 200 shown inFIG. 2 corresponding to respective elements of the embodiment of theDSL unit 100 shown inFIG. 1 are numbered with like reference numbers that are incremented by 100. - The methods and techniques described here may be implemented in digital electronic circuitry, or with a programmable processor (for example, a special-purpose processor or a general-purpose processor such as a computer) firmware, software, or in combinations of them. Apparatus embodying these techniques may include appropriate input and output devices, a programmable processor, and a storage medium tangibly embodying program instructions for execution by the programmable processor. A process embodying these techniques may be performed by a programmable processor executing a program of instructions to perform desired functions by operating on input data and generating appropriate output. The techniques may advantageously be implemented in one or more programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and DVD disks. Any of the foregoing may be supplemented by, or incorporated in, specially-designed application-specific integrated circuits (ASICs).
- A number of embodiments of the invention defined by the following claims have been described. Nevertheless, it will be understood that various modifications to the described embodiments may be made without departing from the spirit and scope of the claimed invention. Accordingly, other embodiments are within the scope of the following claims.
Claims (34)
Priority Applications (2)
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US10/641,702 US7190783B2 (en) | 2003-08-15 | 2003-08-15 | Integrated digital subscriber line transceiver |
CA2456397A CA2456397C (en) | 2003-08-15 | 2004-01-28 | Integrated digital subscriber line transceiver |
Applications Claiming Priority (1)
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US10/641,702 US7190783B2 (en) | 2003-08-15 | 2003-08-15 | Integrated digital subscriber line transceiver |
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US20050047432A1 true US20050047432A1 (en) | 2005-03-03 |
US7190783B2 US7190783B2 (en) | 2007-03-13 |
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US10/641,702 Active 2025-08-23 US7190783B2 (en) | 2003-08-15 | 2003-08-15 | Integrated digital subscriber line transceiver |
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US (1) | US7190783B2 (en) |
CA (1) | CA2456397C (en) |
Cited By (3)
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US20040014493A1 (en) * | 2001-01-26 | 2004-01-22 | Adtran, Inc. | Use of T1 facility data link to transport status and configuration data packets for loop-powered T1 radio |
US20070253443A1 (en) * | 2006-04-27 | 2007-11-01 | Sbc Knowledge Ventures L.P. | Data services over G.SHDSL transport infrastructure |
CN110601721A (en) * | 2019-10-23 | 2019-12-20 | 四川灵通电讯有限公司 | Dynamic management device for power consumption of digital subscriber line and application method |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20060188259A1 (en) * | 2005-02-19 | 2006-08-24 | James Furey | HDSL optical fiber transmission system and method |
US8098587B2 (en) * | 2005-12-22 | 2012-01-17 | At&T Intellectual Property I, L.P. | Network access device |
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US7023877B1 (en) * | 2001-10-31 | 2006-04-04 | Godigital Networks Corporation | Small form factor digital voice multiplexer with multiple DSL outputs |
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US6959376B1 (en) * | 2001-10-11 | 2005-10-25 | Lsi Logic Corporation | Integrated circuit containing multiple digital signal processors |
US7023877B1 (en) * | 2001-10-31 | 2006-04-04 | Godigital Networks Corporation | Small form factor digital voice multiplexer with multiple DSL outputs |
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US20040014493A1 (en) * | 2001-01-26 | 2004-01-22 | Adtran, Inc. | Use of T1 facility data link to transport status and configuration data packets for loop-powered T1 radio |
US7539479B2 (en) * | 2001-01-26 | 2009-05-26 | Adtran, Inc. | Use of T1 facility data link to transport status and configuration data packets for loop-powered T1 radio |
US20070253443A1 (en) * | 2006-04-27 | 2007-11-01 | Sbc Knowledge Ventures L.P. | Data services over G.SHDSL transport infrastructure |
EP2011292A2 (en) * | 2006-04-27 | 2009-01-07 | AT&T Intellectual Property I, L.P. | Data services over g.shdsl transport infrastructure |
EP2011292A4 (en) * | 2006-04-27 | 2011-01-05 | At & T Ip I Lp | Data services over g.shdsl transport infrastructure |
CN110601721A (en) * | 2019-10-23 | 2019-12-20 | 四川灵通电讯有限公司 | Dynamic management device for power consumption of digital subscriber line and application method |
Also Published As
Publication number | Publication date |
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CA2456397C (en) | 2011-11-01 |
CA2456397A1 (en) | 2005-02-15 |
US7190783B2 (en) | 2007-03-13 |
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