US20050045936A1 - Dynamic random access memory cell layout and fabrication method thereof - Google Patents
Dynamic random access memory cell layout and fabrication method thereof Download PDFInfo
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- US20050045936A1 US20050045936A1 US10/761,985 US76198504A US2005045936A1 US 20050045936 A1 US20050045936 A1 US 20050045936A1 US 76198504 A US76198504 A US 76198504A US 2005045936 A1 US2005045936 A1 US 2005045936A1
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- 229910052710 silicon Inorganic materials 0.000 claims description 16
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 claims 2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
- H10B12/373—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate the capacitor extending under or around the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Definitions
- the invention relates to a memory cell of a semiconductor device, and more particularly to a dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof.
- DRAM dynamic random access memory
- a dynamic random access memory (DRAM) cell typically includes a memory cell coupled to a storage capacitor.
- the storage capacitor is formed within a deep trench etched into a semiconductor substrate.
- the storage capacitor is accessed using an access transistor which allows charge to be stored in the storage capacitor or retrieves charge from the storage capacitor depending on whether the desired action is a read or write function.
- dopant outdiffusion near a wordline can cause a short channel effect in the access transistor channel, thus reducing subthreshold conduction and causing a fail in retention time.
- FIG. 1 is a conventional DRAM cell layout. Deep trench capacitors 10 are disposed under passing wordlines 12 . Access transistors 14 are electrically coupled to storage nodes 16 of the trench capacitors 10 through diffusion regions 18 which may be either a source or a drain of the access transistors 14 . Diffusion regions 20 are electrically connected to bitline contacts 22 which connect to bitlines (not shown) to read and write to the storage nodes 16 through the access transistors 14 . Access transistors 14 are activated by the wordlines 12 . When voltage is applied to the wordlines 12 , a channel below the wordline 12 conducts and allows current to flow between diffusion regions 18 and 20 and into or out of the storage node 16 . Wordlines 12 are preferably spaced across the smallest possible distance to conserve the layout area. The smallest possible distance is typically a minimum feature size “F”.
- FIG. 2 is a cross-section along line 2 - 2 of FIG. 1 . Elements of FIG. 2 are labeled as described in FIG. 1 .
- the storage nodes 16 are isolated from a doped well 24 by a dielectric collar 26 .
- a shallow trench isolation (STI) 28 is provided over the storage nodes 16 to electrically isolate the passing wordlines 12 formed above storage nodes 16 .
- the diffusion region 18 of the access transistor 14 is connected to the storage node 16 through a buried strap (BS) 32 and a BS out-diffusion region 30 .
- BS buried strap
- BS buried strap
- an object of the present invention is to provide a DRAM cell layout and a fabrication method thereof to improve subthreshold conduction and retention time performance.
- a dynamic random access memory cell layout has a first gate conductor pair and a second gate conductor pair extending along a first direction, in which each gate conductor pair comprises a first gate conductive line and a second gate conductive line.
- a bitline pair has a first bitline and a second bitline, which extend along a second direction and intersect the gate conductor pairs.
- a first active area extends along the second direction to cross the first gate conductor pair.
- a second active area extends along the second direction to cross the second gate conductor pair.
- Each active area has a first deep trench and a second deep trench formed in a substrate underneath the first gate conductive line and the second gate conductive line, respectively.
- a bitline contact is formed between the first gate conductive line and the second gate conductive line to be electrically connected to the corresponding bitline.
- a common source/drain region is formed in the substrate between the first gate conductive line and the second gate conductive line to be electrically connected to the bitline contact.
- a first vertical transistor and a second vertical transistor are formed overlying the first deep trench and the second deep trench, respectively. Each vertical transistor has a buried strap out-diffusion region formed in the substrate adjacent to one sidewall of the deep trench.
- FIG. 1 is a conventional DRAM cell layout.
- FIG. 2 is a cross-section along line 2 - 2 of FIG. 1 .
- FIG. 3 is a DRAM cell layout of deep trenches and active areas according to the first embodiment of the present invention.
- FIG. 4 is a cross-section along line 4 - 4 of FIG. 3 .
- FIG. 5 is a DRAM cell layout of deep trenches and active areas according to the second embodiment of the present invention.
- FIG. 6 is a three-dimensional diagram of a vertical transistor according to the second embodiment of the present invention.
- FIGS. 7A-7L are cross-sections of a fabrication method for above-described deep trenches and vertical transistors.
- FIG. 3 is a DRAM cell layout of deep trenches and active areas according to the first embodiment of the present invention.
- the DRAM cell layout comprises a plurality of gate conductor pairs P 1 , P 2 and P 3 and a plurality of bitlines BL 1 and BL 2 .
- Each of the gate conductor pairs P 1 , P 2 and P 3 comprises a first gate conductive line GC 1 and a second gate conductive line GC 2 arranged parallel to each other.
- the gate conductive lines GC 1 and GC 2 extending along a first direction and the bitlines BL 1 and BL 2 extending along a second direction intersect to define a plurality of DRAM cells.
- a first active area AA 1 is defined at the intersection of the second gate conductor pair P 2 and the first bitline BL 1 .
- a second active area AA 2 is defined at the intersection of the first gate conductor pair P 1 and the second bitline BL 2 , alternatively, at the intersection of the third gate conductor pair P 3 and the second bitline BL 2 .
- the first active area AA 1 extends along the first bitline BL 1 to cross the first gate conductive line GC 1 and a second gate conductive line GC 2 of the second gate conductor pair P 2 , and comprises two vertical transistors T 1 and T 2 , a common bitline contact BC and two deep trenches DT 1 and DT 2 .
- the first vertical transistor T 1 is formed on a region where the first deep trench DT 1 is partially overlapped with the first gate conductive line GC 1 .
- the second vertical transistor T 2 is formed on a region where the second deep trench DT 2 is partially overlapped with the second gate conductive line GC 2 .
- the second active area AA 2 extends along the second bitline BL 2 to cross the first gate conductive line GC 1 and a second gate conductive line GC 2 of the first gate conductor pair P 1 . Alternatively, the second active area AA 2 crosses the first gate conductive line GC 1 and a second gate conductive line GC 2 of the third gate conductor pair P 3 .
- the second active area AA 2 comprises two vertical transistors T 1 and T 2 , a common bitline contact BC and two deep trenches DT 1 and DT 2 .
- the first vertical transistor T 1 is formed on a region where the first deep trench DT 1 is partially overlapped with the first gate conductive line GC 1 .
- the second vertical transistor T 2 is formed on a region where the second deep trench DT 2 is partially overlapped with the second gate conductive line GC 2 .
- FIG. 4 is a cross-section along line 4 - 4 of FIG. 3 .
- the first deep trench DT 1 and the second deep trench DT 2 are formed by etching a semiconductor silicon substrate 40 , and a shallow trench isolation structure STI is formed outside the first deep trench DT 1 and the second deep trench DT 2 for isolating the first active area AA 1 from the second active area AA 2 .
- a first deep trench capacitor C 1 and a second deep trench capacitor C 2 are formed at the lower portions of the first deep trench DT 1 and the second deep trench DT 2 , respectively.
- a first buried strap out-diffusion region BS 1 is formed in the substrate 40 adjacent to one sidewall of the middle portion of the first deep trench D 1 .
- the first buried strap out-diffusion region BS 1 serves as a source/drain region of the first vertical transistor T 1 , and provides an electrical connection between the first vertical transistor T 1 and the first deep trench capacitor C 1 .
- a second buried strap out-diffusion region BS 2 is formed in the substrate 40 adjacent to one sidewall of the middle portion of the second deep trench D 2 .
- the second buried strap out-diffusion region BS 2 serves as a source/drain region of the second vertical transistor T 2 , and provides an electrical connection between the second vertical transistor T 2 and the second deep trench capacitor C 2 .
- the first gate conductive line GC 1 partially overlaps the upper portion of first deep trench DT 1 to serve as a gate electrode of the first vertical transistor T 1 .
- the second gate conductive line GC 2 partially overlaps the upper portion of second deep trench DT 2 to serve as a gate electrode of the second vertical transistor T 2 .
- a common source/drain region S/D is formed in the substrate 40 between the first gate conductive line GC 1 and the second gate conductive line GC 2 .
- a first vertical channel region is provided between the common source/drain region S/D and the first buried strap out-diffusion region BS 1
- a second vertical channel region is provided between the common source/drain region S/D and the second buried strap out-diffusion region BS 2 .
- the bitline contact BC is formed overlying the common source/drain region S/D and electrically connected to the first bitline BL 1 . Accordingly, the DRAM cell layout of the vertical transistors T 1 and T 2 and the deep trenches DT 1 and DT 2 can prevent deterioration of subthreshold conduction, thus improving retention time performance.
- FIG. 5 is a DRAM cell layout of deep trenches and active areas according to the second embodiment of the present invention.
- FIG. 6 is a three-dimensional diagram of a vertical transistor according to the second embodiment of the present invention. Elements similar to those shown in FIGS. 3 and 4 are omitted here.
- the DRAM cell layout of deep trenches and active areas of the second embodiment is substantially similar to that of the first embodiment, with the similar portions omitted herein.
- the different portion is the profile of the overlapping region between the deep trench and the vertical transistor.
- the sidewall profile of the deep trench is a line.
- the sidewall profile of the deep trench comprises at least three edges. For example, a five-edge sidewall profile, such as a -shaped sidewall.
- the first deep trench DT 1 is partially overlapped with the first gate conductive line GC 1 , and the first deep trench DT 1 comprises a -shaped sidewall within the overlapping portion therebetween.
- the second deep trench DT 2 is partially overlapped with the second gate conductive line GC 2 , and the second deep trench DT 2 comprises a -shaped sidewall within the overlapping portion therebetween. Therefore, the vertical channel region between the common source/drain region S/D and the buried strap out-diffusion region BS becomes a multilateral structure, viewed as a three-dimensional design, which can further improve subthreshold conduction and retention time performance.
- FIGS. 7A-7L are cross-sections of a fabrication method for above-described deep trenches and vertical transistors.
- an array area I and a support area II are defined on a semiconductor silicon substrate 40 .
- a p-type semiconductor silicon substrate 40 is described below for example.
- a pad layer 41 and a reactive ion etching (RIE) method are employed to pattern a deep trench DT in the substrate 40 within the array area I.
- RIE reactive ion etching
- a deep trench capacitor 42 including a bottom electrode plate 44 , a capacitor dielectric 46 and an upper electrode plate 48 is fabricated at the lower portion of the deep trench DT.
- the bottom electrode plate 44 is an n + -type diffusion region
- the capacitor dielectric 46 is an ONO (oxide-nitride-oxide) stack structure
- the upper electrode plate 48 is a first polysilicon layer with n + -type dopants.
- a collar dielectric layer 50 is formed on the sidewall of the deep trench DT.
- a second polysilicon layer 52 with n + -type dopants and a third polysilicon layer 54 are formed in the deep trench DT.
- a thermal diffusion process is employed to make the n + -type dopants diffuse through the third polysilicon layer 54 into the substrate 40 , resulting in a buried strap out-diffusion region 56 in the substrate 40 adjacent to the third polysilicon layer 54 .
- deposition and etching are used to form a top isolating layer 58 on the third polysilicon layer 54 .
- an anti-reflective coating (ARC) layer 60 is formed in the deep trench DT, and a first photoresist layer 62 is patterned on the substrate 40 for defining shallow trench isolations in the array area I and the support area II.
- the exposed portions of the pad layer 41 and the semiconductor silicon substrate 40 are removed to form shallow trenches 63 , as shown in FIG. 7C , thus defining an active area AA within the array area I.
- the ARC layer 60 and the first photoresist layer 62 are removed.
- a nitride liner 64 is conformally deposited on the substrate 40 , and then a first HDP (high density plasma) oxide layer 66 is formed to fill the shallow trenches 63 .
- CMP chemical mechanical polishing
- a second photoresist layer 68 is provided to cover the support area II.
- the first HDP oxide layer 66 within the array area I is removed.
- the second photoresist layer 68 is removed.
- FIG. 7F after removing the nitride liner 64 and the pad layer 41 , a sacrificial oxide layer is formed so as to perform an ion implantation process on the array area I and the support area II for adjusting device threshold voltage.
- FIG. 7G after removing the sacrificial oxide layer, a thermal oxidation process is employed to grow a gate oxide layer 70 on the exposed silicon surface of the substrate 40 .
- a gate polysilicon layer 72 a metallic silicide layer 74 (such as a WSi layer) and a nitride cap layer 76 are successively deposited on the substrate 40 .
- the gate polysilicon layer 72 , the metallic silicide layer 74 and the nitride cap layer 76 within the array area I are patterned as a gate conductive line GC, which partially overlaps two tops of two adjacent deep trenches DT.
- a second HDP oxide layer 80 is formed to fill the shallow trench 63 outside the active area AA of the array area I, and then CMP is employed to level off the top surfaces of the second HDP oxide layer 80 and the gate conductive line GC.
- a first contact hole 82 I is formed to penetrate the gate conductive line GC and the gate oxide layer 70 , thus exposing the substrate 40 .
- a nitride spacer 84 is formed on the sidewall of the first contact hole 82 I, and then an ion implantation process is performed to form a source/drain diffusion region 86 in the semiconductor silicon substrate 40 exposed by the first contact hole 82 I.
- deposition and CMP for a BPSG layer 88 and deposition and annealing for a TEOS oxide layer 90 are successively performed thereon.
- a second contact hole 821 I is formed to expose the first contact hole 82 I and the source/drain diffusion region 86 .
- the second contact hole 821 I is filled with a polysilicon contact layer 92 , and then a W/TiN/Ti layer 94 is formed on the polysilicon contact layer 92 , and then a bitline 96 is patterned thereon.
Abstract
A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.
Description
- 1. Field of the Invention
- The invention relates to a memory cell of a semiconductor device, and more particularly to a dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof.
- 2. Description of the Related Art
- A dynamic random access memory (DRAM) cell typically includes a memory cell coupled to a storage capacitor. Generally the storage capacitor is formed within a deep trench etched into a semiconductor substrate. The storage capacitor is accessed using an access transistor which allows charge to be stored in the storage capacitor or retrieves charge from the storage capacitor depending on whether the desired action is a read or write function. For a buried strap type trench capacitor, dopant outdiffusion near a wordline can cause a short channel effect in the access transistor channel, thus reducing subthreshold conduction and causing a fail in retention time.
-
FIG. 1 is a conventional DRAM cell layout.Deep trench capacitors 10 are disposed under passingwordlines 12.Access transistors 14 are electrically coupled tostorage nodes 16 of thetrench capacitors 10 throughdiffusion regions 18 which may be either a source or a drain of theaccess transistors 14.Diffusion regions 20 are electrically connected tobitline contacts 22 which connect to bitlines (not shown) to read and write to thestorage nodes 16 through theaccess transistors 14.Access transistors 14 are activated by thewordlines 12. When voltage is applied to thewordlines 12, a channel below thewordline 12 conducts and allows current to flow betweendiffusion regions storage node 16. Wordlines 12 are preferably spaced across the smallest possible distance to conserve the layout area. The smallest possible distance is typically a minimum feature size “F”. -
FIG. 2 is a cross-section along line 2-2 ofFIG. 1 . Elements ofFIG. 2 are labeled as described inFIG. 1 . Thestorage nodes 16 are isolated from a doped well 24 by adielectric collar 26. A shallow trench isolation (STI) 28 is provided over thestorage nodes 16 to electrically isolate thepassing wordlines 12 formed abovestorage nodes 16. Thediffusion region 18 of theaccess transistor 14 is connected to thestorage node 16 through a buried strap (BS) 32 and a BS out-diffusion region 30. Considering an overlay tolerance effect, a BS merge phenomenon easily occurs to cause a short channel effect in achannel region 34 underlying agate electrode 36 of theaccess transistor 14. - Accordingly, an object of the present invention is to provide a DRAM cell layout and a fabrication method thereof to improve subthreshold conduction and retention time performance.
- According to the object of the invention, a dynamic random access memory cell layout has a first gate conductor pair and a second gate conductor pair extending along a first direction, in which each gate conductor pair comprises a first gate conductive line and a second gate conductive line. A bitline pair has a first bitline and a second bitline, which extend along a second direction and intersect the gate conductor pairs. Corresponding to the first bitline, a first active area extends along the second direction to cross the first gate conductor pair. Corresponding to the second bitline, a second active area extends along the second direction to cross the second gate conductor pair. Each active area has a first deep trench and a second deep trench formed in a substrate underneath the first gate conductive line and the second gate conductive line, respectively. A bitline contact is formed between the first gate conductive line and the second gate conductive line to be electrically connected to the corresponding bitline. A common source/drain region is formed in the substrate between the first gate conductive line and the second gate conductive line to be electrically connected to the bitline contact. A first vertical transistor and a second vertical transistor are formed overlying the first deep trench and the second deep trench, respectively. Each vertical transistor has a buried strap out-diffusion region formed in the substrate adjacent to one sidewall of the deep trench.
- The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.
-
FIG. 1 is a conventional DRAM cell layout. -
FIG. 2 is a cross-section along line 2-2 ofFIG. 1 . -
FIG. 3 is a DRAM cell layout of deep trenches and active areas according to the first embodiment of the present invention. -
FIG. 4 is a cross-section along line 4-4 ofFIG. 3 . -
FIG. 5 is a DRAM cell layout of deep trenches and active areas according to the second embodiment of the present invention. -
FIG. 6 is a three-dimensional diagram of a vertical transistor according to the second embodiment of the present invention. -
FIGS. 7A-7L are cross-sections of a fabrication method for above-described deep trenches and vertical transistors. - First Embodiment
-
FIG. 3 is a DRAM cell layout of deep trenches and active areas according to the first embodiment of the present invention. The DRAM cell layout comprises a plurality of gate conductor pairs P1, P2 and P3 and a plurality of bitlines BL1 and BL2. Each of the gate conductor pairs P1, P2 and P3 comprises a first gate conductive line GC1 and a second gate conductive line GC2 arranged parallel to each other. The gate conductive lines GC1 and GC2 extending along a first direction and the bitlines BL1 and BL2 extending along a second direction intersect to define a plurality of DRAM cells. A first active area AA1 is defined at the intersection of the second gate conductor pair P2 and the first bitline BL1. A second active area AA2 is defined at the intersection of the first gate conductor pair P1 and the second bitline BL2, alternatively, at the intersection of the third gate conductor pair P3 and the second bitline BL2. - The first active area AA1 extends along the first bitline BL1 to cross the first gate conductive line GC1 and a second gate conductive line GC2 of the second gate conductor pair P2, and comprises two vertical transistors T1 and T 2, a common bitline contact BC and two deep trenches DT1 and DT2. The first vertical transistor T1 is formed on a region where the first deep trench DT1 is partially overlapped with the first gate conductive line GC1. The second vertical transistor T2 is formed on a region where the second deep trench DT2 is partially overlapped with the second gate conductive line GC2.
- The second active area AA2 extends along the second bitline BL2 to cross the first gate conductive line GC1 and a second gate conductive line GC2 of the first gate conductor pair P1. Alternatively, the second active area AA2 crosses the first gate conductive line GC1 and a second gate conductive line GC2 of the third gate conductor pair P3. The second active area AA2 comprises two vertical transistors T1 and T2, a common bitline contact BC and two deep trenches DT1 and DT2. The first vertical transistor T1, is formed on a region where the first deep trench DT1 is partially overlapped with the first gate conductive line GC1. The second vertical transistor T2 is formed on a region where the second deep trench DT2 is partially overlapped with the second gate conductive line GC2.
-
FIG. 4 is a cross-section along line 4-4 ofFIG. 3 . For the first active area AA1, the first deep trench DT1 and the second deep trench DT2 are formed by etching asemiconductor silicon substrate 40, and a shallow trench isolation structure STI is formed outside the first deep trench DT1 and the second deep trench DT2 for isolating the first active area AA1 from the second active area AA2. A first deep trench capacitor C1 and a second deep trench capacitor C2 are formed at the lower portions of the first deep trench DT1 and the second deep trench DT2, respectively. A first buried strap out-diffusion region BS1 is formed in thesubstrate 40 adjacent to one sidewall of the middle portion of the first deep trench D1. The first buried strap out-diffusion region BS1 serves as a source/drain region of the first vertical transistor T1, and provides an electrical connection between the first vertical transistor T1 and the first deep trench capacitor C1. Similarly, a second buried strap out-diffusion region BS2 is formed in thesubstrate 40 adjacent to one sidewall of the middle portion of the second deep trench D2. The second buried strap out-diffusion region BS2 serves as a source/drain region of the second vertical transistor T2, and provides an electrical connection between the second vertical transistor T2 and the second deep trench capacitor C2. The first gate conductive line GC1 partially overlaps the upper portion of first deep trench DT1 to serve as a gate electrode of the first vertical transistor T1. The second gate conductive line GC2 partially overlaps the upper portion of second deep trench DT2 to serve as a gate electrode of the second vertical transistor T2. A common source/drain region S/D is formed in thesubstrate 40 between the first gate conductive line GC1 and the second gate conductive line GC2. Thus, a first vertical channel region is provided between the common source/drain region S/D and the first buried strap out-diffusion region BS1, and a second vertical channel region is provided between the common source/drain region S/D and the second buried strap out-diffusion region BS2. The bitline contact BC is formed overlying the common source/drain region S/D and electrically connected to the first bitline BL1. Accordingly, the DRAM cell layout of the vertical transistors T1 and T2 and the deep trenches DT1 and DT2 can prevent deterioration of subthreshold conduction, thus improving retention time performance. - Second Embodiment
-
FIG. 5 is a DRAM cell layout of deep trenches and active areas according to the second embodiment of the present invention.FIG. 6 is a three-dimensional diagram of a vertical transistor according to the second embodiment of the present invention. Elements similar to those shown inFIGS. 3 and 4 are omitted here. - The DRAM cell layout of deep trenches and active areas of the second embodiment is substantially similar to that of the first embodiment, with the similar portions omitted herein. The different portion is the profile of the overlapping region between the deep trench and the vertical transistor. In the first embodiment, on the overlapping region between the deep trench and the vertical transistor, the sidewall profile of the deep trench is a line. Comparatively, in the second embodiment, on the overlapping region between the deep trench and the vertical transistor, the sidewall profile of the deep trench comprises at least three edges. For example, a five-edge sidewall profile, such as a -shaped sidewall.
- Preferably, on an active area AA, the first deep trench DT1 is partially overlapped with the first gate conductive line GC1, and the first deep trench DT1 comprises a -shaped sidewall within the overlapping portion therebetween. Similarly, the second deep trench DT2 is partially overlapped with the second gate conductive line GC2, and the second deep trench DT2 comprises a -shaped sidewall within the overlapping portion therebetween. Therefore, the vertical channel region between the common source/drain region S/D and the buried strap out-diffusion region BS becomes a multilateral structure, viewed as a three-dimensional design, which can further improve subthreshold conduction and retention time performance.
- Third Embodiment
-
FIGS. 7A-7L are cross-sections of a fabrication method for above-described deep trenches and vertical transistors. - In
FIG. 7A , an array area I and a support area II are defined on asemiconductor silicon substrate 40. A p-typesemiconductor silicon substrate 40 is described below for example. First, apad layer 41 and a reactive ion etching (RIE) method are employed to pattern a deep trench DT in thesubstrate 40 within the array area I. Then, a deep trench capacitor 42 including abottom electrode plate 44, a capacitor dielectric 46 and anupper electrode plate 48 is fabricated at the lower portion of the deep trench DT. Preferably, thebottom electrode plate 44 is an n+-type diffusion region, the capacitor dielectric 46 is an ONO (oxide-nitride-oxide) stack structure, and theupper electrode plate 48 is a first polysilicon layer with n+-type dopants. Next, in a collar dielectric process, acollar dielectric layer 50 is formed on the sidewall of the deep trench DT. Next, asecond polysilicon layer 52 with n+-type dopants and athird polysilicon layer 54 are formed in the deep trench DT. Next, a thermal diffusion process is employed to make the n+-type dopants diffuse through thethird polysilicon layer 54 into thesubstrate 40, resulting in a buried strap out-diffusion region 56 in thesubstrate 40 adjacent to thethird polysilicon layer 54. Next, deposition and etching are used to form a top isolatinglayer 58 on thethird polysilicon layer 54. - In
FIG. 7B , an anti-reflective coating (ARC)layer 60 is formed in the deep trench DT, and afirst photoresist layer 62 is patterned on thesubstrate 40 for defining shallow trench isolations in the array area I and the support area II. Next, using thefirst photoresist layer 62 as a mask, the exposed portions of thepad layer 41 and thesemiconductor silicon substrate 40 are removed to formshallow trenches 63, as shown inFIG. 7C , thus defining an active area AA within the array area I. Then, theARC layer 60 and thefirst photoresist layer 62 are removed. - In
FIG. 7D , anitride liner 64 is conformally deposited on thesubstrate 40, and then a first HDP (high density plasma)oxide layer 66 is formed to fill theshallow trenches 63. Next, chemical mechanical polishing (CMP) is used to level off the top surfaces of the firstHDP oxide layer 66 and thenitride liner 64. Next, inFIG. 7E , asecond photoresist layer 68 is provided to cover the support area II. Next, using thenitride liner 64 as an etching stop layer, the firstHDP oxide layer 66 within the array area I is removed. Then, thesecond photoresist layer 68 is removed. InFIG. 7F , after removing thenitride liner 64 and thepad layer 41, a sacrificial oxide layer is formed so as to perform an ion implantation process on the array area I and the support area II for adjusting device threshold voltage. - In
FIG. 7G , after removing the sacrificial oxide layer, a thermal oxidation process is employed to grow agate oxide layer 70 on the exposed silicon surface of thesubstrate 40. Next, inFIG. 7H , agate polysilicon layer 72, a metallic silicide layer 74 (such as a WSi layer) and anitride cap layer 76 are successively deposited on thesubstrate 40. Then, using athird photoresist layer 78 as a mask to perform an etching process, thegate polysilicon layer 72, themetallic silicide layer 74 and thenitride cap layer 76 within the array area I are patterned as a gate conductive line GC, which partially overlaps two tops of two adjacent deep trenches DT. - In
FIG. 7I , after removing thethird photoresist layer 78, a secondHDP oxide layer 80 is formed to fill theshallow trench 63 outside the active area AA of the array area I, and then CMP is employed to level off the top surfaces of the secondHDP oxide layer 80 and the gate conductive line GC. Next, inFIG. 7J , by performing photolithography and etching on the active area AA of the array area I, a first contact hole 82I is formed to penetrate the gate conductive line GC and thegate oxide layer 70, thus exposing thesubstrate 40. - In
FIG. 7K , anitride spacer 84 is formed on the sidewall of the first contact hole 82I, and then an ion implantation process is performed to form a source/drain diffusion region 86 in thesemiconductor silicon substrate 40 exposed by the first contact hole 82I. Next, deposition and CMP for a BPSG layer 88 and deposition and annealing for aTEOS oxide layer 90 are successively performed thereon. Next, using photolithography and etching, a second contact hole 821I is formed to expose the first contact hole 82I and the source/drain diffusion region 86. Finally, inFIG. 7L , the second contact hole 821I is filled with apolysilicon contact layer 92, and then a W/TiN/Ti layer 94 is formed on thepolysilicon contact layer 92, and then abitline 96 is patterned thereon. - While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (18)
1. A dynamic random access memory cell layout, comprising:
a first gate conductor pair and a second gate conductor pair extending along a first direction, in which each gate conductor pair comprises a first gate conductive line and a second gate conductive line;
a bitline pair extending along a second direction and intersecting the gate conductor pairs, in which the bitline pair comprises a first bitline and a second bitline;
a first active area extending along the second direction, crossing the first gate conductor pair and corresponding to the first bitline; and
a second active area extending along the second direction, crossing the second gate conductor pair and corresponding to the second bitline;
wherein, each active area comprises:
a first deep trench and a second deep trench formed in a substrate underneath the first gate conductive line and the second gate conductive line, respectively;
a bitline contact formed between the first gate conductive line and the second gate conductive line, in which the bitline contact is electrically connected to the corresponding bitline;
a common source/drain region formed in the substrate between the first gate conductive line and the second gate conductive line, in which the common source/drain region is electrically connected to the bitline contact;
a first vertical transistor formed overlying the first deep trench, in which the first vertical transistor comprises a first buried strap out-diffusion region formed in the substrate adjacent to one sidewall of the first deep trench; and
a second vertical transistor formed overlying the second deep trench, in which the second vertical transistor comprises a second buried strap out-diffusion region formed in the substrate adjacent to one sidewall of the second deep trench.
2. The dynamic random access memory cell layout as claimed in claim 1 , wherein the first deep trench is partially overlapped with the first vertical transistor, and the sidewall profile of the first deep trench on the overlapping portion is a line shape.
3. The dynamic random access memory cell layout as claimed in claim 1 , wherein the second deep trench is partially overlapped with the second vertical transistor, and the sidewall profile of the second deep trench on the overlapping portion is a line shape.
4. The dynamic random access memory cell layout as claimed in claim 1 , wherein the first deep trench is partially overlapped with the first vertical transistor, and the sidewall profile of the first deep trench on the overlapping portion comprises at least three edges.
6. The dynamic random access memory cell layout as claimed in claim 1 , wherein the second deep trench is partially overlapped with the second vertical transistor, and the sidewall profile of the second deep trench on the overlapping portion comprises at least three edges.
8. The dynamic random access memory cell layout as claimed in claim 1 , further comprising a first deep trench capacitor formed at the lower portion of the first deep trench.
9. The dynamic random access memory cell layout as claimed in claim 1 , further comprising a second deep trench capacitor formed at the lower portion of the second deep trench.
10. A fabrication method for a dynamic random access memory cell layout, comprising the steps of:
providing a semiconductor silicon substrate having an array area and a support area;
forming a pad layer overlying the semiconductor silicon substrate, in which the pad layer comprises a predetermined deep trench pattern;
forming a first deep trench and a second deep trench in the semiconductor silicon substrate within the array area;
forming a first deep trench capacitor and a second deep trench capacitor at the lower portions of the first deep trench and the second deep trench, respectively;
forming a collar dielectric layer on the sidewalls of the first deep trench and the second deep trench, respectively, in which the collar dielectric layer is disposed over the first deep trench capacitor and the second deep trench capacitor;
forming a polysilicon layer in the first deep trench and the second deep trench, in which the polysilicon layer is surrounded by the collar dielectric layer;
forming a first buried strap out-diffusion region and a second buried strap out-diffusion region in the semiconductor silicon substrate adjacent to the sidewalls of the first deep trench and the second deep trench, respectively, in which the first buried strap out-diffusion region and the second buried strap out-diffusion region are adjacent to the polysilicon layer in the first deep trench and the second deep trench, respectively;
forming a top isolating layer to cover the top of the polysilicon layer in the first deep trench and the second deep trench;
forming two first shallow trenches in the semiconductor silicon substrate within the array area to separate the active area from other areas, in which the first shallow trenches are outside the first deep trench and the second deep trench is within the array area;
forming a second shallow trench in the semiconductor silicon substrate within the support area;
forming a liner on the substrate;
forming a first isolating layer in the first shallow trenches and the second shallow trench, in which the top of the first isolating layer is leveled off with the top of the liner;
forming a photoresist layer to cover the support area;
removing the first isolating layer formed in the first shallow trenches within the array area;
removing the photoresist layer, the exposed liner and the pad layer, in which the semiconductor silicon substrate within the active area of the array area protrude from the top isolating layer;
forming a gate oxide layer on the exposed surface of the semiconductor silicon substrate;
forming a gate conductive structure on the active area between the first deep trench and the second deep trench;
forming a second isolating layer to fill the first shallow trenches, in which the top of the second isolating layer is leveled with the top of the gate conductive structure; and
forming a first contact hole penetrating the gate conductive structure and the gate oxide layer to expose the semiconductor silicon substrate.
11. The fabrication method for a dynamic random access memory cell layout as claimed in claim 10 , further comprising the steps of:
forming a spacer on the sidewall of the first contact hole;
forming a common source/drain diffusion region in the semiconductor substrate exposed within the first contact hole;
forming a first inter-layered dielectric and a second inter-layered dielectric overlying the semiconductor silicon substrate;
forming a second contact hole which penetrates the second inter-layered dielectric and the first inter-layered dielectric to expose the first contact hole and the common source/drain diffusion region;
forming a contact layer in the second contact hole; and
forming a bitline overlying the second inter-layered dielectric, in which the bitline is electrically connected to the contact layer.
12. The fabrication method for a dynamic random access memory cell layout as claimed in claim 10 , wherein the liner is a silicon nitride layer.
13. The fabrication method for a dynamic random access memory cell layout as claimed in claim 10 , wherein the first isolating layer is a HDP (high-density plasma) oxide layer.
14. The fabrication method for a dynamic random access memory cell layout as claimed in claim 10 , wherein the gate conductive structure comprises a polysilicon layer, a metallic silicide layer and a nitride cap layer.
15. The fabrication method for a dynamic random access memory cell layout as claimed in claim 10 , wherein the second isolating layer is a HDP (high-density plasma) oxide layer.
16. The fabrication method for a dynamic random access memory cell layout as claimed in claim 11 , wherein the spacer is a silicon nitride layer.
17. The fabrication method for a dynamic random access memory cell layout as claimed in claim 11 , wherein the first inter-layered dielectric is a BPSG layer.
18. The fabrication method for a dynamic random access memory cell layout as claimed in claim 11 , wherein the second inter-layered dielectric is a TEOS oxide layer.
Priority Applications (2)
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US11/687,573 US20070152263A1 (en) | 2003-09-02 | 2007-03-16 | Dynamic random access memory cell layout and fabrication method thereof |
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TW092124187A TWI223442B (en) | 2003-09-02 | 2003-09-02 | DRAM cell array and its manufacturing method |
TW92124187 | 2003-09-02 |
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US11/687,573 Continuation US20070152263A1 (en) | 2003-09-02 | 2007-03-16 | Dynamic random access memory cell layout and fabrication method thereof |
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US10/972,505 Expired - Lifetime US6919245B2 (en) | 2003-09-02 | 2004-10-25 | Dynamic random access memory cell layout and fabrication method thereof |
US11/687,573 Abandoned US20070152263A1 (en) | 2003-09-02 | 2007-03-16 | Dynamic random access memory cell layout and fabrication method thereof |
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US11/687,573 Abandoned US20070152263A1 (en) | 2003-09-02 | 2007-03-16 | Dynamic random access memory cell layout and fabrication method thereof |
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Cited By (6)
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US20050190590A1 (en) * | 2004-02-27 | 2005-09-01 | International Business Machines Corporation | Gate controlled floating well vertical mosfet |
US20060036325A1 (en) * | 2003-07-31 | 2006-02-16 | Globus Medical Inc. | Anterior prosthetic spinal disc replacement |
US20060228861A1 (en) * | 2005-04-07 | 2006-10-12 | Kang Woo-Tag | Partially recessed DRAM cell structure and method of making the same |
US9017410B2 (en) | 2011-10-26 | 2015-04-28 | Globus Medical, Inc. | Artificial discs |
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TWI334198B (en) * | 2007-03-12 | 2010-12-01 | Nanya Technology Corp | Methods for forming a semiconductor device |
TWI458051B (en) * | 2011-10-21 | 2014-10-21 | Rexchip Electronics Corp | Control Method of Vertical Double - gate Dynamic Random Access Memory |
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US10304518B2 (en) | 2017-06-26 | 2019-05-28 | Micron Technology, Inc. | Apparatuses with compensator lines laid out along wordlines and spaced apart from wordlines by dielectric, compensator lines being independently controlled relative to the wordlines providing increased on-current in wordlines, reduced leakage in coupled transistors and longer retention time in coupled memory cells |
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- 2004-01-21 US US10/761,985 patent/US20050045936A1/en not_active Abandoned
- 2004-10-25 US US10/972,505 patent/US6919245B2/en not_active Expired - Lifetime
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- 2007-03-16 US US11/687,573 patent/US20070152263A1/en not_active Abandoned
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US6204140B1 (en) * | 1999-03-24 | 2001-03-20 | Infineon Technologies North America Corp. | Dynamic random access memory |
US20030201481A1 (en) * | 2000-07-13 | 2003-10-30 | Nanya Technology Corporation | DRAM with vertical transistors and deep trench capacitors |
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US20060036325A1 (en) * | 2003-07-31 | 2006-02-16 | Globus Medical Inc. | Anterior prosthetic spinal disc replacement |
US20050190590A1 (en) * | 2004-02-27 | 2005-09-01 | International Business Machines Corporation | Gate controlled floating well vertical mosfet |
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US20060228861A1 (en) * | 2005-04-07 | 2006-10-12 | Kang Woo-Tag | Partially recessed DRAM cell structure and method of making the same |
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US9017410B2 (en) | 2011-10-26 | 2015-04-28 | Globus Medical, Inc. | Artificial discs |
US9198770B2 (en) | 2013-07-31 | 2015-12-01 | Globus Medical, Inc. | Artificial disc devices and related methods of use |
CN105140223A (en) * | 2014-05-26 | 2015-12-09 | 瑞萨电子株式会社 | Semiconductor device |
US10062773B2 (en) * | 2014-05-26 | 2018-08-28 | Renesas Electronics Corporation | Semiconductor device having a transistor and first and second embedded layers |
Also Published As
Publication number | Publication date |
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US6919245B2 (en) | 2005-07-19 |
TWI223442B (en) | 2004-11-01 |
US20050082590A1 (en) | 2005-04-21 |
TW200511562A (en) | 2005-03-16 |
US20070152263A1 (en) | 2007-07-05 |
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