US20050040811A1 - Universal test interface between a device under test and a test head - Google Patents
Universal test interface between a device under test and a test head Download PDFInfo
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- US20050040811A1 US20050040811A1 US10/954,269 US95426904A US2005040811A1 US 20050040811 A1 US20050040811 A1 US 20050040811A1 US 95426904 A US95426904 A US 95426904A US 2005040811 A1 US2005040811 A1 US 2005040811A1
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- board
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- memory devices
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R21/00—Arrangements for measuring electric power or power factor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
- G01R1/07378—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers
Abstract
In order to form a modular interface between a DUT board, which is housing devices under tests (DUT), to cables connected to a test head, a board spacer is provided that has an array of connectors. Each cable is connected to a respective connector, and the DUT board contains a corresponding array of connection points which are less than or equal to the number of connectors in the arrays on the board spacer. In this way, a common board spacer can be used to connect the cables to DUT boards housing different types of DUTs since the location of the connection points on the board spacer is known and kept constant. This interface allows a high speed and high fidelity connection between the test head and the devices on the DUTs for frequencies in excess of 50 MHz.
Description
- This application is a divisional of U.S. patent application Ser. No. 10/326,392, filed Dec. 23, 2002 in the United States Patent and Trademark Office, which is a divisional of U.S. patent application Ser. No. 09/808,009, filed Mar. 15, 2001 in the United States Patent and Trademark Office, the disclosures of which is incorporated herein by reference.
- 1. Field of the Invention
- This invention relates generally to automatic test equipment used to test integrated circuit elements, and more particularly to interface hardware used in automatic test equipment to connect devices under test to a test head in order to perform the testing.
- 2. Description of the Related Art
- Automatic test equipment (i.e., a tester) is generally used to test semiconductor devices and integrated circuit elements, such as memory or logic for manufacturing defects. A general representation of a tester is shown in
FIG. 1 . As shown, a tester 1 has atester body 10, which is in communication with atest head 20. Thetest head 20 is in communication with devices under test (DUTs) 60 via aninterface 30. TheDUTs 60 are the various integrated circuit elements being tested. In this way,multiple DUTs 60 can be tested rapidly and simultaneously. Further, after a group ofDUTs 60 are tested, a new group ofDUTs 60 are introduced for testing using ahandler 5. - As shown in
FIGS. 2 and 3 , theDUTs 60 are arrayed onDUT boards 80. TheDUT boards 80, also known as socket boards, device interface boards, and load boards, are onrespective board spacers 40, which rest on aspacing frame 50. Theboard spacers 40 are hollowed in the center to allowcables 70 to be attached to theDUT boards 80. EachDUT 60 is connected to arespective cable 70 through solder-lined throughholes 83 in theDUT board 80, with the actual connection being atsolder point 82. As such, eachcable 70 is solder connected, individually, to theDUT board 80. - For a conventional tester 1, when a new type of
DUT 60 is to be tested, thenew DUT 60 is brought to the tester 1 viahandler 5 and connected to a test socket (not shown), completing the electrical connection between thetest head 20 and thenew DUT 60. The test is then performed. After completion of the test, theDUT 60 is then removed from the test socket viahandler 5, and anew DUT 60 of the same type is installed into the test socket using thehandler 5. - If a new type of
DUT 60 is to be tested, theold DUT board 80 must be replaced and anew DUT board 80 inserted in its place. Thenew DUT board 80 will have different connection needs reflecting the new type ofDUT 60. As such, either a new interface assembly must be used, or thecables 70 must be resoldered atdifferent solder points 82. In either case, thecables 70 are custom fitted todifferent DUT boards 80 for each new type ofDUT 60 to be tested. Further, where thecables 70 are resoldered, each change inDUT 60 type requires that the interface assembly, including theboard spacer 40, be partially or wholly disassembled, thecables 70 be soldered ontorespective solder points 82 of thenew DUT board 80, and the interface be reassembled. On the other hand, where the entire interface assembly is replaced, large numbers of interface assemblies must be stored for each type ofDUT 60 to be tested. - This use of solder connections is problematic since it is time consuming to attach the
cables 70 to thesolder points 82 of theDUT boards 80. This problem is exacerbated as both the density and/or number ofDUTs 60 increases. For instance, modern testers can accommodate up to 128DUTs 60 pertest head 20, with changes in the types ofDUTs 60 being made multiple times per week, or even per day. As such, the requirement that the interface be disassembled and reassembled, and the custom soldering to connect thecables 70 to the different types ofDUT boards 80 can require significant time and expense to perform for each change in the type ofDUT 60 to be tested, and also significantly increases the amount of time required to test the DUT 60s. - As shown in
FIG. 4A , one solution to the limitations of solder connection has been to utilize spring loadedpogos 100, such as the pogo pin produced by Everett Charles, which rest onrespective pogo boards 110. Thepogos 100 include an internal spring that allows the top half of thepin 100 to be biased against apad 90 on theDUT board 80, thus forming a communication pathway to arespective DUT 60. Using this system, when a new type ofDUT 60 is to be tested, thecables 70 do not have to be soldered to theDUT board 80. Instead, thecables 70 remain soldered to thepogo boards 110, and thenew DUT board 80 is placed on thepogo board 110 such that thepins 100 are biased againstrespective pads 90 to form the communication pathways. As such, the entire interface does not have to be changed. - However, this solution also is problematic as the number and density of
DUTs 60 being tested increases. As the density ofDUTs 60 being tested increases, smaller andsmaller pogos 100 must be used in order to fit into the space provided under theDUT board 80. As thepogos 100 get smaller, they become more delicate and difficult to work with. Further, aspogos 100 get smaller, their stroke (i.e., the distance that the tip of thepin 100 can travel vertically in order to bias against pad 90) decreases, which means that theDUT board 80 and thepogo boards 110 must be made highly planar to ensure a connection at allpads 90. This increases the production cost for thepogo boards 110 and theDUT boards 80. In addition,pogos 100 are themselves expensive to use. As such,pogos 100 do not present an ideal alternative to solder connection as the density and/or number ofDUTs 60 increases. - Where the
DUT 60 is alogic element 65, it is known to perform lower parallelismtesting using plugs 160 as shown inFIGS. 4B and 4C . For logic elements, thecables 70 are soldered into daughter boards withinplugs 160. Theplugs 160, such as the Micopax plug produced by FCl, are held by aplug holder 180, and are connected torespective receptacles 170. Thereceptacles 170 are connected to alogic board 150. In this way, instead of directly solder-connecting thecables 70 to thelogic board 150, theplugs 160 are received byreceptacles 170 located on thelogic board 150. Not all of theplugs 160 are used for each type oflogic element 65 tested. - However, this configuration is known for use in lower-parallelism testing of
logic elements 65, and requires the use of eight ormore plugs 160 perlogic board 150. Such a configuration is unsuitable for high-density, high-parallelism testing of DUTs, especially where the DUT is a smaller device such as a memory device. In order to test these devices, the DUT boards are smaller, which prevents the use ofnumerous plugs 160. Further, thehandlers 5 that move the memory devices, such as the Advantest M65XX and M67XX series handlers, use spacing frames having a pitch that does not allow the use of a large number ofplugs 160 in order to test these devices. Thus, for high-parallelism testing of memory devices (i.e., simultaneous testing of 32 or more devices), conventional plug arrangements were not possible. - It is an object of the invention to provide a connection system between devices under test and a test head that provides a secure modular connection to the devices under test for high data rates without causing degradation in signal quality.
- It is a further object of the invention to provide a high density, scalable connection system between devices under test and a test head.
- Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
- Accordingly, to achieve these and other objects, an embodiment of the present invention uses an interface between a device under test (DUT) and cables, including a first board having an array of first connectors, each first connector connected to a respective cable, and a second board holding the DUT and having second connectors, each second connector being connected to the DUT and to a respective first connector, and where the number of second connectors is less than the number of first connectors.
- According to another embodiment of the invention, the first connectors and second connectors comprise pairs of header connectors and shielded-controlled impedance connectors.
- According to a further embodiment of the invention, the first connectors and the second connectors comprise pairs of pads allowing a board-to-board connection between the first board and the second board.
- According to another embodiment of the present invention, an interface to perform high-parallelism testing of memory devices comprises a first board holding one of the memory devices and having a receptacle connected to the one memory device, and a plug connected to respective cables and to the receptacle to create a communication pathway, wherein combinations of the first boards and the plugs allow high-parallelism testing of the memory devices.
- According to a still further embodiment of the present invention, a method of connecting a DUT on a DUT board to cables for testing comprises unplugging a first DUT board having a first number of connectors from respective cables held in an array on a board spacer, and plugging a second DUT board having a second number of connectors different from the first number of connectors into the cables.
- According to yet another embodiment of the present invention, a method of connecting a DUT on a DUT board to cables for testing comprises removing a first DUT board having first pads connected to a first DUT from a board spacer having board pads connected to the cables, where respective pairs of first pads and board pads formed a board-to-board connection creating first communication pathways for signals between the cables and the first DUT, and placing a second DUT board having second pads connected to a second DUT onto the board spacer to form a board-to-board connection creating a second communication pathways for signals between the cables and the second DUT.
- According to still another embodiment of the present invention, a method of connecting a memory device on a DUT board to cables for high-parallelism testing of memory devices that comprises unplugging a first DUT board having a first receptacle from a plug connected to respective cables, and plugging a second DUT board having a second receptacle into the plug to form a communication pathway between the memory device and the cables, wherein combinations of the second DUT boards and the plugs allow high-parallelism testing of the memory devices.
- These and other objects and advantages of the invention will become apparent and more readily appreciated from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings of which:
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FIG. 1 is a schematic view showing a conventional tester including the communication between the test body, the test head, the handler, and the devices under test (DUTs); -
FIG. 2 is a side cross sectional view of a conventional solder connected interface between DUT boards and cables including the board spacer and spacing frame; -
FIG. 3 is a side cross sectional view of a conventional solder connection between a cables and the DUT board for an individual DUT; -
FIG. 4A is a side cross sectional view of a conventional pogo interface between the DUT board and the cables using spring loaded pogos mounted on daughter boards; -
FIG. 4B is a side cross sectional view of a conventional plug-receptacle interface between a logic board and the cables; -
FIG. 4C is a bottom view of a conventional logic board showing the receptacles arrayed radially; -
FIG. 5A is a front cross sectional view of an interface according to an embodiment of the present invention using shielded controlled impedance (SCI) connectors; -
FIG. 5B is a side cross sectional view of an interface according to an embodiment of the present invention using SCI connectors showing that not all SCI connectors are used; -
FIG. 6A is a top view of an array of SCI connectors on a board spacer according to an embodiment of the present invention; -
FIG. 6B is a side cross sectional view of the board spacer showing a SCI connector located in an array hole according to an embodiment of the present invention; -
FIG. 7 is a schematic view showing an interface according to another embodiment of the present invention using a plug and receptacle to connect cables a DUT board; -
FIG. 8 is a cross sectional view of a plug showing the cables connecting to PCB according to another embodiment of the present invention; and -
FIG. 9 is a schematic view showing an interface according to yet another embodiment of the present invention using an elastomer to form a conductive pathway between respective pads. - Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.
- For an embodiment of the present invention shown in
FIGS. 5A through 6B , an array of shielded controlled impedance (SCI)connectors 220 are disposed inconnector openings 249 in aboard spacer 230. EachSCI connector 220 is connected to acable 70, which extends throughcable openings 247 in theboard spacer 230. The relative size of thecable openings 247 andconnector openings 249 forming array holes 245 restrains the movement of theSCI connector 220 in the X, Y and Z directions, and prevents theSCI connectors 220 from being pulled through into the interface. The array holes 245 are arranged as part of alarger array 240 on theboard spacer 230. - In order to form a communication pathway between
SCI connectors 220 andrespective DUTs 60, sets ofheaders 210 are arrayed onDUT board 280. Eachheader 210 containsheader connectors 215, which are pairs of pins, each pair having a signal pin and a ground pin. Aconnector 220 from arespective cable 70 connects to oneheader connector 215. As shown inFIGS. 5A and 5B , theheaders 210 are surface mounted to theDUT board 280, and are connected to therespective DUT 60 orDUTs 60 on theDUT board 280, depending on the configuration. Theseheaders 210 andSCI connectors 220, when connected, form the communication pathways between thecables 70 and therespective DUTs 60. - Generally, the
board spacer 230 has fully populatedarrays 240, meaning that eacharray hole 245 in thearray 240 has arespective SCI connector 220. In contrast, as shown inFIG. 5B , theDUT boards 280 do not always require the use of all of theSCI connectors 220, and only connect with selected ones of theconnectors 220 depending on the type ofDUT 60 to be tested. As such, for eachSCI connector 220, there may or may not be acorresponding header connector 215. However, for eachheader connector 215, there is acorresponding SCI connector 220. In this way, theboard spacer 230 forms a modular connector tomultiple DUT boards 280. For each new type ofDUT 60 to be tested, only theDUT board 280 needs to be changed such that theheaders 210 for thatDUT board 280 will connect to selectedSCI connectors 220. - As shown, the
SCI connector 220 is a 2 mm connector having a signal and a ground line. Such 2mm connectors 220 can be WL Gore 2 mm EYEOPENER cable connectors, or SCI connectors from 3M, which are 1×2 2 mm controlled impedance connectors. Similarly, theheader 210 is a surface mount technology 2 mm header, which allows 60-70header connectors 215 to be used on eachDUT board 280. - Of course, it is understood that it is also possible to use
connectors 220 having other distances between signal and ground lines for thesame connector 220, and/or between signal lines and ground lines of adjacent connectors 220 (i.e., other pitches). For instance, it is possible to useconnectors 220 which have a 1.27 mm pitch or a 0.1″ pitch. - Further, while the shown
header 210 is surface mounted to theDUT board 280, it is understood that the through hole connection can be used. It is further understood, but not shown, that theheaders 210 andSCI connectors 220 could be reversed such that theheader 210 is located in thearray 240 and theSCI connector 220 is surface mounted to theDUT board 280. However configured, the interface according to the preferred embodiments of the present invention is able to support high speed and high fidelity signals at frequencies above 50 MHz. - Another embodiment of the present invention is shown in
FIGS. 7 and 8 . As shown inFIG. 7 ,cables 70 are connected to plug 320, which is plugged intoreceptacle 310.Receptacle 310 is mounted toDUT board 380, which holds therespective DUT 60 orDUTs 60, depending on the configuration. TheDUT board 380 is supported by thespacing frame 50 viaboard spacer 300. - Generally, the
plug 320 is attached to thereceptacle 310 using screws, pull pins, a series of cams, or similar attachment mechanisms. However, it is also possible, but not shown, to construct a board spacer to support and hold theplugs 320 in an array. - As shown in
FIG. 8 , theplug 320 comprises aplug 322, which is straddle-mount connected to a printed circuit board (PCB) 323. Theplug 322 andreceptacle 310 pair can be a commercial pair, such as the Micropax plug/receptacle supplied by FCl. - The
PCB 323 includesinternal wires 326 that form communication pathways torespective cables 70. Thecables 70 are connected to therespective wires 326 by conventional methods such as soldering. Thecables 70 are supported usingstrain relief member 328, which is attached tohousing 324 that also protects the assembly. - The
receptacle 310 also has internal connection points (not shown), where the internal connection points are connected toreceptacle wires 315 leading to theDUT 60. The internal connection points and associatedwires 315 may be equal to or less than the number ofwires 326/cables 70 for arespective plug 320, depending on how many of thecables 70 are required to test a specific type ofDUT 60. In this way, thesame plugs 320 can be used forvarious DUT boards 380 holding various types ofDUTs 60, with the difference in connections being provided by selectively connecting to thewires 326 in the respective plugs 320. - Further, using this configuration, the number of
plugs 320 can be reduced such that one or twoplugs 320 are used perDUT board 380. Such a result is especially desirable where theDUT 60 is a memory device, and where space limitations have heretofore prevented the use of plug-receptacle connections. For instance, such an interface would be useful with a M65XX and M67XX Advantest handler which are capable of delivering thirty-two (32) devices per space frame (sixty-four (64) devices AD style), but which has pitch limitations preventing the use of conventional plug configurations. - For still another embodiment of the present invention as shown in
FIG. 9 , aboard spacer 500 includes an array ofpads 510. Eachpad 510 is connected to arespective cable 70.Board spacer 480, which holdsDUTs 60, has a corresponding array ofpads 490. The number ofpads 490 are less than or equal to the number ofpads 510 on theboard spacer 500. TheDUT board 480 is connected to theboard spacer 500 using anelastomer 600, which allows the signal to pass from thepad 510 to thepad 490 and to arespective DUT 60. Theelastomer 600 may be one supplied by Shin-Etsu or Fujipoly. It is understood, that theelastomer 60 does not need to be used in all applications. - By way of example, in order to test a different type of
DUT 60 using the interface according to the embodiment of the present invention shown inFIG. 5A , theDUT board 280 for the first type ofDUT 60 is unplugged from theboard spacer 230, and theDUT board 280 for a new type ofDUT 60 is plugged into theboard spacer 230. TheDUT board 280 for the new type ofDUT 60 might have a different arrangement as to the number of pairs ofprongs 215 withinindividual headers 210 as shown inFIG. 5A , or could be arranged otherwise as to not be fully populated with asmany prongs 215 as there areconnectors 220 - As such, according to the preferred embodiments of the present invention, a common board spacer or connection scheme can be used which allows DUT boards housing different types of DUTs to be interchanged in a tester without having to rewire and reconnect cables to respective DUTs on the DUT board. Instead, they allow the use of predetermined connection points arrayed on a board spacer or in a plug to form the connection to the cables.
- Although a few preferred embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.
Claims (15)
1. An interface to perform high-parallelism testing of memory devices, comprising:
a first board holding one of the memory devices and having a receptacle connected to the one memory device; and
a plug connected to respective cables and to the receptacle to create a communication pathway,
wherein combinations of said first boards and said plugs allow high-parallelism testing of the memory devices.
2. The interface of claim 1 , wherein the one memory device is brought to said first board using a handler using a spacing frame that has a pitch to test thirty-two (32) or more memory devices in the spacing frame.
3. The interface of claim 1 , wherein the one memory device is brought to said first board using a handler using a spacing frame that has a pitch to test sixty-four (64) or more memory devices in the spacing frame.
4. The interface of claim 1 , wherein said first board holds only an additional receptacle, which is connected to an addition plug connected to additional respective cables to create an additional communication pathway.
5. The interface of claim 4 , wherein the receptacles on said first board are parallel with each other.
6. The interface of claim 5 , wherein the one memory device is brought to said first board using a handler using a spacing frame that has a pitch to test thirty-two (32) or more memory devices in the spacing frame.
7. The interface of claim 5 , wherein the one memory device is brought to said first board using a handler using a spacing frame that has a pitch to test sixty-four (64) or more memory devices in the spacing frame.
8. The interface of claim 7 , wherein each connection formed between respective pairs of receptacles and plugs forms a communication pathway for signals having a frequency of at least 50 MHz.
9. A method of connecting a memory device on a DUT board to cables for high-parallelism testing of memory devices, comprising:
unplugging first DUT boards from plugs, where each first DUT board has a first receptacle that is connected to a first memory device and each plug is connected to respective cables; and
plugging second DUT boards into the plugs, where each second DUT board has a second receptacle that is connected to a second memory device so as to form communication pathways between the cables and the second memory device,
wherein the combined second DUT boards and plugs allows high-parallelism testing of the second memory devices.
10. The method of claim 9 , further comprising bringing the second memory devices to the second DUT boards using a handler using a spacing frame, the spacing frame having a pitch to test thirty-two (32) or more memory devices in the spacing frame.
11. The method of claim 9 , further comprising bringing the second memory devices to the second DUT boards using a handler using a spacing frame, the spacing frame having a pitch to test sixty-four (64) or more memory devices in the spacing frame.
12. The method of claim 10 , wherein the second DUT board holds only an additional receptacle that is also connected to the second memory device, and further comprising connecting the additional receptacle to an addition plug that is connected to additional respective cables to create additional communication pathways.
13. The method of claim 12 , further comprising bringing the second memory devices to the second DUT boards using a handler using a spacing frame, the spacing frame having a pitch to test thirty-two (32) or more memory devices in the spacing frame.
14. The method of claim 12 , further comprising bringing the second memory devices to the second DUT boards using a handler using a spacing frame, the spacing frame having a pitch to test sixty-four (64) or more memory devices in the spacing frame.
15. The interface of claim 14 , wherein each connection formed between pairs of respective plugs and second or additional receptacles forms communication pathways for signals having a frequency of at least 50 MHz.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/954,269 US20050040811A1 (en) | 2001-03-15 | 2004-10-01 | Universal test interface between a device under test and a test head |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/808,009 US6552528B2 (en) | 2001-03-15 | 2001-03-15 | Modular interface between a device under test and a test head |
US10/326,392 US6822436B2 (en) | 2001-03-15 | 2002-12-23 | Universal test interface between a device under test and a test head |
US10/954,269 US20050040811A1 (en) | 2001-03-15 | 2004-10-01 | Universal test interface between a device under test and a test head |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/326,392 Division US6822436B2 (en) | 2001-03-15 | 2002-12-23 | Universal test interface between a device under test and a test head |
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US20050040811A1 true US20050040811A1 (en) | 2005-02-24 |
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Application Number | Title | Priority Date | Filing Date |
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US09/808,009 Expired - Fee Related US6552528B2 (en) | 2001-03-15 | 2001-03-15 | Modular interface between a device under test and a test head |
US10/326,392 Expired - Fee Related US6822436B2 (en) | 2001-03-15 | 2002-12-23 | Universal test interface between a device under test and a test head |
US10/954,269 Abandoned US20050040811A1 (en) | 2001-03-15 | 2004-10-01 | Universal test interface between a device under test and a test head |
Family Applications Before (2)
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US09/808,009 Expired - Fee Related US6552528B2 (en) | 2001-03-15 | 2001-03-15 | Modular interface between a device under test and a test head |
US10/326,392 Expired - Fee Related US6822436B2 (en) | 2001-03-15 | 2002-12-23 | Universal test interface between a device under test and a test head |
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US (3) | US6552528B2 (en) |
KR (1) | KR20030024668A (en) |
CN (2) | CN1975440A (en) |
AU (1) | AU2002238862A1 (en) |
TW (1) | TWI225549B (en) |
WO (1) | WO2002075330A2 (en) |
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US20070210811A1 (en) * | 2006-03-07 | 2007-09-13 | Cojocneanu Christian O | Apparatus and method for testing semiconductor devices |
US7528617B2 (en) | 2006-03-07 | 2009-05-05 | Testmetrix, Inc. | Apparatus having a member to receive a tray(s) that holds semiconductor devices for testing |
CN104251968A (en) * | 2014-10-13 | 2014-12-31 | 北京九方宏信交通装备股份有限公司 | Test bench for driving board of railway DC600 power source system |
Also Published As
Publication number | Publication date |
---|---|
US6552528B2 (en) | 2003-04-22 |
WO2002075330A2 (en) | 2002-09-26 |
CN1494659A (en) | 2004-05-05 |
CN1314976C (en) | 2007-05-09 |
KR20030024668A (en) | 2003-03-26 |
US20020130653A1 (en) | 2002-09-19 |
US6822436B2 (en) | 2004-11-23 |
TWI225549B (en) | 2004-12-21 |
WO2002075330A3 (en) | 2003-12-04 |
AU2002238862A1 (en) | 2002-10-03 |
US20030090259A1 (en) | 2003-05-15 |
CN1975440A (en) | 2007-06-06 |
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