US20050020012A1 - Method for manufacturing a nonvolatile memory transistor - Google Patents
Method for manufacturing a nonvolatile memory transistor Download PDFInfo
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- US20050020012A1 US20050020012A1 US10/827,456 US82745604A US2005020012A1 US 20050020012 A1 US20050020012 A1 US 20050020012A1 US 82745604 A US82745604 A US 82745604A US 2005020012 A1 US2005020012 A1 US 2005020012A1
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 7
- 230000005641 tunneling Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a nonvolatile memory transistor which is capable of minimizing the area when adapted to the technology of a sub-micron.
- FIG. 1 is a cross sectional view for explaining the bias condition of an electrically erasable and programmable read only memory (EEPROM) structure manufactured according to the prior art.
- EEPROM electrically erasable and programmable read only memory
- high temperature electrons are implanted to poly- 1 by the F-N tunnel method along a tunnel window by the bias applied upon programming.
- the threshold voltage Vt is increased to form an off-transistor upon reading.
- the high temperature electrons flow out from poly-1 by the F-N tunnel method along the tunnel window by the bias applied upon erasing, and thus the cell threshold voltage Vt is lowered to form a turn-on transistor.
- an EEPROM cell having a select transistor has a relatively large unit cell area, thus, as the unit cell area is lowered to below sub-microns, the competitive power for cell size is lowered, so it is difficult to reduce the cell size.
- the present invention is designed in consideration of the problems of the prior art, and therefore it is an object of the present invention to provide a method for manufacturing a nonvolatile memory transistor capable of minimizing the area when adapted to the technology for sub-microns.
- a method for manufacturing a nonvolatile memory transistor comprising the steps of: forming a trench of a predetermined shape on a silicon substrate; forming a N+ type doped region; etching the silicon substrate; forming ion implanted regions on the sides of the trench by conducting an inclined ion implantation for threshold voltage Vt control ion implantation of a select transistor; forming a poly- 1 layer by depositing an oxide film and then depositing poly- 1 serving as a gate node of the select transistor; after the formation of the poly-1 layer, conducting an etchback to the poly- 1 layer; forming N+ ion implanted regions by conducting a N-type ion implantation in order to form a N+ source junction of a cell transistor; forming a channel of an EEPROM by additionally etching the silicon substrate; forming cell threshold voltage ion implanted regions by conducting an ion implantation in order to control the threshold voltage Vt of the channel of
- FIG. 1 is a cross sectional view for explaining the bias condition of an electrically erasable and programmable read only memory (EEPROM) structure manufactured according to the prior art
- FIGS. 2 a to 2 r are cross sectional views for explaining a method for manufacturing a nonvolatile memory transistor according to a preferred embodiment of the present invention.
- FIGS. 2 a to 2 r are cross sectional views for explaining a method for manufacturing a nonvolatile memory transistor according to a preferred embodiment of the present invention.
- a photoresist layer 102 of a predetermined shape is formed on a silicon substrate 100 .
- the silicon substrate 100 is etched to a predetermined depth, to thus form a trench 104 .
- ion implantation is performed using a N-type dopant, to thus form a N+ type doped region 108 .
- an additional etching of the silicon substrate 100 is performed. This silicon etching is performed in order to etch the N-type doped region ion-implanted to the sides of the trench 104 in FIG. 2 b .
- the silicon-etched sides form a channel portion of a select transistor later.
- an inclined ion implantation is carried out, to form ion implanted regions 110 on the sides of the trench 104 .
- an oxide film 112 is deposited, then poly-1 serving as a gate node of the select transistor is deposited to form a poly-1 layer 116 , and then a POCL3 doping is performed for doping poly-1 (or N type ions are implanted, doped and annealed).
- the poly-1 layer 116 is formed, and an etchback is performed to the poly-1 layer 116 . It is preferred to perform the etchback so that the etchback amount can be about one thirds of the thickness of the silicon-etched surface.
- a second photoresist 118 having a predetermined shape is formed. Then, in order to form an N+ source junction of a cell transistor, an N-type ion implantation is performed to obtain N+ ion implanted regions 120 .
- the second photoresist having the predetermined shape is removed, and then a third photoresist 122 having a predetermined shape is formed in order to perform an additional silicon etching.
- the silicon substrate 100 is additionally etched to form a channel of an EEPROM.
- a stepped portion is formed between the N+ source junction of the cell and the poly- 1 after the etching.
- ion implantation is performed to control the threshold voltage Vt of the channel of the cell to thus form cell threshold voltage ion implanted regions 123 .
- the gate oxidation of the cell is performed to form a cell gate oxide film 124 .
- poly-2 is deposited, and then etched back to form a poly-2 layer 128 .
- the poly-1 layer 128 is utilized later as a floating poly of the cell, and, after the poly-2 deposition, the doping for the poly-2 is carried out by conducting a POCL3 or N-type ion implantation and then annealing.
- a fourth photoresist 130 having a predetermined shape is coated, and then ion implantation is carried out for forming a cell N-type drain junction, thereby forming cell N-type drain junction regions 132 .
- a fifth photoresist 134 having a predetermined shape is coated, and then the poly-2 layer 128 is etched into a predetermined shape so as to form a control gate of the cell overlapped with the poly-2.
- an oxide film 135 is deposited, and then poly-3 is deposited. Then, an etchback process is conducted to form a poly-3 layer 136 .
- a doping is performed also by conducting a POCL3 or N-type ion implantation and then annealing for the purpose of doping.
- Such the poly-3 layer 135 serves as a control gate node of the cell later. Then, as shown in FIG.
- a sixth photoresist 139 having a predetermined shape is formed, and then, using the sixth photoresist 139 having the predetermined shape as a mask, the poly-3 layer 136 , the oxide film 135 , the poly-2 layer 128 , the cell gate oxide film 124 , the etched back poly- 1 layer 116 and the oxide film 112 are simultaneously etched to form a trench 138 .
- an oxide film 140 is filled in the trench 138 .
- FIG. 2 r a finally completed cross sectional view is illustrated.
- the present invention relates to a method for manufacturing a nonvolatile memory transistor, and can provide an EEPROM memory, which is capable of minimizing the area when adapted to the technology for sub-micron.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a nonvolatile memory transistor which is capable of minimizing the area when adapted to the technology of a sub-micron.
- 2. Description of the Related Art
-
FIG. 1 is a cross sectional view for explaining the bias condition of an electrically erasable and programmable read only memory (EEPROM) structure manufactured according to the prior art. - The operation of the EEPROM structure for program, erase and read is shown in the following Table 1.
TABLE 1 V_select V_control Condition V_drain gate gate V_source V_sub Method Program GND Higher Higher than Floating GND F-N than ˜10 V ˜10 V Tunneling Erase Higher Higher GND Floating GND F-N than ˜10 V than ˜10 V Tunneling Read ˜1 V Vcc Vcc GND GND — - As shown in
FIG. 1 and Table 1, high temperature electrons are implanted to poly-1 by the F-N tunnel method along a tunnel window by the bias applied upon programming. By this, the threshold voltage Vt is increased to form an off-transistor upon reading. Additionally, the high temperature electrons flow out from poly-1 by the F-N tunnel method along the tunnel window by the bias applied upon erasing, and thus the cell threshold voltage Vt is lowered to form a turn-on transistor. - In this way, an EEPROM cell having a select transistor has a relatively large unit cell area, thus, as the unit cell area is lowered to below sub-microns, the competitive power for cell size is lowered, so it is difficult to reduce the cell size.
- The present invention is designed in consideration of the problems of the prior art, and therefore it is an object of the present invention to provide a method for manufacturing a nonvolatile memory transistor capable of minimizing the area when adapted to the technology for sub-microns.
- To achieve the above object, there is provided a method for manufacturing a nonvolatile memory transistor according to the present invention, comprising the steps of: forming a trench of a predetermined shape on a silicon substrate; forming a N+ type doped region; etching the silicon substrate; forming ion implanted regions on the sides of the trench by conducting an inclined ion implantation for threshold voltage Vt control ion implantation of a select transistor; forming a poly-1 layer by depositing an oxide film and then depositing poly-1 serving as a gate node of the select transistor; after the formation of the poly-1 layer, conducting an etchback to the poly-1 layer; forming N+ ion implanted regions by conducting a N-type ion implantation in order to form a N+ source junction of a cell transistor; forming a channel of an EEPROM by additionally etching the silicon substrate; forming cell threshold voltage ion implanted regions by conducting an ion implantation in order to control the threshold voltage Vt of the channel of the cell; after the cell threshold voltage ion implantation, forming a cell gate oxide film by conducting the gate oxidation of the cell; forming a poly-2 layer by depositing poly-2 and then conducting an etchback; forming cell N-type drain junction regions by conducting an ion implantation in order to form a cell N-type drain junction; etching the poly-2 layer into a predetermined shape in order to form a control gate of the cell overlapped with the poly-2; forming a ply-3 layer by depositing an oxide film, depositing poly-3 and conducting an etchback; and filling an oxide film so as to be penetrated into the poly-3 layer, the oxide film, the poly-2 layer, the cell gate oxide film, the poly-1 layer and the oxide film under the poly-1 layer.
- Other objects and aspects of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawing in which:
-
FIG. 1 is a cross sectional view for explaining the bias condition of an electrically erasable and programmable read only memory (EEPROM) structure manufactured according to the prior art; and -
FIGS. 2 a to 2 r are cross sectional views for explaining a method for manufacturing a nonvolatile memory transistor according to a preferred embodiment of the present invention. - Hereinafter, a preferred embodiment of the present invention will be described in more detail referring to the drawings. In addition, the following embodiment is for illustration only, not intended to limit the scope of the invention.
-
FIGS. 2 a to 2 r are cross sectional views for explaining a method for manufacturing a nonvolatile memory transistor according to a preferred embodiment of the present invention. - Firstly, as shown in
FIG. 2 a, aphotoresist layer 102 of a predetermined shape is formed on asilicon substrate 100. Next, using thephotoresist layer 102 of the predetermined shape as a mask, thesilicon substrate 100 is etched to a predetermined depth, to thus form atrench 104. Upon etching thesilicon substrate 100, it is preferred to perform etching so that an etched region is not inclined much by forming a right angle if possible. - Continuously, as shown in
FIG. 2 b, in order to form a N+ source junction of a NVM cell, ion implantation is performed using a N-type dopant, to thus form a N+ type dopedregion 108. - In the next step, as shown in
FIG. 2 c, without removing the firstphotoresist layer 102 having a predetermined shape, an additional etching of thesilicon substrate 100 is performed. This silicon etching is performed in order to etch the N-type doped region ion-implanted to the sides of thetrench 104 inFIG. 2 b. The silicon-etched sides form a channel portion of a select transistor later. - And, as shown in
FIG. 2 d, for the ion implantation for threshold voltage Vt control of the select transistor, an inclined ion implantation is carried out, to form ion implantedregions 110 on the sides of thetrench 104. - Continuously, as shown in
FIG. 2 e, anoxide film 112 is deposited, then poly-1 serving as a gate node of the select transistor is deposited to form a poly-1layer 116, and then a POCL3 doping is performed for doping poly-1 (or N type ions are implanted, doped and annealed). - Continually, as shown in
FIG. 2 f, the poly-1layer 116 is formed, and an etchback is performed to the poly-1layer 116. It is preferred to perform the etchback so that the etchback amount can be about one thirds of the thickness of the silicon-etched surface. - Then, as shown in
FIG. 2 g, asecond photoresist 118 having a predetermined shape is formed. Then, in order to form an N+ source junction of a cell transistor, an N-type ion implantation is performed to obtain N+ ion implantedregions 120. - In the next step, as shown in
FIG. 2 h, the second photoresist having the predetermined shape is removed, and then athird photoresist 122 having a predetermined shape is formed in order to perform an additional silicon etching. Continuously, using thethird photoresist 122 having the predetermined shape as a mask, thesilicon substrate 100 is additionally etched to form a channel of an EEPROM. - And, as shown in
FIG. 2 i, due to a stepped portion between the surface of the silicon wafer and the etched back poly-1layer 116 in the silicon etching, a stepped portion is formed between the N+ source junction of the cell and the poly-1 after the etching. Next, ion implantation is performed to control the threshold voltage Vt of the channel of the cell to thus form cell threshold voltage ion implantedregions 123. - Continually, as shown in
FIG. 2 j, after the cell threshold voltage ion implantation, the gate oxidation of the cell is performed to form a cellgate oxide film 124. - In the next step, as shown in
FIG. 2 k, poly-2 is deposited, and then etched back to form a poly-2layer 128. The poly-1layer 128 is utilized later as a floating poly of the cell, and, after the poly-2 deposition, the doping for the poly-2 is carried out by conducting a POCL3 or N-type ion implantation and then annealing. - In the next step, as shown in
FIG. 21 , afourth photoresist 130 having a predetermined shape is coated, and then ion implantation is carried out for forming a cell N-type drain junction, thereby forming cell N-typedrain junction regions 132. - And, as shown in
FIG. 2 m, afifth photoresist 134 having a predetermined shape is coated, and then the poly-2layer 128 is etched into a predetermined shape so as to form a control gate of the cell overlapped with the poly-2. - Continually, as shown in
FIG. 2 n, anoxide film 135 is deposited, and then poly-3 is deposited. Then, an etchback process is conducted to form a poly-3layer 136. In this case, a doping is performed also by conducting a POCL3 or N-type ion implantation and then annealing for the purpose of doping. Such the poly-3layer 135 serves as a control gate node of the cell later. Then, as shown inFIG. 2 o, asixth photoresist 139 having a predetermined shape is formed, and then, using thesixth photoresist 139 having the predetermined shape as a mask, the poly-3layer 136, theoxide film 135, the poly-2layer 128, the cellgate oxide film 124, the etched back poly-1layer 116 and theoxide film 112 are simultaneously etched to form atrench 138. - In the next step, as shown in
FIG. 2 p, anoxide film 140 is filled in thetrench 138. - Continually, as shown in
FIG. 2 r, a finally completed cross sectional view is illustrated. - The operation of the EEPROM structure for program, erase and read is shown in the following Table 2.
TABLE 2 V_select V_control Condition V_drain gate gate V_source V_sub Method Program Vcc Higher Higher than GND GND HCI than ˜10 V ˜10 V Erase Floating Higher Higher than Higher than GND F-N than ˜10 V ˜10 V ˜10 V Tunneling Read ˜1 V Vcc Vcc GND GND — - As described above, the present invention relates to a method for manufacturing a nonvolatile memory transistor, and can provide an EEPROM memory, which is capable of minimizing the area when adapted to the technology for sub-micron.
- The invention may be embodied in other forms without departing from the spirit or essential characteristics thereof. The embodiment disclosed in this application is to be considered as illustrative and not limiting. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all modifications, which come within the meaning and range of equivalency of the claims, are intended to be embraced therein.
Claims (3)
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KR2003-49941 | 2003-07-21 | ||
KR1020030049941A KR100549586B1 (en) | 2003-07-21 | 2003-07-21 | Method for manufacturing nonvolatile memory transistor |
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US6846713B1 US6846713B1 (en) | 2005-01-25 |
US20050020012A1 true US20050020012A1 (en) | 2005-01-27 |
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US10/827,456 Active US6846713B1 (en) | 2003-07-21 | 2004-04-19 | Method for manufacturing a nonvolatile memory transistor |
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US (1) | US6846713B1 (en) |
KR (1) | KR100549586B1 (en) |
CN (1) | CN100339962C (en) |
TW (1) | TWI336118B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060039356A1 (en) * | 2004-07-23 | 2006-02-23 | Citrix Systems, Inc. | Systems and methods for facilitating a peer to peer route via a gateway |
US20060148177A1 (en) * | 2004-12-31 | 2006-07-06 | Dongbuanam Semiconductor Inc. | Method for forming split gate flash nonvolatile memory devices |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100607785B1 (en) * | 2004-12-31 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method for manufacturing split gate flash EEPROM |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5973352A (en) * | 1997-08-20 | 1999-10-26 | Micron Technology, Inc. | Ultra high density flash memory having vertically stacked devices |
US6238976B1 (en) * | 1997-07-08 | 2001-05-29 | Micron Technology, Inc. | Method for forming high density flash memory |
US6583466B2 (en) * | 1998-03-05 | 2003-06-24 | Taiwan Semiconductor Manufacturing Company | Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions |
Family Cites Families (1)
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US6235587B1 (en) * | 1999-10-13 | 2001-05-22 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device with reduced arc loss in peripheral circuitry region |
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2003
- 2003-07-21 KR KR1020030049941A patent/KR100549586B1/en active IP Right Grant
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2004
- 2004-04-19 US US10/827,456 patent/US6846713B1/en active Active
- 2004-04-19 TW TW093110870A patent/TWI336118B/en not_active IP Right Cessation
- 2004-06-22 CN CNB200410059812XA patent/CN100339962C/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6238976B1 (en) * | 1997-07-08 | 2001-05-29 | Micron Technology, Inc. | Method for forming high density flash memory |
US5973352A (en) * | 1997-08-20 | 1999-10-26 | Micron Technology, Inc. | Ultra high density flash memory having vertically stacked devices |
US6583466B2 (en) * | 1998-03-05 | 2003-06-24 | Taiwan Semiconductor Manufacturing Company | Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060039356A1 (en) * | 2004-07-23 | 2006-02-23 | Citrix Systems, Inc. | Systems and methods for facilitating a peer to peer route via a gateway |
US20060148177A1 (en) * | 2004-12-31 | 2006-07-06 | Dongbuanam Semiconductor Inc. | Method for forming split gate flash nonvolatile memory devices |
US7704834B2 (en) * | 2004-12-31 | 2010-04-27 | Dongbu Hitek Co., Ltd. | Method for forming split gate flash nonvolatile memory devices |
Also Published As
Publication number | Publication date |
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TW200504946A (en) | 2005-02-01 |
KR100549586B1 (en) | 2006-02-08 |
US6846713B1 (en) | 2005-01-25 |
CN1577808A (en) | 2005-02-09 |
CN100339962C (en) | 2007-09-26 |
TWI336118B (en) | 2011-01-11 |
KR20050011099A (en) | 2005-01-29 |
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