US20050014296A1 - Mocvd of tio2 thin film for use as feram h2 passivation layer - Google Patents
Mocvd of tio2 thin film for use as feram h2 passivation layer Download PDFInfo
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- US20050014296A1 US20050014296A1 US10/621,863 US62186303A US2005014296A1 US 20050014296 A1 US20050014296 A1 US 20050014296A1 US 62186303 A US62186303 A US 62186303A US 2005014296 A1 US2005014296 A1 US 2005014296A1
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- 239000010409 thin film Substances 0.000 title claims abstract description 48
- 238000002161 passivation Methods 0.000 title claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 43
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910003087 TiOx Inorganic materials 0.000 claims abstract description 39
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 5
- 230000008021 deposition Effects 0.000 claims description 18
- 239000002243 precursor Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 6
- 229910015844 BCl3 Inorganic materials 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- TVMXDCGIABBOFY-UHFFFAOYSA-N octane Chemical compound CCCCCCCC TVMXDCGIABBOFY-UHFFFAOYSA-N 0.000 claims description 4
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 4
- 239000006200 vaporizer Substances 0.000 claims description 4
- 238000009499 grossing Methods 0.000 claims 12
- 238000005137 deposition process Methods 0.000 claims 3
- 238000002955 isolation Methods 0.000 claims 3
- 229910052741 iridium Inorganic materials 0.000 description 5
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 5
- 239000010936 titanium Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- -1 Ferroelectrics Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- DHXVGJBLRPWPCS-UHFFFAOYSA-N Tetrahydropyran Chemical compound C1CCOCC1 DHXVGJBLRPWPCS-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
Definitions
- This invention relates to oxide thin film processes for H 2 passivation layers, ferroelectric memory device structures and integrated processes for ferroelectric non-volatile memory devices, and specifically, to a method of depositing a TiO 2 thin film which is used as an H 2 passivation layer.
- MFMIS Metal, Ferroelectrics, Insulator, and Silicon
- MFIS Metal, Ferroelectrics, Insulator, and Silicon transistor ferroelectric memory devices
- forming gas annealing generally is necessary to reduce trapped charges in high-k gate oxides and to improve the contact between metal connections and the source and the drain.
- forming gas annealing degrades the properties of ferroelectric thin films. Therefore, a H 2 passivation layer, covering the ferroelectric thin film, is an important structure in fabrication of IT ferroelectric memory devices.
- a method of forming an H 2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiO x thin film, where 0 ⁇ x ⁇ 2, on a damascene structure; plasma space etching of the TiO x thin film to form a TiO x sidewall; annealing the TiO x side wall thin film to form a TiO 2 thin film; depositing a layer of ferroelectric material; and metallizing the structure to form a FeRAM.
- Another object of the invention is to provide a TiO x thin film having good step coverage on a damascene structure.
- a further object of the invention is to use a plasma space etching process on a TiO x thin film to form a TiO 2 thin film as a H 2 passivation layer.
- FIGS. 1-8 depict steps in device formation according to the method of the invention.
- FIGS. 9 and 10 are microphotographs of the structure during device fabrication.
- TiO x may be deposited in either of two embodiments to make TiO 2 as a H 2 passivation layer.
- a CVD process is used to deposit Ti or TiO x thin films on a damascene structure, providing good step coverage, followed by plasma space etching of the TiO x thin film to form a TiO x sidewall, and annealing the TiO x side wall thin film to form a TiO 2 thin film.
- the second embodiment of the method of the invention includes a CVD process to deposit a TiO x or TiO 2 thin film on a damascene structure, again providing good step coverage, annealing the TiO x thin film to form a TiO 2 thin film, and plasma space etching the TiO 2 thin film to form a sidewall on the trench structure.
- a silicon wafer 10 is prepared for fabrication of IC devices, which preparation may include doping to form a P-type silicon wafer, including threshold adjustment ion implantation, for use as a substrate for a Lead Germanium Oxide (Pb 5 Ge 3 O 11 ) (PGO) MFMPOS one-transistor FeRAM device.
- FIG. 1 depicts the structure following wafer preparation, STI and filling of the trenches so formed with oxide 12 , growth of a gate oxide 14 and deposition of a polysilicon layer 16 , and, in this example, ion implantation to form an N + source 18 and an N + drain 20 .
- the oxide is smoothed by CMP, photoresist is applied and the polysilicon layer etched.
- FIG. 2 depicts the structure following CVD of oxide, which is smoothed by CMP, stopping at the level of polysilicon layer 16 .
- a larger size bottom electrode 22 which, in the preferred embodiment, is an Iridium electrode is deposited and patterned.
- Another layer of oxide 24 is deposited by CVD and smoothed by CMP, stopping at the level of the Iridium layer.
- tetraethylorthosilicate oxide (oxane or TEOS) 26 is deposited by CVD, patterned and etched to form trench structures.
- FIG. 3 depicts the structure following CVD of a TiO x layer 28 , where 0 ⁇ x ⁇ 2.
- the MOCVD process includes preparing a MOCVD precursor, including dissolving 0.2 mol Ti(OC 3 H 7 ) 4 in Octane, resulting in a precursor solution having a concentration of 0.2 mol Ti(OC 3 H 7 ) 4 .
- the precursor solution is injected into a vaporizer at temperature in the range of between about 80° C. to 120° C. by a liquid controller at a rate of between about 0.1 ml/min to 0.5 ml/min to form a precursor gases.
- TiO x layer 28 may be, in the first embodiment of the method of the invention, plasma space etched, then annealed in an oxygen atmosphere to form a TiO 2 thin film.
- the structure is HF dipped to clean the surface of Iridium bottom electrode 20 , resulting in the structure depicted in FIG. 4 .
- the plasma space etching process for TiO x thin film 22 includes setting TCP Rf power at about 370 W and setting the bias power to about 130 W at a chamber pressure of about 5 torr.
- the etching chemicals used in the process include BCl 3 at a flow rate of about 30 sccm, and Cl 2 at a flow rate of about 58 sccm.
- FIG. 5 depicts the structure following selective deposition of a ferroelectric thin film 24 by MOCVD.
- the upper surface of the FE and TiO x extend above the level of the lastly deposited oxide layer because PGO may be selectively deposited on iridium and TiO 2 , but will not form on SiO 2 , therefor, the PGO will only be deposited on those areas which have exposed iridium and TiO 2 .
- FIG. 6 depicts the structure following CMP of ferroelectric thin film 30 , surrounding TiO x 28 , and oxide 26 .
- FIG. 7 depicts the structure following deposition and annealing of a high-k oxide 32 , deposition of a top electrode layer 34 , and patterning and etching of the top electrode layer to form top electrodes 34 .
- FIG. 8 depicts the FeRAM constructed according to the first embodiment of the method of the invention following etching of contact holes and metallization 36 .
- FIG. 9 depicts the structure following deposition of TiO x thin film layer 28 , which illustrates deposition on oxide trench structures with very good step coverage.
- FIG. 10 depicts the structure after plasma space etching, and illustrates the TiO x side wall thin film formed on oxide trench structures.
Abstract
Description
- This invention relates to oxide thin film processes for H2 passivation layers, ferroelectric memory device structures and integrated processes for ferroelectric non-volatile memory devices, and specifically, to a method of depositing a TiO2 thin film which is used as an H2 passivation layer.
- Metal, Ferroelectrics, Insulator, and Silicon (MFMIS) and Metal, Ferroelectrics, Insulator, and Silicon (MFIS) transistor ferroelectric memory devices have been proposed for use as FeRAM devices. In the integration processes of such devices, forming gas annealing generally is necessary to reduce trapped charges in high-k gate oxides and to improve the contact between metal connections and the source and the drain. However, forming gas annealing degrades the properties of ferroelectric thin films. Therefore, a H2 passivation layer, covering the ferroelectric thin film, is an important structure in fabrication of IT ferroelectric memory devices.
- A method of forming an H2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiOx thin film, where 0<x<2, on a damascene structure; plasma space etching of the TiOx thin film to form a TiOx sidewall; annealing the TiOx side wall thin film to form a TiO2 thin film; depositing a layer of ferroelectric material; and metallizing the structure to form a FeRAM.
- It is an object of the invention to provide a TiO2 thin film as a H2 passivation layer for improving the properties of 1 T ferroelectric memory devices.
- Another object of the invention is to provide a TiOx thin film having good step coverage on a damascene structure.
- A further object of the invention is to use a plasma space etching process on a TiOx thin film to form a TiO2 thin film as a H2 passivation layer.
- This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.
-
FIGS. 1-8 depict steps in device formation according to the method of the invention. -
FIGS. 9 and 10 are microphotographs of the structure during device fabrication. - In the method of the invention, TiOx may be deposited in either of two embodiments to make TiO2 as a H2 passivation layer. In the first embodiment of the method of the invention, a CVD process is used to deposit Ti or TiOx thin films on a damascene structure, providing good step coverage, followed by plasma space etching of the TiOx thin film to form a TiOx sidewall, and annealing the TiOx side wall thin film to form a TiO2 thin film. The second embodiment of the method of the invention includes a CVD process to deposit a TiOx or TiO2 thin film on a damascene structure, again providing good step coverage, annealing the TiOx thin film to form a TiO2 thin film, and plasma space etching the TiO2 thin film to form a sidewall on the trench structure.
- Referring initially to
FIG. 1 , asilicon wafer 10 is prepared for fabrication of IC devices, which preparation may include doping to form a P-type silicon wafer, including threshold adjustment ion implantation, for use as a substrate for a Lead Germanium Oxide (Pb5Ge3O11) (PGO) MFMPOS one-transistor FeRAM device.FIG. 1 depicts the structure following wafer preparation, STI and filling of the trenches so formed withoxide 12, growth of agate oxide 14 and deposition of apolysilicon layer 16, and, in this example, ion implantation to form an N+ source 18 and an N+ drain 20. The oxide is smoothed by CMP, photoresist is applied and the polysilicon layer etched. -
FIG. 2 depicts the structure following CVD of oxide, which is smoothed by CMP, stopping at the level ofpolysilicon layer 16. A largersize bottom electrode 22, which, in the preferred embodiment, is an Iridium electrode is deposited and patterned. Another layer ofoxide 24 is deposited by CVD and smoothed by CMP, stopping at the level of the Iridium layer. tetraethylorthosilicate oxide (oxane or TEOS) 26 is deposited by CVD, patterned and etched to form trench structures. -
FIG. 3 depicts the structure following CVD of a TiOx layer 28, where 0<x<2. As will be apparent to those of skill in the art, when x=0, the CVD is only of titanium. The MOCVD process includes preparing a MOCVD precursor, including dissolving 0.2 mol Ti(OC3H7)4 in Octane, resulting in a precursor solution having a concentration of 0.2 mol Ti(OC3H7)4. The precursor solution is injected into a vaporizer at temperature in the range of between about 80° C. to 120° C. by a liquid controller at a rate of between about 0.1 ml/min to 0.5 ml/min to form a precursor gases. The feed line is maintained at between about 80° C. to 120° C., the deposition temperature is between about 380° C. to 420° C., the deposition pressure is maintained at between about 0.5 torr to 5 torr, and the deposition time ranges from between about five minutes to thirty minutes, depending on the required TiO2 thickness. TiOx layer 28 may be, in the first embodiment of the method of the invention, plasma space etched, then annealed in an oxygen atmosphere to form a TiO2 thin film. The structure is HF dipped to clean the surface ofIridium bottom electrode 20, resulting in the structure depicted inFIG. 4 . The plasma space etching process for TiOxthin film 22 includes setting TCP Rf power at about 370 W and setting the bias power to about 130 W at a chamber pressure of about 5 torr. The etching chemicals used in the process include BCl3 at a flow rate of about 30 sccm, and Cl2 at a flow rate of about 58 sccm. -
FIG. 5 depicts the structure following selective deposition of a ferroelectricthin film 24 by MOCVD. The upper surface of the FE and TiOx extend above the level of the lastly deposited oxide layer because PGO may be selectively deposited on iridium and TiO2, but will not form on SiO2, therefor, the PGO will only be deposited on those areas which have exposed iridium and TiO2. -
FIG. 6 depicts the structure following CMP of ferroelectricthin film 30, surroundingTiO x 28, andoxide 26. -
FIG. 7 depicts the structure following deposition and annealing of a high-k oxide 32, deposition of atop electrode layer 34, and patterning and etching of the top electrode layer to formtop electrodes 34. -
FIG. 8 depicts the FeRAM constructed according to the first embodiment of the method of the invention following etching of contact holes andmetallization 36. -
FIG. 9 depicts the structure following deposition of TiOxthin film layer 28, which illustrates deposition on oxide trench structures with very good step coverage. -
FIG. 10 depicts the structure after plasma space etching, and illustrates the TiOx side wall thin film formed on oxide trench structures. - In the second embodiment of the method of the invention, the same processes are followed, as described in connection with
FIGS. 1-3 . The annealing step, described in connection withFIG. 7 , is next performed, converting TiOx to TiO2, which is then followed by the steps described in connection withFIGS. 4-6 and 8. - Thus, a method for MOCVD TiO2 thin film as FeRAM H2 passivation layer has been disclosed. It will be appreciated that further variations and modifications thereof may be made within the scope of the invention as defined in the appended claims.
Claims (20)
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US6642563B2 (en) * | 2000-09-28 | 2003-11-04 | Kabushiki Kaisha Toshiba | Semiconductor memory including ferroelectric gate capacitor structure, and method of fabricating the same |
US6645807B2 (en) * | 2001-09-06 | 2003-11-11 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing semiconductor device |
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US6642563B2 (en) * | 2000-09-28 | 2003-11-04 | Kabushiki Kaisha Toshiba | Semiconductor memory including ferroelectric gate capacitor structure, and method of fabricating the same |
US6645807B2 (en) * | 2001-09-06 | 2003-11-11 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing semiconductor device |
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