US20050005421A1

US20050005421A1 - High performance silicon condenser microphone with perforated single crystal silicon backplate

Info

Publication number: US20050005421A1
Application number: US10/916,196
Authority: US
Inventors: Zhe Wang; Qingxin Zhang
Original assignee: Knowles Electronics LLC
Current assignee: Knowles Electronics LLC
Priority date: 2002-09-13
Filing date: 2004-08-11
Publication date: 2005-01-13
Also published as: US7132307B2; US6667189B1; US20040179705A1

Abstract

A silicon condenser microphone is described. The silicon condenser microphone of the present invention comprises a perforated backplate comprising a portion of a single crystal silicon substrate, a support structure formed on the single crystal silicon substrate, and a floating silicon diaphragm supported at its edge by the support structure and lying parallel to the perforated backplate and separated from the perforated backplate by an air gap.

Description

TECHNICAL FIELD

The invention relates to a method of manufacturing a silicon condenser microphone, and more particularly, to a method of manufacturing a high performance silicon condenser microphone using a silicon micro-machining process.

BACKGROUND

Silicon condenser microphones have long been an attractive research and development subject. Various microphone designs have been invented and conceptualized by using silicon micro-machining technology. Despite various structural configurations and materials, the silicon condenser microphone consists of four basic elements: a movable compliant diaphragm, a rigid and fixed backplate (which together form a variable air gap capacitor), a voltage bias source, and a pre-amplifier. These four elements fundamentally determine the performance of the condenser microphone. In pursuit of high performance; i.e., high sensitivity, low bias, low noise, and wide frequency range, the key design considerations are to have a large size of diaphragm and a large air gap. The former will help increase sensitivity as well as lower electrical noise, and the later will help reduce acoustic noise of the microphone. However, the large diaphragm requires a large span of anchored supports and correspondingly a large backplate. Also, a large air gap requires a thick sacrificial layer. These present major difficulties in silicon micro-machining processes. Due to constraints of material choices and intrinsic stress issues in silicon micro-machining, the silicon microphones reported so far have not achieved sensitivity of more than 20 mV/Pa.
Miniaturized silicon microphones have been extensively developed for over sixteen years, since the first silicon piezoelectric microphone reported by Royer in 1983. In 1984, Hohm reported the first silicon electret-type microphone, made with a metallized polymer diaphragm and silicon backplate. And two years later, he reported the first silicon condenser microphone made entirely by silicon micro-machining technology. Since then a number of researchers have developed and published reports on miniaturized silicon condenser microphones of various structures and performance.
Some of these reports include the following:

- 1) D. Hohm and R. Gerhard-Multhaupt, “Silicon-dioxide electret transducer”, J. Acoust. Soc. Am., Vol. 75, 1984, pp. 1297-1298.
- 2) D. Hohm and G. Hess, “A Subminiature condenser microphone with silicon nitride membrane and silicon backplate”, J. Acoust. Soc. Am., Vol. 85, 1989, pp. 476-480.
- 3) Murphy, P. et al., “Subminiature silicon integrated electret capacitor microphone”, IEEE Trans. Electr. Ins., Vol. 24, 1989, pp. 495-498.
- 4) Bergqvist, J. et al., “A new condenser microphone in silicon”, Sensors and Actuators, Vol. A21-23, 1990, pp. 123-125.
- 5) Kuhnel, W. et al., “A Silicon condenser microphone with structured backplate and silicon nitride membrane,” Sensors and Actuators, Vol. 30, 1991, pp. 251-258.
- 6) Scheeper, P. R. et al., “Fabrication of silicon condenser microphones using single wafer technology”, Journal of Microelectromechanical Systems, Vol. 1, No. 3, 1992, pp. 147-154.
- 7) Scheeper, P. R. et al., “A Review of Silicon Microphones”, Sensors and Actuators A, Vol. 44, July 1994, pp. 1-11.
- 8) Bergqvist, J. et al., “A Silicon Microphone using bond and etch-back technology”, Sensors and Actuators A, vol. 45, 1994, pp. 115-124.
- 9) Zou, Quanbo et al., “Theoretical and experimental studies of single-chip-processed miniature silicon condenser microphone with corrugated diaphragm”, Sensors and Actuators A, Vol. 63, 1997, pp. 209-215.
- 10) Brauer, M. et al., “Silicon microphone based on surface and bulk micromachining”, Journal of Micromech. Microeng., Vol. 11, 2001, pp. 319-322.
- 11) Bergqvist, J. and V. Rudolf, “A silicon condenser microphone with a highly perforated backplate”, Transducer 91, pp. 266-269.

U.S. Pat. No. 5,870,482 to Loeppert et al reveals a silicon microphone. U.S. Pat. No. 5,490,220 to Loeppert shows a condenser and microphone device. U.S. patent application Publication 2002/0067663 to Loeppert et al shows a miniature acoustic transducer. U.S. Pat. No. 6,088,463 to Rombach et al teaches a silicon condenser microphone process. U.S. Pat. No. 5,677,965 to Moret et al shows a capacitive transducer. U.S. Pat. Nos. 5,146,435 and 5,452,268 to Bernstein disclose acoustic transducers. U.S. Pat. No. 4,993,072 to Murphy reveals a shielded electret transducer.
However, none of the silicon condenser microphones mentioned above has been reported to achieve sensitivity above 20 mV/Pa. In terms of conventional condenser microphones (i.e. non-silicon), very few products can have sensitivity as high as 100 mV/Pa. For example, Bruel & Kjoer, Denmark (B&K) has only one microphone available with this high sensitivity (B&K 4179, 1-inch diameter). Its dynamic range is about 140 dB (200 Pa) and frequency range is 5-7 kHz. However, this microphone must be fit onto a bulky pre-amplifier and requires a polarization voltage of 200V

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a silicon condenser microphone having high sensitivity and low noise.
Another object of the invention is to provide a silicon condenser microphone design having high sensitivity and low noise.
A further object of the invention is to provide a method for fabricating a silicon condenser microphone using via contact processes for a planar process.
Yet another object of the invention is to provide a method for fabricating a silicon condenser microphone using buckling of a composite diaphragm to prevent stiction in a wet release process.
In accordance with the objects of this invention a silicon condenser microphone is achieved. The silicon condenser microphone of the present invention comprises a perforated backplate comprising a portion of a single crystal silicon substrate, a support structure formed on the single crystal silicon substrate, and a floating silicon diaphragm supported at its edge by the support structure and lying parallel to the perforated backplate and separated from the perforated backplate by an air gap.
Also in accordance with the objects of this invention a method of fabricating a silicon condenser microphone having high sensitivity and low noise is achieved. A single crystal silicon substrate (P−) is provided. First ions (P+) of a first conductivity type are implanted into the single crystal silicon substrate to form a pattern of acoustic holes in a central portion of the substrate. Second ions (N−) of a second conductivity type opposite the first conductivity type are implanted into the substrate and surrounding the pattern of acoustic holes to form a backplate region. Third ions (P+) of the first conductivity type are implanted overlying the pattern of acoustic holes. Fourth ions (N+) of the second conductivity type are implanted overlying a portion of the backplate region not surrounding the pattern of acoustic holes to form an ohmic contact region. A front side nitride layer is deposited overlying the backplate region. A back side nitride layer is deposited on an opposite surface of the substrate. A front side sacrificial oxide layer is deposited overlying the front side nitride layer. A back side sacrificial oxide layer is deposited overlying the back side nitride layer. First trenches are etched through the front side sacrificial oxide layer to the ohmic contacts, and to the substrate off the backplate region. The first trenches are filled with a first polysilicon layer which is patterned to form polysilicon caps overlying the first trenches and to form polysilicon endplates surrounding the pattern of acoustic holes. A first oxide layer is deposited overlying the patterned first polysilicon layer. The first oxide layer is etched to the polysilicon layer followed by a thin oxide deposition to form the tiny holes for first dimples overlying the endplates. A second polysilicon layer is deposited overlying the first oxide layer and filling the first dimple holes. The second polysilicon layer is etched to form a functional layer of a composite diaphragm and its lead-out to a bond pad. A second oxide layer is deposited overlying the first oxide layer and the functional diaphragm. A narrow and continuous opening on the second oxide layer is etched on an inner edge of the functional diaphragm. A third polysilicon layer is deposited overlying the second oxide layer and filling the openings whereby a portion of the second oxide layer is enclosed between the second and third polysilicon layers to form a compressive layer of the composite diaphragm. The third polysilicon layer is patterned to remain filling the narrow and continuous opening to form a protective layer over the compressive layer of the composite diaphragm. The first and second oxide layers are etched followed by a thin oxide deposition to form second dimple holes overlying the first dimples. A deep oxide trench etching is made through the endplates and the sacrificial oxide layer to the substrate to form the supporting struts. The first and second oxide layers are etched to make anchor openings to the polysilicon caps, endplates, and bond pads. A nitride layer is deposited overlying the second oxide layer and filling the second dimple holes, the oxide trenches and the anchor openings. The nitride layer is patterned to expose the bond pads and the composite diaphragm within the second dimples. Thereafter, the backside sacrificial oxide layer is removed and the backside nitride layer is patterned. From the backside, the silicon substrate is etched away to the backplate region. The pattern of acoustic holes is selectively etched away. The backside nitride layer and the frontside nitride layer exposed by the acoustic holes are etched away from the backside. The frontside sacrificial oxide layer is removed using a wet etching method wherein the compressive layer of the composite diaphragm causes the composite diaphragm to buckle in a direction away from the backplate region. After drying, the protective layer and the compressive layer of the composite diaphragm are removed wherein the functional diaphragm flattens to complete fabrication of a silicon condenser microphone.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of this description, there is shown:
FIGS. 1 through 20 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention.
FIG. 21 schematically illustrates in cross-sectional representation a completed microphone of the present invention.
FIG. 22 graphically illustrates a typical simulated frequency response for a microphone of the present invention.
FIG. 23 graphically illustrates simulated and tested frequency responses for a microphone of the present invention.
FIG. 24 graphically illustrates the tested equivalent noise level for a microphone of the present invention.
FIG. 25 graphically illustrates tested frequency responses for a microphone of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention discloses a novel design and process for making a silicon condenser microphone. Referring now more particularly to FIG. 1, there is shown a semiconductor substrate 10, preferably composed of P-doped monocrystalline silicon. A thermal oxide layer 12 is grown on the surface of the substrate to a thickness of between about 270 and 330 Angstroms.
Referring now to FIG. 2, P+ implants 16 are made through a mask, not shown. These implanted regions 16 will form acoustic holes on the backplate in the later selective silicon etching process. The P+ implant condition must ensure the acoustic hole size at a desired backplate thickness. Now, an N− implanted region 18 is formed using a second mask, not shown. The N− implant condition must ensure a low stress backplate so that the backplate will not deform after the release process at the end of the fabrication process. The implanted ions are driven in to a depth of about 10 microns, which is the depth of the N− region. Because of the dosage difference, the P+ region has a larger drive-in depth.
The thermal oxide layer 12 is removed, for example, by wet etching. Now a second thermal oxide layer 20 is grown on the surface of the substrate to a thickness of between about 270 and 330 Angstroms, as illustrated in FIG. 3. A P++ implantation region 22 is formed at the surface of the substrate using a PMOS source/drain implant condition. A N++ implantation region 24 is formed elsewhere at the surface of the substrate using an NMOS source/drain implant condition. A backside P++ implantation region 26 is formed on the backside of the wafer using a PMOS source/drain implant condition. Now, a shallow drive-in source/drain annealing is performed and the thermal oxide layer 20 is removed.
Referring now to FIG. 4, a composite dielectric layer is formed on front and back sides of the wafer. First a thermal oxide layer is grown on the front and back sides (illustrated as top and bottom of the drawing figure) to a thickness of between about 270 and 330 Angstroms. Next, a silicon nitride layer is deposited by low pressure chemical vapor deposition (LPCVD) over the thermal oxide layer on the front and back sides of the wafer to a thickness of between about 1400 and 1600 Angstroms. The composite oxide/nitride layer 30 is patterned to expose the P++ contact on the wafer edge. The composite oxide/nitride layer will act as an etching stop on the frontside and as a silicon etching mask on the backside.
Now, a tetraethoxysilane (TEOS) oxide layer is deposited over the composite oxide/nitride layer on both the front and back sides of the wafer by LPCVD to a thickness of between about 1800 and 2200 Angstroms. Finally, a second nitride layer is deposited over the TEOS layer only on the back side of the wafer by plasma enhanced chemical vapor deposition (PECVD). This will provide an excellent mask for silicon etching by KOH on the backside of the wafer. The composite layer of thermal oxide, nitride, and TEOS oxide on the top side of the wafer is represented by 30 in FIG. 4. The composite layer of thermal oxide, nitride, TEOS oxide, and PECVD nitride on the back side of the wafer is represented by 32.
Now, sacrificial oxide layers are deposited on the front and back sides of the wafer as shown in FIG. 5. The oxide layer on the back side of the wafer provides stress balance. Sacrificial oxide layers 40 and 42 may be formed in successive steps. For example, a first layer of phosphosilicate glass (PSG) is deposited on the front side of the wafer to a thickness of about 3 microns, followed by a TEOS oxide layer deposited by PECVD to a thickness of about 1 micron. Next, a 3 micron layer of PSG and a successive 1 micron layer of PE-TEOS is deposited on the back side of the wafer. Then, a 2 μm layer of PSG is deposited on the PE-TEOS layer on the front side of the wafer, followed by 1 μm of PE-TEOS and 1 μm of PSG. This completes the front side sacrificial oxide layer 40. The backside sacrificial oxide layer 42 may be completed in the same way by depositing a 2 μm layer of PSG is deposited on the PE-TEOS layer on the back side of the wafer, followed by 1 μm of PE-TEOS and 1 μm of PSG. Other combinations of steps and materials can be used. The wafer is annealed; for example, at between about 950 and 1150° C. for about 30 minutes. The annealing serves to densify the composite sacrificial oxide layer.
Referring now to FIG. 6, deep trenches are etched through the sacrificial oxide layer 40 and the composite dielectric layer 30 to the silicon substrate.
Now, a polysilicon layer 46 is deposited over the top oxide layer and within the trenches. Simultaneously, polysilicon 48 is deposited on the bottom oxide layer 42. The polysilicon layer is patterned to leave a polysilicon cap of about 1.5 μm in thickness over the filled trenches and elsewhere as shown in FIG. 7. The filled trenches provide via contacts to the N-type doped backplate as well as the isolation walls to protect the oxide outside the diaphragm area. The caps are formed to provide supports for the diaphragm. Now the wafer is annealed; for example, at between about 950 and 1150° C. for about 90 minutes. This annealing causes the polysilicon 46 to be doped by the phosphorous component in the PSG.
Now the diaphragm is to be formed. An oxide layer 50 is deposited over the patterned polysilicon layer, as shown in FIG. 8. For example, the oxide layer 50 may comprise a first layer of TEOS oxide deposited by LPCVD to a thickness of between about 900 and 1100 Angstroms and a second layer of PSG oxide having a thickness of between about 8100 and 9900 Angstroms. The LP-TEOS layer is necessary to prevent PSG from bubbling and serious reflow in later high temperature annealing steps. Other materials like PE-TEOS oxide may also be used. Now, the oxide layer 50 is etched to the polysilicon layer 46 above the acoustic holes 16. A thin oxide layer, not shown, is deposited conformally over the oxide layer 50 to a thickness of between about 900 and 1100 Angstroms and lining the holes etched to the polysilicon layer to form dimple holes 53. Oxide layer 50 includes this additional thin oxide layer in the drawing figures.
Now a layer of polysilicon 58 is deposited over the oxide layer 50 and filling the dimple holes to form the dimples 53, as shown in FIG. 10. The thickness of the polysilicon layer should be about 3 μm. The polysilicon layer 58 is patterned as shown. The section 59 is a lead-out to a bond pad.
As illustrated in FIG. 11, a PSG layer 60 is deposited over the oxide layer 50 and the polysilicon layer 58 to a thickness of between about 4500 and 5500 Angstroms. A narrow and continuous opening is etched through the PSG layer 60 to the polysilicon layer 58. A polysilicon layer 62 is deposited over the PSG layer and filling the opening, as shown in FIG. 12. The polysilicon layer 62 has a thickness of between about 3500 and 4100 Angstroms. The polysilicon layer 62 encloses the PSG layer overlying the polysilicon layer 58.
Referring now to FIG. 13, the oxide layer 60 is etched to form dimple holes 65 directly overlying the dimple holes 53 filled with the diaphragm layer 58. Another oxide layer is deposited over the oxide layer 60 and lining the dimple holes 65. This oxide layer is not shown apart from the oxide layer 60 in the drawings. Because of this oxide layer, the dimples do not contact the diaphragm layer 58. Deep trenches 67 are etched through the oxide layer 60, the polysilicon layer 46, and the oxide layer 40 to the silicon substrate adjacent to but outside the edges of the diaphragm 58. Anchor openings 69 are also etched, preferably using a wet etching recipe, to the horizontal polysilicon structures 46 overlying the first deep trenches filled with polysilicon 46 and overlying the second deep trenches 67. A wet etching recipe is preferred so that a sloped opening is formed. The sloped opening will prevent sharp corners in a later nitride deposition.
As illustrated in FIG. 14, a nitride layer 70 is deposited over the wafer and filling the dimple holes 65, trenches 67, and openings 69. The nitride layer is deposited by PECVD for low tensile stress to a thickness of about 3 μm. The nitride layer 72 within the deep trenches 67 forms supporting struts for the diaphragm. The nitride layer 74 within the anchor openings 69 forms anchors.
The nitride layer 70 is etched using, for example, a combination of dry and wet etching to form openings 75 to bonding pads 46 and 59 and to clear the nitride from the area of the diaphragm.
A contact 81 is opened by a dry and wet etching process to the substrate surface, as shown in FIG. 15. The etching is made on the wafer edge to open the contact to the P++ region which connects all P+ acoustic holes. A chromium layer is deposited over the substrate to a thickness of between about 700 and 900 Angstroms followed by a gold seed layer having a thickness of between about 2200 and 2600 Angstroms. Gold is electroplated selectively onto the seed layer to form bond pads 83 having a thickness of about 2 μm.
Referring now to FIG. 16, layers 48 and 42 are stripped from the backside of the wafer. Then, layer 32 is etched away where it is not covered by a mask, not shown, using a nitride etching recipe.
Now, a KOH etching is performed using the composite layer 32 as mask, to open the back side of the wafer as shown in FIG. 17. The etching is a selective etching of silicon using a four electrode electro-chemical etching (ECE) configuration. The N− region contacts a positive electrode (working electrode) while the P+ acoustic hole region connects to a negative electrode (cathode). A negative electrode (counterelectrode) is inserted in the KOH solution. A reference electrode in the KOH solution provides the referential potential. By the four-electrode configuration, the N− region and the p-type substrate are inverse biased. The silicon is etched until the N− region is reached. The sudden increased current in the N− region causes oxide passivation to prevent N− from being etched. The etching continues at the P+ acoustic holes because of the reverse biasing. The potentials of all the electrodes are required to be controlled properly. This is the key to the ECE technique. Etching stops at the nitride in layer 30. Back side opening 91 is shown.
Cr/Au as the sputtered ECE metal layer is etched. 83 is plated by Au about 2 microns thick and so remains. A blanket nitride stripping from the back side of the wafer removes layer 32 completely and also strips nitride layer 30 where it is exposed by the acoustic holes, as illustrated in FIG. 18.
The wafer is now cut by a high speed spinning diamond cutter, called dicing. Now, the wafer is subjected to a dip in a hydrofluoric acid solution, preferably about 49% HF, for about 3.5 minutes. This dip removes the sacrificial oxide layer 40 through the backside opening as well as the frontside gaps, as shown in FIG. 19.
FIG. 19 shows compressive buckling of the diaphragm 58. The sandwiched compressive layer 60 causes buckling during the wet release step. This compressive buckling is desirable as it can counter the stiction force during drying and thus prevent the diaphragm from sticking to the backplate 100. The device is rinsed and then dried. For example, rinsing is in de-ionized water for about 30 minutes and in methanol for 30 minutes. Drying is done in an oven at 90° C. The dimples 58 are there to minimize the constraints to the diaphragm for the desired simply-supported boundary condition. Dimples can touch either to the poly caps 46 or to the top nitride 70.
Now, the protective layer 62 and the compressive layer 60 of the composite diaphragm are removed. First the polysilicon layer 62 is removed by a dry etching. A second dry etching step removes the PSG oxide layer 60. No masking is required in these removal steps because either polysilicon etching or oxide etching does not attack the other exposed layers. The two dry etching process steps have high selectivity to each other.
The completed microphone is shown in FIG. 20. After the compressive oxide is removed, the stress is released and the diaphragm flattened.

A number of design variations are proposed to cover the sensitivity from 25 mV/Pa to above 100 mV/Pa. FIG. 21 and Table I illustrate the microphone design parameters and Table II illustrates simulated performance parameters. In FIG. 21, the die size E is 3980 μm. E is variable and could be smaller for a smaller diaphragm, for example. Diaphragm size A, air gap B, acoustic hole size C, and acoustic hole pitch D are illustrated.

TABLE I


Design Variations

	1	2	3	4	5

Diaphragm	2000	1000	1000	2000	2000
size (μm)
Diaphragm	3	2	2	2	2
thickness
(μm)
Air Gap	8	8	8	8	8
(μm)
Backplate	10	10	10	10	10
thickness
(μm)
Acoustic	20	30	40	40	40
hole (μm)
Acoustic	60	84	100	100	84
hole pitch
(μm)
# acous.	850	95	75	300	425
holes
Acoustic	10.80%	10.90%	15.30%	15.20%	12.20%
perforation

TABLE II


Design Variations

	1	2	3	4	5

Zero-bias	3.10	0.80	0.74	2.95	3.48
capac. (pF)
Collapse	15.6	33.41	34.89	16.69	15.74
voltage (V)
Bias volt. (V)	10.4	22.27	23.27	10.69	10.49
Sensitivity	−19.63	−31.89	−29.43	−19.7	−19.71
dB ref 1 V/Pa
Sensitivity	104	25	34	103	103
mV/Pa
Low roll-off	3	<3	<3	4	4
(Hz)
High roll-off	3600	10,000	9000	6500	6600
(Hz)
Over pressure	52	247	252	52	52
(Pa)

Table I illustrates design parameter variations that have been reduced to practice for 5 sample dies. Table II illustrates the simulation results for the 5 sample dies. Important results are the bias voltage (=2/3 of the collapse voltage) and Sensitivity in mV/Pa. Over pressure is shown where deflection is less than 2/3 of the gap height. The design parameters of design variations 1, 4, and 5 enable high sensitivities above 100 mV/Pa while those of design variations 2 and 3 give lower sensitivities (33 mV/Pa) but a wider frequency response.
FIG. 22 illustrates a typical frequency response for design variation number 4 with a bias voltage of 10.7 volts. The present invention has been reduced to practice. FIG. 23 provides a simulation and test correlation at a bias voltage of 10 volts. Line 231 shows the simulated results for a microphone of the present invention. Line 232 shows the actual tested frequency response of a microphone fabricated according to the process of the present invention. FIG. 24 illustrates the tested equivalent noise level of a microphone fabricated according to the process of the present invention at a bias voltage of 10 volts. The equivalent noise level (ENL) is equal to the microphone self-noise divided by the microphone sensitivity. The ENL decides the minimum sound pressure level that can be detected by the microphone. The tested ENL in FIG. 24 was 9.4 dBA.
FIG. 25 illustrates tested frequency responses for a microphone fabricated according to the process of the present invention at a bias voltage of 8 volts showing a sensitivity of 25 mV/Pa. The test results shown in these graphs have proven that the invented microphone design and fabrication method can produce the microphone with any desired high performance—higher sensitivity (>100 mV/Pa) in a narrow frequency range (<3 KHz) or lower sensitivity (>20 mV/Pa) in a wider frequency range (>10 KHz).
The microphone design and fabrication process of the present invention produces a high performance microphone with the highest sensitivity and lowest noise achieved. The microphone of the present invention includes a stress-free polysilicon diaphragm. The composite diaphragm design includes compressive buckling for anti-stiction. After release and drying, the compressive layers on the diaphragm are removed. The fabrication process is a planar process despite thick sacrificial layers. Via contacts are formed by polysilicon filling and self-doping.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Claims

1. A method of fabricating a perforated silicon diaphragm comprising:

providing a single crystal silicon substrate of a first conductivity type;

blanket implanting first ions of a second conductivity type opposite said first conductivity type into said single crystal silicon substrate to form an etch stop layer;

selectively implanting second ions of said first conductivity type into said single crystal silicon substrate to form a pattern of holes in a portion of said substrate;

implanting third ions of said first conductivity type overlying said pattern of holes and forming a first ohmic contact region;

implanting fourth ions of said second conductivity type not surrounding said pattern of holes to form a second ohmic contact region;

thereafter depositing a nitride layer on a frontside and a backside of said silicon substrate;

forming contacts through said nitride layer to said first and second ohmic contact regions;

thereafter patterning said backside nitride layer; and

from the backside, etching away said silicon substrate not covered by said nitride layer to said etch stop layer and simultaneously selectively etching away said pattern of holes to complete formation of said perforated diaphragm.

2. The method according to claim 1 wherein said first conductivity type is P-type and wherein said second conductivity type is N-type.

3. The method according to claim 1 wherein said first ions are N− ions, said second ions are P+ ions, said third ions are P++ ions, and said fourth ions are N++ ions.

4. The method according to claim 1 wherein said nitride layer is deposited by low pressure chemical vapor deposition.

5. The method according to claim 1 wherein said nitride layer has a thickness of between about 1000 and 1500 Angstroms.

6. The method according to claim 1 wherein said etch stop layer has a depth into said silicon substrate of between about 1 and 10 microns.

7. The method according to claim 1 wherein said step of forming contacts through said nitride layer to said first and second ohmic contact regions comprises:

etching contact openings through said nitride layer to said first and second ohmic contact regions;

depositing a metal layer within said contact openings and overlying said nitride layer; and

patterning said metal layer to form a first electrode contacting said first ohmic contact region and a second electrode contacting said second ohmic contact region.

8. The method according to claim 1 wherein said step of etching away said silicon substrate not covered by said nitride layer to said etch stop layer and simultaneously selectively etching away said pattern of holes comprises KOH with a 4 electrode electrochemical etching (ECE) configuration.

9. A method of fabricating a perforated silicon diaphragm comprising:

providing a single crystal silicon substrate of a first conductivity type;

blanket implanting first ions of a second conductivity type opposite said first conductivity type into said single crystal silicon substrate to form an etch stop layer wherein a depth of said etch stop layer into said silicon substrate determines a thickness of said perforated diaphragm;

thereafter patterning said backside nitride layer; and

10. The method according to claim 9 wherein said first conductivity type is P-type and wherein said second conductivity type is N-type.

11. The method according to claim 9 wherein said first ions are N− ions, said second ions are P+ ions, said third ions are P++ ions, and said fourth ions are N++ ions.

12. The method according to claim 9 wherein said nitride layer is deposited by low pressure chemical vapor deposition.

13. The method according to claim 9 wherein said nitride layer has a thickness of between about 1000 and 1500 Angstroms.

14. The method according to claim 9 wherein said etch stop layer has a depth into said silicon substrate of between about 1 and 10 microns.

15. The method according to claim 9 wherein said step of forming contacts through said nitride layer to said first and second ohmic contact regions comprises:

16. The method according to claim 9 wherein said step of etching away said silicon substrate not covered by said nitride layer to said etch stop layer and simultaneously selectively etching away said pattern of holes comprises KOH with a 4 electrode electrochemical etching (ECE) configuration.

17. A method of fabricating a perforated silicon diaphragm comprising:

providing a single crystal silicon substrate of a first conductivity type;

blanket implanting at a first dose first ions of a second conductivity type opposite said first conductivity type into said single crystal silicon substrate to form an etch stop layer wherein a depth of said etch stop layer into said silicon substrate determines a thickness of said perforated diaphragm;

selectively implanting at a second dose second ions of said first conductivity type into said single crystal silicon substrate to form a pattern of holes in a portion of said substrate;

implanting at a third dose third ions of said first conductivity type overlying said pattern of holes and forming a first ohmic contact region;

implanting at a fourth dose fourth ions of said second conductivity type not surrounding said pattern of holes to form a second ohmic contact region;

thereafter patterning said backside nitride layer; and

18. The method according to claim 17 wherein said first dose is lower than the second, third, and fourth doses.

19. The method according to claim 17 wherein said first conductivity type is P-type and wherein said second conductivity type is N-type.

20. The method according to claim 17 wherein said first ions are N− ions, said second ions are P+ ions, said third ions are P++ ions, and said fourth ions are N++ ions.

21. The method according to claim 17 wherein all of said steps up to said patterning said backside nitride layer step can be CMOS compatible processes.

22. The method according to claim 17 wherein, said etch stop layer has a depth into said silicon substrate of between about 1 and 10 microns.

23. The method according to claim 17 wherein said step of forming contacts through said nitride layer to said first and second ohmic contact regions comprises:

24. The method according to claim 17 wherein said step of etching away said silicon substrate not covered by said nitride layer to said etch stop layer and simultaneously selectively etching away said pattern of holes corn with a 4 electrode electrochemical etching (ECE) configuration.

25. The method according to claim 23 wherein said step of implanting at a third dose third ions of said first conductivity type overlying said pattern of holes connects said pattern of holes together to provide external electric biases for said ECE configuration.