US20050001309A1 - Printed wiring board for mounting semiconductor - Google Patents

Printed wiring board for mounting semiconductor Download PDF

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Publication number
US20050001309A1
US20050001309A1 US10/869,857 US86985704A US2005001309A1 US 20050001309 A1 US20050001309 A1 US 20050001309A1 US 86985704 A US86985704 A US 86985704A US 2005001309 A1 US2005001309 A1 US 2005001309A1
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US
United States
Prior art keywords
taper
shaped
hole
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US10/869,857
Inventor
Akinori Tanaka
Toru Yamada
Tadashi Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JAPAN CIRUIT INDUSTRIAL Co Ltd
Original Assignee
JAPAN CIRUIT INDUSTRIAL Co Ltd
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Filing date
Publication date
Priority claimed from JP2003175723A external-priority patent/JP2005012035A/en
Priority claimed from JP2004036225A external-priority patent/JP2005228916A/en
Application filed by JAPAN CIRUIT INDUSTRIAL Co Ltd filed Critical JAPAN CIRUIT INDUSTRIAL Co Ltd
Assigned to JAPAN CIRUIT INDUSTRIAL CO., LTD. reassignment JAPAN CIRUIT INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ANDO, TADASHI, TANAKA, AKINORI, YAMADA, TORU
Publication of US20050001309A1 publication Critical patent/US20050001309A1/en
Priority to US11/700,821 priority Critical patent/US7514298B2/en
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15173Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09563Metal filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/0959Plated through-holes or plated blind vias filled with insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827Tapered, e.g. tapered hole, via or groove
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal

Definitions

  • the present invention relates to a printed wiring board suitable for use in electronic equipment, electrical equipment, a computer, telecommunications equipment, etc. More specifically, it relates to a printed wiring board used for a pin grid array, a ball grid array, a chip size package, MCM, etc., which mounts a semiconductor.
  • a high density of a printed wiring board is required in accordance with high integration of a semiconductor. Particularly, not only an increase in the number of layers and a fine line of a wiring pattern but also a decrease in the size of a plated penetrating through hole are rapidly advancing with regard to a semiconductor-mounting printed wiring board used in the above fields.
  • the decrease in the through hole size can contribute an improvement in the density of a wiring pattern, since it can decrease the size of a pad for the through hole.
  • a through hole land and a ball pad and/or a bump pad are disposed separately, so that there is a limit to the density increase.
  • the hole is filled with an insulating resin or an electrically conductive paste for preventing an influence on parts to be mounted.
  • an insulating resin or an electrically conductive paste for preventing an influence on parts to be mounted.
  • the present inventors have proposed a printed wiring board having a taper-shaped through hole obtained by plating an internal wall surface and a small-diameter side end of a taper-shaped penetration hole to plate the internal wall surface and seal the small-diameter side end (JP-A-2000-77568, JP-A-2000-77809).
  • the above printed wiring board does not overcome the problem of high density of a wiring pattern.
  • a ball pad or a bump pad is disposed separately from a through hole land, and these are connected to each other.
  • the through hole land can be directly used as a ball pad or a bump pad, a further high density can be actualized.
  • the above process of resin-filling and lid-plating requires a number of steps and, in addition, the thickness of copper on an external layer becomes large, so that it is difficult to make a fine wiring. Further, with regard to a general through hole, it is difficult to fill it by plating.
  • the present invention 1 provides a printed wiring board for mounting a semiconductor, which printed wiring board has a taper-shaped through hole connecting an upper surface circuit and a lower surface circuit, and/or an internal layer circuit, the taper-shaped through hole being obtained by plating an inner wall surface and a small-diameter side end of a taper-shaped penetration hole with a metal to plate the inner wall surface and seal the small-diameter side end, wherein a ball pad or a bump pad is formed at at least a small-diameter side end of the taper-shaped through hole.
  • the present invention 2 provides a printed wiring board for mounting a semiconductor, comprising a plurality of taper-shaped through holes electrically conducting an upper surface circuit and a lower surface circuit, and ball pads and/or bump pads respectively provided on upper portions and lower portions of the taper-shaped through holes, the taper-shaped through holes being obtained by plating internal wall surfaces and small-diameter side ends of taper-shaped penetration holes with a metal to plate the internal wall surfaces and seal the small-diameter side ends, wherein the center position of at least one through hole of the through holes is one-sided within the ball pad and/or the bump pad corresponding to the at least one through hole or within a peripheral area which is 100 m or less outside from the edge of the ball pad and/or the bump pad corresponding to the at least one through hole.
  • FIG. 1 is an explanatory drawing showing a printed wiring board of the present invention, in which ball pads are formed at small-diameter side ends of taper-shaped through holes.
  • FIG. 2 is an explanatory drawing showing a printed wiring board of the present invention, in which taper-shaped through holes are filled by plating and bump pads are formed at small-diameter side ends and ball pads are formed at large-diameter side ends.
  • FIG. 3 is an explanatory drawing showing a printed wiring board of the present invention, in which taper-shaped through holes are filled with a solder resist and solder balls are mounted on small-diameter side ends.
  • FIG. 4 is an explanatory drawing showing a printed wiring board of the present invention, in which pads are formed at both side ends of taper-shaped through holes filled by plating and solder precoats and solder balls are mounted.
  • FIG. 5 is an explanatory drawing showing a printed wiring board of the present invention, in which taper-shaped through holes made in a four-layer board are filled with a solder resist and ball pads and solder balls are mounted on small-diameter side ends.
  • FIG. 6 is an explanatory drawing showing a printed wiring board of the present invention, in which taper-shaped through holes made in a four-layer board are filled by plating and solder balls and solder precoats are mounted on pads formed on both side ends.
  • FIG. 7 is an explanatory drawing showing the wiring state of a printed wiring board having taper-shaped through holes of which the center positions are one-sided from the arrangement of the center positions of other taper-shaped through holes and taper-shaped through holes of which the center positions are not one-sided.
  • FIG. 8 is an explanatory drawing showing the wiring state of a printed wiring board having taper-shaped through holes of which the center positions are one-sided from the arrangement of the center positions of other taper-shaped through holes and taper-shaped through holes of which the center positions are not one-sided.
  • FIG. 9 is an explanatory drawing showing the wiring state of a printed wiring board having taper-shaped through holes of which the center positions are one-sided from the arrangement of the center positions of other taper-shaped through holes and taper-shaped through holes of which the center positions are not one-sided.
  • An insulating substrate 1 ( FIG. 1 (A)) used in the printed wiring board of the present invention is a laminate or a glass-fiber-containing or glass-fabric-containing laminate of an epoxy resin, a cyanate resin, a bismaleimide triazine resin, a polyimide resin, a polyphenylene ether resin, etc.
  • a film-like insulating material can be also used.
  • the insulating material is not specially limited so long as it is an insulating material which is used as a printed wiring board or a semiconductor package.
  • a double-side board or a multilayer board can also be used.
  • As an insulating substrate 1 there may be also used a substrate having conductive layers 2 ( FIG. 1 (A)), such as copper foils, on upper and lower surfaces. These materials will be generically called “substrate, etc.” hereinafter.
  • a taper-shaped penetration hole 3 ( FIG. 1 (B)) is made at a position of a substrate, etc., at which the penetration hole is to be made, and upper and lower surfaces of the insulating substrate of the taper-shaped penetration hole are electrically conducted to each other by a panel plating method (electroless plating 4 and electroplating 5 , etc.), to make a through hole 8 and simultaneously seal its small-diameter side end with a plating metal. Thereafter, patterns are formed on the upper and lower surfaces by a known subtractive method. In the formation of the patterns, a ball pad 6 ( FIG. 1 (E)) is disposed on the taper-shaped through hole portion.
  • patterns are formed by a pattern plating method (additive method, semi-additive method, etc.) and simultaneously the inside of the through hole is plated to electrically connect the upper surface and the lower surface and to plate and seal the small-diameter side end, whereby a ball pad or bump pad is disposed at the through hole portion.
  • a pattern plating method additive method, semi-additive method, etc.
  • the taper-shaped penetration hole is formed by preferably laser processing, more preferably UV-laser processing.
  • a general cylindrical penetration hole is made in a substrate, etc., with a UV laser, it can be made by overlapping small laser-processing spots, i.e. by trepanning processing, as disclosed in U.S. Pat. No. 5,593,606.
  • the taper-shaped penetration hole of the present invention is made by similar trepanning. It is preferred that a laser energy and the number of shots are selected such that the processing progresses more in the central part of the penetration hole than in a marginal part of the penetration hole, as seen from the upper surface of the substrate, etc.
  • UV laser processing conditions differ depending upon the thickness of a material to be processed or the thickness of a metal conductor, while the processing is carried out by controlling the energy of one shot, positions of shots, the number of shots, the total energy, etc.
  • the penetration hole is made by a method in which a copper foil in a position where the penetration hole is to be made is removed by etching and then the copper-clad laminate is processed by laser irradiation, a method in which a copper surface is treated by blackening treatment or etching treatment and then a laser is irradiated, or a method in which an entry sheet for laser processing is disposed and then a laser is irradiated.
  • it is required to control an irradiation energy, the number of pulses, the diameter of a mask, etc.
  • a backup sheet for laser processing may be disposed on a laser-outgoing side.
  • a carbon dioxide gas laser and a UV laser may be used in combination in the laser processing.
  • the UV laser may be used for forming an opening of the small-diameter side end after carrying out processing with the carbon dioxide gas laser.
  • the entry sheet for laser processing or as the backup sheet for laser processing there may be used an entry sheet or a backup sheet disclosed in JP-A-1999-346059A.
  • the diameter of the small-diameter side end of the taper-shaped penetration hole is preferably 5-70 ⁇ m.
  • the diameter of the small-diameter side end of the taper-shaped penetration hole is preferably 5-70 ⁇ m.
  • the above diameter is smaller than 5 ⁇ m, it is difficult to continuously supply a plating solution into the inside of the hole on the small-diameter side in plating processing even when the plating solution is stirred or shaken.
  • the small-diameter side end can be sealed with a plating metal, the cross-section area, at the small-diameter part, of a plating layer for electrically connecting an upper conductor and a lower conductor of the insulating substrate becomes small, so that connection reliability decreases.
  • the opening diameter of the small-diameter side end is more preferably 10 to 50 ⁇ m, further more preferably 15 to 40 ⁇ m.
  • the diameter of a large-diameter side end is preferably 200 ⁇ m at maximum.
  • the diameter of the large-diameter side end is more preferably 150 ⁇ m or less, further more preferably 100 ⁇ m or less.
  • the plating processing can be carried out by a general method such as panel plating or pattern plating.
  • the inside of the taper-shaped through hole may be filled and plated by concurrent use of pulse plating.
  • the hole-filling plating of the taper-shaped through hole is suitable when the large-diameter side end of the taper-shaped through hole is used as a ball pad or a bump pad.
  • the inside of the taper-shaped through hole plated and sealed may be covered or filled with an insulating material.
  • a coating composition which is generally called a solder resist can be used as the insulating material.
  • thermosetting resin a UV (ultraviolet) curable resin, a resin curable by UV and heat, etc. These resins may contain an inorganic filler component.
  • the solder resist is disposed on both the external surfaces.
  • the solder resist is disposed such that no solder resist is placed at portions at which a bondfinger pad, a ball pad, a bump pad, a mold gate, etc., are formed.
  • the above portions with no solder resist are properly treated by a surface-treatment such as electrolytic nickel/gold plating, electroless nickel/gold plating, organic rust prevention or a solder precoat, as required.
  • a surface-treatment such as electrolytic nickel/gold plating, electroless nickel/gold plating, organic rust prevention or a solder precoat, as required.
  • Different surface-treatments between the upper surface and the lower surface can be carried out, as required. Further, a partially different treatment may be carried out as required.
  • FIG. 2 shows an example in which a taper-shaped through hole is filled by plating in the plating step of FIG. 1 (D), a bump pad 9 is formed at the small-diameter side end and a ball pad 6 is formed at the large-diameter side end.
  • FIG. 3 shows an embodiment in which a solder ball 10 is mounted on a ball pad 6 at the small-diameter side end of a printed wiring board produced by the step of FIG. 1 (F).
  • FIG. 4 shows an embodiment in which a solder precoat 11 is mounted on the bump pad 9 (upper surface) formed at the small-diameter side end of the printed wiring board of FIG.
  • FIG. 5 shows an embodiment in which a taper-shaped through hole made in a four-layered board is filled with a solder resist 7 and a solder ball 10 is mounted on a ball pad 6 formed at the small-diameter side end.
  • FIG. 6 shows an embodiment in which a taper-shaped through hole made in a four-layered board is filled by plating and a solder precoat 11 is mounted on a bump pad 9 at the small-diameter side end and a solder ball 10 is mounted on a ball pad 6 at the large-diameter side end.
  • the thus-obtained printed wiring boards are able to be more densified as a package for mounting a semiconductor, so that they have advantages that more terminals can be disposed when an area is the same or an area can be decreased when the number of terminals is the same.
  • the center position of a specific taper-shaped through hole of taper-shaped through holes is not disposed at the center of a ball pad or a bump pad but it is disposed one-sidedly from the center positions of the other taper-shaped through holes in file and/or row direction(s).
  • FIG. 7 shows an embodiment in which ball pads are formed at the small-diameter side and the ball pads are disposed in four files (four lines counted from the top).
  • the center positions of specific taper-shaped through holes disposed in the center portion are one-sided in the right direction (right figure of FIG. 7 ).
  • the above one-sided disposition can widen a specific through hole land spacing on the large-diameter side (component side in FIG.
  • FIG. 8 shows an embodiment in which ball pads are formed at the small-diameter side ends and the ball pads are disposed in five files. This embodiment is an example in which the center positions of the through holes in the first file from the bond pad side are one-sided to the bond pad side and to the opposite direction side (right figure of FIG.
  • FIG. 9 shows embodiments in which ball pads are disposed in five files.
  • the right figure of FIG. 9 shows an example in which the one-sidedness of the center position is 100 ⁇ m or less. When it exceeds 100 ⁇ m, it is required to separately dispose a through hole land.
  • the right figure of FIG. 7 for example, means a figure drawn on the right as one faces the paper.
  • CSP chip scale package
  • FIG. 7 showing a general embodiment, there is a wiring 15 which can not secure a wiring connecting a bond pad 13 , as a junction with IC, to a through hole 8 .
  • the center positions of through holes 8 in the center portion are one-sided with regard to the center position of the other through hole 8 , as shown in the figure, thereby actualizing a wiring 16 in the same line/space rule.
  • CSP chip scale package
  • CSP chip scale package
  • the present invention has been explained mainly with regard to a double-side substrate, while a similar design can be actualized with regard to a multilayer substrate. Further, a similar design can be also actualized with regard to flip chip in place of wire bonding, and densification is possible.
  • a produced printed wiring board can be more densified as a package for mounting a semiconductor, so that it has advantages that more terminals can be disposed when an area is the same or an area can be decreased when the number of terminals is the same.
  • a high-densified printed wiring board for mounting a semiconductor by making a taper-shaped through hole of which a side end is sealed and forming a bump pad or a ball pad on the side end of the through hole.
  • the center position of a specific taper-shaped through hole of the above taper-shaped through holes is not positioned at the center of the ball pad or bump pad and is disposed one-sidedly in file and/or row direction(s) from the arrangement of the center positions of the other taper-shaped through holes.
  • the above one-sided disposition of the specific taper-shaped through hole broadens a specific land spacing on the large-diameter side end side of the taper-shaped through hole and increases the number of wirings locatable at the above space, whereby there is provided a higher-densified printed wiring board for mounting a semiconductor.
  • a BT (bismaleimide triazine resin) double-side copper-clad laminate (“CCL-HL832HS”, supplied by Mitsubishi Gas Chemical Company, Inc.) having 3- ⁇ m thick copper foils on both surfaces and a 100-m thick glass fabric inserted therein was used as a laminate.
  • a backup sheet (“LSB-90”, supplied by Mitsubishi Gas Chemical Company, Inc.) made of an aluminum foil was bonded to a lower surface of the laminate, and then taper-shaped penetration holes were made in the laminate with an UV laser (“YB-HYS401T 01 ”, supplied by Matsushita Industrial Information Equipment Co., Ltd.). Table 1 shows UV laser processing conditions.
  • the cross-sectional shape of the taper-shaped penetration holes obtained was a conical shape having a small-diameter side end of 20 ⁇ m and a large-diameter side end of 80 Mm.
  • copper plating was carried out by electroless plating and electroplating.
  • an electric current density 5A/dm 2 substrate
  • an inner wall surface of each taper-shaped through hole was plated to form a copper layer and simultaneously the small-diameter side end thereof was sealed by the plating to connect the copper foils on the upper and lower surfaces to each other, where by taper-shaped through holes were obtained.
  • the thickness of the plating was 15 to 28 ⁇ m in the through holes. The cross section thereof was checked.
  • Finger pad portions on the upper side (component side) and ball pad portions (shape of a solder mask define SMD) on the lower side (ball side) were made to be openings. Then, final curing was carried out. Then, electrolytic nickel/gold plating was carried out through a plating lead to plate the surfaces of the finger pads and the ball pads with gold (See FIG. 1 ).
  • An epoxy double-side copper-clad laminate (“E679FB”, supplied by Hitachi Chemical Co., Ltd.) having 12- ⁇ m thick copper foils on both surfaces and a 100- ⁇ m thick glass fabric inserted therein was used as a laminate.
  • the laminate was treated with a hydrogen peroxide/sulfuric acid type soft etching agent (“CPE 900 ”, supplied by Mitsubishi Gas Chemical Company, Inc.), to decrease the thickness of the copper foils on the external layers to 5 ⁇ m.
  • CPE 900 hydrogen peroxide/sulfuric acid type soft etching agent
  • taper-shaped through holes were made in the laminate with a UV laser (“YB-HYS401T 01 , supplied by Matsushita Industrial Information Equipment Co., Ltd.).
  • the UV processing conditions were the same as those in Example 1.
  • pattern plating was carried out. That is, after electroless copper plating, dry film plating resists were disposed on both surfaces of the laminate. The dry films in pattern portions and through hole portions (including ball pads and bump pads) which portions were required to be plated, were removed, and then electroplating was carried out. The above electroplating used a pulsed current, and the through holes were filled by the plating. Then, the dry films were peeled off and then the entire surface was etched with a soft etching solution, to remove the base copper layers and to leave patterns. As a pattern of the pattern plating, bump pads were formed at the through hole small-diameter side ends and ball pads were formed at the large-diameter side ends.
  • a solder resist (“PSR4000AUS308, supplied by TAIYO INK MFG. CO., LTD.) was formed by a general method such that the bump pads and the ball pads became openings. Then, the openings were treated by an organic rust prevention treatment (“GLICOAT-SMD [F2(LX)]”, supplied by SHIKOKU CORPORATION) (see FIG. 2 ).
  • a chip size package (CSP) substrate having a design shown in the right figure of FIG. 7 , as an arrangement of a pattern, and taper-shaped through holes was prepared as follows.
  • a BT (bismaleimide triazine resin) double-side copper-clad laminate (“CCL-HL832HS “supplied by Mitsubishi Gas Chemical Company, Inc.) having 3- ⁇ m thick copper foils on both surfaces and a 100- ⁇ m thick glass fabric inserted therein was used as a laminate.
  • a backup sheet (“LSB-90”, supplied by Mitsubishi Gas Chemical Company, Inc.) made of an aluminum foil was bonded to a lower surface of the laminate, and then taper-shaped penetration holes were made in the laminate with an UV laser (“YB-HYS401T 01 ”, supplied by Matsushita Industrial Information Equipment Co., Ltd.). Table 2 shows UV laser processing conditions.
  • the cross-sectional shape of the taper-shaped penetration holes obtained was a conical shape having a small-diameter side end of 20 ⁇ m and a large-diameter side end of 80 ⁇ m.
  • copper plating was carried out by electroless plating and electroplating.
  • an electric current density 5A/dm 2 substrate
  • an inner wall surface of each taper-shaped through hole was plated to form a copper layer and simultaneously the small-diameter side end thereof was sealed by the plating to connect the copper foils on the upper and lower surfaces to each other, whereby taper-shaped through holes were obtained.
  • the thickness of the plating was 15 to 28 ⁇ m in the through holes. The cross section thereof was checked.
  • Bond pad portions on the upper side (component side) and ball pad portions (shape of a solder mask define SMD) on the lower side (ball side) were made to be openings. Then, final curing was carried out. Then, electrolytic nickel/gold plating was carried out through a plating lead to plate the surfaces of the bond pads and the ball pads with gold (See FIG. 1 ).
  • the taper-shaped through holes having sealed ends were made and the center positions of some of the through holes were one-sided from the center of corresponding pads, whereby there was provided a printed wiring board for mounting a semiconductor, of which the number of wirings was increased, i.e., which was high-densified.

Abstract

A printed wiring board for mounting a semiconductor, which printed wiring board has a taper-shaped through hole connecting an upper surface circuit and a lower surface circuit, and/or an internal layer circuit, the taper-shaped through hole being obtained by plating an inner wall surface and a small-diameter side end of a taper-shaped penetration hole with a metal to plate the inner wall surface and seal the small-diameter side end, wherein a ball pad or a bump pad is formed at at least a small-diameter side end of the taper-shaped through hole.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a printed wiring board suitable for use in electronic equipment, electrical equipment, a computer, telecommunications equipment, etc. More specifically, it relates to a printed wiring board used for a pin grid array, a ball grid array, a chip size package, MCM, etc., which mounts a semiconductor.
  • PRIOR ARTS OF THE INVENTION
  • A high density of a printed wiring board is required in accordance with high integration of a semiconductor. Particularly, not only an increase in the number of layers and a fine line of a wiring pattern but also a decrease in the size of a plated penetrating through hole are rapidly advancing with regard to a semiconductor-mounting printed wiring board used in the above fields. The decrease in the through hole size can contribute an improvement in the density of a wiring pattern, since it can decrease the size of a pad for the through hole. However, a through hole land and a ball pad and/or a bump pad are disposed separately, so that there is a limit to the density increase. Further, with regard to a conventional cylindrical through hole, the hole is filled with an insulating resin or an electrically conductive paste for preventing an influence on parts to be mounted. However, there have been arising some problems such as sink or falling-off of the filling resin and moisture permeation. For solving the above problems, the present inventors have proposed a printed wiring board having a taper-shaped through hole obtained by plating an internal wall surface and a small-diameter side end of a taper-shaped penetration hole to plate the internal wall surface and seal the small-diameter side end (JP-A-2000-77568, JP-A-2000-77809).
  • However, the above printed wiring board does not overcome the problem of high density of a wiring pattern.
  • Generally, a ball pad or a bump pad is disposed separately from a through hole land, and these are connected to each other. When the through hole land can be directly used as a ball pad or a bump pad, a further high density can be actualized. However, for utilizing a through hole part as a ball pad or a bump pad, it is required to carry out lid-plating after filling the through hole with a resin. The above process of resin-filling and lid-plating requires a number of steps and, in addition, the thickness of copper on an external layer becomes large, so that it is difficult to make a fine wiring. Further, with regard to a general through hole, it is difficult to fill it by plating.
  • In the present fields, there is a tendency to a narrow pitch or a multi-row arrangement of ball pads or bump pads for achieving a further high density. In this case, it is required to arrange a number of wirings between through hole lands. However, the space between through holes is limited so that it is impossible to secure a necessary number of wirings.
  • SUMMARY OF THE INVENTION
  • It is an object of the present invention to provide a high-densified printed wiring board for mounting a semiconductor.
  • The present invention 1 provides a printed wiring board for mounting a semiconductor, which printed wiring board has a taper-shaped through hole connecting an upper surface circuit and a lower surface circuit, and/or an internal layer circuit, the taper-shaped through hole being obtained by plating an inner wall surface and a small-diameter side end of a taper-shaped penetration hole with a metal to plate the inner wall surface and seal the small-diameter side end, wherein a ball pad or a bump pad is formed at at least a small-diameter side end of the taper-shaped through hole.
  • The present invention 2 provides a printed wiring board for mounting a semiconductor, comprising a plurality of taper-shaped through holes electrically conducting an upper surface circuit and a lower surface circuit, and ball pads and/or bump pads respectively provided on upper portions and lower portions of the taper-shaped through holes, the taper-shaped through holes being obtained by plating internal wall surfaces and small-diameter side ends of taper-shaped penetration holes with a metal to plate the internal wall surfaces and seal the small-diameter side ends, wherein the center position of at least one through hole of the through holes is one-sided within the ball pad and/or the bump pad corresponding to the at least one through hole or within a peripheral area which is 100 m or less outside from the edge of the ball pad and/or the bump pad corresponding to the at least one through hole.
  • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is an explanatory drawing showing a printed wiring board of the present invention, in which ball pads are formed at small-diameter side ends of taper-shaped through holes.
  • FIG. 2 is an explanatory drawing showing a printed wiring board of the present invention, in which taper-shaped through holes are filled by plating and bump pads are formed at small-diameter side ends and ball pads are formed at large-diameter side ends.
  • FIG. 3 is an explanatory drawing showing a printed wiring board of the present invention, in which taper-shaped through holes are filled with a solder resist and solder balls are mounted on small-diameter side ends.
  • FIG. 4 is an explanatory drawing showing a printed wiring board of the present invention, in which pads are formed at both side ends of taper-shaped through holes filled by plating and solder precoats and solder balls are mounted.
  • FIG. 5 is an explanatory drawing showing a printed wiring board of the present invention, in which taper-shaped through holes made in a four-layer board are filled with a solder resist and ball pads and solder balls are mounted on small-diameter side ends.
  • FIG. 6 is an explanatory drawing showing a printed wiring board of the present invention, in which taper-shaped through holes made in a four-layer board are filled by plating and solder balls and solder precoats are mounted on pads formed on both side ends.
  • FIG. 7 is an explanatory drawing showing the wiring state of a printed wiring board having taper-shaped through holes of which the center positions are one-sided from the arrangement of the center positions of other taper-shaped through holes and taper-shaped through holes of which the center positions are not one-sided.
  • FIG. 8 is an explanatory drawing showing the wiring state of a printed wiring board having taper-shaped through holes of which the center positions are one-sided from the arrangement of the center positions of other taper-shaped through holes and taper-shaped through holes of which the center positions are not one-sided.
  • FIG. 9 is an explanatory drawing showing the wiring state of a printed wiring board having taper-shaped through holes of which the center positions are one-sided from the arrangement of the center positions of other taper-shaped through holes and taper-shaped through holes of which the center positions are not one-sided.
  • DETAILED DESCRIPTION OF THE INVENTION
  • The present invention 1 will be explained with reference to FIG. 1. An insulating substrate 1 (FIG. 1(A)) used in the printed wiring board of the present invention is a laminate or a glass-fiber-containing or glass-fabric-containing laminate of an epoxy resin, a cyanate resin, a bismaleimide triazine resin, a polyimide resin, a polyphenylene ether resin, etc. A film-like insulating material can be also used. The insulating material is not specially limited so long as it is an insulating material which is used as a printed wiring board or a semiconductor package. A double-side board or a multilayer board can also be used. As an insulating substrate 1, there may be also used a substrate having conductive layers 2 (FIG. 1 (A)), such as copper foils, on upper and lower surfaces. These materials will be generically called “substrate, etc.” hereinafter.
  • A taper-shaped penetration hole 3 (FIG. 1(B)) is made at a position of a substrate, etc., at which the penetration hole is to be made, and upper and lower surfaces of the insulating substrate of the taper-shaped penetration hole are electrically conducted to each other by a panel plating method (electroless plating 4 and electroplating 5, etc.), to make a through hole 8 and simultaneously seal its small-diameter side end with a plating metal. Thereafter, patterns are formed on the upper and lower surfaces by a known subtractive method. In the formation of the patterns, a ball pad 6 (FIG. 1(E)) is disposed on the taper-shaped through hole portion. Otherwise, patterns are formed by a pattern plating method (additive method, semi-additive method, etc.) and simultaneously the inside of the through hole is plated to electrically connect the upper surface and the lower surface and to plate and seal the small-diameter side end, whereby a ball pad or bump pad is disposed at the through hole portion.
  • The taper-shaped penetration hole is formed by preferably laser processing, more preferably UV-laser processing. When a general cylindrical penetration hole is made in a substrate, etc., with a UV laser, it can be made by overlapping small laser-processing spots, i.e. by trepanning processing, as disclosed in U.S. Pat. No. 5,593,606. On the other hand, the taper-shaped penetration hole of the present invention is made by similar trepanning. It is preferred that a laser energy and the number of shots are selected such that the processing progresses more in the central part of the penetration hole than in a marginal part of the penetration hole, as seen from the upper surface of the substrate, etc. It is preferred to dispose an entry sheet for laser processing or a backup sheet on an upper surface or a lower surface of the substrate, etc., during the processing in view of smooth progress of working. UV laser processing conditions differ depending upon the thickness of a material to be processed or the thickness of a metal conductor, while the processing is carried out by controlling the energy of one shot, positions of shots, the number of shots, the total energy, etc.
  • When a penetration hole is made in a copper-clad laminate with a carbon dioxide gas laser, the penetration hole is made by a method in which a copper foil in a position where the penetration hole is to be made is removed by etching and then the copper-clad laminate is processed by laser irradiation, a method in which a copper surface is treated by blackening treatment or etching treatment and then a laser is irradiated, or a method in which an entry sheet for laser processing is disposed and then a laser is irradiated. For making a taper-shaped penetration hole, it is required to control an irradiation energy, the number of pulses, the diameter of a mask, etc. For avoiding injuring a processing table, a backup sheet for laser processing may be disposed on a laser-outgoing side. A carbon dioxide gas laser and a UV laser may be used in combination in the laser processing. For example, the UV laser may be used for forming an opening of the small-diameter side end after carrying out processing with the carbon dioxide gas laser. As the entry sheet for laser processing or as the backup sheet for laser processing, there may be used an entry sheet or a backup sheet disclosed in JP-A-1999-346059A.
  • The diameter of the small-diameter side end of the taper-shaped penetration hole is preferably 5-70 μm. When the above diameter is smaller than 5 μm, it is difficult to continuously supply a plating solution into the inside of the hole on the small-diameter side in plating processing even when the plating solution is stirred or shaken. Further, even when the small-diameter side end can be sealed with a plating metal, the cross-section area, at the small-diameter part, of a plating layer for electrically connecting an upper conductor and a lower conductor of the insulating substrate becomes small, so that connection reliability decreases. On the other hand, when the above diameter is larger than 70 μm, there occur problems in plating processing for panel plating that the small-diameter side end cannot be sealed or that it is difficult to form a pattern with high accuracy since the thickness of plating becomes too large. Moreover, in a pattern plating method, it is required to use a thick plating resist for increasing the thickness of plating in order to seal the small-diameter side end by plating, so that it is similarly difficult to form a pattern with high accuracy. The opening diameter of the small-diameter side end is more preferably 10 to 50 μm, further more preferably 15 to 40 μm. The diameter of a large-diameter side end is preferably 200 μm at maximum. When it is larger than 200 μm, the diameter of a land becomes large, which prevents densification. In addition, when plating for hole-filling is carried out, the plating takes a long time, which results in a cost increase. The diameter of the large-diameter side end is more preferably 150 μm or less, further more preferably 100 μm or less.
  • The plating processing can be carried out by a general method such as panel plating or pattern plating. The inside of the taper-shaped through hole may be filled and plated by concurrent use of pulse plating. The hole-filling plating of the taper-shaped through hole is suitable when the large-diameter side end of the taper-shaped through hole is used as a ball pad or a bump pad.
  • In the present invention, the inside of the taper-shaped through hole plated and sealed may be covered or filled with an insulating material. A coating composition which is generally called a solder resist can be used as the insulating material. Further, there can be used a thermosetting resin, a UV (ultraviolet) curable resin, a resin curable by UV and heat, etc. These resins may contain an inorganic filler component.
  • After forming patterns on both external surfaces, the solder resist is disposed on both the external surfaces. Generally, the solder resist is disposed such that no solder resist is placed at portions at which a bondfinger pad, a ball pad, a bump pad, a mold gate, etc., are formed. The above portions with no solder resist are properly treated by a surface-treatment such as electrolytic nickel/gold plating, electroless nickel/gold plating, organic rust prevention or a solder precoat, as required. Different surface-treatments between the upper surface and the lower surface can be carried out, as required. Further, a partially different treatment may be carried out as required.
  • A variety of embodiments of the present invention will be explained with reference to FIG. 2 to FIG. 6 hereinafter. FIG. 2 shows an example in which a taper-shaped through hole is filled by plating in the plating step of FIG. 1(D), a bump pad 9 is formed at the small-diameter side end and a ball pad 6 is formed at the large-diameter side end. FIG. 3 shows an embodiment in which a solder ball 10 is mounted on a ball pad 6 at the small-diameter side end of a printed wiring board produced by the step of FIG. 1(F). FIG. 4 shows an embodiment in which a solder precoat 11 is mounted on the bump pad 9 (upper surface) formed at the small-diameter side end of the printed wiring board of FIG. 2 and a solder pad 10 is mounted on the ball pad 6 (lower surface) at the large-diameter side end. FIG. 5 shows an embodiment in which a taper-shaped through hole made in a four-layered board is filled with a solder resist 7 and a solder ball 10 is mounted on a ball pad 6 formed at the small-diameter side end. FIG. 6 shows an embodiment in which a taper-shaped through hole made in a four-layered board is filled by plating and a solder precoat 11 is mounted on a bump pad 9 at the small-diameter side end and a solder ball 10 is mounted on a ball pad 6 at the large-diameter side end.
  • The thus-obtained printed wiring boards are able to be more densified as a package for mounting a semiconductor, so that they have advantages that more terminals can be disposed when an area is the same or an area can be decreased when the number of terminals is the same.
  • In the present invention 2, the center position of a specific taper-shaped through hole of taper-shaped through holes is not disposed at the center of a ball pad or a bump pad but it is disposed one-sidedly from the center positions of the other taper-shaped through holes in file and/or row direction(s). FIG. 7 shows an embodiment in which ball pads are formed at the small-diameter side and the ball pads are disposed in four files (four lines counted from the top). In FIG. 7, the center positions of specific taper-shaped through holes disposed in the center portion are one-sided in the right direction (right figure of FIG. 7). The above one-sided disposition can widen a specific through hole land spacing on the large-diameter side (component side in FIG. 7) and, as a result, the number of wirings locatable at the above space can be increased. In many cases, to increase the number of wirings is not required in all through hole land spacings but is required in a specific through hole land spacing. In such cases, the present invention is effective. The above spacing increase utilizes that the diameter of the small-diameter side of a taper-shaped through hole is small. FIG. 8 shows an embodiment in which ball pads are formed at the small-diameter side ends and the ball pads are disposed in five files. This embodiment is an example in which the center positions of the through holes in the first file from the bond pad side are one-sided to the bond pad side and to the opposite direction side (right figure of FIG. 8), which actualizes an increase in the number of wirings on the component side (on the large-diameter side). The one-sidedness distance of the center position of the taper-shaped through hole is generally within a ball pad or a bump pad. However, even when the center position is disposed outside the pad, the effect of the present invention can be obtained if the center position is located at 100 μm or less outside from the pad end. FIG. 9 shows embodiments in which ball pads are disposed in five files. The right figure of FIG. 9 shows an example in which the one-sidedness of the center position is 100 μm or less. When it exceeds 100 μm, it is required to separately dispose a through hole land. In this case, it is impossible to achieve a high-density wiring in a specific portion, which is the object of the present invention. In FIG. 7, FIG. 8 and FIG. 9, the right figure of FIG. 7, for example, means a figure drawn on the right as one faces the paper.
  • The embodiments shown in FIGS. 7-9 are explained with reference to examples more in detail. FIG. 7 shows embodiments of a chip scale package (CSP) having a line/space={fraction (40/40)}μm, a bond pad width/space={fraction (75/35)}μm, a ball pad diameter of 350 μm, four ball pad files, a ball pad pitch of 400 μm and a through hole land diameter of 160 μm, wherein the large-diameter side end diameter is 80 μm and the small-diameter side end diameter is 20 μm. In the left figure of FIG. 7 showing a general embodiment, there is a wiring 15 which can not secure a wiring connecting a bond pad 13, as a junction with IC, to a through hole 8. In the right figure of FIG. 7 being an embodiment of the present invention, the center positions of through holes 8 in the center portion are one-sided with regard to the center position of the other through hole 8, as shown in the figure, thereby actualizing a wiring 16 in the same line/space rule.
  • FIG. 8 shows embodiments of a chip scale package (CSP) having a line/space={fraction (40/40)}μm, a bond pad width/space={fraction (75/35)}μm, a ball pad diameter of 350 μm, five ball pad files, a ball pad pitch of 500 μm and a through hole land diameter of 160 μm, wherein the large-diameter side end diameter is 80 μm and the small-diameter side end diameter is 20 μm. In the left figure of FIG. 8 showing a general embodiment, there is a wiring 15 which can not connect a bond pad 13 to a through hole 8. In the right figure of FIG. 8 showing an embodiment of the present invention, the center positions of three through holes positioned nearest to the bond pads 13 side are one-sided as shown in the figure, thereby actualizing a wiring 16 in the same line/space rule.
  • FIG. 9 shows embodiments of a chip scale package (CSP) having a line/space={fraction (40/40)}μm, a bond pad width/space={fraction (75/35)}μm, a ball pad diameter of 450 μm, five ball pad files, a ball pad pitch of 500 μm and a through hole land diameter of 160 μm, wherein the large-diameter side end diameter is 80 μm and the small-diameter side end diameter is 20 μm. In the left figure of FIG. 9 showing a general embodiment, there is a wiring 15 which can not connect a bond pad 13 to a through hole 8. In the right figure of FIG. 9 showing an embodiment of the present invention, the center positions of through holes positioned nearest to bond pads are one-sided as shown in the figure, thereby actualizing a wiring 16 in the same line/space rule.
  • The present invention has been explained mainly with regard to a double-side substrate, while a similar design can be actualized with regard to a multilayer substrate. Further, a similar design can be also actualized with regard to flip chip in place of wire bonding, and densification is possible.
  • In the present invention 2, a produced printed wiring board can be more densified as a package for mounting a semiconductor, so that it has advantages that more terminals can be disposed when an area is the same or an area can be decreased when the number of terminals is the same.
  • EFFECT OF THE INVENTION
  • There can be provided a high-densified printed wiring board for mounting a semiconductor by making a taper-shaped through hole of which a side end is sealed and forming a bump pad or a ball pad on the side end of the through hole.
  • In a high-density printed wiring board for mounting a semiconductor provided by making taper-shaped through holes of which side ends are sealed and forming bump pads or ball pads on the side ends of the through holes, the center position of a specific taper-shaped through hole of the above taper-shaped through holes is not positioned at the center of the ball pad or bump pad and is disposed one-sidedly in file and/or row direction(s) from the arrangement of the center positions of the other taper-shaped through holes. The above one-sided disposition of the specific taper-shaped through hole broadens a specific land spacing on the large-diameter side end side of the taper-shaped through hole and increases the number of wirings locatable at the above space, whereby there is provided a higher-densified printed wiring board for mounting a semiconductor.
  • EXAMPLES
  • The present invention will be explained more in detail with reference to Examples hereinafter.
  • Example 1
  • A BT (bismaleimide triazine resin) double-side copper-clad laminate (“CCL-HL832HS”, supplied by Mitsubishi Gas Chemical Company, Inc.) having 3-μm thick copper foils on both surfaces and a 100-m thick glass fabric inserted therein was used as a laminate. A backup sheet (“LSB-90”, supplied by Mitsubishi Gas Chemical Company, Inc.) made of an aluminum foil was bonded to a lower surface of the laminate, and then taper-shaped penetration holes were made in the laminate with an UV laser (“YB-HYS401T01”, supplied by Matsushita Industrial Information Equipment Co., Ltd.). Table 1 shows UV laser processing conditions. The cross-sectional shape of the taper-shaped penetration holes obtained was a conical shape having a small-diameter side end of 20 μm and a large-diameter side end of 80 Mm. Then, copper plating was carried out by electroless plating and electroplating. By controlling an electric current density (5A/dm2 substrate) during the electroplating, an inner wall surface of each taper-shaped through hole was plated to form a copper layer and simultaneously the small-diameter side end thereof was sealed by the plating to connect the copper foils on the upper and lower surfaces to each other, where by taper-shaped through holes were obtained. The thickness of the plating was 15 to 28 μm in the through holes. The cross section thereof was checked. As a result, it was found that the small diameter side ends of the copper-plated taper-shaped through holes were sealed by the copper plating. After the completion of the plating, a pattern formation on both the external surfaces was carried out by a general subtractive method, that is, by using a dry film etching resist and carrying out etching. In the pattern formation, a pattern arrangement was selected such that the small-diameter side ends of the taper-shaped through holes became ball pads. Then, a solder resist (“PSR4000AUS308, supplied by TAIYO INK MFG. CO., LTD.) was applied and dried, and patterns were formed. Finger pad portions on the upper side (component side) and ball pad portions (shape of a solder mask define SMD) on the lower side (ball side) were made to be openings. Then, final curing was carried out. Then, electrolytic nickel/gold plating was carried out through a plating lead to plate the surfaces of the finger pads and the ball pads with gold (See FIG. 1).
    TABLE 1
    UV laser processing conditions (per hole)
    Diameter of Processing
    processing pitch on Total
    Energy track track Number of energy
    Step μJ/pulse μm μm shots μJ
    1 100 30 12 9 900
    2 100 64 8 27 2,700
    3 160 55 18 11 1,760
    4 130 50 15 11 1,430
    5 130 40 15 9 1,170
    6 130 30 15 7 910
    7 160 4 2 7 1,120
    8 160 4 2 7 1,120
  • An epoxy double-side copper-clad laminate (“E679FB”, supplied by Hitachi Chemical Co., Ltd.) having 12-μm thick copper foils on both surfaces and a 100-μm thick glass fabric inserted therein was used as a laminate. The laminate was treated with a hydrogen peroxide/sulfuric acid type soft etching agent (“CPE900”, supplied by Mitsubishi Gas Chemical Company, Inc.), to decrease the thickness of the copper foils on the external layers to 5 μm. Then, taper-shaped through holes were made in the laminate with a UV laser (“YB-HYS401T01, supplied by Matsushita Industrial Information Equipment Co., Ltd.). The UV processing conditions were the same as those in Example 1.
  • Then, pattern plating was carried out. That is, after electroless copper plating, dry film plating resists were disposed on both surfaces of the laminate. The dry films in pattern portions and through hole portions (including ball pads and bump pads) which portions were required to be plated, were removed, and then electroplating was carried out. The above electroplating used a pulsed current, and the through holes were filled by the plating. Then, the dry films were peeled off and then the entire surface was etched with a soft etching solution, to remove the base copper layers and to leave patterns. As a pattern of the pattern plating, bump pads were formed at the through hole small-diameter side ends and ball pads were formed at the large-diameter side ends. After the completion of the pattern plating, a solder resist (“PSR4000AUS308, supplied by TAIYO INK MFG. CO., LTD.) was formed by a general method such that the bump pads and the ball pads became openings. Then, the openings were treated by an organic rust prevention treatment (“GLICOAT-SMD [F2(LX)]”, supplied by SHIKOKU CORPORATION) (see FIG. 2).
  • Example 3
  • A chip size package (CSP) substrate having a design shown in the right figure of FIG. 7, as an arrangement of a pattern, and taper-shaped through holes was prepared as follows.
  • A BT (bismaleimide triazine resin) double-side copper-clad laminate (“CCL-HL832HS “supplied by Mitsubishi Gas Chemical Company, Inc.) having 3-μm thick copper foils on both surfaces and a 100-μm thick glass fabric inserted therein was used as a laminate. A backup sheet (“LSB-90”, supplied by Mitsubishi Gas Chemical Company, Inc.) made of an aluminum foil was bonded to a lower surface of the laminate, and then taper-shaped penetration holes were made in the laminate with an UV laser (“YB-HYS401T01”, supplied by Matsushita Industrial Information Equipment Co., Ltd.). Table 2 shows UV laser processing conditions. The cross-sectional shape of the taper-shaped penetration holes obtained was a conical shape having a small-diameter side end of 20 μm and a large-diameter side end of 80 μm. Then, copper plating was carried out by electroless plating and electroplating. By controlling an electric current density (5A/dm2 substrate) during the electroplating, an inner wall surface of each taper-shaped through hole was plated to form a copper layer and simultaneously the small-diameter side end thereof was sealed by the plating to connect the copper foils on the upper and lower surfaces to each other, whereby taper-shaped through holes were obtained. The thickness of the plating was 15 to 28 μm in the through holes. The cross section thereof was checked. As a result, it was found that the small diameter side ends of the copper-plated taper-shaped through holes were sealed by the copper plating. After the completion of the plating, a pattern formation on both the external surfaces was carried out by a general subtractive method, that is, by using a dry film etching resist and carrying out etching. In the pattern formation, according to the above design, there was adopted a pattern arrangement in which the small-diameter side ends of some of the taper-shaped through holes were located within ball pads respectively but the above small-diameter side ends were not located in the centers of the ball pads. Then, a solder resist (“PSR4000AUS308, supplied by TAIYO INK MFG. CO., LTD.) was applied and dried, and patterns were formed. Bond pad portions on the upper side (component side) and ball pad portions (shape of a solder mask define SMD) on the lower side (ball side) were made to be openings. Then, final curing was carried out. Then, electrolytic nickel/gold plating was carried out through a plating lead to plate the surfaces of the bond pads and the ball pads with gold (See FIG. 1).
    TABLE 2
    UV laser processing conditions (per hole)
    Diameter of Processing
    processing pitch on Total
    Energy track track Number of energy
    Step μJ/pulse μm μm shots μJ
    1 100 30 12 9 900
    2 100 64 8 27 2,700
    3 160 55 18 11 1,760
    4 130 50 15 11 1,430
    5 130 40 15 9 1,170
    6 130 30 15 7 910
    7 160 4 2 7 1,120
    8 160 4 2 7 1,120
  • The taper-shaped through holes having sealed ends were made and the center positions of some of the through holes were one-sided from the center of corresponding pads, whereby there was provided a printed wiring board for mounting a semiconductor, of which the number of wirings was increased, i.e., which was high-densified.

Claims (14)

1. A printed wiring board for mounting a semiconductor, which printed wiring board has a taper-shaped through hole connecting an upper surface circuit and a lower surface circuit, and/or an internal layer circuit,
the taper-shaped through hole being obtained by plating an inner wall surface and a small-diameter side end of a taper-shaped penetration hole with a metal to plate the inner wall surface and seal the small-diameter side end,
wherein a ball pad or a bump pad is formed at at least a small-diameter side end of the taper-shaped through hole.
2. The printed wiring board according to claim 1,
wherein the diameter of the small-diameter side end of the taper-shaped penetration hole is 5 to 70 μm and the diameter of a large-diameter side end of the taper-shaped penetration hole is larger than that of the small-diameter side end by at least 10 μm and is 200 μm at maximum.
3. The printed wiring board according to claim 1,
wherein the taper-shaped penetration hole is made by laser-processing.
4. The printed wiring board according to claim 3,
wherein the laser-processing is UV-laser processing.
5. The printed wiring board according to claim 1,
wherein the plating is carried out by electroless plating, or electroplating and electroless plating or direct plating.
6. The printed wiring board according to claim 1,
wherein the metal used for the plating is at least one metal selected from the group consisting of gold, silver, copper, nickel and palladium.
7. The printed wiring board according to claim 1,
wherein the plated and sealed taper-shaped through hole is filled with an insulating material.
8. The printed wiring board according to claim 1,
wherein a ball pad for connecting a mother board is formed at the plated and sealed small-diameter side end.
9. The printed wiring board according to claim 1,
wherein a bump pad for connecting a semiconductor element is formed at the plated and sealed small-diameter side end.
10. The printed wiring board according to claim 1,
wherein the taper-shaped through hole is filled by plating.
11. The printed wiring board according to claim 1,
wherein the ball pad is formed at one of a large-diameter side end and the small-diameter side end of the taper-shaped through hole and the bump pad is formed at the other end.
12. The printed wiring board according to claim 1,
wherein the ball pad and/or the bump pad are formed by solder mask.
13. A printed wiring board for mounting a semiconductor, comprising a plurality of taper-shaped through holes electrically conducting an upper surface circuit and a lower surface circuit, and ball pads and/or bump pads respectively provided on upper portions and lower portions of the taper-shaped through holes,
the taper-shaped through holes being obtained by plating internal wall surfaces and small-diameter side ends of taper-shaped penetration holes with a metal to plate the internal-wall surfaces and seal the small-diameter side ends,
wherein the center position of at least one through hole of the through holes is one-sided within the ball pad and/or the bump pad corresponding to the at least one through hole or within a peripheral area which is 100 μm or less outside from the edge of the ball pad and/or the bump pad corresponding to the at least one through hole.
14. The printed wiring board according to claim 13,
which has an internal layer circuit and a taper-shaped throughhole electrically connecting the upper surface circuit, the lower surface circuit and the internal layer circuit.
US10/869,857 2003-06-20 2004-06-18 Printed wiring board for mounting semiconductor Abandoned US20050001309A1 (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005006280A1 (en) * 2005-02-10 2006-08-24 Infineon Technologies Ag Semiconductor component with a pressure contact by a housing ground and method for producing the same
US7902660B1 (en) * 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7977163B1 (en) 2005-12-08 2011-07-12 Amkor Technology, Inc. Embedded electronic component package fabrication method
US20110233786A1 (en) * 2010-03-24 2011-09-29 Soichi Homma Semiconductor device and method for manufacturing the same
US8119455B1 (en) 2002-11-08 2012-02-21 Amkor Technology, Inc. Wafer level package fabrication method
US8188584B1 (en) 2002-11-08 2012-05-29 Amkor Technology, Inc. Direct-write wafer level chip scale package
US20120257361A1 (en) * 2011-04-06 2012-10-11 Sony Corporation Display device and electronic apparatus
US20170231092A1 (en) * 2007-06-28 2017-08-10 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG120200A1 (en) 2004-08-27 2006-03-28 Micron Technology Inc Slanted vias for electrical circuits on circuit boards and other substrates
KR100669788B1 (en) * 2004-11-26 2007-01-16 삼성에스디아이 주식회사 Method of forming slope by use of laser ablation technique, method of forming recessed portion, method of manufacturing organic thin film tranasistor, and organic thin film transistor manufactured by the method
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US8062975B2 (en) * 2009-04-16 2011-11-22 Freescale Semiconductor, Inc. Through substrate vias
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Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3787252A (en) * 1968-07-05 1974-01-22 Honeywell Inf Systems Italia Connection means for semiconductor components and integrated circuits
US5065228A (en) * 1989-04-04 1991-11-12 Olin Corporation G-TAB having particular through hole
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5662987A (en) * 1995-02-17 1997-09-02 International Business Machines Corporation Multilayer printed wiring board and method of making same
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6284353B1 (en) * 1997-01-10 2001-09-04 Ibiden Co., Ltd. Printed wiring board and method of manufacturing the same
US20020004982A1 (en) * 1998-09-18 2002-01-17 Takayuki Haze Method for producing a doublesided wiring board
US6340841B2 (en) * 1999-01-25 2002-01-22 Shinko Electric Industries Co., Ltd. Build-up board package for semiconductor devices
US20020180027A1 (en) * 2001-05-31 2002-12-05 Yoshihide Yamaguchi Semiconductor module and method of making the device
US20020185311A1 (en) * 2001-06-07 2002-12-12 Charles Cohn Printed wiring board having a discontinuous plating layer and method of manufacture thereof
US20030178388A1 (en) * 2002-03-22 2003-09-25 Phillips Kenneth L. Inverted micro-vias
US6753600B1 (en) * 2003-01-28 2004-06-22 Thin Film Module, Inc. Structure of a substrate for a high density semiconductor package
US6828510B1 (en) * 1999-06-02 2004-12-07 Ibiden Co., Ltd. Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
US6835294B2 (en) * 2001-06-07 2004-12-28 Shipley Company, L.L.C. Electrolytic copper plating method
US6916873B2 (en) * 2000-11-29 2005-07-12 Taiyo Ink Manufacturning Co., Ltd. Liquid thermosetting resin composition, printed wiring boards and process for their production

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373957A (en) * 2001-06-14 2002-12-26 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
TWI245381B (en) * 2003-08-14 2005-12-11 Via Tech Inc Electrical package and process thereof

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3787252A (en) * 1968-07-05 1974-01-22 Honeywell Inf Systems Italia Connection means for semiconductor components and integrated circuits
US5065228A (en) * 1989-04-04 1991-11-12 Olin Corporation G-TAB having particular through hole
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5662987A (en) * 1995-02-17 1997-09-02 International Business Machines Corporation Multilayer printed wiring board and method of making same
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6284353B1 (en) * 1997-01-10 2001-09-04 Ibiden Co., Ltd. Printed wiring board and method of manufacturing the same
US20020004982A1 (en) * 1998-09-18 2002-01-17 Takayuki Haze Method for producing a doublesided wiring board
US6340841B2 (en) * 1999-01-25 2002-01-22 Shinko Electric Industries Co., Ltd. Build-up board package for semiconductor devices
US6828510B1 (en) * 1999-06-02 2004-12-07 Ibiden Co., Ltd. Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
US6916873B2 (en) * 2000-11-29 2005-07-12 Taiyo Ink Manufacturning Co., Ltd. Liquid thermosetting resin composition, printed wiring boards and process for their production
US20020180027A1 (en) * 2001-05-31 2002-12-05 Yoshihide Yamaguchi Semiconductor module and method of making the device
US20020185311A1 (en) * 2001-06-07 2002-12-12 Charles Cohn Printed wiring board having a discontinuous plating layer and method of manufacture thereof
US6835294B2 (en) * 2001-06-07 2004-12-28 Shipley Company, L.L.C. Electrolytic copper plating method
US20030178388A1 (en) * 2002-03-22 2003-09-25 Phillips Kenneth L. Inverted micro-vias
US6753600B1 (en) * 2003-01-28 2004-06-22 Thin Film Module, Inc. Structure of a substrate for a high density semiconductor package

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9054117B1 (en) 2002-11-08 2015-06-09 Amkor Technology, Inc. Wafer level package and fabrication method
US9406645B1 (en) 2002-11-08 2016-08-02 Amkor Technology, Inc. Wafer level package and fabrication method
US8501543B1 (en) 2002-11-08 2013-08-06 Amkor Technology, Inc. Direct-write wafer level chip scale package
US8486764B1 (en) 2002-11-08 2013-07-16 Amkor Technology, Inc. Wafer level package and fabrication method
US9871015B1 (en) 2002-11-08 2018-01-16 Amkor Technology, Inc. Wafer level package and fabrication method
US8952522B1 (en) 2002-11-08 2015-02-10 Amkor Technology, Inc. Wafer level package and fabrication method
US8119455B1 (en) 2002-11-08 2012-02-21 Amkor Technology, Inc. Wafer level package fabrication method
US8188584B1 (en) 2002-11-08 2012-05-29 Amkor Technology, Inc. Direct-write wafer level chip scale package
US8691632B1 (en) 2002-11-08 2014-04-08 Amkor Technology, Inc. Wafer level package and fabrication method
US8298866B1 (en) 2002-11-08 2012-10-30 Amkor Technology, Inc. Wafer level package and fabrication method
US10665567B1 (en) 2002-11-08 2020-05-26 Amkor Technology, Inc. Wafer level package and fabrication method
US8710649B1 (en) 2002-11-08 2014-04-29 Amkor Technology, Inc. Wafer level package and fabrication method
DE102005006280B4 (en) * 2005-02-10 2006-11-16 Infineon Technologies Ag Semiconductor component with a through-contact by a housing ground and method for producing the same
DE102005006280A1 (en) * 2005-02-10 2006-08-24 Infineon Technologies Ag Semiconductor component with a pressure contact by a housing ground and method for producing the same
US20060189124A1 (en) * 2005-02-10 2006-08-24 Gottfried Beer Semiconductor device having a through contact through a housing composition and method for producing the same
US7977163B1 (en) 2005-12-08 2011-07-12 Amkor Technology, Inc. Embedded electronic component package fabrication method
US7902660B1 (en) * 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US20170231092A1 (en) * 2007-06-28 2017-08-10 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
US10306760B2 (en) * 2007-06-28 2019-05-28 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
US20110233786A1 (en) * 2010-03-24 2011-09-29 Soichi Homma Semiconductor device and method for manufacturing the same
US20120257361A1 (en) * 2011-04-06 2012-10-11 Sony Corporation Display device and electronic apparatus
US9715152B2 (en) * 2011-04-06 2017-07-25 Sony Corporation Display device and electronic apparatus

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US20070173135A1 (en) 2007-07-26
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TWI336220B (en) 2011-01-11
KR20040111198A (en) 2004-12-31

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