US20040266037A1 - Direct chip attach structure and method - Google Patents
Direct chip attach structure and method Download PDFInfo
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- US20040266037A1 US20040266037A1 US10/603,258 US60325803A US2004266037A1 US 20040266037 A1 US20040266037 A1 US 20040266037A1 US 60325803 A US60325803 A US 60325803A US 2004266037 A1 US2004266037 A1 US 2004266037A1
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Definitions
- This invention relates, in general, to electronic device packaging, and more specifically to a structure and method for forming reliable interconnects in flip-chip type electronic packages.
- Semiconductor chips usually are encapsulated in a device package prior to installation into an electronic system.
- Device or chip packages perform several key functions including, a) interconnective leads that allow the chip to be connected to the electronic system; b) physical protection; c) environmental protection; and d) heat dissipation. These functions present chipmakers with a number of design and manufacturing challenges that must be balanced with other factors such as cost.
- Flip-chip packaging is one type of electronic chip packaging technology, and has been in existence for more than 30 years. Flip-chip packaging has progressed to include a wide variety of materials and methods for bumping, attaching and underfilling devices. Although the technology has progressed, challenges still exist in solving problems with higher frequency applications, tighter space requirements, reduced costs, and general device performance.
- DCA direct chip attach
- PCB printed circuit board
- flex circuit a circuit such as a printed circuit board (PCB) or a flex circuit.
- metal studs such as gold studs are attached to the chip, and the structure is then encapsulated with a passivation material or mold compound.
- openings are formed in the mold compound to expose the metal studs, and solder balls or bumps are then attached through the openings to provide contacts to the encapsulated chip.
- the solder bumps on the DCA device are then attached to the printed circuit board, flex circuit, or next level of assembly.
- solder ball/metal stud interface One problem with current DCA structures occurs at the solder ball/metal stud interface.
- the solder ball comprises a lead/tin alloy and the metal stud comprises gold
- the gold tends to dissolve into the solder ball over time. This creates a gap between the gold stud and the solder ball, which leads to poor contact and weak joints. The poor contact and weak joints results in device reliability and performance problems.
- FIG. 1 illustrates, an enlarged cross-sectional view of a direct chip attach device according to the present invention
- FIGS. 2-5 illustrate, enlarged cross-sectional views of the direct chip attach device of FIG. 1 at various stages of fabrication
- FIG. 6 illustrates, a side-view of an apparatus according to the present invention for forming the direct chip attach device of FIG. 1.
- the present invention provides a direct chip attach (DCA) structure that includes a barrier layer formed between a conductive stud and a solder bump.
- DCA direct chip attach
- the barrier layer comprises nickel.
- the present invention provides a method for forming a DCA structure having a barrier layer.
- an electronic chip is attached to a lead frame structure and a conductive stud is attached to a bond pad on a surface of the chip.
- the lead frame substrate and electronic chip are then encapsulated in, for example, a mold cavity.
- openings are formed in the encapsulating material to expose the conductive stud.
- a barrier layer is then deposited on the conductive stud.
- a solder ball is attached to the barrier layer.
- an electroless nickel barrier layer is formed by immersing the structure in an electroless nickel plating bath, forcing a stream of plating solution onto the surface of the structure to enhance deposition of the barrier layer.
- agitation is used to enhance deposition in the electroless plating bath.
- FIGS. 1-6 The present invention is better understood by referring to FIGS. 1-6 together with the following detailed description. For ease of understanding, like elements or regions are labeled the same throughout the detailed description and FIGURES.
- FIG. 1 shows an enlarged cross-sectional view of a direct chip attach (DCA) device 1 according to the present invention.
- DCA device 1 includes a lead frame or support substrate 2 and an electronic chip, device or component 3 .
- Chip 3 includes bond pads or contacts 13 on an upper or outer surface 14 .
- Chip 3 is attached to lead frame 2 with a die attach layer 17 .
- Lead frame 2 further includes a flag 18 , which provides an upper or topside contact to lower surface 19 of chip 3 .
- chip 3 comprises a power MOSFET device for example
- contacts 13 form source contacts
- flag 18 forms a topside drain or drain contact.
- DCA device 1 also includes conductive bumps, balls, or studs 22 , which are attached to contacts 13 .
- a conductive stud 22 is also attached to flag 18 .
- a barrier layer 24 is formed on an upper, bonding, or exposed surface of studs 22 .
- Barrier layer 24 comprises a material that is, metallurgically compatible with studs 22 and solder bumps 9 , and that prevents the elements or components of studs 22 and solder balls 9 from diffusing, inter-mixing or dissolving into each other.
- barrier layer 24 preferably comprises a nickel layer.
- barrier layer 41 is approximately 2 microns to approximately 7 microns thick.
- DCA device 1 further includes an encapsulant or protective layer 4 covering chip 3 and flag 18 .
- Protective layer 4 has openings 6 formed in an upper or major surface 7 .
- Solder or conductive balls, spheres, or bumps 9 are coupled to chip 3 and lead frame 2 through or in openings 6 .
- FIG. 2 illustrates an enlarged cross-sectional view of DCA device 1 at an early stage of fabrication.
- chip 3 is attached to lead frame 2 using conventional die attach processes such as eutectic die attach, conductive epoxies or soft solder processes to form a die attach layer 17 .
- chip 3 is attached using a lead/tin (Pb/Sn) soft solder process.
- chip 3 comprises a power MOSFET, logic, sensor device, passive device, or bipolar device.
- Chip 3 includes bond pads or contacts 13 on an upper surface 14 .
- Bond pads 13 comprise, for example, aluminum/aluminum-silicon/aluminum-silicon-copper multi-layer structure.
- Lead frame 2 including flag 18 preferably comprises copper, a copper alloy (e.g., TOMAC 4, TAMAC 5, 2ZFROFC, or CDA194), a copper plated iron/nickel alloy (e.g., copper plated Alloy 42), or the like.
- conductive studs 22 are attached to bond pads 13 .
- a conductive stud 22 is also attached to flag 18 .
- the height of flag 18 is designed to match the height of conductive studs 22 and bond pads 13 , and a stud 22 is not placed on flag 18 .
- Conductive studs 22 are attached using, for example, ultrasonic, thermocompression, or thermosonic bonding techniques.
- Conductive studs 22 comprise, for example, gold or copper.
- conductive studs 22 are formed with wire bond balls using conventional wiring bonding techniques. Preferably, any remaining portion of wire above the wire bond ball is removed, which leaves only conductive studs 22 on bond pads 13 and flag 18 as shown in FIG. 3.
- conductive studs 22 are formed using solder balls that are reflowed for electrical and mechanical attachment to bond pads 13 and flag 18 .
- conductive studs 22 are formed using conductive epoxies.
- conductive studs 22 have a height from about 75 microns to about 1,500 microns.
- FIG. 4 shows an enlarged cross-sectional view of DCA device 1 after an encapsulation step to form protective layer 4 , and after the formation of openings 6 .
- chip 3 and lead frame 2 are encapsulated using conventional transfer molding techniques.
- Protective layer 4 comprises, for example, an epoxy novolac-based resin.
- encapsulant 4 is post-cured, and openings 6 are then formed using chemical etching or laser burning techniques to expose upper surfaces of conductive studs 22 .
- openings 6 are formed in-situ during the molding process using pins that contact studs 22 to prevent molding compound from covering the upper surfaces of studs 22 .
- a sub-assembly 41 is formed.
- FIG. 5 shows an enlarged cross-sectional view of DCA device 1 or sub-assembly 41 at a next step of fabrication where a masking layer 51 is formed over lead frame 2 .
- a masking layer 51 prevents conductive material from depositing on lead frame 2 . That is, masking layer 51 provides a more efficient process whereby conductive material preferentially deposits on studs 22 in openings 6 and not on lead frame 2 .
- masking layer 51 is preferred with commercially available electroless nickel plating solutions, such as NiPlate BP100000M, BP100000S, or BP R(available from Shipley-Ronan) in order to achieve more optimum nickel deposition rates on gold conductive studs.
- Masking layer 51 preferably comprises an adhesive lead frame tape, a polyester film such as Mylar®, or other adhesive polymer films.
- conductive studs 22 depositing barrier materials on conductive studs 22 is challenging due to an electric double layer that forms when DCA device 1 is placed in a electroless plating solution.
- An electric double layer occurs at the interface between an electrode (e.g., conductive stud 22 ) and an electrolyte solution that is created by charge-charge interaction (i.e., charge separation). This leads to an alignment of oppositely charged ions at the surface of the electrode.
- the electric double layer has a thickness that can impede or slow the deposition process.
- FIG. 6 illustrates a side view of a preferred plating apparatus 61 according to the present invention for overcoming the challenges set forth above.
- Plating apparatus 61 includes a bath 63 containing a plating solution 71 , a jetting, pumping or injecting device 66 , and an agitating or mixing device 68 . While DCA device 1 is placed in bath 63 , plating solution 71 is injected or forced towards openings 6 through injecting device 66 as illustrated by flow lines 73 .
- Injecting device 66 comprises, for example, a pump 76 having an inlet 77 and an outlet 78 (shown in phantom), a manifold 79 (shown in phantom), and nozzles 81 .
- Nozzles 81 are placed to direct plating solution 71 towards or directly to openings 6 of DCA device 1 .
- nozzles 81 each have an orifice or opening with a diameter of approximately 1 to 3 mm to provide a solid stream of plating solution. Although 3 nozzles 81 are shown, more or less can be used depending on the characteristics of the device (e.g., geometries, materials, sizes, etc.) being plated.
- pump 76 may be external to bath 63 with inlet 77 and outlet 78 extended to couple pump 76 to bath 63 and manifold 79 .
- injecting device 61 helps overcome the impact of the small dimensions of openings 6 on the formation of barrier layer 24 . Also, injecting device 61 functions to reduce the thickness of the electric double layer, and thereby increase the concentration gradient of the material being deposited (e.g., nickel) on conductive studs 22 in the region near conductive studs 22 (i.e., the interface layer between plating solution 71 and conductive studs 22 ). This in turn enhances barrier layer 24 growth rates.
- the material being deposited e.g., nickel
- plating device 61 alternatively or further includes an agitating device 68 .
- Agitating device comprises, for example, a mechanical stirring device, a magnetic stirring device, or the like.
- Agitating device 68 functions to agitate plating solution 71 as indicated by flow lines 76 , and further enhances the deposition rate during the formation of barrier layer 24 .
- plating solution 71 e.g., NiPlate BP100000M, BP100000, or BP R available from Shipley-Ronan
- injection device 66 preferably provides a flow rate of plating solution 71 of approximately 19 to 38 liters/min.
- agitation device 68 rotates at approximately 80 to 100 rotations per minute (rpm). The above parameters, consumables, and conditions produce, for example, a nickel growth rate of approximately 0.25 microns per minute.
- electrolytic plating techniques may be used to form barrier layer 24 when chip 3 comprises a device that can pass or conduct current during the plating process.
- electrolytic plating techniques can be used when chip 3 comprises a diode device that passes current in a forward bias mode during plating.
- an improved DCA device structure having a barrier layer formed between a conductive stud and a solder bump.
- the barrier layer prevents elements of the conductive stud and solder bump from inter-mixing thereby avoiding the formation of voids and gaps. This improves interconnect integrity and device performance and reliability. Additionally, a method and apparatus for forming the barrier layer has been described that is cost effective and reproducible, and overcomes the shortcomings of conventional electroless plating techniques.
Abstract
Description
- This invention relates, in general, to electronic device packaging, and more specifically to a structure and method for forming reliable interconnects in flip-chip type electronic packages.
- Semiconductor chips usually are encapsulated in a device package prior to installation into an electronic system. Device or chip packages perform several key functions including, a) interconnective leads that allow the chip to be connected to the electronic system; b) physical protection; c) environmental protection; and d) heat dissipation. These functions present chipmakers with a number of design and manufacturing challenges that must be balanced with other factors such as cost.
- Flip-chip packaging is one type of electronic chip packaging technology, and has been in existence for more than 30 years. Flip-chip packaging has progressed to include a wide variety of materials and methods for bumping, attaching and underfilling devices. Although the technology has progressed, challenges still exist in solving problems with higher frequency applications, tighter space requirements, reduced costs, and general device performance.
- Current flip-chip package designs for semiconductor components include direct chip attach (DCA) structures. DCA refers to the direct attachment of an electronic chip to a circuit such as a printed circuit board (PCB) or a flex circuit. In typical DCA structures, metal studs such as gold studs are attached to the chip, and the structure is then encapsulated with a passivation material or mold compound. Next, openings are formed in the mold compound to expose the metal studs, and solder balls or bumps are then attached through the openings to provide contacts to the encapsulated chip. The solder bumps on the DCA device are then attached to the printed circuit board, flex circuit, or next level of assembly.
- One problem with current DCA structures occurs at the solder ball/metal stud interface. For example, when the solder ball comprises a lead/tin alloy and the metal stud comprises gold, the gold tends to dissolve into the solder ball over time. This creates a gap between the gold stud and the solder ball, which leads to poor contact and weak joints. The poor contact and weak joints results in device reliability and performance problems.
- Accordingly, a need exists for more reliable DCA structures. Additionally, a need exists for a cost effective and reproducible method of forming a more reliable DCA structure.
- FIG. 1 illustrates, an enlarged cross-sectional view of a direct chip attach device according to the present invention;
- FIGS. 2-5 illustrate, enlarged cross-sectional views of the direct chip attach device of FIG. 1 at various stages of fabrication; and
- FIG. 6 illustrates, a side-view of an apparatus according to the present invention for forming the direct chip attach device of FIG. 1.
- In general, the present invention provides a direct chip attach (DCA) structure that includes a barrier layer formed between a conductive stud and a solder bump. In a preferred embodiment, the barrier layer comprises nickel.
- In addition, the present invention provides a method for forming a DCA structure having a barrier layer. In particular, an electronic chip is attached to a lead frame structure and a conductive stud is attached to a bond pad on a surface of the chip. The lead frame substrate and electronic chip are then encapsulated in, for example, a mold cavity. Next, openings are formed in the encapsulating material to expose the conductive stud. A barrier layer is then deposited on the conductive stud. Next, a solder ball is attached to the barrier layer.
- In a preferred embodiment, an electroless nickel barrier layer is formed by immersing the structure in an electroless nickel plating bath, forcing a stream of plating solution onto the surface of the structure to enhance deposition of the barrier layer. Alternatively or additionally, agitation is used to enhance deposition in the electroless plating bath.
- The present invention is better understood by referring to FIGS. 1-6 together with the following detailed description. For ease of understanding, like elements or regions are labeled the same throughout the detailed description and FIGURES.
- FIG. 1 shows an enlarged cross-sectional view of a direct chip attach (DCA)
device 1 according to the present invention.DCA device 1 includes a lead frame orsupport substrate 2 and an electronic chip, device orcomponent 3.Chip 3 includes bond pads orcontacts 13 on an upper orouter surface 14.Chip 3 is attached tolead frame 2 with adie attach layer 17. -
Lead frame 2 further includes aflag 18, which provides an upper or topside contact tolower surface 19 ofchip 3. Whenchip 3 comprises a power MOSFET device for example, contacts 13 form source contacts, andflag 18 forms a topside drain or drain contact. -
DCA device 1 also includes conductive bumps, balls, orstuds 22, which are attached tocontacts 13. In a preferred embodiment, aconductive stud 22 is also attached toflag 18. - According to the present invention, a
barrier layer 24 is formed on an upper, bonding, or exposed surface ofstuds 22.Barrier layer 24 comprises a material that is, metallurgically compatible withstuds 22 andsolder bumps 9, and that prevents the elements or components ofstuds 22 andsolder balls 9 from diffusing, inter-mixing or dissolving into each other. For example, whenstuds 22 comprise gold andsolder balls 9 comprise a lead/tin alloy,barrier layer 24 preferably comprises a nickel layer. Preferably,barrier layer 41 is approximately 2 microns to approximately 7 microns thick. By preventing the elements ofconductive studs 22 andsolder balls 9 from inter-mixing and forming gaps or voids in the interconnect structure,barrier layer 24 provides a DCA device that has a more reliable interconnect structure. -
DCA device 1 further includes an encapsulant orprotective layer 4 coveringchip 3 andflag 18.Protective layer 4 hasopenings 6 formed in an upper ormajor surface 7. Solder or conductive balls, spheres, orbumps 9 are coupled tochip 3 andlead frame 2 through or inopenings 6. - Turning now to FIGS. 2-5, a preferred method for forming
DCA device 1 is described. FIG. 2 illustrates an enlarged cross-sectional view ofDCA device 1 at an early stage of fabrication. In this step,chip 3 is attached to leadframe 2 using conventional die attach processes such as eutectic die attach, conductive epoxies or soft solder processes to form a dieattach layer 17. For example,chip 3 is attached using a lead/tin (Pb/Sn) soft solder process. - By way of example,
chip 3 comprises a power MOSFET, logic, sensor device, passive device, or bipolar device.Chip 3 includes bond pads orcontacts 13 on anupper surface 14.Bond pads 13 comprise, for example, aluminum/aluminum-silicon/aluminum-silicon-copper multi-layer structure.Lead frame 2 includingflag 18 preferably comprises copper, a copper alloy (e.g., TOMAC 4, TAMAC 5, 2ZFROFC, or CDA194), a copper plated iron/nickel alloy (e.g., copper plated Alloy 42), or the like. - Next, as shown in FIG. 3,
conductive studs 22 are attached tobond pads 13. In a preferred embodiment, aconductive stud 22 is also attached toflag 18. In an alternative embodiment, the height offlag 18 is designed to match the height ofconductive studs 22 andbond pads 13, and astud 22 is not placed onflag 18. -
Conductive studs 22 are attached using, for example, ultrasonic, thermocompression, or thermosonic bonding techniques.Conductive studs 22 comprise, for example, gold or copper. In one embodiment,conductive studs 22 are formed with wire bond balls using conventional wiring bonding techniques. Preferably, any remaining portion of wire above the wire bond ball is removed, which leaves onlyconductive studs 22 onbond pads 13 andflag 18 as shown in FIG. 3. - Alternatively,
conductive studs 22 are formed using solder balls that are reflowed for electrical and mechanical attachment tobond pads 13 andflag 18. In a further embodiment,conductive studs 22 are formed using conductive epoxies. Preferably,conductive studs 22 have a height from about 75 microns to about 1,500 microns. - FIG. 4 shows an enlarged cross-sectional view of
DCA device 1 after an encapsulation step to formprotective layer 4, and after the formation ofopenings 6. Preferably,chip 3 andlead frame 2 are encapsulated using conventional transfer molding techniques.Protective layer 4 comprises, for example, an epoxy novolac-based resin. After the molding process,encapsulant 4 is post-cured, andopenings 6 are then formed using chemical etching or laser burning techniques to expose upper surfaces ofconductive studs 22. Alternatively,openings 6 are formed in-situ during the molding process using pins that contactstuds 22 to prevent molding compound from covering the upper surfaces ofstuds 22. At this stage of fabrication, a sub-assembly 41 is formed. - FIG. 5 shows an enlarged cross-sectional view of
DCA device 1 orsub-assembly 41 at a next step of fabrication where amasking layer 51 is formed overlead frame 2. Whenbarrier layer 24 is deposited using electroless plating techniques, maskinglayer 51 prevents conductive material from depositing onlead frame 2. That is, maskinglayer 51 provides a more efficient process whereby conductive material preferentially deposits onstuds 22 inopenings 6 and not onlead frame 2. - In particular, the authors found that when
conductive studs 22 comprise gold andlead frame 2 comprises copper, maskinglayer 51 is preferred with commercially available electroless nickel plating solutions, such as NiPlate BP100000M, BP100000S, or BP R(available from Shipley-Ronan) in order to achieve more optimum nickel deposition rates on gold conductive studs. Maskinglayer 51 preferably comprises an adhesive lead frame tape, a polyester film such as Mylar®, or other adhesive polymer films. - Additionally, because
openings 6 in some DCA devices have very small diameter, on the order of 0.2 to 0.5 millimeters (mm) wide, the authors further found that conventional electroless plating techniques were insufficient for formingbarrier layer 24. Specifically, conventional techniques, where devices are simply immersed an electroless bath, are inadequate because deposition rates are far too slow and inconsistent. - Additionally, depositing barrier materials on
conductive studs 22 is challenging due to an electric double layer that forms whenDCA device 1 is placed in a electroless plating solution. An electric double layer occurs at the interface between an electrode (e.g., conductive stud 22) and an electrolyte solution that is created by charge-charge interaction (i.e., charge separation). This leads to an alignment of oppositely charged ions at the surface of the electrode. The electric double layer has a thickness that can impede or slow the deposition process. - Accordingly, FIG. 6 illustrates a side view of a
preferred plating apparatus 61 according to the present invention for overcoming the challenges set forth above.Plating apparatus 61 includes abath 63 containing aplating solution 71, a jetting, pumping or injectingdevice 66, and an agitating or mixingdevice 68. WhileDCA device 1 is placed inbath 63, platingsolution 71 is injected or forced towardsopenings 6 through injectingdevice 66 as illustrated byflow lines 73. - Injecting
device 66 comprises, for example, apump 76 having aninlet 77 and an outlet 78 (shown in phantom), a manifold 79 (shown in phantom), andnozzles 81.Nozzles 81 are placed todirect plating solution 71 towards or directly toopenings 6 ofDCA device 1. Preferably,nozzles 81 each have an orifice or opening with a diameter of approximately 1 to 3 mm to provide a solid stream of plating solution. Although 3nozzles 81 are shown, more or less can be used depending on the characteristics of the device (e.g., geometries, materials, sizes, etc.) being plated. Additionally, pump 76 may be external tobath 63 withinlet 77 andoutlet 78 extended to couplepump 76 tobath 63 andmanifold 79. - By forcing
plating solution 71 towardsopenings 6, injectingdevice 61 helps overcome the impact of the small dimensions ofopenings 6 on the formation ofbarrier layer 24. Also, injectingdevice 61 functions to reduce the thickness of the electric double layer, and thereby increase the concentration gradient of the material being deposited (e.g., nickel) onconductive studs 22 in the region near conductive studs 22 (i.e., the interface layer between platingsolution 71 and conductive studs 22). This in turn enhancesbarrier layer 24 growth rates. - As shown in FIG. 6, plating
device 61 alternatively or further includes an agitatingdevice 68. Agitating device comprises, for example, a mechanical stirring device, a magnetic stirring device, or the like. Agitatingdevice 68 functions to agitateplating solution 71 as indicated byflow lines 76, and further enhances the deposition rate during the formation ofbarrier layer 24. - To provide uniform barrier layers24, plating solution 71 (e.g., NiPlate BP100000M, BP100000, or BP R available from Shipley-Ronan) is maintained for example, at a process temperature of approximately 85 to 95 degrees Celsius during plating. Also,
injection device 66 preferably provides a flow rate of platingsolution 71 of approximately 19 to 38 liters/min. Additionally,agitation device 68 rotates at approximately 80 to 100 rotations per minute (rpm). The above parameters, consumables, and conditions produce, for example, a nickel growth rate of approximately 0.25 microns per minute. - Although an electroless plating process has been described, electrolytic plating techniques may be used to form
barrier layer 24 whenchip 3 comprises a device that can pass or conduct current during the plating process. For example, electrolytic plating techniques can be used whenchip 3 comprises a diode device that passes current in a forward bias mode during plating. - Thus it is apparent that there has been provided, in accordance with the present invention, an improved DCA device structure having a barrier layer formed between a conductive stud and a solder bump. The barrier layer prevents elements of the conductive stud and solder bump from inter-mixing thereby avoiding the formation of voids and gaps. This improves interconnect integrity and device performance and reliability. Additionally, a method and apparatus for forming the barrier layer has been described that is cost effective and reproducible, and overcomes the shortcomings of conventional electroless plating techniques.
- Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.
Claims (21)
Priority Applications (4)
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US10/603,258 US6835580B1 (en) | 2003-06-26 | 2003-06-26 | Direct chip attach structure and method |
TW093116592A TWI337771B (en) | 2003-06-26 | 2004-06-09 | Direct chip attach structure and method |
CNB2004100600702A CN100483695C (en) | 2003-06-26 | 2004-06-25 | Direct chip attach structure and method |
HK05106264.1A HK1073722A1 (en) | 2003-06-26 | 2005-07-22 | Direct chip attach structure and method |
Applications Claiming Priority (1)
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US10/603,258 US6835580B1 (en) | 2003-06-26 | 2003-06-26 | Direct chip attach structure and method |
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US6835580B1 US6835580B1 (en) | 2004-12-28 |
US20040266037A1 true US20040266037A1 (en) | 2004-12-30 |
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US10/603,258 Expired - Lifetime US6835580B1 (en) | 2003-06-26 | 2003-06-26 | Direct chip attach structure and method |
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CN (1) | CN100483695C (en) |
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DE102007002157A1 (en) * | 2007-01-15 | 2008-07-17 | Infineon Technologies Ag | Semiconductor arrangement e.g. flap-ship-suitable power semiconductor arrangement, has drain-contact-soldering ball electrically connected with electrode plating, and source and gate soldering balls connected source and gate contact layers |
US20080251903A1 (en) * | 2007-04-16 | 2008-10-16 | Infineon Technologies Ag | Semiconductor module |
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US20110198743A1 (en) * | 2010-02-16 | 2011-08-18 | Ivan Nikitin | Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device |
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IT201800020998A1 (en) * | 2018-12-24 | 2020-06-24 | St Microelectronics Srl | Process for manufacturing semiconductor devices and corresponding semiconductor device |
US11056458B2 (en) | 2018-11-29 | 2021-07-06 | Infineon Technologies Ag | Package comprising chip contact element of two different electrically conductive materials |
IT202000032267A1 (en) * | 2020-12-23 | 2022-06-23 | St Microelectronics Srl | ENCAPSULATED ELECTRONIC DEVICE WITH HIGH THERMAL DISSIPATION AND RELATED MANUFACTURING PROCEDURE |
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IT202000032267A1 (en) * | 2020-12-23 | 2022-06-23 | St Microelectronics Srl | ENCAPSULATED ELECTRONIC DEVICE WITH HIGH THERMAL DISSIPATION AND RELATED MANUFACTURING PROCEDURE |
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Also Published As
Publication number | Publication date |
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US6835580B1 (en) | 2004-12-28 |
CN1577817A (en) | 2005-02-09 |
CN100483695C (en) | 2009-04-29 |
TW200509332A (en) | 2005-03-01 |
TWI337771B (en) | 2011-02-21 |
HK1073722A1 (en) | 2005-10-14 |
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