US20040257879A1 - Method of programming and erasing a non-volatile semiconductor memory - Google Patents
Method of programming and erasing a non-volatile semiconductor memory Download PDFInfo
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- US20040257879A1 US20040257879A1 US10/462,654 US46265403A US2004257879A1 US 20040257879 A1 US20040257879 A1 US 20040257879A1 US 46265403 A US46265403 A US 46265403A US 2004257879 A1 US2004257879 A1 US 2004257879A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000003491 array Methods 0.000 claims abstract description 10
- 230000001174 ascending effect Effects 0.000 claims abstract description 9
- 238000013500 data storage Methods 0.000 claims abstract description 9
- 238000009413 insulation Methods 0.000 claims abstract description 6
- 230000005689 Fowler Nordheim tunneling Effects 0.000 claims description 7
- 230000001186 cumulative effect Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 description 25
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
- G11C11/5635—Erasing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
Definitions
- the present invention relates to a method of programming and erasing a non-volatile semiconductor memory, in particular to a method of operating the flash memory that is capable of supporting multi-level data storage with enhanced conductivity and without noise disturbance.
- the structure of a memory cell ( 70 ) in a conventional NAND flash memory, as shown in FIG. 1, comprises:
- the stacked gate ( 80 ) is built with a control gate ( 78 ), three successive insulation layers ( 82 , 84 , 86 ) of silicon oxide, silicon nitride and silicon oxide respectively, and a floating gate ( 88 ).
- the above-mentioned memory cell ( 70 ) of the NAND flash memory still has several shortcomings:
- FIG. 2 shows a cross-section of the memory cells ( 70 ) of a NAND memory built in the form of a memory array
- FIG. 3 shows an equivalent circuit for the memory array ( 700 ).
- all memory cells ( 70 ) are formed on top of the same p-well ( 72 ) which is formed by an n-source ( 74 ) or an n-drain ( 76 ), and the diffusion region over the p-well is connected to a bit line (BL).
- BL bit line
- a bit line voltage (V BL ) is applied over the bit line (BL), and a word line voltage (V WL ) is simultaneously applied on a predetermined word line (WL) in order to induce FN tunneling for writing into a predetermined memory cell ( 70 a ). Since the selected memory cells ( 70 a ) and the non-selected memory cells ( 70 b ) are all located above a common p-well ( 72 ), the voltage applied on selected memory cells ( 70 a ) will affect other memory cells ( 70 b ) down the line sharing the same word line (WL) as a result of the FN tunnel effect. The original status of the non-selected memory cell ( 70 b ) therefore will be seriously affected. Thus, the selectivity and the efficiency of such programming/erasing operations are in question.
- the structure of the memory device includes:
- STI shallow trench insulation
- bit lines disposed on the p-substrate ( 32 ) and extending downward to the shallow p-well ( 36 ) through a conductive plug ( 40 ).
- the shallow p-well ( 36 ) forms a common electrode of the memory cell arrays (M). Since a shallow p-well ( 36 ) is connected to a bit line (BL) through a conductive plug ( 40 ), this design is equivalent to a buried bit line.
- a 5V positive voltage pulse is applied on a predetermined bit line (BL), and a 10V negative voltage is simultaneously applied on the word line of the selected memory cell to create the FN tunnel effect.
- a new operation mode has been proposed along with the above-mentioned NAND flash memory.
- a negative voltage is applied on the word line (WL) of a selected memory cell in the programming operation (PGM)
- a positive voltage is applied on the word line (WL) of a selected memory cell in the erasing operation (ERS)
- PGM programming operation
- ERS erasing operation
- FIG. 6 in which a positive voltage pulse is used for PGM, whilst a negative voltage pulse is for ERS. It is noted that this operation mode can support multi-level storage on the above-mentioned flash memory.
- FIG. 7 shows the distribution of a threshold voltage (Vth) for conventional flash memory cells, in which the erasing operation (ERS) is done using the negative voltage range, and the programming with multi-level storage using the positive voltage range.
- Vth threshold voltage
- the positive voltage range is provided with 1-3V for the multi-level data storage, this means there will be only a narrow pulse width allowance for each type of data stored in the same cell.
- Vth the pass gate voltage
- the pass gate voltage (Vpass) is also increased proportionally to maintain the proper potential for the FN tunneling.
- the increased pass gate voltage (Vpass) entails more power consumption, which is obviously counter to the present design trend of low-power memory devices.
- the disclosure of the above-mentioned pattern application can solve the apparent dilemma.
- the pulse width of the threshold voltage (Vth) should be suitably restrained for the use of positive voltages in erasing, in order to avoid the concomitant increase of pass gate voltage (Vpass) along with the threshold voltage (Vth).
- the main object of the present invention is to provide a method of operating a flash memory with multi-level data storage to enhance conductivity and prevent noise disturbance.
- the threshold voltages (Vth) for such memory operations on the flash memory are defined, such that the threshold voltage (Vth) for erasing (ERS) occurs in the positive voltage range, whilst the programming (PGM) with multi-level data storage occurs in the negative voltage range. Since the threshold voltages (Vth) for multi-level data storage are defined in the negative voltage range, the voltage difference between the floating gate and the shallow p-well can be suitably increased to create a larger gate drive for higher pass gate voltage (Vpass) having enhanced conductivity and without noise disturbance.
- a self-limiting means is started along with the erasing operation to prevent the continuous ascending of threshold voltage as the erasing is in progress (i.e. the increase in cumulative time). It is known that a continuous ascending threshold voltage (Vth) will adversely affect the efficiency of the erasing operation (ERS) in progress.
- the architecture of the above-mentioned flash memory comprises:
- a plurality of shallow trench insulation (STI) layers being disposed over the first conductivity substrate and in between several shallow ion wells for mutual isolation of memory cell arrays;
- bit lines being disposed on the first conductivity substrate and extending downward to the shallow ion wells through respective conductive plugs;
- each memory cell array is formed by a plurality of memory cells, of which one end is connected to a selection transistor;
- each memory cell includes a diffused drain and a diffused source over the first conductivity shallow ion well, a floating gate on the surface of the first conductivity shallow ion well and in between the diffused drain and source, and a control gate disposed on the top portion of floating gate and connected by a word line.
- a negative voltage is applied to a word line in programming a memory cell, and a positive voltage is simultaneously applied to the related bit line.
- the bit line is connected to the shallow ion well through the conductive plug forming a common electrode to induce the Fowler-Nordheim tunneling between the floating gate of the selected memory cell and the shallow ion well, and to force electron ejection from the floating gate into the shallow ion well, thus accomplishing the selective programming operation (PGM).
- ERS erasing operation
- a positive voltage is applied on a word line, and at the same time a negative voltage is applied on a source line connected by a selection transistor to force the bit line to enter a floating state in order to induce FN tunneling forcing ejection of electrons from the shallow ion well into the floating gate thus accomplishing the selective erasing operation (ERS).
- the self-limiting means is started along with the erasing operation (ERS) after a positive pulse and a negative pulse are applied respectively on a word line and a source line.
- the positive pulse and the negative pulse applied respectively on a bit line and a word line force a discharge of minority electrons from the floating gate in order to suppress the rising threshold voltage (Vth) as the erasing is in progress (i.e. the increase in cumulative time).
- Vth rising threshold voltage
- the voltage convergence speed of the above-mentioned self-limiting means will vary in accordance with the voltage level used in discharge and the pulse width.
- FIG. 1 is a diagram of the structure of a memory cell in the conventional flash memory
- FIG. 2 is a cross-sectional view of the memory array in a conventional NAND memory
- FIG. 3 is an equivalent circuit diagram of a memory array in conventional NAND flash memory
- FIG. 4 is a schematic view of a conventional memory structure
- FIG. 5 is a distribution of the threshold voltage of memory cells of FIG. 4;
- FIG. 6 is a distribution of the threshold voltage (Vth) for operating conventional memory cells
- FIG. 7 is a distribution of the threshold voltage (Vth) for operating conventional memory cells with multi-level storage
- FIG. 8 is a distribution of the threshold voltage (Vth) for the present invention with multi-level storage
- FIG. 9 is a cross-sectional view of the structure of memory cell array in accordance with the present invention.
- FIG. 10 is a cross-sectional view of the structure of memory cell array for another embodiment of the invention.
- FIG. 11 is an equivalent circuit diagram of the memory cell array of the present invention.
- FIG. 12 is a table showing the operating voltages for the present invention.
- FIG. 13 is a chart showing the self-limiting means to control threshold voltage (Vth) in accordance with the present invention.
- FIG. 14 is a waveform of the discharge pulse in accordance with the present invention.
- the present invention provides a method of programming flash memory with multi-level storage in the negative voltage range and erasing flash memory in the positive voltage range, as shown in FIG. 8, with enhanced conductivity and without noise disturbance.
- a self-limiting means is performed along with the erasing operation (ERS) to prevent the continuous ascending of threshold voltage (Vth) as the erasing is in progress.
- the memory cell structure in accordance with the present invention as shown in FIG. 9 comprises:
- a plurality of a first conductivity shallow ion wells ( 14 ) being disposed in the second conductivity deep ion wells ( 12 );
- a plurality of memory cell arrays (M) being formed over the first conductivity shallow ion wells ( 14 );
- a plurality of shallow trench insulation (STI) layers ( 16 ) being disposed over the first conductivity substrate ( 10 ) and in between the shallow ion wells ( 14 ) for mutual isolation of different memory cell arrays (M) (as shown in FIG. 10);
- bit lines (BL) being disposed on the first conductivity substrate ( 10 ) and extended to shallow ion wells ( 14 ) through respective conductive plugs ( 18 ), where, in the current embodiment, the first conductivity material is a P-type, and the second conductivity material is an N-type.
- Each memory cell ( 20 ) has a drain ( 22 ) and a source ( 24 ) corresponding to the position of the diffusion region on the shallow ion wells ( 14 ), a floating gate ( 26 ) created on the surface of the shallow ion wells ( 14 ) and in between the drain ( 22 ) and the source ( 24 ), and a control gate ( 28 ) created above the floating gate ( 26 ), wherein the floating gate ( 26 ) can be formed with an ONO structure, and the control gate ( 28 ) is connected to the corresponding word line (WL), as shown in FIG. 11.
- FIG. 11 shows the equivalent circuit diagram of the above-mentioned memory cell, where a plurality of memory cells are interconnected to form a memory cell array (M), and one end of the memory cell array (M) is connected by a selection transistor (T).
- a threshold voltage (Vth) for an erasing operation (ERS) is defined in the positive voltage range
- a threshold voltage for programming (PGM) with multi-level storage is defined in the negative voltage range.
- a negative voltage is applied on a selected word line (WL), and a positive voltage is simultaneously applied on a selected bit line (BL).
- the bit line (BL) is connected to the shallow ion wells ( 14 ) through the conductive plug ( 18 ) to form a common electrode.
- the Fowler-Nordheim tunneling is induced in between the shallow ion well ( 14 ) and the floating gate ( 26 ) over the selected word line (WL), forcing the ejection of electrons from the floating gate ( 26 ) into the shallow ion wells ( 14 ) to cause the given threshold voltage (Vth) to appear on the selected memory cell for selective programming (PGM).
- the operating conditions are shown in table 11 .
- ERS In the erasing mode (ERS), a positive voltage is applied over a selected word line (WL), and a negative voltage is simultaneously applied on the source line (SL) of the selection transistor (T) to force the bit line to enter a state of float to induce Fowler-Nordheim tunneling.
- the FN tunnel effect will force the ejection of electrons from the shallow ion wells ( 14 ) into the floating gate ( 26 ) to accomplish selective erasing (ERS).
- the above-mentioned erasing operation (ERS) is performed in the positive voltage range with a fixed voltage level. There is therefore no need to increase the voltage difference between the floating gate ( 26 ) and the shallow p-wells ( 14 ) as in the case of the programming operation (PGM) for supporting multi-level storage, thus obviating the problem of concomitant increase of threshold voltage (Vth) and pass gate voltage (Vpass). Since the threshold voltage (Vth) in the erasing operation (ERS) is directly related to the erasing time, as demonstrated in FIG. 13, the longer it takes for the erasing operation; the higher will be the threshold voltage (Vth).
- a self-limiting means is simultaneously started when the erasing operation (ERS) is performed, by which a discharge of electrons is allowed for an appropriate length of time after the Fowler-Nordheim tunneling to confine the threshold voltage (Vth) within a predetermined value range to prevent the continuous ascending of the threshold voltage as the erasing is in progress (i.e. the increase in cumulative time).
- ERS erasing operation
- FIG. 14 The method of self-limiting means is illustrated in FIG. 14.
- a positive voltage pulse is first applied over a selected word line (WL), and a pulse of negative voltage is simultaneously applied over a selected source line (SL) to induce the Fowler-Nordheim tunneling for the erasing operation (ERS).
- a stopper pulse (SP) of negative voltage is applied on the word line (WL)
- a positive voltage pulse is simultaneously applied on the bit line (BL), forcing the source line (SL) to enter a state of floating to induce the ejection of minority electrons from the floating gate ( 26 ) into the shallow ion wells ( 14 ).
- This release of minority electrons from the floating gate ( 26 ) will force the threshold voltage (Vth) to decrease, thus suppressing the continuous ascending of the threshold voltage as the erasing is in progress (i.e. the increase in cumulative time).
- the above-mentioned self-limiting means will yield different voltage convergence speeds due to the different potentials for the stopper pulse (SP) and the pulse widths.
- the results of the self-limiting means yield the same threshold voltages (Vth) under the various conditions, where the curve denoted by ⁇ represents the first stopper pulse of discharge (SP) with the potential on the word line (WL) set at ⁇ 8V, the potential on the bit line (BL) at 7V, and the pulse width of 14 ⁇ sec; the curve denoted by ⁇ represents the second stopper pulse of discharge (SP) with the potential on the word line (WL) set at ⁇ 7V, the potential on the bit line (BL) at 7V, and the pulse width of 80 ⁇ sec, the curve denoted by ⁇ represents the third stopper pulse of discharge (SP) with the potential on the word line (WL) set at ⁇ 6V, the potential on the bit line (BL) at 7V, and the pulse width of 600 ⁇ sec.
- the present invention chooses to use the positive voltage range for erasing (ERS) and the negative voltage range for programming (PGM) with multi-level storage.
- the voltage difference between the floating gate ( 26 ) and the shallow p-wells ( 14 ) has to be suitably increased to support the multi-level data storage, such that the negative value of a threshold voltage (Vth) will be increased for heightening pass gate voltage (Vpass) to enhance conductivity.
- the self-limiting means in conjunction with the erasing operation (ERS) is necessary to confine the threshold voltage (Vth) in a predetermined range to prevent the continuous ascending of the threshold voltage as the erasing is in progress (i.e. the increase in cumulative time).
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a method of programming and erasing a non-volatile semiconductor memory, in particular to a method of operating the flash memory that is capable of supporting multi-level data storage with enhanced conductivity and without noise disturbance.
- 2. Description of Related Arts Programming and erasing of a flash memory is usually performed by channel hot electron (CHE) or Fowler-Nordheim tunneling (FN tunneling). However, using CHE to write into memory cells usually requires excessively high power consumption. The industry has therefore developed a NAND flash memory that is operated with low power.
- The structure of a memory cell (70) in a conventional NAND flash memory, as shown in FIG. 1, comprises:
- a p-well (72);
- an n-source (74) formed on top of the p-well (72);
- an n-drain (76) formed on top of the p-well (72) corresponding to the position of the n-source (74);
- a stacked gate (80), formed on the surface of the p-well (72), disposed in between the n-drain (76) and the n-source (74); wherein
- The stacked gate (80) is built with a control gate (78), three successive insulation layers (82, 84, 86) of silicon oxide, silicon nitride and silicon oxide respectively, and a floating gate (88).
- The above-mentioned memory cell (70) of the NAND flash memory still has several shortcomings:
- FIG. 2 shows a cross-section of the memory cells (70) of a NAND memory built in the form of a memory array, and FIG. 3 shows an equivalent circuit for the memory array (700). In the NAND flash memory, all memory cells (70) are formed on top of the same p-well (72) which is formed by an n-source (74) or an n-drain (76), and the diffusion region over the p-well is connected to a bit line (BL).
- When programming a NAND memory cell, a bit line voltage (VBL) is applied over the bit line (BL), and a word line voltage (VWL) is simultaneously applied on a predetermined word line (WL) in order to induce FN tunneling for writing into a predetermined memory cell (70 a). Since the selected memory cells (70 a) and the non-selected memory cells (70 b) are all located above a common p-well (72), the voltage applied on selected memory cells (70 a) will affect other memory cells (70 b) down the line sharing the same word line (WL) as a result of the FN tunnel effect. The original status of the non-selected memory cell (70 b) therefore will be seriously affected. Thus, the selectivity and the efficiency of such programming/erasing operations are in question.
- With reference to FIG. 4, a method of randomly programming non-volatile semiconductor memory has been proposed to solve the above-mentioned problem. One implementation of the scheme (as shown in FIG. 4) is explained hereinafter. The structure of the memory device includes:
- a p-substrate (32);
- a plurality of deep n-wells (34) disposed on top of the p-substrate (32);
- a plurality of shallow p-wells (36) disposed in the above deep n-wells (34);
- a plurality of memory cell arrays (M) created above the shallow p-wells (36);
- a plurality of shallow trench insulation (STI) layers (38) disposed over the p-substrate (32) and in between the respective shallow p-wells (36), for isolating memory cell arrays (M); and
- a plurality of bit lines (BL) disposed on the p-substrate (32) and extending downward to the shallow p-well (36) through a conductive plug (40).
- In the architecture of the above-mentioned memory device, the shallow p-well (36) forms a common electrode of the memory cell arrays (M). Since a shallow p-well (36) is connected to a bit line (BL) through a conductive plug (40), this design is equivalent to a buried bit line. When programming the flash memory cells, a 5V positive voltage pulse is applied on a predetermined bit line (BL), and a 10V negative voltage is simultaneously applied on the word line of the selected memory cell to create the FN tunnel effect. Since adjacent memory cell arrays (M) are isolated by the STI layer (38) in other shallow p-wells, those memory cells having the same word line (WL) as the selected memory cell will not be affected by the FN tunnel effect, thus overcoming the previously encountered problem when programming a NAND flash memory.
- A new operation mode has been proposed along with the above-mentioned NAND flash memory. As shown in FIG. 5, a negative voltage is applied on the word line (WL) of a selected memory cell in the programming operation (PGM), and a positive voltage is applied on the word line (WL) of a selected memory cell in the erasing operation (ERS), in contrast to the conventional method of PGM and ERS, as shown in FIG. 6, in which a positive voltage pulse is used for PGM, whilst a negative voltage pulse is for ERS. It is noted that this operation mode can support multi-level storage on the above-mentioned flash memory.
- FIG. 7 shows the distribution of a threshold voltage (Vth) for conventional flash memory cells, in which the erasing operation (ERS) is done using the negative voltage range, and the programming with multi-level storage using the positive voltage range. If the positive voltage range is provided with 1-3V for the multi-level data storage, this means there will be only a narrow pulse width allowance for each type of data stored in the same cell. It is necessary to increase the voltage range for multi-level data storage, for example using 1-5V instead of 1-3V. However, with the increased threshold voltage (Vth), the pass gate voltage (Vpass) is also increased proportionally to maintain the proper potential for the FN tunneling. However, the increased pass gate voltage (Vpass) entails more power consumption, which is obviously counter to the present design trend of low-power memory devices. The disclosure of the above-mentioned pattern application can solve the apparent dilemma.
- However, since the threshold voltage (Vth) is rising gradually in relation to the erasing time, the pulse width of the threshold voltage (Vth) should be suitably restrained for the use of positive voltages in erasing, in order to avoid the concomitant increase of pass gate voltage (Vpass) along with the threshold voltage (Vth).
- The main object of the present invention is to provide a method of operating a flash memory with multi-level data storage to enhance conductivity and prevent noise disturbance.
- To this end, the threshold voltages (Vth) for such memory operations on the flash memory are defined, such that the threshold voltage (Vth) for erasing (ERS) occurs in the positive voltage range, whilst the programming (PGM) with multi-level data storage occurs in the negative voltage range. Since the threshold voltages (Vth) for multi-level data storage are defined in the negative voltage range, the voltage difference between the floating gate and the shallow p-well can be suitably increased to create a larger gate drive for higher pass gate voltage (Vpass) having enhanced conductivity and without noise disturbance.
- When performing an erasing operation (ERS) in the positive voltage range, a self-limiting means is started along with the erasing operation to prevent the continuous ascending of threshold voltage as the erasing is in progress (i.e. the increase in cumulative time). It is known that a continuous ascending threshold voltage (Vth) will adversely affect the efficiency of the erasing operation (ERS) in progress.
- The architecture of the above-mentioned flash memory comprises:
- one first conductivity substrate;
- a plurality of second conductivity deep ion wells being disposed on top the first conductivity substrate;
- a plurality of shallow ion wells being disposed in the respective second conductivity deep ion wells;
- a plurality of memory cell arrays over the first conductivity shallow ion wells;
- a plurality of shallow trench insulation (STI) layers being disposed over the first conductivity substrate and in between several shallow ion wells for mutual isolation of memory cell arrays;
- a plurality of bit lines being disposed on the first conductivity substrate and extending downward to the shallow ion wells through respective conductive plugs; wherein
- each memory cell array is formed by a plurality of memory cells, of which one end is connected to a selection transistor;
- each memory cell includes a diffused drain and a diffused source over the first conductivity shallow ion well, a floating gate on the surface of the first conductivity shallow ion well and in between the diffused drain and source, and a control gate disposed on the top portion of floating gate and connected by a word line.
- Under the above memory architecture, a negative voltage is applied to a word line in programming a memory cell, and a positive voltage is simultaneously applied to the related bit line. The bit line is connected to the shallow ion well through the conductive plug forming a common electrode to induce the Fowler-Nordheim tunneling between the floating gate of the selected memory cell and the shallow ion well, and to force electron ejection from the floating gate into the shallow ion well, thus accomplishing the selective programming operation (PGM).
- In the erasing operation (ERS), a positive voltage is applied on a word line, and at the same time a negative voltage is applied on a source line connected by a selection transistor to force the bit line to enter a floating state in order to induce FN tunneling forcing ejection of electrons from the shallow ion well into the floating gate thus accomplishing the selective erasing operation (ERS).
- The self-limiting means is started along with the erasing operation (ERS) after a positive pulse and a negative pulse are applied respectively on a word line and a source line. The positive pulse and the negative pulse applied respectively on a bit line and a word line force a discharge of minority electrons from the floating gate in order to suppress the rising threshold voltage (Vth) as the erasing is in progress (i.e. the increase in cumulative time).
- The voltage convergence speed of the above-mentioned self-limiting means will vary in accordance with the voltage level used in discharge and the pulse width.
- The features and structure of the present invention will be more clearly understood when taken in conjunction with the accompanying drawings.
- FIG. 1 is a diagram of the structure of a memory cell in the conventional flash memory;
- FIG. 2 is a cross-sectional view of the memory array in a conventional NAND memory;
- FIG. 3 is an equivalent circuit diagram of a memory array in conventional NAND flash memory;
- FIG. 4 is a schematic view of a conventional memory structure;
- FIG. 5 is a distribution of the threshold voltage of memory cells of FIG. 4;
- FIG. 6 is a distribution of the threshold voltage (Vth) for operating conventional memory cells;
- FIG. 7 is a distribution of the threshold voltage (Vth) for operating conventional memory cells with multi-level storage;
- FIG. 8 is a distribution of the threshold voltage (Vth) for the present invention with multi-level storage;
- FIG. 9 is a cross-sectional view of the structure of memory cell array in accordance with the present invention;
- FIG. 10 is a cross-sectional view of the structure of memory cell array for another embodiment of the invention;
- FIG. 11 is an equivalent circuit diagram of the memory cell array of the present invention;
- FIG. 12 is a table showing the operating voltages for the present invention;
- FIG. 13 is a chart showing the self-limiting means to control threshold voltage (Vth) in accordance with the present invention; and
- FIG. 14 is a waveform of the discharge pulse in accordance with the present invention.
- The present invention provides a method of programming flash memory with multi-level storage in the negative voltage range and erasing flash memory in the positive voltage range, as shown in FIG. 8, with enhanced conductivity and without noise disturbance.
- In addition, a self-limiting means is performed along with the erasing operation (ERS) to prevent the continuous ascending of threshold voltage (Vth) as the erasing is in progress.
- To this end, the memory cell structure in accordance with the present invention as shown in FIG. 9 comprises:
- a first conductivity substrate (10);
- a plurality of a second conductivity deep ion wells (12), being disposed on top of the first conductivity substrate (10);
- a plurality of a first conductivity shallow ion wells (14) being disposed in the second conductivity deep ion wells (12);
- a plurality of memory cell arrays (M) being formed over the first conductivity shallow ion wells (14);
- a plurality of shallow trench insulation (STI) layers (16) being disposed over the first conductivity substrate (10) and in between the shallow ion wells (14) for mutual isolation of different memory cell arrays (M) (as shown in FIG. 10);
- a plurality of bit lines (BL) being disposed on the first conductivity substrate (10) and extended to shallow ion wells (14) through respective conductive plugs (18), where, in the current embodiment, the first conductivity material is a P-type, and the second conductivity material is an N-type.
- Each memory cell (20) has a drain (22) and a source (24) corresponding to the position of the diffusion region on the shallow ion wells (14), a floating gate (26) created on the surface of the shallow ion wells (14) and in between the drain (22) and the source (24), and a control gate (28) created above the floating gate (26), wherein the floating gate (26) can be formed with an ONO structure, and the control gate (28) is connected to the corresponding word line (WL), as shown in FIG. 11.
- FIG. 11 shows the equivalent circuit diagram of the above-mentioned memory cell, where a plurality of memory cells are interconnected to form a memory cell array (M), and one end of the memory cell array (M) is connected by a selection transistor (T).
- With this type of memory cell array (M), a threshold voltage (Vth) for an erasing operation (ERS) is defined in the positive voltage range, and a threshold voltage for programming (PGM) with multi-level storage is defined in the negative voltage range.
- After laying out the architecture of the memory cell, the detailed procedures for the above operations are to be explained.
- In the programming mode (PGM), a negative voltage is applied on a selected word line (WL), and a positive voltage is simultaneously applied on a selected bit line (BL). The bit line (BL) is connected to the shallow ion wells (14) through the conductive plug (18) to form a common electrode. Under a given voltage difference between the floating gate (26) and the shallow p-well, (14), the Fowler-Nordheim tunneling is induced in between the shallow ion well (14) and the floating gate (26) over the selected word line (WL), forcing the ejection of electrons from the floating gate (26) into the shallow ion wells (14) to cause the given threshold voltage (Vth) to appear on the selected memory cell for selective programming (PGM). The operating conditions are shown in table 11.
- Since the multi-level storage is operated on the negative voltage range, the increase in voltage difference between the floating gate (26) and the shallow p-well (14) creates a larger gate drive for pass gate voltage (Vpass) having enhanced conductivity.
- In the erasing mode (ERS), a positive voltage is applied over a selected word line (WL), and a negative voltage is simultaneously applied on the source line (SL) of the selection transistor (T) to force the bit line to enter a state of float to induce Fowler-Nordheim tunneling. The FN tunnel effect will force the ejection of electrons from the shallow ion wells (14) into the floating gate (26) to accomplish selective erasing (ERS).
- The above-mentioned erasing operation (ERS) is performed in the positive voltage range with a fixed voltage level. There is therefore no need to increase the voltage difference between the floating gate (26) and the shallow p-wells (14) as in the case of the programming operation (PGM) for supporting multi-level storage, thus obviating the problem of concomitant increase of threshold voltage (Vth) and pass gate voltage (Vpass). Since the threshold voltage (Vth) in the erasing operation (ERS) is directly related to the erasing time, as demonstrated in FIG. 13, the longer it takes for the erasing operation; the higher will be the threshold voltage (Vth). To suppress this trend of ascending voltage value, in accordance with the present invention, a self-limiting means is simultaneously started when the erasing operation (ERS) is performed, by which a discharge of electrons is allowed for an appropriate length of time after the Fowler-Nordheim tunneling to confine the threshold voltage (Vth) within a predetermined value range to prevent the continuous ascending of the threshold voltage as the erasing is in progress (i.e. the increase in cumulative time).
- The method of self-limiting means is illustrated in FIG. 14. A positive voltage pulse is first applied over a selected word line (WL), and a pulse of negative voltage is simultaneously applied over a selected source line (SL) to induce the Fowler-Nordheim tunneling for the erasing operation (ERS). Thereafter, to induce the discharge of minority electrons, a stopper pulse (SP) of negative voltage is applied on the word line (WL), and a positive voltage pulse is simultaneously applied on the bit line (BL), forcing the source line (SL) to enter a state of floating to induce the ejection of minority electrons from the floating gate (26) into the shallow ion wells (14). This release of minority electrons from the floating gate (26) will force the threshold voltage (Vth) to decrease, thus suppressing the continuous ascending of the threshold voltage as the erasing is in progress (i.e. the increase in cumulative time).
- The above-mentioned self-limiting means will yield different voltage convergence speeds due to the different potentials for the stopper pulse (SP) and the pulse widths. In FIG. 13 the results of the self-limiting means yield the same threshold voltages (Vth) under the various conditions, where the curve denoted by ▴ represents the first stopper pulse of discharge (SP) with the potential on the word line (WL) set at −8V, the potential on the bit line (BL) at 7V, and the pulse width of 14 μsec; the curve denoted by represents the second stopper pulse of discharge (SP) with the potential on the word line (WL) set at −7V, the potential on the bit line (BL) at 7V, and the pulse width of 80 μsec, the curve denoted by ▪ represents the third stopper pulse of discharge (SP) with the potential on the word line (WL) set at −6V, the potential on the bit line (BL) at 7V, and the pulse width of 600 μsec.
- The above-mentioned stopper pulses with different discharge times and intensity of the discharge pulse therefore result in the same threshold voltage with different voltage convergence speeds.
- In summary, the present invention chooses to use the positive voltage range for erasing (ERS) and the negative voltage range for programming (PGM) with multi-level storage. During the programming (PGM) of memory cells, the voltage difference between the floating gate (26) and the shallow p-wells (14) has to be suitably increased to support the multi-level data storage, such that the negative value of a threshold voltage (Vth) will be increased for heightening pass gate voltage (Vpass) to enhance conductivity. The self-limiting means in conjunction with the erasing operation (ERS) is necessary to confine the threshold voltage (Vth) in a predetermined range to prevent the continuous ascending of the threshold voltage as the erasing is in progress (i.e. the increase in cumulative time).
- The foregoing description of the preferred embodiments of the present invention is intended to be illustrative only and, under no circumstances, should the scope of the present invention be so restricted.
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