US20040255230A1

US20040255230A1 - Configurable decoder

Info

Publication number: US20040255230A1
Application number: US10/457,592
Authority: US
Inventors: Inching Chen; Anthony Chun; Amit Dagan
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2003-06-10
Filing date: 2003-06-10
Publication date: 2004-12-16
Also published as: WO2005002061A1; US7536630B2; US20050034051A1; TW200509542A; TWI256773B; EP1639714A1

Abstract

Briefly, a configurable decoder to decode signals of communication systems is provided. The configurable decoder may include a programmable metric data generator to reconfigure an add-compare-select unit according to a predetermined data structure provided by a desired communication protocol and a programmable traceback unit to provide decoded data according to the desired communication protocol.

Description

BACKGROUND OF THE INVENTION

At least one of the goals of the wireless communications industry is to provide “always-on” voice and data access to mobile users equipped with cellular telephones, personal data assistants or personal computers. A radio product that meets this goal may need to be able to support multiple wireless standards for Wide Area Networks (WAN), Wireless Local Area Networks (WLAN) and Wireless Personal Area Networks (WPAN).

Wireless communications are subject to numerous impairments such as noise, multipath fading and interference. Forward Error Correction (FEC) may be incorporated in at least some of these wireless standards to improve the reliability of data sent over a noisy transmission link. The FEC technique may use convolutional encoding in the transmitter followed by Viterbi decoding in the receiver. Viterbi decoding may be integrated into numerous communications standards, including IEEE 802.11a, 3G WCDMA and GSM/GPRS and the like.

While the decoding methods may be similar for these standards, the parameters of the error correction code may differ. Thus, the Viterbi decoder used with one communication standard may not be suitable to be used with other communication standards.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanied drawings in which: [0004]
FIG. 1 is a schematic illustration of a portion of a communication system according to an exemplary embodiment of the present invention; [0005]
FIG. 2 is a block diagram of a reconfigurable Viterbi decoder according to an exemplary embodiment of the present invention; [0006]
FIG. 3 is a block diagram of a metric data generator according to an exemplary embodiment of the present invention; [0007]
FIG. 4 is a block diagram of a path metric state machine according to an exemplary embodiment of the present invention; [0008]
FIG. 5 is a block diagram of a branch metric state machine according to an exemplary embodiment of the present invention; [0009]
FIG. 6 is a block diagram of a traceback unit according to an exemplary embodiment of the present invention; and [0010]
FIG. 7 is an example of a Trellis diagram according to the art.[0011]
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. [0012]

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention. [0013]
Some portions of the detailed description, which follow, are presented in terms of algorithms and symbolic representations of operations on data bits or binary digital signals within a computer memory. These algorithmic descriptions and representations may be the techniques used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art. [0014]
Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices. In addition, the term “plurality” may be used throughout the specification to describe two or more components, devices, elements, parameters and the like. For example, “plurality of address generators” describes two or more address generators. [0015]
It should be understood that the present invention may be used in a variety of applications. Although the present invention is not limited in this respect, the circuits and techniques disclosed herein may be used in many apparatuses such as units of an wired network for example, local area network (LAN) and/or wireless communication system, such as for example, a WLAN communication system and/or in any other unit and/or device that need a decoder. Units of WLAN communication system intended to be included within the scope of the present invention include, by way of example only, mobile units (MU), access points (AP), wireless receivers, and the like. [0016]
Types of WLAN communication systems intended to be within the scope of the present invention include, although are not limited to, “IEEE-Std 802.11, 1999 Edition (ISO/IEC 8802-11: 1999)” standard, and more particularly in “IEEE-Std 802.11b-1999 Supplement to 802.11-1999,Wireless LAN MAC and PHY specifications: Higher speed Physical Layer (PHY) extension in the 2.4 GHz band”, “IEEE-Std 802.11a-1999, Higher speed Physical Layer (PHY) extension in the 5 GHz band” standard, and the like. [0017]
Although the scope of the present invention is not limited in this respect, the circuits and techniques disclosed herein may also be used in units of a cellular communication systems, digital communication systems, satellite communication systems and the like. [0018]
Turning to FIG. 1, a portion of an exemplary [0019] wireless communication system 100 according to some embodiments of the invention is shown. Wireless communication system 100 may include at least one fixed station (FS) 110, for example, a base station of a cellular communication system, an access point of a WLAN, and the like.
In some embodiments of the invention, FS [0020] 110 may include at least a transmitter 120 and an antenna 122. Antenna 122 may be a dipole antenna and/or any other antenna suitable for use in wireless communication. In an exemplary embodiment of the present invention, transmitter 120 may include a data generator (DG) 124 to generate data for transmission, an encoder 126, for example, a Forward Error Correction encoder, to encode the data generated by data generator 124, and a transmitting unit (TX) 128.
Although the scope of the present invention is not limited in this respect, [0021] encoder 126 may encode the data according to the type of the wireless communication system. For example, encoder 126 may encode the data according to WLAN IEEE-standard 802.11a, 802.11b, 802.11g and/or according to one of the cellular standards such as, for example, Global System for Mobile Communication (GSM), Enhanced Data for GSM Evolution (EDGE), Code Division Multiple Access (CDMA), Wideband CDMA and the like. A transmitter (TX) unit 128 may modulate the encoded data with a radio frequency (RF) signal according to the desired wireless communication system standard and may transmit the signal using antenna 122 over a wireless link 130.
Furthermore, [0022] wireless communication system 100 may include at least one mobile station (MS) 140, for example, a cellphone, a mobile unit (MU) of WLAN, and the like. Although the scope of the present invention is not limited in this respect, in this embodiment of the present invention mobile station 130 may include a receiver 150 to receive the encoded modulated signal with an antenna 152, e.g., a dipole antenna.
In some embodiments of the present invention, [0023] receiver 150 may include a baseband (BB) unit 154 to demodulate the received signal and to provide the encoded data to a configurable decoder 156, for example, a configurable trellis decoder and/or a configurable Viterbi decoder, which are described in detail below with reference to FIGS. 2-6.
Although the scope of the present invention is in no way limited in this respect, [0024] configurable decoder 156 may be programmed with a circuit description language, which may be downloaded from a download server 160, if desired. In some embodiments of the present invention, download server 160 may be for example, a wireless device and/or a wired device.
Although the scope of the present invention is not limited in this respect, [0025] configurable decoder 156 may be reconfigured by the downloaded circuit description to decode a received data according to the desired communication standard, for example, IEEE 802.11a, GSM or the like. The decoded data may be processed by a processor 158, for example, a digital signal processor, an application processor and the like, if desired.
Turning to FIG. 2, a block diagram of a configurable Viterbi [0026] decoder 200 according to an exemplary embodiment of the invention is shown. Although the scope of the present invention is not limited in this respect, configurable Viterbi decoder 200 may include a programmable metric data generator 210, which may compute a branch metric based on the probability of a received symbol being substantially equal to a branch symbol. For example, metric data generator 210 may compute squared Euclidean distances between a symbol received within an input signal 220 and the branch symbols that may be generated by the programmable metric data generator 210, if desired. Additionally or alternatively, in other embodiments of the present invention, metric data generator 210 may computed Hamming distances between a symbol received within an input signal 220 and the branch symbols that may be generated by the programmable metric data generator 210, if desired.
Although the scope of the present invention is not limited in this respect, programmable [0027] metric data generator 210 may provide plurality of branch metrics and plurality of path metrics to an Add-Compare-Select (ACS) unit 230. As is known to one skilled in the art, Viterbi decoders may use a Viterbi algorithm to search states of a trellis diagram for a best surviving branch. ACS unit 230 may compute path metrics and may select the best surviving branch into a state of the trellis. Furthermore, ACS unit 230 may be reconfigured for processing multiple communications standards according to a predetermined data structure provided by a desired communication protocol e.g. IEEE 802.11b-1999.
As is known in the art, the Viterbi decoding algorithm may represent the convolutional encoder as a state machine that may be graphically depicted by a trellis diagram [0028] 700 illustrated in FIG. 7. Trellis diagram 700 may include a stage 740, states 710, path metrics 730 and branch metrics 720. The number of states S per trellis stage 740 may be a function of a memory length of a convolutional encoder, for example, encoder 126. The code trellis may represent an encoder state as a node of the trellis diagram, for example, state 710, that may be connected to previous states via branches 720. Associated with a branch are an encoded symbol and a decoded symbol. In this example, certain branch connections may be allowed and may be a function of a code generator matrix (not shown). For example, in a given received sequence of noisy and corrupted symbols, ACS unit 230 may search trellis diagram 700 to find the most likely transmitted sequence and the resulting decoded bit sequence.
Although the scope of the present invention is not limited in this respect, for a received encoded symbol, [0029] configurable Viterbi decoder 200 may generate soft branch metrics substantially equivalent to the squared Euclidean distance between the received symbol and the encoded symbol associated with the branch of the trellis diagram. For example, for a code with rate R=k/n, wherein k is the number of input bits and n is the number of encoded bits, there are 2ⁿdifferent possible branch metrics 720 for the received symbol. The branch metrics 720 may be computed for every symbol as it is received and stored in memory.
Although the scope of the present invention is not limited in this respect, [0030] branch metrics 720 may be proportional to the probability of error for that symbol. Branch metrics 720 may be summed over a sequence of symbols to obtain a path metric 730 that may be proportional to the probability of that sequence. A Viterbi algorithm may be used to find the transmitted sequence that minimizes the Euclidean distance with respect to the received sequence.
Although the scope of the present invention is not limited in this respect, in embodiments of the present invention, for a symbol time t, [0031] ACS unit 230 may perform an ACS function to accumulate the path metrics for the S states 710 of trellis diagram 700. The ACS function may recursively compute new path metrics 730 as the sum of a path metric from a previous state and the branch metric on the branch connecting the current state with a previous state. The 2^kcompeting path metrics may be compared to produce a branch. The branch that produces the minimum path metric may be selected and the best path metric of the selected path metrics may be stored in memory. The S previous path metrics 730 and branch metrics 720 may be stored in memory and the appropriate values may be read out to be processed by ACS function.
Although the scope of the present invention is not limited in this respect, [0032] ACS unit 230 may include a predetermined number of units A. The ACS function may be performed by A ACS units, where A≦the number of states S in a stage of the trellis diagram. For example, if A<S, then trellis stage 710 may be processed in multiple clock cycles. At the clock cycle, ACS units may compute a new path metric using the appropriate previous path and branch metrics. In some embodiments of the invention, the ACS function may include 2^kadders and a 2^k—way compare unit.
Although the scope of the present invention is not limited in this respect, in embodiments of the invention the 2[0033] ⁿ branch metrics 720 and the 2^k previous path metrics 730 that are associated with the ACS function may be dependent upon the code trellis and may be reconfigured according to the desired wireless standard. In some embodiments of the invention, the path and branch metric storage elements may be provided by metric data generator 210 to ACS unit 230 according to the desired communication standard.
Although the scope of the present invention is not limited in this respect, the exemplary embodiment of the invention, [0034] configurable Viterbi decoder 200 may further include a programmable traceback unit 240 which may store the winning branch decisions and may be used to reconstruct the state and decoded bit sequence. Metric data generator unit 210 and programmable traceback unit 240 may be programmed via a programming port 260, although the scope of the present invention is in no way limited in this respect.
Turning to FIG. 3, a block diagram of a metric [0035] data generator unit 210 according to an exemplary embodiment of the present invention is shown. Although the scope of the present invention is not limited in this respect, metric data generator unit 210 may include a path metric data generator unit (PM-DGU) 300 and a branch metric data generator unit (BM-DGU) 350. In addition, PM-DGU 300 may include a path metric (PM) memory unit 320 and a PM state machine 330, which are described below with reference to FIG. 4. In addition, BM-DGU 350 may include a branch metric (BM), a memory unit 360, and a BM state machine 370. BM state machine 370 is described in detail below with reference to FIG. 5.
Although the scope of the present invention is not limited in this respect, PM-[0036] DGU 300 may include at least two units a PM memory unit 320 that may store the previous and new path metrics, and a PM state machine 330 that may read and shuffle the path metric values from the PM memory unit 320.
In some embodiment of the present invention, [0037] PM memory unit 320 may include two or more buffers to enable path metrics to be generated and stored while previous path metrics remain in memory. For example, to process a trellis having S states and b bits per path metric, a memory size of 2S×b bits may be needed.
Additionally and/or alternatively, [0038] PM memory unit 320 may be organized into upper and lower memory segments 327, 328, respectively. For example, upper memory segment 327 may be used for radix-2 codes while both memory segments 327 and 328 may be used for radix-4 codes. Furthermore, upper memory segment 327 and/or lower memory segment 328 may be divided into vectors of length 2×A×b bits. For example, upper segment 327 and/or lower segment 328 may contain V=S (2A) of these vectors (not shown).
Although the scope of the present invention is not limited in this respect, [0039] PM memory unit 320 may have a write port 322 to enable new path metrics to be written in vectors of length A×b bits. The path metric values may be stored in the vectors in numerical order (i.e. corresponding to state 0, 1, 2, . . . , S−1). In addition, PM memory unit 320 may have two read ports 324 and 326 to enable both upper and lower memory segments 327 and 328 to be read simultaneously for radix-4 codes, if desired. Previous path metrics may be written in vectors of length 2×A×b bits.
Turning to FIG. 4, a block diagram of [0040] PM state machine 330 according to an exemplary embodiment of the invention is shown. PM state machine 330 may include address generator units 410 and 420, a shuffler 430, and a multiplexer 440.
Although the scope of the present invention is not limited in this respect, 2[0041] ^kaddress generators may be used to select vectors of A previous path metrics from PM memory unit 320. For example, address generator units 410 and 420 may select the appropriate vectors that will be read from PM memory unit 320 to the shuffler 430 by controlling read ports 324 and 326, if desired. In this example, PM state machine 330 may provide path metrics to eight ACS units, thus, A=8. Furthermore, the number of states may be set to S=256. For a radix-2 code, k=1 and a total of 16 path metrics may be read in a clock cycle. Additionally and/or alternatively, for a radix-4 code, k=2, a total of 32 path metrics may be read in a clock cycle. In this embodiment of the invention, for 10-bit path metrics (b=10) PM memory unit 320 may be allocated to vectors of V=256/16=16. Thus, sixteen 10-bit path metrics may be provided to address generator units 410, 420. In this example, address generators 410 and 420 may be 4 bit address generators, if desired.
Although the scope of the present invention is not limited in this respect, [0042] shuffler 430 may shuffle the appropriate path metrics to be routed to the ACS units. Shuffler 430 may shuffle the path metrics that are input to multiplexer 440. Multiplexer 440 may have 2-bit control line 435 and may select different sets of path metrics to be input to ACS unit 230. In one exemplary embodiment of the invention, multiplexer 440 may include sixteen 4:1 10-bit multiplexers that may be connected to inputs 445 and 446 of ACS unit 230. Although the scope of the present invention is not limited in this respect, shuffler 430 and multiplexer 440 may be implemented in programmable logic and may be modified for different codes based on the desired communication standard.
Turning to FIG. 5, a block diagram of BM-[0043] DGU 350 according to an exemplary embodiment of the present invention is shown. Although the scope of the present invention is not limited in this respect, BM-DGU 350 may include BM memory Unit 510 that may store newly generated branch metrics. For example, BM memory unit 510 may store a total of 2ⁿb_m-bit branch metrics, if desired. In addition, BM-DGU 350 may include BM state machine 520. BM state machine 520 may read the appropriate branch metric values from the BM memory unit 510 and may distribute the branch metric values to ACS unit 230, if desired.
Although the scope of the present invention is not limited in this respect, [0044] BM state machine 520 may generate the read addresses for the stored branch metrics that are required for ACS unit 230. BM state machine 520 may include a multiplexer 530 that may include two sets of 2 A multiplexers 532 and 535. Multiplexers 532 and 535 may switch 1 of 2^kbranch metric values to ACS unit 230, if desired. For example, for radix-2 codes one set of multiplexers may be used, e.g., multiplexer 532, while for radix-4 both sets of multiplexers 532 and 535 may be used. Furthermore, BM state machine 520 may include a router 540 that may select the controls on branch metric multiplexers 532 and 535.
Although the scope of the present invention is not limited in this respect, in one embodiment of the present invention, [0045] multiplexer 530 may include two sets of sixteen 8:1 multiplexers implemented in programmable logic device. A set of 8:1 multiplexer may select 1 of the 8 possible patterns of branch metrics. Router 540 may control the multiplexer settings based on the desired communication standard.
Turning to FIG. 6, a block diagram of [0046] traceback unit 240 according to an exemplary embodiment of the invention is shown. Although the scope of the present invention is not limited in this respect, traceback unit 240 may include a cache memory 610 that may store selected branches of the branch metric, a traceback state machine 620 to receive read bits from the cache memory and to output a read address and decoded bits, and a configuration control 630 that, in some embodiments of the invention, may configure cache memory 610 and traceback state machine 620 according to the desired communication standard.
Although the scope of the present invention is not limited in this respect, [0047] traceback unit 240 may perform the following functions of a Viterbi decoder. The first function may be a write function that may write the branch decisions made by the ACS unit 230 into cache memory 610. For example, for a code rate k/n, a decision may include k bits. For the A ACS units, where A≦the number of states S in the trellis, a total of A branch decisions may be written to the cache memory 610 in every clock cycle. A command line 640 may configure traceback state machine to receive radix-2 code or radix-4 code, if desired. For example, for a radix-2 code (i.e. k=1 for code rate 1/n) one bit is written for a state at a stage of the trellis. For a radix-4 code (i.e. k=2 for code rate 2/n), two bits may be written for a state at a stage of the trellis. The traceback write function may be performed sequentially through cache memory 610, i.e., from s=0, 1, 2, . . . , A−1, for a time t.
Although the scope of the present invention is not limited in this respect, [0048] traceback unit 240 may perform a traceback function that may read branch decisions d from cache memory 610. The traceback function may begin at an arbitrary state (row) at column t′ in the cache memory 610 and may follow the trellis backwards to times t′−1, t′−2., etc. A branch decision d(t′, S(t′)) at time t′ may be used to generate the next read address S(d,t′−1). Furthermore, the traceback function may be performed over some number of branches T (the traceback length) from time t′ until the various surviving paths converge at time t′−T. Although the scope of the present invention is not limited in this respect, the minimum value of T is a function of the code rate and number of states.
Although the scope of the present invention is not limited in this respect, [0049] traceback unit 240 may perform a decode function that may read branch decisions from cache memory 610. For example, the decode function may be performed on a “converged” portion of the trellis and may begin from the last state specified by the traceback function at time t′−T. This branch decision at time t′ may be used to generate the next read address corresponding to the previous stage of the trellis S(d,t′−1). The decode function may proceed backwards in time over D trellis stages until time t-T-D. In some embodiments of the present invention, the read operations for the traceback and decode function may be similar; the only difference may be that for the decode function valid decoded bits may be output. The decoded bits are a function of the decision bits d(t′,S(t′)) that were read from cache memory 610 and the current state S(d,t′). A decode read may provide one decoded bit for Radix-2 codes or two decoded bits for Radix-4 codes, if desired.
Although the scope of the present invention is not limited in this respect, the traceback writes and reads functions may be performed simultaneously on different areas of [0050] cache memory 610. For example, a traceback unit architecture may use a single read and a single write pointer thus the read and decode operations may be performed sequentially. Other architectures of traceback unit 240 may use two or more read pointers, thus the read and decode operations may be performed in parallel and multiple traceback state machines may be used.
In embodiments of the present invention, [0051] cache memory 610 may be used to store the branch decisions. In some embodiments, cache memory 610 may be conceptualized as a rectangular matrix where the number of rows in the memory is equal to the number of states S and the number of columns in the memory is a function of the traceback length T and the traceback architecture. For example, a memory cell of cache memory 610 may be 1-bit wide.
Although the scope of the present invention is not limited in this respect, [0052] cache memory 610 may be organized into upper and lower sections; the upper section may be used for radix-2 codes and both sections may be used for radix-4 codes.
Although the scope of the present invention is not limited in this respect, in some embodiments of the invention, [0053] cache memory 610 may be visualized as an array of S rows and L columns, where a row corresponds to a trellis state s and a column corresponds to a stage t of the trellis. After a sufficient number of branch decisions are written to cache memory 610, the encoder state sequence is reconstructed by starting from a column at time t′, reading a stored branch decision, and generating the address for a row (state) in the next most recent column at time t′−1. The traceback read operation may proceed in reverse time order from a recent column to an older column.
Although the scope of the present invention is not limited in this respect, traceback state machine (TB-SM) [0054] 620 may receive as an input the traceback decision bits d (615) for example, d=2 bits, that were read from the cache memory 610 corresponding to the received symbol at time t and state S(t). TB-SM 620 may output the next read address for time t−1 and decoded bits x (625).
Although the scope of the present invention is not limited in this respect, TB-[0055] SM 620 may be implemented to perform the function of a traceback read address generator. The outputs of the TB-SM 620 may be a read address output 618 and decoded bits output 625, if desired. As noted above, traceback is the process of using the stored branch decisions to recreate the encoder state sequence. For example, encoder 126 at transmitter 120 may be represented as a state machine in which the input bits trigger the state transitions. TB-SM 620 may be similar to encoder 126 except that the state transitions are backwards in time from time t, t−1, t−2, . . .
In some embodiments of the invention, TB-[0056] SM 620 may be triggered by decision bits 615 d(t, S(t)) that are read at time t from an address corresponding to state S(t). The state S(t−1) at time t−1 may be generated as a function of the state S(t) at time t and the decision bits d(t, S(t)) at time t and corresponds to the address in the cache memory 610 in which the decision bits 615 d(t−1, S(t−1)) for time t−1 are read. Decision bits 615 may then be used to produce the state at time t−2, and so on, and the process may be repeated, although the scope of the present invention is not limited in this respect.
Although the scope of the present invention is not limited in this respect, decoded [0057] bits 625 may be a function of the bits that are read from the cache memory 610. Until the trellis “converges” after T trellis stages, where T corresponds to the traceback length, the decoded bits are considered unreliable. The value of T is a function of the number of states S and the code rate k/n.
Although the scope of the present invention is not limited in this respect, read [0058] address output 618 may include r bits. In embodiments of the invention, read address bits may include c counter bits that represent the upper c bits of the cache memory 610 read address. In this embodiment, c bits may be interpreted as the index of the column of the cache memory 610 while the lower a bits of the address correspond to the row of the cache memory 610. The value of a is a function of the number of states S for the code where a=log₂(S).
In some embodiment of the invention, the value of r=c+a may be constant for a particular decoder implementation and may be dependent upon the organization of [0059] cache memory 610. However, the values of c and a may vary depending upon the code since the number of states may vary.
Although the scope of the present invention is not limited in this respect, [0060] configuration control 630 may configure cache memory 610 and TB-SM 620 by programming the required architecture to cache memory 610 and TB-SM 620. The architecture of cache memory 610 and TB-SM 620 may vary according to the desired communication standard.
In alternative embodiments of the present invention, a programmable traceback unit may have separate address generator units for each code type. In another alternative embodiment, the address generator may be implemented by a look-up table that may be modified according to a code type. [0061]
Although the scope of the present invention is not limited in this respect, PM-[0062] state machine 360, BM state machine 460 and TB-SM 620, may be implemented using standard RAM-based Programmable Logic Devices (PLD) such as, for example, Programmable Array Logic (PAL) and/or a Programmable Logic Array (PLA).
Although the scope of the present invention is not limited in this respect, in some embodiments of the invention, BM state machine [0063] 460 may be implemented by using a PLA and PM state machine 360, and TB-SM 240 may be implemented using a PAL, if desired.
Although the scope of the present invention is not limited in this respect, PM-[0064] state machine 360, BM state machine 460 and TB-SM 620 may be programmed by downloading a new circuit description to the PLD. The circuit description may be written in a standard Hardware Description Language (HDL).
While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention. [0065]

Claims

What is claimed is:

1. An apparatus comprises:

a programmable metric data generator to reconfigure an add-compare-select unit according to a predetermined data structure provided by a desired communication protocol; and

a programmable traceback unit to provide decoded data according to the desired communication protocol.

2. The apparatus of claim 1, wherein the programmable metric data generator comprise a first programmable logic device to be programmed using a hardware description language and the programmable traceback unit comprises a second programmable logic device to be programmed using the hardware description language.

3. The apparatus of claim 1 wherein the programmable metric generator is able to compute a branch metric based on the probability of a received symbol being substantially equal to a branch symbol.

4. The apparatus of claim 1, wherein the programmable metric generator is able to compute a squared Euclidean distance or Hamming distance between a received symbol and a branch symbol.

5. The apparatus of claim 1, wherein the programmable metric generator further comprises at least one of a path metric data generator and a branch metric generator.

6. The apparatus of claim 5, wherein the path metric data generator comprises:

a path metric state machine to read and to shuffle the path metrics values.

7. The apparatus of claim 5, wherein the path metric data generator comprises

a path metric memory unit to store a plurality of path metrics and the path metric state machine.

8. The apparatus of claim 5, wherein the path metric state machine comprises:

a plurality of address generators to select a predetermined number of previously generated path metrics stored in the path metric memory unit;

a shuffler to route the path metrics to the add-compare-select unit; and

a multiplexer to select the path metrics to be input to the add-compare-select unit.

9. The apparatus of claim 8, wherein the shuffler and the multiplexer are implemented in a programmable logic and are able to be programmed according to the desired communication protocol.

10. The apparatus of claim 5, wherein the branch metric generator comprises:

a branch metric state machine to read branch metric values from the branch metric memory unit and to distribute the branch metric values to the add-compare-select unit.

11. The apparatus of claim 5, wherein the branch metric generator comprises:

a branch metric memory unit to store a plurality of a newly generated branch metrics.

12. The apparatus of claim 10, wherein the branch metric state machine comprises a programmable logic device able to be programmed according to the desired communication protocol.

13. The apparatus of claim 1, wherein the add-compare-select unit comprises a predetermined number of add-compare select units.

14. The apparatus of claim 1, wherein the programmable traceback unit is able to store winning branch decisions.

15. The apparatus of claim 1, wherein the programmable traceback unit is able to reconstruct a state sequence and to reconstruct a decoded bit sequence.

16. The apparatus of claim 1, wherein the programmable traceback unit comprises:

a traceback state machine to receive a bit read from the cache memory and to output a read address and decoded bits.

17. The apparatus of claim 1, wherein the programmable traceback unit comprises:

a cache memory to store a selected branch of the branch metric and the traceback state machine.

18. The apparatus of claim 16, wherein the traceback state machine comprises a traceback read address generator.

19. The apparatus of claim 16, wherein the traceback state machine is implemented by a random accessed memory based programmable logic device to be programmed by downloading a circuit description of the traceback state machine.

20. The apparatus of claim 1 is configured to decode a received signal.

21. An apparatus comprising:

a dipole antenna to receive a signal; and

a configurable decoder to decode the received signal, the decoder comprising a programmable metric data generator to reconfigure an add-compare-select unit according to data structure of the received signal.

22. The apparatus of claim 21, wherein the configurable decoder further comprises:

a programmable traceback unit; and

the programmable metric data generator comprise a first programmable logic device to be programmed using a hardware description language and the programmable traceback unit comprises a second programmable logic device to be programmed using the hardware description language.

23. The apparatus of claim 21, wherein the programmable metric generator is able to compute Hamming distance between a received symbol and a branch symbol.

24. The apparatus of claim 21, wherein the programmable metric generator further comprises a path metric data generator and a branch metric data generator.

25. The apparatus of claim 24, wherein the path metric data generator comprises:

a path metric memory unit to store a plurality of path metrics; and

a path metric state machine to read and to shuffle the path metrics values.

26. The apparatus of claim 25, wherein the path metric state machine comprises:

a shuffler to route the appropriate path metrics to the add-compare-select unit; and

27. The apparatus of claim 26, wherein the shuffler and the multiplexer are implemented in programmable logic and are able to be programmed according to the desired communication protocol.

28. The apparatus of claim 25, wherein the branch metric generator comprises:

a branch metric memory to store a plurality of newly generated branch metrics; and

a branch metric state machine to read branch metric values from the branch metric memory and to distribute the branch metric values to the add-compare-select unit.

29. The apparatus of claim 28, wherein the branch metric state machine comprises a programmable logic device and is able to be programmed according to a desired communication protocol.

30. The apparatus of claim 21, wherein the add-compare-select unit comprises a predetermined number of add-compare select units.

31. The apparatus of claim 21, further comprising a programmable traceback unit to store winning branch decisions.

32. The apparatus of claim 21, wherein the programmable traceback unit is able to reconstruct a state and to reconstruct a decoded bit sequence.

33. The apparatus of claim 21, wherein the programmable traceback unit comprises:

a cache memory to store two or more selected branches of the branch metric; and

a traceback state machine to receive two or more bits read from the cache memory and to output a read address and two or more decoded bits.

34. The apparatus of claim 33, wherein the traceback state machine comprises a traceback read address generator.

35. The apparatus of claim 33, wherein the traceback state machine is implemented by a random access memory based programmable logic device to be programmed by downloading a circuit description of the traceback state machine.

36. The apparatus of claim 21 is configured to decode a received signal.

37. A method comprising:

reconfiguring a decoder by downloading a circuit description of a state machine of the decoder,

wherein the circuit description is able to program the state machine of the decoder.

38. The method of claim 37, wherein the state machine comprises at least one of a state machine of a path metric generator and a state machine of a branch metric generator and wherein reconfiguring comprises:

reconfiguring at least one of the state machine of the path metric and the state machine of the branch metric generator.

39. The method of claim 37, wherein the state machine comprises a state machine of a traceback unit and wherein reconfiguring comprises:

reconfiguring the state machines of the traceback unit.

40. A communication system comprises:

a transmitter to transmit an encoded signal; and

a receiver comprising a reconfigurable decoder able to be reconfigured to decode the encoded signal by downloading a circuit description to reconfigure the circuit of the decoder.

41. The communication system of claim 40, wherein the reconfigurable decoder comprises:

a programmable metric data generator to reconfigure data routing to an add-compare-select unit according to data structure of the encoded signal provided by a desired communication protocol.

42. The communication system of claim 41, wherein the programmable metric data generator further comprises a path metric data generator and a branch metric data generator.

43. The communication system of claim 42, wherein the path metric state machine comprises:

a plurality of address generators to select a predetermined number of previous generated path metrics stored in the path metric memory;

a shuffler to route at least some of the path metrics to the add-compare-select unit; and

a multiplexer to select from at least some path metrics the path metrics to be input to the add-compare-select unit.

44. The communication system of claim 43, wherein the shuffler and the multiplexer are both implemented in a programmable logic able to be programmed according to the desired communication protocol.

45. The communication system of claim 43, wherein the branch metric generator comprises:

46. The communication system of claim 45, wherein the branch metric state machine comprises programmable logic able to be programmed according to the desired communication protocol.

47. The communication system of claim 40, wherein the reconfigurable decoder comprises a programmable traceback unit.

48. The communication system of claim 47, wherein the programmable traceback unit comprises:

a cache memory to store two or more selected branches of the branch metric; and

49. The communication system of claim 47, wherein the traceback state machine is implemented by a random access memory based programmable logic device to be programmed by downloading a circuit description of the traceback state machine.